Method for manufacturing a semiconductor structure

Abstract

The present invention discloses a manufacturing method of a semiconductor structure, belonging to the field of semiconductor technology. The manufacturing method includes: providing a substrate, on which a gate structure of a semiconductor device is disposed, and the gate structure protrudes on the substrate; forming sidewall structures on both sides of the gate structure; forming a contact hole etching stop layer on the substrate, the gate structure and the sidewall structures; cleaning the contact hole etching stop layer; preprocessing the contact hole etching stop layer; and forming a dielectric layer on the contact hole etching stop layer. By the manufacturing method of a semiconductor structure provided by the present invention, defects such as voids and gaps generated in the interlayer dielectric layer can be reduced, and the yield of the semiconductor structure can be improved.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and particularly relates to a method for fabricating a semiconductor structure. Background Art

[0002] With the development of semiconductor technology, the density of circuit elements has been continuously increasing. By filling a dielectric layer between adjacent circuit elements to physically and electrically isolate the elements, improper interactions can usually be prevented. However, with the increasing demand for high integration and high performance of very large scale integrated circuits, the gap width between circuit elements has correspondingly decreased, and the aspect ratio has increased, which requires further improvement in the quality of the dielectric layer.

[0003] Currently, for example, before depositing the interlayer dielectric layer, a contact etch stop layer (CESL) is first deposited, and after the deposition is completed, a cleaning process is introduced to remove impurities on the surface of the contact etch stop layer. However, during the cleaning process, due to the uneven surface of the substrate, moisture remains between the gaps, and the moisture chemically bonds with the contact etch stop layer, resulting in a slower filling speed at the bottom during the process of filling the interlayer dielectric layer, and the dielectric layer seals prematurely, easily forming defects such as voids or seams, which may cause leakage in subsequent manufacturing processes, thereby affecting the performance of the chip. Summary of the Invention

[0004] The purpose of the present invention is to provide a method for fabricating a semiconductor structure. By using the method for fabricating a semiconductor structure provided by the present invention, defects such as voids and seams generated in the interlayer dielectric layer can be reduced, and the yield of the semiconductor structure can be improved.

[0005] To solve the above technical problems, the present invention provides a method for fabricating a semiconductor structure, which at least includes the following steps:

[0006] Provide a substrate, on which a gate structure of a semiconductor device is provided, and the gate structure protrudes from the substrate;

[0007] Form sidewall structures on both sides of the gate structure;

[0008] Form a contact etch stop layer on the substrate, the gate structure, and the sidewall structures;

[0009] Clean the contact etch stop layer;

[0010] Perform a pretreatment on the contact etch stop layer; and

[0011] Form a dielectric layer on the contact etch stop layer.

[0012] In one embodiment of the present invention, the pretreatment includes heat treatment and plasma treatment.

[0013] In one embodiment of the present invention, the temperature of the heat treatment is 180°C to 240°C, and the time of the heat treatment is 20s to 40s.

[0014] In one embodiment of the present invention, the heat treatment is carried out in an inert gas atmosphere, and the inert gas is helium or argon.

[0015] In one embodiment of the present invention, the steps of the plasma treatment include:

[0016] Putting the substrate after the heat treatment into a plasma chamber; and

[0017] Introducing a silane compound for a preset time at a preset temperature and a preset power.

[0018] In one embodiment of the present invention, the silane compound includes silane or disilane.

[0019] In one embodiment of the present invention, the preset temperature is 400°C to 450°C, the preset power is 450W to 550W, and the preset time is 5s to 10s.

[0020] In one embodiment of the present invention, in the plasma treatment, the distance between the substrate and the gas nozzle is controlled to be 1000 mils to 1200 mils.

[0021] In one embodiment of the present invention, after the contact hole etch stop layer is cleaned, a water-rich layer is formed at the bottom of the gap between adjacent gate structures.

[0022] In one embodiment of the present invention, through pretreatment of the contact hole etch stop layer, the water-rich layer at the bottom of the gap between adjacent gate structures is transformed into a silicon-rich layer.

[0023] In summary, the present invention provides a method for manufacturing a semiconductor structure. The unexpected technical effect of this application is that it can solve the problem of water residue caused by the unevenness of the semiconductor structure on the substrate and its chemical combination with the contact hole etch stop layer, so that the deposition rate of the bottom interlayer dielectric layer is not affected, and the interlayer dielectric layer will not be sealed prematurely, thereby ensuring that the deposition of the interlayer dielectric layer on the substrate has a bottom-up filling effect, thereby reducing defects such as voids and cracks in the interlayer dielectric layer, avoiding leakage in subsequent processes, and improving the yield of semiconductor devices. While improving the quality of the interlayer dielectric layer, it reduces the raw material loss in the plasma treatment process and reduces the production cost. The deposition method of the interlayer dielectric layer can be applied to different processes, improve the quality of the deposited dielectric layer, and improve the manufacturing yield of semiconductor devices.

[0024] Of course, it is not necessary for any product implementing the present invention to simultaneously achieve all the advantages described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] To more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0026] Figure 1 It is a schematic diagram of a gate structure on a substrate and the substrate in an embodiment of the present invention.

[0027] Figure 2 It is a schematic diagram of a dummy gate structure on a substrate and the substrate in another embodiment of the present invention.

[0028] Figure 3 It is a schematic diagram of forming self-aligned metal silicide in an embodiment of the present invention.

[0029] Figure 4 It is a schematic diagram of forming a contact hole etch stop layer in an embodiment of the present invention.

[0030] Figure 5 It is a schematic diagram of the contact hole etch stop layer after cleaning in an embodiment of the present invention.

[0031] Figure 6 It is a schematic diagram of the contact hole etch stop layer after pretreatment in an embodiment of the present invention.

[0032] Figure 7 It is a schematic diagram of forming an interlayer dielectric layer and planarizing it in an embodiment of the present invention.

[0033] Figure 8 It is the influence of the preset time of plasma treatment on the quality of the interlayer dielectric layer in an embodiment of the present invention.

[0034] Figure 9 It is a schematic diagram of forming a metal connection structure in the interlayer dielectric layer in an embodiment of the present invention.

[0035] Figure 10 It is a schematic diagram after planarizing the interlayer dielectric layer in another embodiment of the present invention.

[0036] Reference Signs Description:

[0037] 10. Substrate; 11. Shallow trench isolation structure; 12. Gate dielectric layer; 13. Gate structure; 14. Sidewall structure; 15. Lightly doped region; 16. Heavily doped region; 17. Self-aligned metal silicide; 18. Contact hole etch stop layer; 19. Water-rich layer; 20. Silicon-rich layer; 21. Interlayer dielectric layer; 22. First metal connection structure; 23. Second metal connection structure; 121. First dielectric layer; 122. Second dielectric layer; 131. Pseudo gate structure; 132. First hard mask layer; 133. Second hard mask layer. Detailed implementation manners

[0038] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0039] It should be noted that the illustrations provided in this embodiment only schematically illustrate the basic concept of the present invention. Therefore, only the components related to the present invention are shown in the drawings, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0040] In the present invention, it should be noted that when terms such as "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. appear, the orientation or positional relationship indicated is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the present application. In addition, when terms such as "first" and "second" appear, they are only used for descriptive and distinguishing purposes and cannot be understood as indicating or implying relative importance.

[0041] Please refer to Figure 1As shown, in an embodiment of the present invention, a substrate 10 is provided. The substrate 10 can be any material suitable for forming semiconductor devices, and the substrate 10 is, for example, silicon carbide (SiC), indium phosphide (InP), gallium arsenide (GaAs), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), silicon germanium (GeSi), sapphire, silicon wafer, or other semiconductor materials formed by III / V compounds, etc. It also includes a stacked structure composed of these semiconductor materials, or silicon on insulator, silicon-on-insulator stacked, silicon germanium on insulator, and germanium on insulator, etc. The present invention does not limit the type of the substrate 10, and it can be selected according to the manufacturing requirements of semiconductor devices. In this embodiment, the substrate 10 is, for example, a doped silicon wafer, and the doping type can be P-type or N-type.

[0042] Please refer to Figure 1As shown, in an embodiment of the present invention, a plurality of semiconductor devices are disposed on a substrate 10. The present invention does not limit the types of semiconductor devices. The semiconductor devices are, for example, a field effect transistor (FET), a metal-oxide-semiconductor field-effect transistor (MOSFET), a complementary metal oxide semiconductor (CMOS), an insulated gate bipolar transistor (IGBT), a thyristor, a charge coupled device (CCD), a constant voltage diode, a high-frequency diode, a light-emitting diode (LED), a gate turn-off thyristor (GTO), a digital signal processor (DSP), a fast recovery diode (FRD), a high-efficiency diode (HED), a light-triggered thyristor (LTT), a photo relay, or a microprocessor, etc., and one or several of them can be specifically selected according to manufacturing requirements. In this embodiment, the semiconductor device is, for example, a multi-finger MOS transistor, and the multi-finger MOS transistor is isolated from other semiconductor devices by a shallow trench isolation structure 11. Among them, the shallow trench isolation structure 11 can be prepared by any forming method, and the present invention does not make specific limitations.

[0043] Please refer to Figure 1 As shown, in an embodiment of the present invention, the semiconductor device includes a plurality of gate structures 13. The gate structures 13 protrude from the substrate 10. In an embodiment of the present invention, the distance between adjacent gate structures 13 is, for example, 30 nm to 50 nm. A gate dielectric layer 12 is disposed between the gate structure 13 and the substrate 10. Among them, the gate dielectric layer 12 is, for example, silicon dioxide, a high-k dielectric layer, a low-k dielectric layer, or a combination of multiple dielectric layers. The gate structure 13 is, for example, a polysilicon gate or a polysilicon dummy gate, etc. Sidewall structures 14 are disposed on both sides of the gate structure 13, and the sidewall structures 14 are, for example, silicon oxide, silicon nitride, or a stacked structure of silicon oxide and silicon nitride. In this embodiment, the sidewall structure 14 is, for example, a stacked structure of silicon oxide and silicon nitride.

[0044] Please refer to Figure 2 As shown, in another embodiment of the present invention, when the gate of the semiconductor device is a metal gate for example, the gate dielectric layer includes a first dielectric layer 121 and a second dielectric layer 122. Among them, the first dielectric layer 121 is silicon dioxide for example, and the second dielectric layer 122 is a high-k dielectric layer for example. A polysilicon dummy gate structure 131 is disposed on the second dielectric layer 122 to be removed in subsequent processes to form a metal gate. A hard mask layer is also disposed on the polysilicon dummy gate structure 131. The hard mask layer includes a first hard mask layer 132 and a second hard mask layer 133. The first hard mask layer 132 is a silicon nitride layer for example, and the second hard mask layer 133 is a silicon oxide layer for example, to protect the dummy gate structure 131 during the formation of the interlayer dielectric layer and the planarization process, and ensure the height of the finally formed metal gate. In this embodiment, for example, taking the gate dielectric layer 12 as silicon dioxide and the gate structure 13 as a polysilicon gate, the manufacturing method of the semiconductor structure is described.

[0045] Please refer to Figure 1 As shown, in an embodiment of the present invention, the semiconductor device further includes a lightly doped region 15 and a heavily doped region 16. Among them, the lightly doped region 15 and the heavily doped region 16 have the same doping type and are opposite to the doping type of the substrate 10. The edge of the lightly doped region 15 overlaps with a part of the gate structure 13, and the edge of the heavily doped region 16 is aligned with the edge of the sidewall structure 14 away from the gate structure 13, and the depth of the heavily doped region 16 is greater than the depth of the lightly doped region 15 to serve as the source and drain of the semiconductor device.

[0046] Please refer to Figure 1 and Figure 3 As shown, in an embodiment of the present invention, after the semiconductor device is formed, a self-aligned metal silicide 17 is formed on the heavily doped region 16 and the gate structure 13 of the semiconductor device. The self-aligned metal silicide 17 is low-resistance nickel silicide (NiSi), cobalt silicide (CoSi 2 ) or titanium silicide (TiSi 2 ) etc. By forming the self-aligned metal silicide 17, the contact resistance between the subsequently formed metal connection structure and the semiconductor device is reduced, the performance of the semiconductor device is improved, and at the same time, the heavily doped region is prevented from being broken down or leaking, so that the stability of the semiconductor device can be improved. And the self-aligned metal silicide 17 can also serve as the contact structure of the semiconductor device to lead out the source, drain and gate of the semiconductor device.

[0047] Please refer to Figures 3 to 4As shown, in an embodiment of the present invention, after the formation of the self-aligned metal silicide 17, a contact hole etching stop layer 18 is formed on the substrate 10. Among them, the contact hole etching stop layer 18 covers the substrate 10, the gate structure 13, and the sidewall structure 14, and the contact hole etching stop layer 18 is, for example, a silicon nitride layer with a thickness of, for example, 80 Å to 200 Å. In an embodiment of the present invention, the contact hole etching stop layer 18 is prepared, for example, by a low-temperature deposition method such as Plasma Enhanced Chemical Vapor Deposition (PECVD), and the deposition sources include a nitrogen source and a silicon source. Among them, the nitrogen source is selected from one or a combination of nitrogen gas (N 2 ), ammonia gas (NH 3 ), etc., and the silicon source is selected from one or several combinations of silane (SiH 4 ), disilane (Si 2 H 6 ), dichlorosilane (SiH 2 Cl 2 ), trichlorosilane (SiHCl 3 ), tetrachlorosilane (SiCl 4 ), or hexachlorodisilane (Si 2 Cl 6 ), etc.

[0048] Please refer to Figures 4 to 5As shown, in an embodiment of the present invention, after the contact hole etch stop layer 18 is formed, the contact hole etch stop layer 18 is cleaned to remove possible particulate impurities and the like on the contact hole etch stop layer 18, so as to improve the interface performance between the subsequently formed interlayer dielectric layer and the contact hole etch stop layer 18. Specifically, at room temperature, the substrate on which the contact hole etch stop layer 18 is formed is placed in a cleaning chamber, and nitrogen and water are introduced simultaneously. Nitrogen and water are ejected from the same outlet, and nitrogen atomizes the water to improve the cleaning effect and avoid damaging the contact hole etch stop layer 18. Among them, the flow rate of nitrogen is, for example, 40 L / min to 120 L / min, the flow rate of water is, for example, 60 L / min to 200 L / min, and the cleaning time is, for example, 10 s to 40 s. After cleaning the contact hole etch stop layer 18, the residual moisture on the substrate surface is removed by a wafer spin dryer. However, due to the protruding gate structure and the like on the substrate 10, there is residual moisture between the gaps of adjacent gate structures 13, forming a water-rich layer 19. If the deposition of the interlayer dielectric layer is directly carried out, the deposition temperature is relatively high, resulting in the residual moisture chemically bonding with the contact hole etch stop layer 18 to form Si-OH bonds. The surface of the top contact hole etch stop layer 18 is rich in N-H bonds. The electronegativity of N-H bonds is relatively small, while the electronegativity of Si-OH is relatively large. The nucleation reaction during the deposition of the interlayer dielectric layer occurs at a faster rate on N-H bonds than on Si-OH bonds, resulting in a faster deposition rate at the top of the gaps of the gate structures 13 during the deposition process of the interlayer dielectric layer, causing the interlayer dielectric layer to seal prematurely, generating defects such as voids or gaps.

[0049] Please refer to Figures 5 to 6 As shown, in an embodiment of the present invention, after cleaning the contact hole etch stop layer 18, the substrate contact hole etch stop layer 18 is pre-treated, and the pre-treatment includes, for example, heat treatment and plasma treatment. Among them, the temperature of the heat treatment is, for example, 180 °C to 240 °C, the time of the heat treatment is, for example, 20 s to 40 s, and the heat treatment is carried out, for example, in an inert gas atmosphere. The inert gas is, for example, helium or argon, etc., and the flow rate of the inert gas is, for example, 1800 sccm to 2500 sccm, so as to prevent the contact hole etch stop layer 18 from being oxidized during the process of removing moisture. Through the heat treatment, most of the moisture in the water-rich layer 19 can be removed, while a small part of the moisture combines with the contact hole etch stop layer 18 in the form of Si-OH valence bonds and is difficult to remove through the heat treatment.

[0050] Please refer to Figures 5 to 6 As shown, in an embodiment of the present invention, after the heat treatment, plasma treatment is carried out. Among them, the plasma includes, for example, hydrogen plasma and silicon plasma, etc. In this embodiment, the substrate 10 after the heat treatment is placed in a plasma chamber, and at a preset temperature and a preset power, silane (SiH 4 ) or disilane (Si2 H 6 ), etc. For the preset time of the silane compound, control the distance between the substrate 10 and the gas nozzle to be, for example, 1000 mils to 1200 mils to improve the uniformity of plasma treatment. In this embodiment, the preset temperature is, for example, 400 °C to 450 °C, the preset power is, for example, 450 W to 550 W, the preset time is, for example, 5 s to 10 s, and the flow rate of the silane compound is, for example, 400 sccm to 600 sccm. The silane compound generates hydrogen plasma and silicon plasma in the plasma chamber. The generated hydrogen plasma reacts with -OH and consumes the -OH bond. Synchronously, the silicon plasma combines with Si- in the water-rich layer to form Si-Si, forming the silicon-rich layer 20. Among them, the silicon-rich layer 20 is formed at the bottom of the gap between adjacent gate structures 13, and the thickness of the silicon-rich layer 20 is, for example, atomic level, and the thickness in the drawings is only for illustration.

[0051] Please refer to Figures 6 to 7 As shown, in an embodiment of the present invention, after pre-treating the contact hole etch stop layer 18, an interlayer dielectric layer 21 is formed on the contact hole etch stop layer 18. Among them, the interlayer dielectric layer 21 is, for example, silicon dioxide or a low dielectric constant (Low-K) material to improve the reliability of the semiconductor structure. And the interlayer dielectric layer 21 is, for example, deposited by a high aspect ratio process (High Aspect Ratio Process, HRAP) to improve the filling ability of the interlayer dielectric layer 21. Through plasma treatment, the water-rich layer 19 is transformed into the silicon-rich layer 20. When the HRAP deposits the interlayer dielectric layer, it has no dependence on the Si-Si bond. Therefore, the deposition rate of the interlayer dielectric layer at the bottom is greater than that at the top, thus avoiding defects such as voids. In this embodiment, specifically, a silicon-containing precursor and an oxygen-containing precursor are used to deposit in a temperature range of, for example, 400 °C to 500 °C and at a pressure of, for example, 30 torr to 760 torr. Among them, the silicon-containing precursor, for example, includes one of silane or tetraethyl orthosilicate (TEOS), etc., and the oxygen-containing precursor, for example, includes O 2 or O 3 etc. In this embodiment, the silicon-containing precursor is, for example, TEOS, and the oxygen-containing precursor is, for example, O 3, the deposition of the interlayer dielectric layer is carried out at a temperature of, for example, 430 °C and a pressure of 500 torr, and the deposition time is, for example, 100 s to 200 s. When depositing the interlayer dielectric layer 21, the interlayer dielectric layer 21 covers the shallow trench isolation structure 11 and the contact hole etch stop layer 18. After forming the interlayer dielectric layer 21, a planarization process is performed on the interlayer dielectric layer 21, for example, removing a part of the interlayer dielectric layer 21 through a Chemical Mechanical Polishing (CMP) process to ensure that the surface of the interlayer dielectric layer 21 is planar, improving the convenience of subsequent operations.

[0052] Please refer to Figures 7 to 8 As shown, in an embodiment of the present invention, the influence of the conditions of plasma treatment of the contact hole etch stop layer 18 on the HARP process in depositing the interlayer dielectric layer 21 is studied. In this embodiment, the silane compound is controlled, for example, to be silane, and the flow rate of the silane compound is fixed, the preset temperature is consistent, the distance between the substrate 10 and the gas nozzle is consistent, and the preset time of plasma treatment is controlled to change to confirm the influence of the plasma treatment time on the subsequent deposition of the interlayer dielectric layer. Among them, when depositing the interlayer dielectric layer 21 on the substrate 10 without plasma treatment, there are more defects, especially at the edge of the substrate 10. This is because after cleaning, during the spin-drying process, there is more moisture remaining around the substrate 10 than in the center. Therefore, there are more defects in the interlayer dielectric layer 21 formed at the edge of the substrate 10. As the preset time of plasma treatment increases, the defects in the interlayer dielectric layer 21 gradually decrease. Until the preset time is 7 s, there are basically no defects. As the time increases, the treatment effect is not further improved. Therefore, by controlling the plasma treatment time within the preset range, it is possible to ensure that the deposition quality of the interlayer dielectric layer is good, and it will not cause premature sealing of the interlayer dielectric layer, thereby improving the filling effect of the interlayer dielectric layer and preventing defects such as voids and gaps. Similarly, by changing the preset temperature, preset power, flow rate, etc., the optimal ranges of the preset temperature, preset power, flow rate, etc. are obtained, which can improve the quality of the interlayer dielectric layer while reducing the loss of raw materials or time during the plasma treatment process and reducing the production cost.

[0053] Please refer to Figure 7 and Figure 9As shown, in an embodiment of the present invention, after planarizing the interlayer dielectric layer 21, a metal connection structure is formed within the interlayer dielectric layer 21. In this embodiment, the remaining thickness of the interlayer dielectric layer 21 on the gate structure 13 is, for example, 60 nm to 100 nm. In other embodiments, the remaining thickness of the interlayer dielectric layer 21 on the gate structure 13 can be selected according to manufacturing requirements. Specifically, after forming the interlayer dielectric layer 21, a plurality of openings (not shown in the figure) are formed within the interlayer dielectric layer 21. In this embodiment, the openings are, for example, respectively disposed on the gate structure 13 and the heavily doped region 16, and the openings are completed through two-step etching. Specifically, a patterned photoresist layer (not shown in the figure) is formed on the interlayer dielectric layer 21 to locate the positions of the openings. Using the patterned photoresist layer as a mask and the contact hole etch stop layer 18 as an etch stop layer, the etching of the interlayer dielectric layer 21 is stopped when reaching the contact hole etch stop layer 18. The etching conditions are changed to remove the exposed contact hole etch stop layer 18, forming openings that expose the self-aligned metal silicide 17 on the gate structure 13 and the heavily doped region 16 for leading out the gate, source, and drain. Among them, the openings are, for example, formed by dry etching, and the etching gas can be, for example, a combination of one or several gases such as trifluoromethane (CHF 3 ), difluoromethane (CH 2 F 2 ), nitrogen trifluoride (NF 3 ), sulfur hexafluoride (SF 6 ), or nitrogen (N 2 ), or a combination of them and oxygen (O 2 ). In other embodiments, a combination process of dry etching and wet etching or a wet etching process can be used to form the openings.

[0054] Please refer to Figure 9As shown, in an embodiment of the present invention, after forming an opening, a conductive material is deposited in the opening to form a plurality of metal connection structures. When depositing the conductive material, a barrier layer (not shown in the figure) may be first deposited in the opening, and the barrier layer is, for example, a material with good adhesion such as tantalum (Ta), titanium (Ti), tantalum nitride (TaN), or titanium nitride (TiN), and the thickness of the barrier layer is, for example, 2 nm to 8 nm. By providing the barrier layer, the adhesion between the conductive material and the sidewall of the opening is enhanced. At the same time, the diffusion of the conductive material into the dielectric layer is reduced, the electromigration phenomenon is reduced, and the electrical performance of the semiconductor structure is improved. Among them, the conductive material is, for example, a low-resistance material such as copper, aluminum, or tungsten. In this embodiment, the conductive material is, for example, tungsten. Tungsten is formed, for example, by physical vapor deposition or electroplating, and tungsten fills the opening until it covers the interlayer dielectric layer 21, and then the tungsten is planarized so that the tungsten is flush with the interlayer dielectric layers 21 on both sides. The metal connection structure includes a first metal connection structure 22 and a second metal connection structure 23. The first metal connection structure 22 communicates with the self-aligned metal silicide 17 on the gate structure 13, and the second metal connection structure 23 communicates with the self-aligned metal silicide 17 on the heavily doped region 16. By controlling the quality of the interlayer dielectric layer 21, defects such as voids or gaps in the interlayer dielectric layer 21 are avoided, so that the metal connection structure is not filled in the voids or gaps, thereby reducing the defects of the formed metal connection structure, reducing the leakage phenomenon, and improving the reliability of the semiconductor structure.

[0055] Please refer to Figure 2 and Figure 10 As shown, in another embodiment of the present invention, during the formation of the metal gate, when planarizing the interlayer dielectric layer 21, non-selective grinding is used to simultaneously remove the contact hole etch stop layer 18, the second hard mask layer 133, and the first hard mask layer 132 on the dummy gate structure 131, exposing the surface of the dummy gate structure 131. Among them, the dummy gate structure 131 is flush with the interlayer dielectric layers 21 on both sides. After planarization, the dummy gate structure 131 is removed to form a metal gate. By controlling the quality of the interlayer dielectric layer 21, defects such as voids or gaps in the interlayer dielectric layer 21 are avoided, so that when forming the metal gate, residual metal materials in the interlayer dielectric layer 21 due to the exposure of voids or gaps are avoided, and at the same time, problems such as insufficient metal gate height, short circuit, or open circuit are avoided. That is, the method for preparing the dielectric layer in the present application can be applied to different links of the semiconductor manufacturing process to improve the manufacturing yield of semiconductor devices. In other embodiments, the method of improving the deposition process of the dielectric layer can also be applied to filling processes such as shallow trench isolation process or deep trench isolation process (DTI) to improve the filling effect.

[0056] In summary, the present invention provides a method for fabricating a semiconductor structure. The unexpected technical effect of this application is as follows: By preprocessing the contact hole etch stop layer, the problem of moisture residue caused by the unevenness of the semiconductor structure on the substrate and its chemical bonding with the contact hole etch stop layer is solved. As a result, the deposition rate of the bottom interlayer dielectric layer is not affected, and the interlayer dielectric layer will not be sealed prematurely, thereby ensuring that the interlayer dielectric layer is filled from bottom to top on the substrate, reducing defects such as voids and gaps generated in the interlayer dielectric layer, avoiding leakage in subsequent processes, and improving the yield of semiconductor devices. While improving the quality of the interlayer dielectric layer, the raw material loss during the plasma treatment process is reduced, and the production cost is lowered. The deposition method of the interlayer dielectric layer can be applied to different processes to improve the quality of the deposited dielectric layer and the fabrication yield of semiconductor devices.

[0057] The embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and variations can be made according to the content of this specification. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of the present invention, so that those skilled in the art can well understand and utilize the present invention. The present invention is only limited by the claims and their full scope and equivalents.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: At least the following steps are included: Providing a substrate, on which a gate structure of a semiconductor device is disposed, and the gate structure is protrudingly disposed on the substrate; forming sidewall structures on both sides of the gate structure; forming a contact hole etching stop layer on the substrate, the gate structure and the sidewall structure; Cleaning the contact hole etch stop layer, so that after the contact hole etch stop layer is cleaned, a water-rich layer is formed at the bottom of the gap between adjacent gate structures; Pre-treating the contact hole etching stop layer; the pre-treating includes heating treatment and plasma treatment, and through the pre-treating, the water-rich layer at the bottom of the gap between adjacent gate structures is transformed into a silicon-rich layer; as well as A dielectric layer is formed on the contact hole etch stop layer.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The temperature of the heating treatment is 180° C. to 240° C., and the time of the heating treatment is 20s to 40s.

3. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The heat treatment is performed in an inert gas atmosphere, and the inert gas is helium or argon.

4. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The steps of plasma treatment include: placing the substrate after the heating treatment into a plasma chamber; and At the preset temperature and preset power, silicon hydride is introduced for a preset time.

5. The method for manufacturing a semiconductor structure according to claim 4, characterized in that: The silicon hydride compound includes monosilane or disilane.

6. The method for manufacturing a semiconductor structure according to claim 4, characterized in that: The preset temperature is 400° C. to 450° C., the preset power is 450W to 550W, and the preset time is 5s to 10s.

7. The method for manufacturing a semiconductor structure according to claim 4, characterized in that: During the plasma treatment, the distance between the substrate and the gas nozzle is controlled to be 1000 mils to 1200 mils.

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