Formation method of semiconductor structure

Abstract

A forming method of a semiconductor structure comprises the steps that a plurality of initial grids and initial interlayer dielectric layers are formed on a substrate, the initial interlayer dielectric layers are located on the side walls of the initial grids, the initial interlayer dielectric layers comprise first dielectric layers and second dielectric layers located on the first dielectric layers, and the second dielectric layers and the first dielectric layers are made of different materials; the plurality of initial grids comprise invalid regions; the ineffective region and the plurality of fin parts at the bottom of the ineffective region are etched, fin cutting grooves are formed in the plurality of fin parts and the initial grid electrode, and the fin cutting grooves penetrate through the plurality of fin parts in the second direction; forming a second isolation structure in the fin cut-off groove; after the second isolation structure is formed, the second dielectric layer is removed; after the second dielectric layer is removed, the second isolation structure and the initial grid electrode are flattened until the second isolation structure and the initial grid electrode are flush with the top surface of the first dielectric layer, the initial interlayer dielectric layer is used for forming an interlayer dielectric layer, the initial grid electrode is used for forming a grid electrode, and stress loss caused by formation of a fin cut-off groove in the fin part is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art

[0002] In the existing semiconductor field, fin field effect transistors (FinFETs) have stronger short channel suppression capabilities and stronger operating currents, and are now widely used in various semiconductor devices.

[0003] FinFET devices usually use double diffusion break (DDB) structure and single diffusion break (SDB) structure to achieve isolation of active area. Among them, SDB structure only takes up the width of a pseudo gate structure, forming a higher device density and smaller device area. Therefore, in advanced process nodes, SDB process has replaced DDB process and become the mainstream.

[0004] Strained silicon technology introduces strain, i.e. stress change, to the channel layer in the design of device structure and materials to change the lattice structure of the channel layer substrate, thereby increasing the mobility of carriers in the channel layer and improving device performance. Direct epitaxy of channel materials with stress in the channel layer will become a development trend. Germanium silicon materials have become a hot topic in the research of new channel materials due to their high carrier mobility, higher device reliability and compatibility with existing silicon-based processes.

[0005] However, along with the advantage of size reduction, the SDB structure causes the FinFET device to suffer from channel stress loss, making it difficult to realize the advantages of strained silicon technology. Therefore, for FinFET devices, how to maintain stress becomes a technical difficulty of the SDB process. Summary of the invention

[0006] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure to improve the performance of the formed semiconductor structure.

[0007] In order to solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a base, a plurality of fins located on the surface of the base, and a first isolation structure located on the surface of the base, the first isolation structure being located on the sidewall surface of the plurality of fins, and the top surface of the first isolation structure being lower than the top surface of the plurality of fins, and the plurality of fins being parallel to a first direction; forming a plurality of initial gates and an initial interlayer dielectric layer on the substrate, the initial interlayer dielectric layer being located on the sidewalls of the plurality of initial gates and exposing the top surfaces of the plurality of initial gates, the initial interlayer dielectric layer comprising a first dielectric layer and a second dielectric layer located on the first dielectric layer, the second dielectric layer Different from the material of the first dielectric layer, several of the initial gates are parallel to a second direction, the second direction is perpendicular to the first direction, and several of the initial gates include an invalid area; the invalid area and several of the fins at the bottom of the invalid area are etched to form fin cutting grooves in several of the fins and the initial gates, and the fin cutting grooves penetrate several of the fins in the second direction; a second isolation structure is formed in the fin cutting groove; after forming the second isolation structure, the second dielectric layer is removed; after removing the second dielectric layer, the second isolation structure and the initial gate are flattened until they are flush with the top surface of the first dielectric layer, an interlayer dielectric layer is formed with the initial interlayer dielectric layer, and a gate is formed with the initial gate.

[0008] Optionally, the substrate includes a gate cut-off region, which is parallel to the first direction and located between adjacent fins; some of the initial gates span the gate cut-off region; after forming the initial gates and the initial interlayer dielectric layer and before forming the fin cut-off groove, it also includes: removing the initial gates on the gate cut-off region, forming a gate cut-off groove in the initial interlayer dielectric layer, and the gate cut-off groove passes through the initial gates in the first direction; and forming a third isolation structure in the gate cut-off groove.

[0009] Optionally, the third isolation structure is formed before the fin cutting groove is formed.

[0010] Optionally, the fin cutting groove is located between two adjacent third isolation structures, and exposes side walls of the third isolation structure.

[0011] Optionally, a bottom surface of the gate cutting groove is lower than a surface of the substrate.

[0012] Optionally, the method for forming a gate cut-off groove also includes: forming a first hard mask layer on the surface of several of the initial gates and the initial interlayer dielectric layer, the first hard mask layer exposing the top surfaces of several of the initial gates on the gate cut-off area; and etching several of the initial gates using the first hard mask layer as a mask.

[0013] Optionally, the method for forming the third isolation structure includes: forming a first dielectric material layer in the gate cut-off groove and on the surface of the first hard mask layer; and planarizing the first dielectric material layer and the first hard mask layer until the surface of the initial interlayer dielectric layer is exposed.

[0014] Optionally, before forming the first hard mask layer, an initial protective layer is also formed on the top surface of several of the initial gates and the surface of the initial interlayer dielectric layer; before etching several of the initial gates, the initial protective layer is also etched using the first hard mask layer as a mask to form a protective layer; the planarization process exposes the protective layer on the surface of the initial interlayer dielectric layer.

[0015] Optionally, the material of the protective layer includes titanium nitride.

[0016] Optionally, the method for forming the fin cutting groove also includes: forming a second hard mask layer on the top surface of several of the initial gates and the protective layer, the second hard mask layer exposing the protective layer on the invalid area; using the second hard mask layer as a mask, etching the protective layer, the invalid area and several of the fins at the bottom of the invalid area.

[0017] Optionally, the method for forming the second isolation structure includes: forming a second dielectric material layer in the fin cut-off groove and on the surface of the second hard mask layer; using a first planarization process to planarize the second dielectric material layer and the second hard mask layer until the surface of the protective layer is exposed; after the first planarization process, using a second planarization process to planarize the second dielectric material layer and the protective layer until the top surface of the initial interlayer dielectric layer is exposed.

[0018] Optionally, the method for forming the fin cutting groove also includes: forming a second hard mask layer on the top surface of several of the initial gates and the initial interlayer dielectric layer, the second hard mask layer exposing the invalid area; using the second hard mask layer as a mask, etching the invalid area and several of the fins at the bottom of the invalid area.

[0019] Optionally, the method for forming the second isolation structure includes: forming a second dielectric material layer in the fin cutting groove and on the surface of the second hard mask layer; and planarizing the second dielectric material layer and the second hard mask layer until the top surface of the initial interlayer dielectric layer is exposed.

[0020] Optionally, the method for forming the fin cutting groove further includes: after etching the ineffective area, etching the first isolation structure at the bottom of the ineffective area, and the fin cutting groove is also located in the first isolation structure.

[0021] Optionally, after the planarization process, the method further includes: forming an etch stop layer on the surface of the interlayer dielectric layer and a third dielectric layer located on the etch stop layer.

[0022] Optionally, the fins on both sides of the initial gate have source and drain layers, and the initial interlayer dielectric layer is also located on the surface of the source and drain layers; after forming the third dielectric layer, it also includes: forming openings in the third dielectric layer, the etch stop layer and the interlayer dielectric layer, the openings exposing the surfaces of the source and drain regions; and forming a zero metal layer in the openings.

[0023] Optionally, the method for forming the plurality of initial gates and the initial interlayer dielectric layer includes: forming a plurality of dummy gates and the initial interlayer dielectric layer on the substrate, the initial interlayer dielectric layer exposing the top surfaces of the plurality of dummy gates; and replacing the plurality of dummy gates to form the plurality of initial gates.

[0024] Optionally, the method for forming the initial interlayer dielectric layer includes: after forming a number of the pseudo gates, forming an initial first dielectric layer on the substrate, the initial first dielectric layer exposing the top surfaces of a number of the pseudo gates; etching back the initial first dielectric layer to form the first dielectric layer; and forming the second dielectric layer on the surface of the first dielectric layer.

[0025] Optionally, a bottom surface of the fin cutting groove is lower than a top surface of the first isolation structure.

[0026] Optionally, the material of the fin includes silicon germanium.

[0027] Optionally, the material of the initial gate includes metal.

[0028] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0029] In the method for forming a semiconductor structure provided by the technical solution of the present invention, the initial interlayer dielectric layer includes a first dielectric layer and a second dielectric layer located on the first dielectric layer, the second dielectric layer and the first dielectric layer are made of different materials, the first dielectric layer is used to form an interlayer dielectric layer, and the initial gate is used to form a gate. The existence of the second dielectric layer is conducive to maintaining the height of the initial gate and making the initial interlayer dielectric layer have a larger thickness. Therefore, the thicker initial interlayer dielectric layer and the higher initial gate on the surface of the fin make it easier to maintain the stress inside the fin during the formation of the fin cutting groove, reduce the stress loss inside the fin caused by the formation of the fin cutting groove, and improve the performance of the device.

[0030] Furthermore, before etching the initial gates, the initial protective layer is etched using the first hard mask layer as a mask to form a protective layer. During the process of planarizing the first dielectric material layer and the first hard mask layer, the protective layer plays a protective role and helps to improve the flatness of the formed surface.

[0031] Furthermore, after removing the second dielectric layer, the second isolation structure and the initial gate are planarized until they are flush with the top surface of the first dielectric layer to obtain a relatively flat surface. Then, an etch stop layer and a third dielectric layer located on the etch stop layer are formed on the surface of the interlayer dielectric layer. The formation process of the third dielectric layer and the etch stop layer does not require a planarization process to obtain a relatively flat surface. Subsequently, a zero metal layer is formed in the third dielectric layer and the etch stop layer, which is beneficial to improve the accuracy of the critical dimensions and height of the zero metal layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figures 1 to 6 It is a structural schematic diagram of each step of a method for forming a semiconductor structure;

[0033] Figures 7 to 31 It is a structural schematic diagram of each step of the method for forming a semiconductor structure in an embodiment of the present invention. DETAILED DESCRIPTION

[0034] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to direct contact.

[0035] As described in the background art, how to maintain stress in FinFET devices becomes a technical difficulty of the SDB process. Now, a method for forming a semiconductor structure is described and analyzed.

[0036] Figures 1 to 6 The present invention is a structural schematic diagram of each step of a method for forming a semiconductor structure.

[0037] Please refer to Figures 1 to 3 , Figure 1 for Figure 2 and Figure 3 The top view of the interlayer dielectric layer is omitted. Figure 2 for Figure 1 Schematic diagram of the cross-sectional structure along the EE1 direction, Figure 3 for Figure 1 A schematic cross-sectional structure diagram along the FF1 direction in the figure provides a substrate, the substrate includes a base 100, a plurality of fins 101 located on the base 100, and a first isolation structure 102, the first isolation structure 102 is located on part of the side walls of the plurality of fins 101, and the top surfaces of the plurality of fins 101 are higher than the top surface of the isolation structure 102; a plurality of pseudo gate structures are formed on the substrate across the plurality of fins 101, each of the pseudo gate structures includes a pseudo gate (not shown in the figure) and a sidewall 103 located on the side wall of the pseudo gate; an interlayer dielectric layer 104 is formed on the surface of the substrate and the pseudo gate structure, the top surface of the interlayer dielectric layer 104 exposes the top surface of the pseudo gate; the pseudo gate is replaced by a metal gate 105.

[0038] Please refer to Figures 4 to 6 , Figure 4 for Figure 5 and Figure 6 A top view of the structure. Figure 5 for Figure 4 Schematic diagram of the cross-sectional structure along the EE1 direction, Figure 6 for Figure 4 In the schematic diagram of the cross-sectional structure along the FF1 direction, a mask layer 106 is formed on the surface of the interlayer dielectric layer 104 and the metal gate 105, and the mask layer 106 exposes a portion of the bottom surface of the metal gate 105; using the mask 106 as a mask, the metal gate 105 is etched to form an initial cutting groove (not shown in the figure) in the interlayer dielectric layer 104; the first isolation structure 102 and the fin 101 exposed by the initial cutting groove are etched to form a cutting groove 107.

[0039] In the above-mentioned method for forming a semiconductor structure, the material of the fin 101 includes germanium silicon. Subsequently, a second isolation structure is formed in the cut-off groove 107 as the sdb structure of the FinFET device. However, since the cut-off groove 107 is formed after the metal gate 105 is formed, during the etching process of the fin 101, the thickness of the interlayer dielectric layer 104 on the fin 101 is relatively thin, making it difficult to maintain the stress in the fin 101, which easily causes the stress release of the device channel, thereby weakening the advantages of strained silicon technology.

[0040] In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, wherein the initial interlayer dielectric layer includes a first dielectric layer and a second dielectric layer located on the first dielectric layer, the second dielectric layer and the first dielectric layer are made of different materials, the first dielectric layer is used to form an interlayer dielectric layer, and the initial gate is used to form a gate, and the existence of the second dielectric layer is conducive to maintaining the height of the initial gate and making the initial interlayer dielectric layer have a larger thickness, thereby the thicker initial interlayer dielectric layer and the higher initial gate on the surface of the fin are conducive to maintaining the stress inside the fin during the formation of the fin cutting groove, reducing the stress loss inside the fin caused by the formation of the fin cutting groove, and improving the performance of the device.

[0041] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0042] Figures 7 to 31 It is a structural schematic diagram of each step of the method for forming a semiconductor structure in an embodiment of the present invention.

[0043] Please refer to Figure 7 and Figure 8 , Figure 7 for Figure 8 A top view of the structure. Figure 8 for Figure 7 A schematic diagram of the cross-sectional structure along the HH1 direction is provided, wherein a substrate is provided, the substrate comprising a base 201, a plurality of fins 202 located on the surface of the base 201, and a first isolation structure 203 located on the surface of the base 201, wherein the first isolation structure 203 is located on a partial side wall surface of the plurality of fins 202, and a top surface of the first isolation structure 203 is lower than a top surface of the plurality of fins 202, and the plurality of fins 202 are parallel to a first direction X.

[0044] In this embodiment, the material of the substrate 201 is silicon. In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of III-V group elements, silicon on insulator (SOI) or germanium on insulator (GOI). Among them, the multi-element semiconductor material composed of III-V group elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

[0045] In this embodiment, the substrate includes a gate cut-off region PC, which is parallel to the first direction X and located between adjacent fins 202. The gate cut-off region PC is used to define the position of a gate cut-off groove, which is used to form a third isolation structure. Specifically, two gate cut-off regions PC of different lengths are shown.

[0046] In this embodiment, the material of the fin 202 includes germanium silicon. The fin 202 is used to form a germanium silicon channel device.

[0047] Specifically, the fin 202 includes a bottom region (not shown in the figure) and a channel region (not shown in the figure) located on the bottom region, the material of the bottom region is silicon, the material of the channel region is silicon germanium, and the first isolation structure 203 is located on the side wall of the bottom region and exposes the channel region.

[0048] Subsequently, a plurality of initial gates and an initial interlayer dielectric layer are formed on the substrate, wherein the initial interlayer dielectric layer is located on the sidewalls of the plurality of initial gates and exposes the top surfaces of the plurality of initial gates, wherein the initial interlayer dielectric layer includes a first dielectric layer and a second dielectric layer located on the first dielectric layer, wherein the second dielectric layer and the first dielectric layer are made of different materials, wherein the plurality of initial gates are parallel to a second direction Y, wherein the second direction Y is perpendicular to the first direction X, and wherein the plurality of initial gates include an invalid region.

[0049] In this embodiment, the formation methods of the initial gate and the initial interlayer dielectric layer are described in detail. Figures 9 to 16 .

[0050] Please refer to Figures 9 to 12 , Fig. 9 The schematic diagram of the top view of the initial interlayer dielectric layer is omitted. Fig.10 for Fig. 9 Schematic diagram of the cross-sectional structure along the HH1 direction, Fig.11 for Fig. 9 Schematic diagram of the cross-sectional structure along the MM1 direction, Fig.12 for Fig. 9 The cross-sectional structure diagram along the NN1 direction in FIG. 1 shows that a plurality of dummy gates 204 and the initial interlayer dielectric layer are formed on the substrate, and the initial interlayer dielectric layer exposes the top surfaces of a plurality of the dummy gates 204 .

[0051] The initial interlayer dielectric layer includes a first dielectric layer 206 and a second dielectric layer 207 located on the first dielectric layer 206, and the second dielectric layer 207 and the first dielectric layer 206 are made of different materials. The first dielectric layer 206 is used to form an interlayer dielectric layer, and the dummy gate 204 is used to form a gate to occupy a position. Before the fin is cut, the existence of the second dielectric layer 207 makes the initial interlayer dielectric layer have a larger thickness and is conducive to maintaining the height of the dummy gate 204, thereby maintaining the height of the initial gate.

[0052] In this embodiment, the method for forming the initial interlayer dielectric layer includes: after forming a plurality of the pseudo gates 204, forming an initial first dielectric layer (not shown in the figure) on the substrate, wherein the initial first dielectric layer exposes the top surfaces of the plurality of the pseudo gates 204; etching back the initial first dielectric layer to form the first dielectric layer 206; and forming the second dielectric layer 207 on the surface of the first dielectric layer 206.

[0053] Specifically, the method for forming the initial first dielectric layer also includes: forming a third dielectric material layer (not shown in the figure) on the substrate, the top surface of the third dielectric material layer is higher than the top surfaces of the plurality of pseudo gates 204; and planarizing the third dielectric material layer until the top surfaces of the plurality of pseudo gates 204 are exposed to form the initial first dielectric layer.

[0054] In this embodiment, after forming a plurality of the dummy gates 204 and before forming the third dielectric material layer, a sidewall spacer 205 is formed on the sidewall of each of the dummy gates 204 .

[0055] In this embodiment, source and drain layers are provided in the fins on both sides of the initial gate, and the initial interlayer dielectric layer is also located on the surface of the source and drain layers.

[0056] Specifically, the method for forming the second dielectric layer 207 further includes: forming a fourth dielectric material layer (not shown) on the surface of the first dielectric layer 206, and planarizing the fourth dielectric material layer until the top surfaces of several dummy gates 204 are exposed.

[0057] In this embodiment, the material of some of the dummy gates 204 is polysilicon.

[0058] Please refer to Figures 13 to 16 , Fig.13 This is a top view of the structure. Fig.14 for Fig.13 Schematic diagram of the cross-sectional structure along the HH1 direction, Fig.15 for Fig.13 Schematic diagram of the cross-sectional structure along the MM1 direction, Fig.16 for Fig.13 The cross-sectional structure diagram along the NN1 direction in FIG. 1 is a schematic diagram showing a cross-sectional structure of the dummy gates 204 , where a plurality of the initial gates 208 are formed by replacing the dummy gates 204 .

[0059] In this embodiment, the material of the initial gate 208 includes metal.

[0060] In this embodiment, some of the initial gates 208 cross the gate cut-off region PC.

[0061] Some of the initial gates 208 include an inactive region FC, where the inactive region FC is used to define a location of a fin-cutting groove, where the fin-cutting groove is used to form a second isolation structure.

[0062] In this embodiment, the third isolation structure is formed before the fin cutting groove is formed. In another embodiment, the third isolation structure may be formed after the second isolation structure is formed.

[0063] In this embodiment, after forming the initial gates 208 and the initial interlayer dielectric layer, and before forming the fin cutting groove, please refer to Figures 17 to 22 .

[0064] Please refer to Figures 17 to 19 , Fig.17 This is a top view of the structure. Fig.18 for Fig.17 Schematic diagram of the cross-sectional structure along the HH1 direction, Fig.19 for Fig.17 The schematic cross-sectional structure diagram along the MM1 direction in FIG. 1 shows a plurality of initial gate electrodes 208 on the gate cut-off region PC, and a gate cut-off groove 209 is formed in the initial interlayer dielectric layer. The gate cut-off groove 209 penetrates the plurality of initial gate electrodes 208 in the first direction X.

[0065] In this embodiment, the method for forming the gate cut-off groove 209 further includes: forming a first hard mask layer 210 on the surface of the plurality of initial gates 208 and the initial interlayer dielectric layer, wherein the first hard mask layer 210 exposes the top surfaces of the plurality of initial gates 208 on the gate cut-off region PC; using the first hard mask layer 210 as a mask, etching the plurality of initial gates 208. Specifically, the first hard mask layer 210 also exposes the initial interlayer dielectric layer on the gate cut-off region PC; and using the first hard mask layer 210 as a mask, etching the initial interlayer dielectric layer and a portion of the substrate.

[0066] In this embodiment, the bottom surface of the gate cutting groove 209 is lower than the surface of the substrate 201 .

[0067] The material of the first hard mask layer 210 includes a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbon oxynitride.

[0068] The first hard mask layer 210 may be a single-layer structure or a multi-layer structure. In this embodiment, the first hard mask layer 210 is a double-layer structure, including a silicon nitride mask layer (not shown in the figure) and a silicon oxide mask layer (not shown in the figure) located on the silicon nitride mask layer.

[0069] In this embodiment, before forming the first hard mask layer 210, an initial protection layer (not shown in the figure) is formed on the top surface of the initial gates 208 and the surface of the initial interlayer dielectric layer; before etching the initial gates 208, the initial protection layer is etched using the first hard mask layer 210 as a mask to form a protection layer 211. In another embodiment, the protection layer may not be formed.

[0070] Before etching the initial gate electrodes 208 , the initial protection layer is further etched using the first hard mask layer 210 as a mask to form a protection layer 211 .

[0071] In this embodiment, the material of the protection layer 211 includes titanium nitride.

[0072] Please refer to Figure 20 to Figure 22 , Fig. 20 This is a top view of the structure. Fig.21 for Fig. 20 Schematic diagram of the cross-sectional structure along the HH1 direction, Fig. 22 for Fig. 20 The cross-sectional structure diagram along the MM1 direction in FIG. 1 shows a third isolation structure 212 formed in the gate cutting groove 209 .

[0073] In this embodiment, the method for forming the third isolation structure 212 includes: forming a first dielectric material layer (not shown in the figure) in the gate cut-off groove 209 and on the surface of the first hard mask layer 210; and planarizing the first dielectric material layer and the first hard mask layer 210 until the surface of the initial interlayer dielectric layer is exposed.

[0074] Specifically, the planarization process exposes the protective layer 211 on the surface of the initial interlayer dielectric layer. In the process of planarizing the first dielectric material layer and the first hard mask layer 210, the protective layer 211 plays a protective role, which is conducive to improving the flatness of the formed surface.

[0075] Please refer to Figure 23 to Figure 25 , Fig.23 This is a top view of the structure. Fig.24 for Fig.23 Schematic diagram of the cross-sectional structure along the HH1 direction, Fig.25 for Fig.23 In the schematic diagram of the cross-sectional structure along the NN1 direction, the invalid area FC and the several fins 202 at the bottom of the invalid area FC are etched to form fin cutting grooves 213 in the several fins 202 and the initial gate 208, and the fin cutting grooves 213 penetrate the several fins 202 in the second direction Y.

[0076] Here, the first dielectric layer 206 is used to form an interlayer dielectric layer, and the initial gate 208 is used to form a gate. As mentioned above, the existence of the second dielectric layer 207 is conducive to maintaining the height of the initial gate 208 and making the initial interlayer dielectric layer have a larger thickness. Therefore, the thicker initial interlayer dielectric layer and the thicker initial gate 208 on the surface of the fin 202 are conducive to maintaining the stress inside the fin 202 during the formation of the fin cutting groove 213, reducing the stress loss caused by the formation of the fin cutting groove 213 inside the fin 202, and improving the performance of the device.

[0077] In this embodiment, the method for forming the fin cutting groove 213 further includes: after etching the ineffective region FC, etching the first isolation structure 203 at the bottom of the ineffective region FC, and the fin cutting groove 213 is also located in the first isolation structure 203 .

[0078] In this embodiment, the fin cutting groove 213 is located between two adjacent third isolation structures 208 and exposes the sidewalls of the third isolation structure 212 .

[0079] In this embodiment, a bottom surface of the fin cutting groove 213 is lower than a top surface of the first isolation structure 203 .

[0080] In this embodiment, the method for forming the fin cutting groove 213 also includes: forming a second hard mask layer 214 on the top surface of several of the initial gates 208 and the protective layer 211, the second hard mask layer 214 exposing the protective layer on the invalid region FC; using the second hard mask layer 214 as a mask, etching the protective layer 211, the invalid region FC and several of the fins 202 at the bottom of the invalid region FC.

[0081] The material of the second hard mask layer 214 includes a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbon oxynitride.

[0082] The second hard mask layer 214 may be a single-layer structure or a multi-layer structure. In this embodiment, the second hard mask layer 214 is a single-layer structure, and its material is silicon nitride.

[0083] In another embodiment, the method for forming the fin cutting groove also includes: forming a second hard mask layer on the top surface of several of the initial gates and the initial interlayer dielectric layer, the second hard mask layer exposing the invalid area; using the second hard mask layer as a mask, etching the invalid area and several of the fins at the bottom of the invalid area.

[0084] Please refer to Figure 26 to Figure 28 , Fig.26 This is a top view of the structure. Fig. 27for Fig.26 Schematic diagram of the cross-sectional structure along the HH1 direction, Fig.28 for Fig.26 The cross-sectional structure diagram along the NN1 direction in FIG. 2 shows a second isolation structure 215 formed in the fin cutting groove 214 .

[0085] In this embodiment, the method for forming the second isolation structure 215 includes: forming a second dielectric material layer (not shown in the figure) in the fin cutting groove 213 and on the surface of the second hard mask layer 214; using a first planarization process to planarize the second dielectric material layer and the second hard mask layer 214 until the surface of the protective layer 211 is exposed; after the first planarization process, using a second planarization process to planarize the second dielectric material layer and the protective layer 211 until the top surface of the initial interlayer dielectric layer is exposed.

[0086] In another embodiment, the method for forming the second isolation structure includes: forming a second dielectric material layer in the fin cutting groove and on the surface of the second hard mask layer; and planarizing the second dielectric material layer and the second hard mask layer until the top surface of the initial interlayer dielectric layer is exposed.

[0087] Please refer to Fig.29 , Fig.29 The viewing direction is the same as Fig.28 After forming the second isolation structure 215 , the second dielectric layer 207 is removed.

[0088] Please refer to Fig.30 , Fig.30 The viewing direction is the same as Fig.28 After removing the second dielectric layer 207 , the second isolation structure 215 and the initial gate 208 are planarized until they are flush with the top surface of the first dielectric layer 206 , and an interlayer dielectric layer 216 is formed with the initial interlayer dielectric layer, and a gate 217 is formed with the initial gate 208 .

[0089] Here, the planarization process is used to obtain a relatively flat surface.

[0090] In this embodiment, after the planarization process, please refer to Fig.31 .

[0091] Please refer to Fig.31 , Fig.31 The viewing direction is the same as Fig.28 An etch stop layer 218 and a third dielectric layer 219 located on the etch stop layer 218 are formed on the surface of the interlayer dielectric layer 216 .

[0092] In this embodiment, after forming the third dielectric layer 219, it also includes: forming an opening (not shown in the figure) in the third dielectric layer 219, the etch stop layer 218 and the interlayer dielectric layer 216, wherein the opening exposes the surface of the source and drain regions; and forming a zero metal layer (not shown in the figure) in the opening.

[0093] As described above, after removing the second dielectric layer 207, the second isolation structure 215 and the initial gate 208 are planarized to obtain a relatively flat surface, and then an etch stop layer 218 and a third dielectric layer 219 located on the etch stop layer 218 are formed on the surface of the interlayer dielectric layer 216. The formation process of the third dielectric layer 219 and the etch stop layer 218 does not require a planarization process to obtain a relatively flat surface. Subsequently, a zero metal layer is formed in the third dielectric layer 219 and the etch stop layer 218, which is beneficial to improve the accuracy of the critical dimensions and height of the zero metal layer.

[0094] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a base, a plurality of fins located on a surface of the base, and a first isolation structure located on the surface of the base, wherein the first isolation structure is located on a partial sidewall surface of the plurality of fins, and a top surface of the first isolation structure is lower than a top surface of the plurality of fins, and the plurality of fins are parallel to a first direction; Forming a plurality of initial gates and an initial interlayer dielectric layer on the substrate, wherein the initial interlayer dielectric layer is located on the sidewalls of the plurality of initial gates and exposes the top surfaces of the plurality of initial gates, the initial interlayer dielectric layer comprises a first dielectric layer and a second dielectric layer located on the first dielectric layer, the second dielectric layer and the first dielectric layer are made of different materials, the plurality of initial gates are parallel to a second direction, the second direction is perpendicular to the first direction, and the plurality of initial gates comprise an invalid region; Etching the invalid region and the plurality of fins at the bottom of the invalid region to form fin cutting grooves in the plurality of fins and the initial gate, wherein the fin cutting grooves penetrate the plurality of fins in the second direction; forming a second isolation structure in the fin cutting groove; After forming the second isolation structure, removing the second dielectric layer; After removing the second dielectric layer, the second isolation structure and the initial gate are planarized until they are flush with the top surface of the first dielectric layer, and an interlayer dielectric layer is formed with the initial interlayer dielectric layer, and a gate is formed with the initial gate.

2. The method for forming a semiconductor structure according to claim 1, wherein: The substrate comprises a gate cut-off region, the gate cut-off region is parallel to the first direction and is located between adjacent fins; some of the initial gates cross the gate cut-off region; After forming the plurality of initial gates and the initial interlayer dielectric layer and before forming the fin cutting groove, the method further comprises: removing the plurality of initial gates on the gate cutting region and forming a gate cutting groove in the initial interlayer dielectric layer, wherein the gate cutting groove penetrates the plurality of initial gates in the first direction; A third isolation structure is formed in the gate cutting groove.

3. The method for forming a semiconductor structure according to claim 2, wherein: The third isolation structure is formed before the fin cutting groove is formed.

4. The method for forming a semiconductor structure according to claim 3, wherein: The fin cutting groove is located between two adjacent third isolation structures and exposes the sidewalls of the third isolation structure.

5. The method for forming a semiconductor structure according to claim 2, wherein: The bottom surface of the gate cutting groove is lower than the surface of the substrate.

6. The method for forming a semiconductor structure according to claim 2, wherein: The method for forming a gate cut-off groove also includes: forming a first hard mask layer on the surface of several of the initial gates and the initial interlayer dielectric layer, wherein the first hard mask layer exposes the top surfaces of several of the initial gates on the gate cut-off region; and etching several of the initial gates using the first hard mask layer as a mask.

7. The method for forming a semiconductor structure according to claim 6, wherein: The method for forming the third isolation structure includes: forming a first dielectric material layer in the gate cutting groove and on the surface of the first hard mask layer; and planarizing the first dielectric material layer and the first hard mask layer until the surface of the initial interlayer dielectric layer is exposed.

8. The method for forming a semiconductor structure according to claim 7, wherein: Before forming the first hard mask layer, an initial protective layer is formed on the top surface of several of the initial gates and the surface of the initial interlayer dielectric layer; before etching several of the initial gates, the initial protective layer is etched using the first hard mask layer as a mask to form a protective layer; the planarization process exposes the protective layer on the surface of the initial interlayer dielectric layer.

9. The method for forming a semiconductor structure according to claim 8, wherein: The material of the protection layer includes titanium nitride.

10. The method for forming a semiconductor structure according to claim 8, wherein: The method for forming the fin cutting groove also includes: forming a second hard mask layer on the top surface of several of the initial gates and the protective layer, the second hard mask layer exposing the protective layer on the invalid area; using the second hard mask layer as a mask, etching the protective layer, the invalid area and several of the fins at the bottom of the invalid area.

11. The method for forming a semiconductor structure according to claim 10, wherein: The method for forming the second isolation structure includes: forming a second dielectric material layer in the fin cutting groove and on the surface of the second hard mask layer; using a first planarization process to planarize the second dielectric material layer and the second hard mask layer until the surface of the protective layer is exposed; after the first planarization process, using a second planarization process to planarize the second dielectric material layer and the protective layer until the top surface of the initial interlayer dielectric layer is exposed.

12. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the fin cutting groove also includes: forming a second hard mask layer on the top surface of the initial gates and the initial interlayer dielectric layer, the second hard mask layer exposing the invalid area; using the second hard mask layer as a mask, etching the invalid area and the fins at the bottom of the invalid area.

13. The method for forming a semiconductor structure according to claim 12, wherein: The method for forming the second isolation structure includes: forming a second dielectric material layer in the fin cutting groove and on the surface of the second hard mask layer; and planarizing the second dielectric material layer and the second hard mask layer until the top surface of the initial interlayer dielectric layer is exposed.

14. The method for forming a semiconductor structure according to claim 12, wherein: The method for forming the fin cutting groove further includes: after etching the ineffective area, etching the first isolation structure at the bottom of the ineffective area, and the fin cutting groove is also located in the first isolation structure.

15. The method for forming a semiconductor structure according to claim 1, wherein: After the planarization process, the method further includes: forming an etch stop layer on the surface of the interlayer dielectric layer and a third dielectric layer located on the etch stop layer.

16. The method for forming a semiconductor structure according to claim 15, wherein: The fins on both sides of the initial gate have source and drain layers in them, and the initial interlayer dielectric layer is also located on the surface of the source and drain layers; After forming the third dielectric layer, the method further includes: forming openings in the third dielectric layer, the etch stop layer and the interlayer dielectric layer, wherein the openings expose the surfaces of the source and drain regions; A zero metal layer is formed in the opening.

17. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the initial gates and the initial interlayer dielectric layer comprises: forming a plurality of dummy gates and the initial interlayer dielectric layer on the substrate, wherein the initial interlayer dielectric layer exposes the top surfaces of the dummy gates; and replacing the dummy gates to form the initial gates.

18. The method for forming a semiconductor structure according to claim 17, wherein: The method for forming the initial interlayer dielectric layer comprises: after forming a plurality of the dummy gates, forming an initial first dielectric layer on the substrate, wherein the initial first dielectric layer exposes the top surfaces of a plurality of the dummy gates; etching back the initial first dielectric layer to form the first dielectric layer; and forming the second dielectric layer on the surface of the first dielectric layer.

19. The method for forming a semiconductor structure according to claim 1, wherein: A bottom surface of the fin cutting groove is lower than a top surface of the first isolation structure.

20. The method for forming a semiconductor structure according to claim 1, wherein: The material of the fin includes silicon germanium.

21. The method for forming a semiconductor structure according to claim 1, wherein: The material of the initial gate includes metal.

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