Self-aligned gate end cap (SAGE) architecture with improved cap

Abstract

A self-aligned gate end cap (SAGE) architecture with an improved cap is described, as well as a method of manufacturing a self-aligned gate end cap (SAGE) architecture with an improved cap. In an example, an integrated circuit structure includes a first gate structure over a first semiconductor fin. A second gate structure is over the second semiconductor fin. A gate cap isolation structure is between the first gate structure and the second gate structure. The gate end cap isolation structure has a higher-k dielectric cap layer on the lower-k dielectric wall. The higher-k dielectric cap layer includes hafnium and oxygen, and has a monoclinic crystallinity of 70% or more.

Description

[0001] This application is a divisional application of the Chinese invention patent application with application number 202211456766.1, application date November 21, 2020, and invention name “Self-Aligned Gate End Cap (SAGE) Architecture with Improved Cover”. Technical Field

[0002] Embodiments of the present disclosure are in the field of semiconductor devices and processes, and more particularly, in the field of a self-aligned gate endcap (SAGE) architecture with an improved cap, and a method of manufacturing the self-aligned gate endcap (SAGE) architecture with an improved cap. Background Art

[0003] Over the past several decades, the scaling of features in integrated circuits has been the driving force behind the growing semiconductor industry. Scaling to smaller and smaller features enables an increased density of functional units on the limited substrate area of ​​a semiconductor chip. For example, shrinking transistor size allows an increased number of memory or logic devices to be included on a chip, resulting in the manufacture of products with increased capacity. But the drive for larger and larger capacities is not without its problems. The need to optimize the performance of each device becomes increasingly apparent.

[0004] In the manufacture of integrated circuit devices, multi-gate transistors such as tri-gate transistors have become more common as device sizes continue to shrink. In conventional processes, tri-gate transistors are typically manufactured on bulk silicon substrates or silicon-on-insulator substrates. In some cases, bulk silicon substrates are preferred because of their lower cost and because they enable less complex tri-gate manufacturing processes.

[0005] However, scaling multi-gate transistors is not without consequences. As the size of these basic building blocks of microelectronic circuits decreases, and as the absolute number of basic building blocks fabricated in a given area increases, the constraints on the photolithographic processes used to pattern these building blocks have become overwhelming. In particular, there may be a tradeoff between the minimum size of a feature patterned in a semiconductor stack (the critical dimension) and the spacing between these features. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 Plan views of adjacent integrated circuit structures for a conventional architecture with relatively wide spacing (left hand side (a)) and adjacent integrated circuit structures for a self-aligned gate end cap (SAGE) architecture with relatively tight spacing (right hand side (b)) are shown according to embodiments of the present disclosure.

[0007] Figure 2 A plan view of a conventional layout of a fin-based semiconductor device including one that accommodates end-to-end spacing is shown.

[0008] Figure 3 Shown are cross-sectional views taken through a fin for a conventional architecture (left hand side (a)) and a self-aligned gate end cap (SAGE) architecture (right hand side (b)) according to an embodiment of the present disclosure.

[0009] Figures 4A-4D A cross-sectional view showing important process operations in a conventional FinFET or tri-gate process manufacturing scheme.

[0010] Figures 5A-5D Cross-sectional views are shown of important process operations in a self-aligned gate end cap process fabrication scheme for FinFET or tri-gate devices according to an embodiment of the present disclosure.

[0011] Figures 6A-6F Cross-sectional views representing various operations in a method of fabricating a self-aligned gate end cap (SAGE) structure with an improved cap, in accordance with an embodiment of the present disclosure are illustrated.

[0012] Fig. 7A Shown are cross-sectional views through a channel region of an integrated circuit structure without an etched SAGE wall cap (left hand side) and with a partially etched SAGE wall cap (right hand side) in accordance with an embodiment of the present disclosure.

[0013] Figure 7B Shown are cross-sectional views through the channel region of an integrated circuit structure without an etched SAGE wall cap (left hand side) and an integrated circuit structure with a fully etched SAGE wall cap (right hand side) according to an embodiment of the present disclosure.

[0014] Figure 7C Shown are cross-sectional views through a channel region of an integrated circuit structure without an etched SAGE wall cap (left hand side) and an integrated circuit structure with a combination of partially and fully etched SAGE wall caps (right hand side) according to an embodiment of the present disclosure.

[0015] Fig.7D Cross-sectional views through a source or drain region of an integrated circuit structure without an etched SAGE wall cap (left hand side) and with a partially etched SAGE wall cap (right hand side) are shown in accordance with an embodiment of the present disclosure.

[0016] Fig. 8A A cross-sectional view of a non-planar semiconductor device having a multiple self-aligned gate end cap isolation structure architecture according to an embodiment of the present disclosure is shown.

[0017] Figure 8B The embodiment according to the present disclosure is shown along Fig. 8AA plan view of a semiconductor device taken along the a-a' axis.

[0018] Figures 9A-9C A cross-sectional view illustrating important process operations in another self-aligned gate end cap process fabrication scheme for FinFET or tri-gate devices according to an embodiment of the present disclosure is shown.

[0019] Fig.10 A computing device according to one implementation of an embodiment of the present disclosure is shown.

[0020] Fig.11 An interposer including one or more embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0021] A self-aligned gate end cap (SAGE) architecture with an improved cover and a method of manufacturing a self-aligned gate end cap (SAGE) architecture with an improved cover are described. In the following description, many specific details, such as specific integration and material systems, are set forth in order to provide a thorough understanding of the embodiments of the present disclosure. It will be apparent to those skilled in the art that these embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features such as integrated circuit design layouts are not described in detail so as not to unnecessarily obscure the embodiments of the present disclosure. In addition, it should be understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.

[0022] Certain terms may also be used in the following description for reference purposes only and are therefore not intended to be limiting. For example, terms such as "upper," "lower," "above," and "below" refer to directions in the drawings to which reference is made. Terms such as "front," "rear," "back," and "side" describe the orientation and / or position of portions of a component within a consistent but arbitrary reference system, which is made clear by reference to the text and associated drawings describing the component in question. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar meaning.

[0023] Embodiments described herein may relate to front-end-of-line (FEOL) semiconductor processing and structures. FEOL is the first part of integrated circuit (IC) fabrication where individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in a semiconductor substrate or layer. FEOL typically covers everything up to (but not including) the deposition of metal interconnect layers. After the last FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any wires).

[0024] Embodiments described herein may relate to back-end-of-line (BEOL) semiconductor processing and structures. BEOL is the second part of IC manufacturing where individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with wiring (e.g., one or more metallization layers) on the wafer. BEOL includes contacts, insulating layers (dielectrics), metal layers, and bonding locations for chip-to-package connections. In the BEOL portion of the manufacturing stage, contacts (pads), interconnects, vias, and dielectric structures are formed. For modern IC processes, more than 10 metal layers may be added in the BEOL.

[0025] The embodiments described below may be applied to FEOL processing and structures, BEOL processing and structures, or both FEOL and BEOL processing and structures. In particular, although exemplary processing schemes are illustrated using FEOL processing cases, such methods may also be applied to BEOL processing. Likewise, although exemplary processing schemes are illustrated using BEOL processing cases, such methods may also be applied to FEOL processing.

[0026] One or more embodiments of the present disclosure relate to semiconductor structures or devices having one or more gate end cap structures. In addition, a method for fabricating a gate end cap isolation structure in a self-aligned manner is described. In one or more embodiments, a monoclinic doped hafnium oxide (HfO 2 ) as an etch-resistant protection layer to achieve self-aligned gate end cap (SAGE) cap improvements. Embodiments described herein can address issues associated with scaling diffusion end-to-end spacing in ultra-scaling process technologies.

[0027] To provide a broad background, prior art approaches rely on lithographic scaling of gate end-to-end (poly cut) to define the minimum technical gate overlap of the diffusion. The minimum technical gate overlap of the diffusion is a key component in the diffusion end-to-end spacing. The associated gate line (poly cut) process is typically limited by lithography, registration, and etch bias considerations, and ultimately sets the minimum diffusion end-to-end distance. Other approaches such as contact on active gate (COAG) architectures have been aimed at improving this diffusion spacing capability. However, improvements in this technology area are still highly sought after.

[0028] To provide a basis for highlighting the advantages of embodiments of the present disclosure, it is first understood that the advantages of the self-aligned gate end cap (SAGE) architecture over non-SAGE approaches can include achieving higher layout density, and in particular diffusion to diffusion spacing scaling. As an example, Figure 1 Plan views of adjacent integrated circuit structures for a conventional architecture with relatively wide spacing (left hand side (a)) and adjacent integrated circuit structures for a SAGE architecture with relatively tight spacing (right hand side (b)) are shown in accordance with an embodiment of the present disclosure.

[0029] refer to Figure 1 On the left hand side (a) of FIG. 1 , the layout 100 includes a first integrated circuit structure 102 and a second integrated circuit structure 104 based on semiconductor fins 106 and 108, respectively. Each device 102 and 104 has a gate electrode 110 or 112, respectively. In addition, each device 102 and 104 has a trench contact (TCN) 114 or 116, respectively, at the source and drain regions of the fins 106 and 108, respectively. Gate vias 118 and 120 and trench contact vias 119 and 121 are also shown.

[0030] Reference again Figure 1 On the left hand side (a), gate electrodes 110 and 112 have relatively wide end cap regions 122, which are respectively located outside the corresponding fins 106 and 108. TCNs 114 and 116 each have a relatively large end-to-end spacing 124, which are also respectively located outside the corresponding fins 106 and 108.

[0031] In contrast, reference Figure 1 On the right-hand side (b) of FIG. 1 , layout 150 includes a first integrated circuit structure 152 and a second integrated circuit structure 154 based on semiconductor fins 156 and 158, respectively. Each device 152 and 154 has a gate electrode 160 or 162, respectively. In addition, each device 152 and 154 has a trench contact (TCN) 164 or 166, respectively, at the source and drain regions of the fins 156 and 158, respectively. Gate vias 168 and 170 and trench contact vias 169 and 171 are also shown.

[0032] Reference again Figure 1 On the right-hand side (b), gate electrodes 160 and 162 have relatively tight end cap regions that are located outside corresponding fins 156 and 158, respectively. TCNs 164 and 166 each have relatively tight end-to-end spacing 174 that are also located outside corresponding fins 156 and 158, respectively.

[0033] To provide further context, scaling of the gate endcap and trench contact (TCN) endcap areas are important contributors to improving transistor layout area and density. The gate and TCN endcap areas refer to the gate and TCN overlap of the diffusion region / fin of a semiconductor device. As an example, Figure 2 A plan view of a conventional layout 200 including a fin-based semiconductor device accommodating end-to-end spacing is shown.

[0034] refer to Figure 2, the first semiconductor device 202 and the second semiconductor device 204 are based on semiconductor fins 206 and 208, respectively. Each device 202 and 204 has a gate electrode 210 or 212, respectively. In addition, each device 202 and 204 has a trench contact (TCN) 214 or 216, respectively, at the source and drain regions of the fins 206 and 208, respectively. The gate electrodes 210 and 212 and the TCNs 214 and 216 each have an end cap region, which is located outside the corresponding fins 206 and 208, respectively.

[0035] Reference again Figure 2 , typically, the gate and TCN end cap dimensions must include a margin for mask registration errors to ensure robust transistor operation for the worst case mask misregistration, leaving an end-to-end spacing of 218. Therefore, another important design rule that is critical to improving transistor layout density is the spacing between two adjacent end caps facing each other. However, the parameter of "2*end cap + end-to-end spacing" is becoming increasingly difficult to scale using photolithography patterning to meet the scaling requirements of new technologies. In particular, due to the longer overlap length between the TCN and the gate electrode, the additional end cap length required to allow for mask registration errors also increases the gate capacitance value, thereby increasing product dynamic energy consumption and reducing performance. Previous solutions have focused on improving the registration budget and patterning or resolution improvements to achieve reductions in both end cap size and end cap to end cap spacing.

[0036] According to embodiments of the present disclosure, methods are described for providing self-aligned gate end caps and TCN overlap of semiconductor fins without the need to allow mask registration. In one such embodiment, a disposable spacer is fabricated on the semiconductor fin sidewalls that determines the gate end cap and contact overlap dimensions. The spacer-defined end cap process enables the gate and TCN end cap regions to be self-aligned with the semiconductor fin, and therefore no additional end cap length is required to account for mask misregistration. In addition, the methods described herein do not necessarily require lithographic patterning at previously required stages because the gate and TCN end cap / overlap dimensions remain fixed, resulting in improved (i.e., reduced) device-to-device variability of electrical parameters.

[0037] According to one or more embodiments of the present disclosure, scaling is achieved by reducing the overlap of the gate end cap with the diffusion by constructing the SAGE wall. As an example, Figure 3 Shown are cross-sectional views taken through a fin for a conventional architecture (left hand side (a)) and a self-aligned gate end cap (SAGE) architecture (right hand side (b)) according to an embodiment of the present disclosure.

[0038] refer to Figure 3On the left hand side (a) of FIG. 3 , the integrated circuit structure 300 includes a substrate 302 having a fin 304 protruding therefrom. The height (H Si ) 306 is defined by an isolation structure 308 that laterally surrounds a lower portion of the fin 304. A gate structure may be formed over the integrated circuit structure 300 to fabricate a device. However, the disconnection in this gate structure is accommodated by increasing the spacing between the fins 304.

[0039] In contrast, reference Figure 3 On the right-hand side (b) of FIG. 3 , the integrated circuit structure 350 includes a substrate 352 having a fin 354 protruding therefrom. The height (H Si ) 356 is set by an isolation structure 358 that laterally surrounds the lower portion of the fin 354. An isolation SAGE wall 360 (which may include a hard mask, as shown) is included within the isolation structure 358 and between adjacent fins 354. The distance between the isolation SAGE wall 360 and the nearest fin 354 defines a gate end cap spacing 362. A gate structure can be formed above the integrated circuit structure 350 and between the isolation SAGE walls 360 to manufacture a device. The disconnection in this gate structure is imposed by the isolation SAGE wall 360. Since the isolation SAGE wall 360 is self-aligned, it is possible to minimize restrictions from conventional methods to achieve more aggressive diffusion to diffusion spacing. In addition, since the gate structure includes disconnections at all locations, the various gate structure portions can be layered by local interconnects formed above the isolation SAGE wall 360.

[0040] To provide a side-by-side comparison, Figures 4A-4D A cross-sectional view showing important process operations in a conventional FinFET or tri-gate process manufacturing scheme is shown. Figures 5A-5D Cross-sectional views are shown of important process operations in a self-aligned gate end cap process fabrication scheme for FinFET or tri-gate devices according to an embodiment of the present disclosure.

[0041] refer to Figure 4A and Figure 5A , a bulk semiconductor substrate 400 or 500, such as a bulk single crystal silicon substrate, is provided having fins 402 or 502 etched therein, respectively. In an embodiment, the fins are formed directly in the bulk substrate 400 or 500 and are thus formed continuously with the bulk substrate 400 or 500. It should be understood that within the substrate 400 or 500, shallow trench isolation structures may be formed between the fins. Figure 5A, after patterning to form the fin 502, a hard mask layer 504 (such as a silicon nitride hard mask layer) and a pad oxide layer 506 (such as a silicon dioxide layer) remain on top of the fin 502. In contrast, referring to Figure 4A , such that the hard mask layer and pad oxide layer have been removed.

[0042] refer to Figure 4B , a dummy or permanent gate dielectric layer 410 is formed on the exposed surface of the semiconductor fin 402, and a dummy gate layer 412 is formed over the resulting structure. Figure 5B , a dummy or permanent gate dielectric layer 510 is formed on the exposed surface of the semiconductor fin 502 , and dummy spacers 512 are formed adjacent to the resulting structure.

[0043] refer to Figure 4C , gate end cap cut patterning is performed, and isolation region 414 is formed at the resulting patterned dummy gate end 416. In conventional process schemes, a larger gate end cap must be fabricated to allow for gate mask misalignment, as shown by arrow region 418. In contrast, referring to Figure 5C , by depositing and planarizing the Figure 5B An isolation layer is provided on the structure to form a self-aligned isolation region 514. In one such embodiment, Figure 4C and Figure 5C Compared with the conventional gate end cap process, the self-aligned gate end cap process does not require additional space for mask alignment.

[0044] refer to Figure 4D , using permanent gate electrode replacement Figure 4C 414. In the case of using a dummy gate dielectric layer, such a dummy gate dielectric layer may also be replaced by a permanent gate dielectric layer in the process. In the specific example shown, a dual metal gate replacement process is performed to provide an N-type gate electrode 420 above the first semiconductor fin 402A and a P-type gate electrode 422 above the second semiconductor fin 402B. The N-type gate electrode 420 and the P-type gate electrode 422 are formed between the isolation region 414, but a P / N junction 424 is formed where they meet. The exact location of the P / N junction 424 may vary depending on the misalignment, as shown by the arrow area 426.

[0045] In contrast, reference Figure 5D , remove the hard mask layer 504 and the pad oxide layer 506, and replace it with a permanent gate electrode Figure 5Cdummy spacers 512 are provided. Where a dummy gate dielectric layer is used, such a dummy gate dielectric layer may also be replaced by a permanent gate dielectric layer in the process. In the specific example shown, a dual metal gate replacement process is performed to provide an N-type gate electrode 520 over the first semiconductor fin 502A and a P-type gate electrode 522 over the second semiconductor fin 502B. The N-type gate electrode 520 and the P-type gate electrode 522 are formed between and are also separated by the gate end cap isolation structure 514.

[0046] Reference again Figure 4D , a local interconnect 440 may be fabricated to contact the N-type gate electrode 420 and the P-type gate electrode 422 to provide a conductive path around the P / N junction 424. Figure 5D , a local interconnect 540 may be fabricated to contact the N-type gate electrode 520 and the P-type gate electrode 522 to provide a conductive path over the intervening isolation structure 514 therebetween. Figure 4D and Figure 5D Both, hard mask 442 or 542 can be formed on local interconnect 440 or 540, respectively. Figure 5D In an embodiment, the continuity of the local interconnect 540 is interrupted by a dielectric plug 550 in case electrical contact disconnection along the gate line is required.

[0047] According to one or more embodiments of the present disclosure, a self-aligned gate end cap (SAGE) processing scheme involves forming a gate / trench contact end cap that is self-aligned with the fin without requiring additional length to account for mask misalignment. Therefore, embodiments can be implemented to enable a reduction in transistor layout area. Embodiments described herein may relate to the manufacture of a gate end cap isolation structure, which may also be referred to as a gate wall, an isolation gate wall, or a self-aligned gate end cap (SAGE) wall.

[0048] On the other hand, monoclinic doped hafnium oxide (HfO 2 ) is used as an anti-etching protection layer for the manufacture of gate end cap structure.

[0049] The methods described herein may require the formation of isolated self-aligned plugs also referred to as "SAGE walls." The SAGE wall architecture may enable continued shrinking of transistor dimensions for future process nodes. In order to make the SAGE architecture feasible, the walls may need to be protected with a capping material that not only protects the underlying film stack from downstream processing, but also provides the electrical isolation required to produce functional circuits by separating the fins and gates when necessary. Two possible challenges associated with SAGE caps can involve challenges associated with the film deposition process itself and challenges associated with the inherent properties of the material. By using HfO grown via thermal atomic layer deposition (ALD), the SAGE cap can be used to generate an isolated self-aligned plug.2 As a covering material, these challenges are largely (although not completely) overcome.

[0050] Atomic layer deposition (ALD) is a process that provides highly uniform film growth, thereby providing the best chance of successfully filling high aspect ratio trenches present on the wafer surface during cap deposition. Because ALD films are conformal, films grown by ALD are less likely to leave voids at the bottom of the trenches, or poorly joined seams where the walls grow together. Such voids or seams may act as paths for short circuits to form further downstream, so preventing their formation is critical. The material itself may need to be able to withstand the extensive chemical etching, process chemicals, and thermal treatments that are exposed to post-wafer SAGE wall formation. Additionally, the material may need to be electrically insulating. Crystalline HfO 2 It is both chemically inert and electrically insulating (high dielectric constant, wide bandgap), which in one embodiment makes it an ideal material for this application.

[0051] To provide context, as a specific embodiment, approximately 34 nm of HfO 2 The film is mostly amorphous with small crystalline domains dispersed throughout the film. To increase its etch resistance and structural stability for downstream processing, the amorphous HfO 2 The film may need to be crystallized. One way to achieve this (while minimizing the burden on other existing features) is to subject the film to thermal annealing. However, in doing so, the resulting HfO 2 The film consists of a mixture of crystalline phases (eg, a mixture of 57% monoclinic, 43% orthorhombic and tetragonal) with a prominent interface where two large mismatched domains meet.

[0052] The resulting grain boundaries can be etched more easily than the individual domains themselves, and open to form channels when exposed to dilute hydrofluoric acid. If these channels are exposed to the surface when depositing a conductive material (e.g., a metal gate), the material can penetrate the SAGE cap, forming a short circuit through the grain. Such defects can have a density of about 10E3-10E4 and are detected as short circuits at the end of the line. This mode can be eliminated by inhibiting the formation of grain boundaries between mismatched domains within the film. Control of the size and morphology of these grain boundaries can be achieved to provide unprecedented control over the defect / electrical properties of the resulting SAGE wall and its reliability.

[0053] According to one or more embodiments of the present disclosure, by adding HfO 2 The introduction of low levels of tantalum Ta (e.g., 0.5-3.0 atomic % Ta relative to the total Ta, Hf, and O) into the film can manipulate the HfO 2Through this manipulation, the main short-circuiting mode observed in the SAGE architecture can be successfully eliminated.

[0054] To provide further context, in prior art processes, HfO 2 Large grain boundaries form in the film. These grain boundaries are more easily etched, which increases the space between the grain boundaries. These spaces may then be filled with other materials (including metallic materials), causing the resulting transistor to short-circuit. In contrast, it is possible to implement the incorporation of Ta into HfO 2 As an exemplary process to demonstrate the latter process, Figures 6A-6F Cross-sectional views representing various operations in a method of fabricating a self-aligned gate end cap (SAGE) structure with an improved cap, in accordance with an embodiment of the present disclosure are illustrated.

[0055] refer to Fig. 6A , the starting structure 600 includes a plurality of fins 604 on a substrate 602. Each fin 604 includes a semiconductor fin portion 606, a dielectric cap 608, and a hard mask 610. A gate end cap structure 612 is between and on either side of the groupings of fins 604 (such as a pair of fins 604). The gate end cap structure 612 includes a lower dielectric constant portion 614 and a higher dielectric constant portion 616. The higher dielectric constant portion 616 may include a hafnium oxide material having a tantalum dopant 617 throughout. An insulating layer 618 may separate the fins 604 and the gate end cap structure 612. The end cap structure 612 may include a liner 619, such as a silicon nitride liner.

[0056] refer to Figure 6B , Fig. 6A The starting structure 600 is annealed to provide an end cap structure 612A having a higher dielectric constant portion 620. In one embodiment, as a result of the annealing process, the higher dielectric constant portion 620 includes hafnium and oxygen and tantalum and has a monoclinic crystallinity of 70% or greater. In a specific embodiment, the total atomic concentration of tantalum is 0.5-3% of the total atomic composition of the film (e.g., total Ta, Hf, and O atoms). In one embodiment, the higher k dielectric constant portion 620 consists essentially of tantalum-doped hafnium oxide (Ta-HfO) having a monoclinic crystallinity of 75% or greater. 2 )composition.

[0057] refer to Figure 6C, the insulating layer 618 is recessed to form a recessed insulating layer 618A. During the recessing, the hard mask layer 610 can be removed from the fin 604 to form the fin 604A, as shown. Moreover, the liner 619 can be eroded to form a recessed liner 619A of the modified end cap structure 612B, as shown.

[0058] refer to Fig.6D , implantation and oxidation processes are performed to form an oxide layer 622 .

[0059] refer to Fig. 6E , removing oxide layer 622. As shown, removing oxide layer 622 can leave fin 604B including semiconductor portion 606A with a thinner upper portion. As shown, reduced dielectric cap 608A can remain on semiconductor portion 606A. Also, as shown, recessed liner 619A of modified end cap structure 612B can be further eroded to form further recessed liner 619B of modified end cap structure 612C.

[0060] refer to Fig. 6F , the gate structure 624 is formed on Fig. 6E In one embodiment, the gate structure 624 includes a gate dielectric and a gate electrode, wherein the gate electrode includes a metal. In one such embodiment, the metal does not penetrate the higher dielectric constant portion 620 of the modified end cap structure 612B.

[0061] Reference again Fig. 6F , according to one or more embodiments of the present disclosure, the integrated circuit structure 650 includes a first gate structure (left 624) on the first semiconductor fin 604B. The second gate structure (right 624) is on the second semiconductor fin 604B. The gate end cap isolation structure (center 612B) is between the first gate structure (left 624) and the second gate structure (right 624). The gate end cap isolation structure (center 612B) has a higher k dielectric constant portion 620 on the lower k dielectric wall 614.

[0062] In an embodiment, the higher-k dielectric constant portion 620 includes hafnium and oxygen and has a monoclinic crystallinity of 70% or greater. In one embodiment, the higher-k dielectric constant portion 620 layer also includes tantalum. In a specific such embodiment, the tantalum has a total atomic concentration of 0.5-3% of the total atomic composition of the film (e.g., total Ta, Hf, and O atoms). In one embodiment, the higher-k dielectric constant portion 620 consists essentially of tantalum-doped hafnium oxide (Ta-HfO) having a monoclinic crystallinity of 70% or greater. 2 )composition.

[0063] According to one or more embodiments, the embodiments disclosed herein may be implemented to overcome critical yield defect modes in the SAGE wall architecture, such as metal shorting through grain boundaries of the SAGE cap material. Embodiments may be HfO with high crystalline phase purity. 2 Reverse engineering of the final product can be achieved by a combination of: (1) phase mapping (e.g., by TEM) to determine the HfO 2 The exact morphological composition of the film, and (2) the elemental composition of the film can be quantified by SIMS or XPS (among other techniques). This combination of information can be used to infer how a uniform crystalline phase is achieved. An example can be shown to detect the transition to HfO 2 Small amounts of metal dopants are added to ALD films to modify or control their phase homogeneity.

[0064] In an embodiment, Ta-doped HfO is deposited in a thermal ALD hot-wall cross-flow reactor. 2 Films. Film growth can be achieved at wafer temperatures between 246°C and 325°C. HfO deposited at 300°C 2 It exhibits minimal film densification in post-deposition annealing (important for film adhesion and another mode of grain boundary shorting) while remaining amorphous as deposited (important for post-deposition planarization).

[0065] In an embodiment, the HfO 2 Deposition cycles were performed until a target thickness of approximately 34 nm was achieved to achieve bulk HfO 2 Each deposition cycle may include: 1. flowing a reactive HF precursor into the reactor, thereby allowing the reactants to adsorb onto the wafer, 2. 2 1. The HF precursor is oxidized by the oxidizing agent. 2. The HF precursor is oxidized by the oxidizing agent. 3. The HF precursor is oxidized by the oxidizing agent. 4. The HF precursor is oxidized by the oxidizing agent. 2 Gas flows into the reactor to purge excess oxidant and reaction byproducts, 5. Repeat steps 1-4 until the target thickness is reached. It should be understood that in one embodiment, water may be pulsed / purged first before the first metal precursor.

[0066] In an embodiment, Ta doping can be performed by adding HfO 2 The dopant layer can be realized by interlacing the layers with the layers containing dopants. The dopant layer can be realized by:

[0067] Doping method 1 : 1. Flow the reactive Ta precursor into the reactor, thereby allowing the reactants to adsorb onto the wafer, 2. Purify N 21. The gas flows into the reactor to remove excess Ta precursor, 2. The reactive oxidizing precursor flows into the reactor to cause a reaction between the Ta precursor and the oxidant, 3. The purified N 2 Gas flows into the reactor to purge excess oxidant and reaction byproducts. 5. Steps 1-4 are repeated until the target thickness is reached.

[0068] Doping method 2 : 1. Flow the reactive Ta precursor into the reactor, thereby allowing the reactants to adsorb onto the wafer, 2. Purify N 2 1. Flow a reactive HF precursor into the reactor to allow the reactant to adsorb to any surface sites not occupied by the Ta precursor. 2. Flow a purified N 2 5. a reactive oxidizing precursor is flowed into the reactor to cause a reaction between the Hf precursor and the Ta precursor and the oxidant, 6. a purified N 2 Gas flows into the reactor to remove excess oxidant and reaction by-products. 7. Repeat operations 1-6 until the target thickness is reached.

[0069] Doping method 3 : 1. Flow the reactive HF precursor into the reactor, thereby allowing the reactants to adsorb onto the wafer, 2. 2 1. Flow a reactive Ta precursor into the reactor to allow the reactant to adsorb onto any surface sites not occupied by the Ta precursor. 2. Flow a purified N 2 5. a reactive oxidizing precursor is flowed into the reactor to cause a reaction between the Hf precursor and the Ta precursor and the oxidant, 6. a purified N 2 Gas flows into the reactor to remove excess oxidant and reaction by-products. 7. Repeat operations 1-6 until the target thickness is reached.

[0070] In the embodiment, as a control example, pure HfO 2 and Ta x Hf 1-x O 2 Both membranes are made by making them 2 The total concentration of Ta in the film was determined by changing the HfO 2 ratio of dopant deposition cycles (e.g., 4:1 HfO2:TaHfO x ) and is used to manipulate HfO 2Phase purity of the film. Films composed of a higher percentage of monoclinic phase tend to have a lower defect density relative to orthorhombic or tetragonal crystalline phases. When the monoclinic percentage (% monoclinic) is equal to or higher than 70% monoclinic (70% monoclinic), the defect mode is nearly eliminated. Without being bound by theory, the inventors believe that by controlling nucleation by doping Ta into the film, the possibility of forming unfavorable adjacent grain boundaries through which shorts can be formed inline is reduced. In another embodiment, crystallization can be achieved by a slower ramp / soak annealing process.

[0071] In another aspect, a SAGE cap reduction, such as a high-k cap etch, is performed to reduce or remove the SAGE wall cap.

[0072] It will be appreciated that the SAGE wall may need to withstand many different process sequences. To minimize variations, a very durable material may be required at least as a cap for the SAGE wall, such as the monoclinic doped hafnium oxide (HfO) described above. 2 ) cap. This material may be essential for process controllability. However, high-k materials and the associated high gate metal layers may add significant cost to the capacitance budget associated with active power. It is likely that any high-k material surrounding the channel and gate contributes to the total capacitance. Therefore, it is important to minimize the high-k component in the SAGE wall, which can be challenging to balance.

[0073] In previous approaches, the lower portion of the SAGE wall is replaced with a lower-k material. However, the high-k cap on top is still a critical portion that contributes to the capacitance near the device. According to one or more embodiments of the present disclosure, after the gate and trench contact (TCN) metal are formed, the unnecessary or excess high-k portion of the SAGE structure is reduced or removed. A HiK etch process that is selective to Si, SiGe, oxides, nitrides, and metals can be used to reduce or remove the high-k (HiK) portion.

[0074] Advantages of implementing one or more embodiments described herein may include reduced capacitance while maintaining the advantages of cell height scaling using SAGE, thereby achieving optimal PPA (power, performance, and area). It should be understood that the etching HiK in the post-SAGE metal gate (MG) process or the trench contact (TCN) process can be detected by XSEM and / or TEM. In an embodiment, in the channel position, the etching or reduction or removal of the HiK portion of the SAGE structure is performed after the metal gate process is completed. Similarly, in the source or drain position, the etching or reduction or removal of the HiK portion of the SAGE structure is performed after the TCN metal process. The etching process can be selective to the metal gate portion and / or the trench contact portion.

[0075] In the first example, Fig. 7A Shown are cross-sectional views through a channel region of an integrated circuit structure without an etched SAGE wall cap (left hand side) and with a partially etched SAGE wall cap (right hand side) in accordance with an embodiment of the present disclosure.

[0076] refer to Fig. 7A On the left hand side, the integrated circuit structure 700 without the etched SAGE wall cap includes a substrate 702 having a fin 704 thereon or above. The lower portion of the fin 704 is surrounded by a shallow trench isolation structure 706, and the upper portion of the fin 704 protrudes above the shallow trench isolation structure 706. A gate stack 708 is above the corresponding one or more fins 704, such as above the corresponding pair of fins 704. Each gate stack 708 may include a gate dielectric (such as a high-k gate dielectric) and a metal gate electrode having an exposed top surface. SAGE walls 710 are on the sides of the gate stack 708 and between the gate stacks 708. Each SAGE wall 710 has a higher-k dielectric cap layer 714 on the lower-k dielectric wall 712. The higher-k dielectric cap layer 714 may be a combination of the above-described Figures 6A-6F 7. The high-k cap described. The higher-k dielectric cap layer 714 has an uppermost surface 715 and a lowermost surface 713. A local conductive interconnect 716 electrically couples the exposed top surfaces of the metal gate electrodes of the adjacent gate stacks 708 and extends over the intervening SAGE wall (intermediate 710). The local conductive interconnect 716 has an uppermost surface 719 and a lowermost surface 717. The lowermost surface 717 of the local conductive interconnect 716 is below the uppermost surface 715 of the higher-k dielectric cap layer 714 of the SAGE wall 710.

[0077] refer to Fig. 7A On the right hand side, an integrated circuit structure 720 with a partially etched SAGE wall cap includes a substrate 702 having a fin 704 thereon or above. A lower portion of the fin 704 is surrounded by a shallow trench isolation structure 706, and an upper portion of the fin 704 protrudes above the shallow trench isolation structure 706. A gate stack 708 is above the corresponding one or more fins 704, such as above a corresponding pair of fins 704. Each gate stack 708 may include a gate dielectric (such as a high-k gate dielectric) and a metal gate electrode having an exposed top surface. SAGE walls 722 are on the sides of the gate stack 708 and between the gate stacks 708. Each SAGE wall 722 has a higher-k dielectric cap layer 724 on the lower-k dielectric wall 712. The higher-k dielectric cap layer 724 may be a dielectric such as a dielectric layer in combination with the dielectric layer described above. Figures 6A-6F724 has an uppermost surface 725. A local conductive interconnect 726 electrically couples the exposed top surfaces of the metal gate electrodes of the adjacent gate stacks 708 and extends above the intervening SAGE wall (intermediate 722). The local conductive interconnect 726 has a lowermost surface 727. The lowermost surface 727 of the local conductive interconnect 726 is above the uppermost surface 725 of the higher k dielectric cap layer 724 of the SAGE wall 722. In one embodiment, as shown, the lowermost surface 727 of the local conductive interconnect 726 is planar for the entire local conductive interconnect 726.

[0078] Reference again Fig. 7A On the right hand side, according to an embodiment of the present disclosure, the integrated circuit structure 720 includes a first gate electrode (left 708) on a first semiconductor fin (one of the left fin 704 pair). A second gate electrode (right 708) is on a second semiconductor fin (one of the right fin 704 pair). A gate end cap isolation structure (middle 722) is between the first gate electrode (left 708) and the second gate electrode (right 708). The gate end cap isolation structure 722 has a higher-k dielectric cap layer 724 on a lower-k dielectric wall 712. A local interconnect 726 is on the first gate electrode (left 708), on the higher-k dielectric cap layer (middle 724), and on the second gate electrode (right 708). The local interconnect 726 has a bottommost surface 727 above the uppermost surface 725 of the higher-k dielectric cap layer (middle 724).

[0079] In one embodiment, the first gate electrode (left 708) and the second gate electrode (right 708) each have an uppermost surface that is coplanar with an uppermost surface 725 of a higher-k dielectric cap layer (middle 724) of a gate end cap isolation structure (middle 722). In one embodiment, a local interconnect 726 electrically connects the first gate electrode (left 708) and the second gate electrode (right 708). In one embodiment, the gate end cap isolation structure (middle 722) includes a vertical seam centered within a lower-k dielectric wall 712, for example, as described below in conjunction with Fig. 9C described.

[0080] In the second example, Figure 7B Shown are cross-sectional views through the channel region of an integrated circuit structure without an etched SAGE wall cap (left hand side) and an integrated circuit structure with a fully etched SAGE wall cap (right hand side) according to an embodiment of the present disclosure.

[0081] refer to Figure 7B On the left hand side, the integrated circuit structure 700 without the etched SAGE wall cover is as described above in conjunction with Fig. 7A Reference Figure 7BOn the right hand side of the , an integrated circuit structure 730 with a completely etched / removed SAGE wall cap includes a substrate 702 having a fin 704 thereon or above. The lower portion of the fin 704 is surrounded by a shallow trench isolation structure 706, and the upper portion of the fin 704 protrudes above the shallow trench isolation structure 706. A gate stack 708 is above the corresponding one or more fins 704, such as above the corresponding fin 704 pair. Each gate stack 708 may include a gate dielectric (such as a high-k gate dielectric) and a metal gate electrode having an exposed top surface. SAGE walls 732 are on the sides of the gate stack 708 and between the gate stacks 708. Each SAGE wall 732 includes only a lower-k dielectric wall 734. A local conductive interconnect 736 electrically couples the exposed top surfaces of the metal gate electrodes of adjacent gate stacks 708 and extends above the intermediate SAGE wall (middle 732). In one embodiment, as shown, the lowermost surface of the local conductive interconnect is planar for the entire local conductive interconnect 736 .

[0082] In the third example, Figure 7C Shown are cross-sectional views through a channel region of an integrated circuit structure without an etched SAGE wall cap (left hand side) and an integrated circuit structure with a combination of partially and fully etched SAGE wall caps (right hand side) according to an embodiment of the present disclosure.

[0083] refer to Figure 7C On the left hand side, the integrated circuit structure 700 without the etched SAGE wall cover is as described above in conjunction with Fig. 7A Reference Figure 7C On the right hand side, an integrated circuit structure 740 with partially etched and fully etched SAGE wall caps includes a substrate 702 having a fin 704 thereon or above. A lower portion of the fin 704 is surrounded by a shallow trench isolation structure 706, and an upper portion of the fin 704 protrudes above the shallow trench isolation structure 706. A gate stack 708 is above the corresponding one or more fins 704, such as above a corresponding pair of fins 704. Each gate stack 708 may include a gate dielectric (such as a high-k gate dielectric) and a metal gate electrode having an exposed top surface. SAGE walls 742A are on the sides of the gate stack 708, and SAGE walls 742B are between the gate stacks 708. Each SAGE wall 742A has a higher-k dielectric cap layer 744 on the lower-k dielectric wall. The higher-k dielectric cap layer 744 may be a combination of the above-described SAGE walls. Figures 6A-6F742A. The higher k dielectric cap layer 744 has an uppermost surface 745 and a lowermost surface 743. The SAGE wall 742B has only a lower k dielectric wall 746. The local conductive interconnect 748 electrically couples the exposed top surfaces of the metal gate electrodes of the adjacent gate stacks 708 and extends above the intervening SAGE wall 742B. The local conductive interconnect 748 has a lowermost surface 742 and an uppermost surface 749. The lowermost surface 742 of the local conductive interconnect 748 is coplanar with the lowermost surface 743 of the higher k dielectric cap layer 744. The uppermost surface 749 of the local conductive interconnect 748 is above the uppermost surface 745 of the higher k dielectric cap layer 744 of the SAGE wall 742A. In one embodiment, as shown, the lowermost surface 742 of the local conductive interconnect 748 is planar for the entire local conductive interconnect 748.

[0084] Fig.7D Cross-sectional views through a source or drain region of an integrated circuit structure without an etched SAGE wall cap (left hand side) and with a partially etched SAGE wall cap (right hand side) are shown in accordance with an embodiment of the present disclosure.

[0085] refer to Fig.7D On the left hand side, the integrated circuit structure 750 without the etched SAGE wall cap includes a substrate 702 having a fin 704 thereon or above. The lower portion of the fin 704 is surrounded by a shallow trench isolation structure 706, and the upper portion of the fin 704 protrudes above the shallow trench isolation structure 706. Conductive trench contacts 756 are above the epitaxial source or drain structures 752 / 754 above the corresponding one or more fins 704 (such as above the corresponding pair of fins 704). The epitaxial source or drain structures 752 and 754 can have opposite conductivities. SAGE walls 710 are on the sides of the conductive trench contacts 756 and between the conductive trench contacts 756. Each SAGE wall 710 has a higher k dielectric cap layer 714 on the lower k dielectric wall 712. The higher k dielectric cap layer 714 can be such as a combination of the above-mentioned. Figures 6A-6F The local conductive interconnect 758 electrically couples the exposed top surfaces of adjacent conductive trench contacts 756 and extends over the intervening SAGE wall (intermediate 710). The local conductive interconnect 758 has a lowermost surface below the uppermost surface of the higher-k dielectric cap layer 714 of the SAGE wall 710.

[0086] refer to Fig.7DOn the right hand side, an integrated circuit structure 760 with a partially etched SAGE wall cap includes a substrate 702 having a fin 704 thereon or above. A lower portion of the fin 704 is surrounded by a shallow trench isolation structure 706, and an upper portion of the fin 704 protrudes above the shallow trench isolation structure 706. Conductive trench contacts 756 (which may be included in a dielectric 757) are above the epitaxial source or drain structures 752 / 754 above the corresponding one or more fins 704 (such as above the corresponding pair of fins 704). The epitaxial source or drain structures 752 and 754 may have opposite conductivities. SAGE walls 722 are on the sides of the conductive trench contacts 756 and between the conductive trench contacts 756. Each SAGE wall 722 has a higher k dielectric cap layer 724 on the lower k dielectric wall 712. The higher k dielectric cap layer 724 may be a dielectric such as a dielectric cap layer 724 in combination with the dielectric cap layer 724 as described above. Figures 6A-6F The high-k cap described. The higher-k dielectric cap layer 724 has an uppermost surface 725. A local conductive interconnect 762 electrically couples the exposed top surfaces of adjacent conductive trench contacts 756 and extends above the intervening SAGE wall (intermediate 722). The local conductive interconnect 762 has a lowermost surface 761 and an uppermost surface 763. The lowermost surface 761 of the local conductive interconnect 762 is above the uppermost surface 725 of the higher-k dielectric cap layer 724 of the SAGE wall 722. In one embodiment, as shown, the lowermost surface 761 of the local conductive interconnect 762 is planar for the entire local conductive interconnect 762.

[0087] Reference again Fig.7D On the right hand side, according to an embodiment of the present disclosure, the integrated circuit structure 760 includes a first trench contact (left 756) on the first epitaxial structure 752 on the first semiconductor fin (one of the fins 704 of the left fin pair). The second trench contact (right 756) is on the second epitaxial structure 754 on the second semiconductor fin (one of the fins 704 of the right fin pair). The gate end cap isolation structure (middle 722) is between the first trench contact (left 756) and the second trench contact (right 756). The gate end cap isolation structure (middle 722) has a higher k dielectric cap layer 724 on the lower k dielectric wall 712. The local interconnect 756 is on the first trench contact (left 756), on the higher k dielectric cap layer 724, and on the second trench contact (right 756). The local interconnect 762 has a lowermost surface 761 above the uppermost surface 725 of the higher k dielectric cap layer 724.

[0088] In one embodiment, the first trench contact (left 756) and the second trench contact (right 756) each have an uppermost surface that is coplanar with the uppermost surface 725 of the higher-k dielectric cap layer 724 of the gate end cap isolation structure (center 722). In one embodiment, a local interconnect 762 electrically connects the first trench contact (left 756) and the second trench contact (right 756). In one embodiment, the gate end cap isolation structure (center 722) includes a vertical seam centered within the lower-k dielectric wall 712, for example, as described below in conjunction with Fig. 9C described.

[0089] On the other hand, the SAGE walls can vary in width, position, and function relative to different devices. In an exemplary embodiment, system-on-chip (SoC) process technology is typically required to support standard logic (e.g., low voltage, thin oxide) transistors and I / O (e.g., high voltage, thick oxide) transistors. The distinction between standard logic devices and high voltage (HVI / O) devices can be achieved through a multi-oxide process sequence, in which logic transistors receive thin high-performance oxides and I / O devices receive thick oxides capable of sustaining higher voltages. As process technology scales, logic devices scale dramatically in size, creating manufacturing challenges for dual oxide formation. According to one or more embodiments of the present disclosure, a high voltage end cap process is combined with an ultra-scaled FinFET transistor architecture to provide a multi-self-aligned end cap process, in which at least some (if not all) of the SAGE structures are manufactured without fin end gaps.

[0090] To provide context, as technology nodes shrink, there is an increasing lack of geometric space in narrow endcap logic devices to accommodate defect-free dual oxide processes that may be required for high voltage transistor manufacturing. Current approaches rely on a single unscaled endcap space to accommodate a single logic oxide process. However, this process may not be compatible with the highly scaled geometries that support dual oxide high voltage SOC technology because the endcap space may not be sufficient to accommodate both oxides (gate dielectrics).

[0091] According to embodiments of the present disclosure, scaling limitations imposed by the requirement to fill the high voltage gate with both high voltage oxide and logic oxide are addressed. In particular, as logic size decreases, the end cap space in the high voltage (HV) device becomes not narrow enough to fill both oxides. In an embodiment, different end cap spaces between logic transistors and high voltage transistors are fabricated separately in a SAGE architecture. The logic transistor end caps are super-scaled by using a self-aligned end cap architecture, while the high voltage transistors have wider end caps to accommodate thicker gate dielectrics. According to embodiments described herein, one or both types of end caps can be fabricated without fin end gaps.

[0092] One or more embodiments described herein relate to or may be referred to as a multi-unidirectional end cap process flow for ultra-scaled logic end caps. To provide context, in a typical SAGE process, a single end cap spacer is deposited to form a self-aligned end cap that separates the fin from the SAGE wall. The embodiments described herein may involve forming different sacrificial spacer thicknesses between the logic and HV gates. Subsequently, a self-aligned end cap wall is formed. Different spacer widths are selected to be thicker in the high voltage region, and a standard thickness is used in the logic region. Different spacer widths can enable successful deposition of high voltage oxide without sacrificing density in the logic region. In an embodiment, the thickness of the different spacers depends on the expected HV oxide thickness.

[0093] As an example of a completed device, Fig. 8A A cross-sectional view of a non-planar semiconductor device having a multiple self-aligned gate end cap isolation structure architecture according to an embodiment of the present disclosure is shown. Figure 8B The embodiment according to the present disclosure is shown along Fig. 8A A plan view of the structure taken along the a-a' axis.

[0094] refer to Fig. 8A , the semiconductor structure 800 includes a non-planar active region (e.g., a fin structure each including a protruding fin portion 804 and a sub-fin region 805) formed from a substrate 802 and within a trench isolation layer 806. In an embodiment, the fin structure is a plurality of fin lines that form a grating structure such as a closely spaced grating structure. In one such embodiment, tight spacing cannot be achieved directly by conventional photolithography. For example, a pattern based on conventional photolithography may be first formed, but the spacing may be halved by patterning using a spacer mask, as is known in the art. Further, the original spacing may be quartered by a second round of spacer mask patterning. Thus, a grating-like fin pattern may have lines spaced at a constant spacing and having a constant width. The pattern may be manufactured by halving the spacing or by quartering the spacing or by other spacing segmentation methods. Each of the individual fins 804 shown may represent a corresponding individual fin, or may represent multiple fins at a given position.

[0095] The gate structure 808 is over the protruding portion 804 of the non-planar active area and over a portion of the trench isolation layer 806. As shown, the gate structure 808 includes a gate electrode 850 and a gate dielectric layer 852. In one embodiment, although not shown, the gate structure 808 may also include a dielectric cap layer.

[0096] The gate structures 808 are separated by narrow self-aligned gate end cap (SAGE) isolation structures or walls 820, 821A, or 821B. The SAGE walls 820 each have a width. In an embodiment, the width of SAGE wall 821A is greater than the width of each SAGE wall 820, and the width of SAGE wall 821B is less than the width of each SAGE wall 820. SAGE walls of different widths can be associated with different device types, as described in the exemplary embodiments herein. It should be understood that the variation in the width of the SAGE walls can be rearranged. Moreover, in other embodiments, the widths are all the same. Each SAGE wall 820, 821A, or 821B may include one or more of a local interconnect 854 or a dielectric plug 899 formed thereon. In an embodiment, each of the SAGE walls 820, 821A, or 821B is recessed below the uppermost surface 897 of the trench isolation layer 806, as shown in FIG. Fig. 8A as shown in .

[0097] According to an embodiment of the present disclosure, SAGE wall 821A is formed in the location where the fin is cut. In a specific embodiment, as shown, SAGE wall 821A is formed over the cut portion 869 of the fin. In an embodiment, SAGE walls 820, 821A, and 821B are manufactured after the fin cutting process.

[0098] In an exemplary embodiment, the semiconductor structure 800 includes a first plurality of semiconductor fins (one or more fins 804 of region 870A) protruding above the substrate 802 and through the uppermost surface 897 of the trench isolation layer 806, and a first gate structure (gate structure 808 of region 870A) above the first plurality of semiconductor fins. A second plurality of semiconductor fins (one or more fins 804 of region 870B) protrude above the substrate 802 and through the uppermost surface 897 of the trench isolation layer 806, and a second gate structure (gate structure 808 of region 870B) is above the second plurality of semiconductor fins. A gate end cap isolation structure (left-hand SAGE wall 820) is between and in contact with the first gate structure and the second gate structure. The semiconductor fins (from region 870A) in the first plurality of semiconductor fins closest to the gate end cap isolation structure are spaced farther from the gate end cap isolation structure than the semiconductor fins (from region 870B) in the second plurality of semiconductor fins closest to the gate end cap isolation structure.

[0099] In an embodiment, region 870A is an I / O region, and region 870B is a logic region. As shown in the figure, in one such embodiment, a second logic region 870C is adjacent to logic region 870B and is electrically connected to logic region 870B by local interconnect 854. Another region 870D can be a location where additional logic or I / O regions can be placed. The embodiments described herein can relate to different intervals with SAGE walls (e.g., with the wider intervals of SAGE walls 821B and left-hand side 820 in region 870A), or can relate to SAGE walls of different widths (e.g., narrower 821B vs. 820 vs. wider 821A), or both different intervals with SAGE walls and different widths of SAGE walls. In an embodiment, the I / O region has a larger interval between SAGE walls than the logic region. In an embodiment, the SAGE walls are wider between adjacent logic regions than between adjacent I / O regions.

[0100] Also visible from this perspective are gate contact 814 and overlying gate contact via 816, as well as overlying metal interconnect 860, all of which are within an interlayer dielectric stack or layer 870. Fig. 8A It can also be seen from the perspective view that in one embodiment, the gate contact 814 is above the non-planar active area. Fig. 8A As shown, an interface 880 exists between the doping profiles of the protruding fin portion 804 and the sub-fin region 805 , although other embodiments do not include such an interface in the doping profiles between these regions.

[0101] refer to Figure 8B , the gate structure 808 is shown as being above the protruding fin portion 804, as isolated by the self-aligned gate end cap isolation structure 820. In an embodiment, the gate structure 808 forms one of a plurality of parallel gate lines that form a grating structure such as a closely spaced grating structure. In one such embodiment, a closely spaced spacing cannot be achieved directly by conventional photolithography. For example, a pattern based on conventional photolithography may be first formed, but the spacing may be halved by patterning using a spacer mask, as is known in the art. Further, the original spacing may be quartered by a second round of spacer mask patterning. Thus, a grating-like gate pattern may have lines spaced apart at a constant spacing and having a constant width. The pattern may be manufactured by halving the spacing or quartering the spacing or other spacing segmentation methods.

[0102] Reference again Figure 8B, the source region 804A and the drain region 804B of the protruding fin portion 804 are shown in this perspective view, although it should be understood that these regions will overlap with the trench contact structure. In one embodiment, the source region 804A and the drain region 804B are doped portions of the original material of the protruding fin portion 804. In another embodiment, the material of the protruding fin portion 804 is removed and replaced with another semiconductor material, for example by epitaxial deposition. In either case, the source region 804A and the drain region 804B can extend below the height of the trench isolation layer 806, that is, into the sub-fin region 805.

[0103] In an embodiment, the semiconductor structure 800 includes a non-planar device, such as, but not limited to, a FinFET or a tri-gate device. In such an embodiment, the corresponding semiconductor channel region is formed by or in a three-dimensional body. In one such embodiment, the gate structure 808 surrounds at least the top surface and a pair of sidewalls of the three-dimensional body.

[0104] The substrate 802 may be composed of a semiconductor material that can withstand the manufacturing process and in which charge can migrate. In an embodiment, the substrate 802 is a bulk substrate composed of a crystalline silicon, silicon / germanium, or germanium layer doped with charge carriers (such as but not limited to phosphorus, arsenic, boron, or a combination thereof) to form an active region 804. In one embodiment, the concentration of silicon atoms in the bulk substrate 802 is greater than 97%. In another embodiment, the bulk substrate 802 is composed of an epitaxial layer grown on top of a different crystalline substrate, for example, a silicon epitaxial layer grown on top of a boron-doped bulk silicon single crystal substrate. The bulk substrate 802 may alternatively be composed of a III-V material. In an embodiment, the bulk substrate 802 is composed of a III-V material, such as but not limited to gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide, or a combination thereof. In one embodiment, bulk substrate 802 is composed of a Group III-V material and the charge carrier dopant impurity atoms are atoms such as, but not limited to, carbon, silicon, germanium, oxygen, sulfur, selenium, or tellurium.

[0105] The trench isolation layer 806 may be composed of a material suitable for ultimately electrically isolating or facilitating the isolation of a portion of the permanent gate structure from the underlying bulk substrate or isolating an active region formed within the underlying bulk substrate (such as an isolation fin active region). For example, in one embodiment, the trench isolation layer 806 is composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0106] The self-aligned gate end cap isolation structures 820, 821A, and 821B can be composed of one or more materials suitable for ultimately electrically isolating portions of the permanent gate structure from each other or facilitating isolation of portions of the permanent gate structure from each other. Exemplary materials or material combinations include single material structures such as silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride. Other exemplary materials or material combinations include multilayer stacks having a lower portion of silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride and an upper portion of a higher dielectric constant material such as hafnium oxide. The following is combined with Figures 9A-9C Describes additional examples.

[0107] The gate structure 808 may be composed of a gate electrode stack including a gate dielectric layer 852 and a gate electrode layer 850. In an embodiment, the gate electrode of the gate electrode stack is composed of a metal gate, and the gate dielectric layer includes a high-k material.

[0108] In an exemplary embodiment, the gate structure 808 of region 870A includes a first gate dielectric 852 that is conformal to the first plurality of semiconductor fins and laterally adjacent to and in contact with a first side of the gate end cap isolation structure (left-hand side 820). The second gate stack of region 870B includes a second gate dielectric 852 that is conformal to the second plurality of semiconductor fins and laterally adjacent to and in contact with a second side of the gate end cap isolation structure opposite the first side of the gate end cap isolation structure. In one embodiment, the first gate dielectric is thicker than the second gate dielectric, such as Fig. 8A As shown. In one embodiment, the first gate dielectric has more dielectric layers (e.g., layers 852A and 852B) than the second gate dielectric (e.g., only layer 852). In an embodiment, the gate dielectric of region 870A is an I / O gate dielectric, and the gate dielectric of region 870B is a logic gate dielectric.

[0109] In an embodiment, the gate dielectric of region 870B is composed of materials such as, but not limited to, hafnium oxide, hafnium oxynitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof. In addition, a portion of the gate dielectric layer may include a native oxide layer formed by the top layers of substrate 802. In an embodiment, the gate dielectric layer is composed of a top high-k portion and a lower portion composed of an oxide of a semiconductor material. In an embodiment, the gate dielectric layer is composed of a top portion of hafnium oxide and a bottom portion of silicon dioxide or silicon oxynitride. In an embodiment, the top high-k portion is composed of a "U" shaped structure, which includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions substantially perpendicular to the top surface of the substrate. In an embodiment, in addition to the high-k material layer, the gate dielectric of region 870A also includes a non-native silicon oxide layer. The non-native silicon oxide layer can be formed using a CVD process and can be formed below or above the high-k material layer. In an exemplary embodiment, the non-native silicon oxide layer (eg, layer 852A) is formed below the high-k material layer (eg, layer 852B).

[0110] In one embodiment, the gate electrode is composed of a metal layer, such as but not limited to metal nitride, metal carbide, metal silicide, metal aluminide, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel, or a conductive metal oxide. In a specific embodiment, the gate electrode is composed of a non-work function setting filling material formed above the metal work function setting layer. In some embodiments, the gate electrode may be composed of a "U" shaped structure, the "U" shaped structure including a bottom portion substantially parallel to the surface of the substrate and two sidewall portions substantially perpendicular to the top surface of the substrate. In another embodiment, at least one of the metal layers forming the gate electrode may simply be a planar layer substantially parallel to the top surface of the substrate, and does not include a sidewall portion substantially perpendicular to the top surface of the substrate. In a further embodiment of the present disclosure, the gate electrode may be composed of a combination of a U-shaped structure and a planar non-U-shaped structure. For example, the gate electrode may be composed of one or more U-shaped metal layers formed on top of one or more planar non-U-shaped layers.

[0111] The spacers associated with the gate electrode stack may be composed of a material suitable for ultimately electrically isolating or facilitating the isolation of the permanent gate structure from an adjacent conductive contact (such as a self-aligned contact). For example, in one embodiment, the spacers are composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0112] The local interconnect 854, the gate contact 814, the overlying gate contact via 816, and the overlying metal interconnect 860 may be composed of a conductive material. In an embodiment, one or more of the contacts or vias are composed of a metal substance. The metal substance may be a pure metal, such as tungsten, nickel, or cobalt, or may be an alloy, such as a metal-metal alloy or a metal-semiconductor alloy (e.g., such as a silicide material). A common example is the use of a copper structure, which may or may not include a barrier layer (such as a Ta or TaN layer) between the copper and the surrounding ILD material. As used herein, the term metal includes alloys, stacks, and other combinations of multiple metals. For example, a metal interconnect line may include a barrier layer, a stack of different metals or alloys, and the like.

[0113] In an embodiment (although not shown), providing structure 800 involves forming a contact pattern that is substantially perfectly aligned to an existing gate pattern while eliminating the use of a lithography step with a very tight registration budget. In one such embodiment, the method enables the use of an inherently highly selective wet etch (e.g., relative to conventionally implemented dry or plasma etching) to generate contact openings. In an embodiment, the contact pattern is formed by utilizing an existing gate pattern in conjunction with a contact plug lithography operation. In one such embodiment, the method enables the elimination of the need for critical lithography operations that would otherwise be used to generate a contact pattern as used in conventional methods. In an embodiment, the trench contact grid is not patterned separately, but is formed between polysilicon (gate) lines. For example, in one such embodiment, the trench contact grid is formed after gate grating patterning but before gate grating cutting.

[0114] Additionally, gate structure 808 may be fabricated by a replacement gate process. In such an arrangement, dummy gate material, such as polysilicon or silicon nitride pillar material, may be removed and replaced with a permanent gate electrode material. In one such embodiment, a permanent gate dielectric layer is also formed in this process, rather than from an earlier process. In an embodiment, the dummy gate is removed by a dry etch or wet etch process. In one embodiment, the dummy gate is composed of polysilicon or amorphous silicon and is formed using a process including the use of SF 6 In another embodiment, the dummy gate is composed of polysilicon or amorphous silicon and is removed by a dry etching process including using aqueous NH 4 In one embodiment, the dummy gate is composed of silicon nitride and is removed using a wet etch process including aqueous phosphoric acid.

[0115] In an embodiment, one or more methods described herein essentially contemplate a combination of dummy and replacement gate processes and dummy and replacement contact processes to obtain structure 800. In one such embodiment, the replacement contact process is performed after the replacement gate process to allow for high temperature annealing of at least a portion of the permanent gate stack. For example, in a specific such embodiment, annealing of at least a portion of the permanent gate structure is performed at a temperature greater than about 600 degrees Celsius, such as after forming the gate dielectric layer. The annealing is performed before forming the permanent contacts.

[0116] Reference again Fig. 8A In an embodiment, a semiconductor device has a contact structure that contacts a portion of a gate electrode formed above an active area. Typically, before forming a gate contact structure (such as a via) above the active portion of the gate and in the same layer as (e.g., in addition to) a trench contact via, one or more embodiments of the present disclosure include first using a gate alignment trench contact process. Such a process can be implemented to form a trench contact structure for semiconductor structure manufacturing (e.g., for integrated circuit manufacturing). In an embodiment, a trench contact pattern is formed that is aligned with an existing gate pattern. In contrast, conventional methods typically involve an additional lithography process that combines selective contact etching with close registration of the lithographic contact pattern with the existing gate pattern. For example, a conventional process may include patterning a polysilicon (gate) grid using separate patterning of contact features.

[0117] It should be understood that Fig. 8A and Figure 8B As illustrated, SAGE walls of different widths may be fabricated. It will also be appreciated that the fabrication of the gate end cap isolation structure may result in the formation of seams within the gate end cap isolation structure. It will also be appreciated that a stack of dielectric layers may be used to form the SAGE wall. It will also be appreciated that the gate end cap isolation structure may differ in composition depending on the spacing of adjacent fins. As an example covering all of these aspects, Figures 9A-9C A cross-sectional view illustrating important process operations in another self-aligned gate end cap process fabrication scheme for FinFET or tri-gate devices according to an embodiment of the present disclosure is shown.

[0118] refer to Fig. 9A , the grouping of fins 900 has a spacer 906. The grouping of fins 900 is adjacent to fin 902 via a larger spacer 904. A sacrificial spacer 916 is formed adjacent to a sidewall of an upper portion of each of the plurality of semiconductor fins 900 and 902.

[0119] refer to Fig. 9B, multiple gate end cap isolation structures 926 and 950 are formed between sacrificial spacers 916. For the purposes of this discussion, at least some of the SAGE walls shown are fabricated after the fin cutting process. In an embodiment, as shown, each of the multiple gate end cap isolation structures 926 formed between the spacers 906 includes a lower dielectric portion 928 and a dielectric cap 930 on the lower dielectric portion 928. The dielectric cap 930 can be a dielectric such as a dielectric cap 930 in combination with the dielectric cap 930 as described above. Figures 6A-6F The high-k cap described. In an embodiment, a plurality of gate end cap isolation structures 926 are formed by depositing and then recessing a first dielectric material, such as a silicon nitride layer, to provide a lower dielectric portion 928. The deposition process may be a conformal process, which in one embodiment provides a seam 932 within the lower dielectric portion 928. Thus, in an embodiment, each of the plurality of gate end cap isolation structures 926 includes a vertical seam 932 centered within the gate end cap isolation structure 926. A dielectric cap material, such as a metal oxide material (e.g., tantalum-doped hafnium oxide), is then formed in the recessed region above the lower dielectric portion 928. The dielectric cap material may be planarized to form the dielectric cap 930, or may be grown upward to directly provide the dielectric cap 930.

[0120] Reference again Fig. 9B In an embodiment, gate end cap isolation structure 926 is between semiconductor fins having spacing 906, and gate end cap isolation structure 950 is between semiconductor fins having spacing 904. Gate end cap isolation structure 926 has a width that is narrower than a corresponding width of gate end cap isolation structure 950. In an embodiment, gate end cap isolation structure 926 has an overall composition that is different from the overall composition of gate end cap isolation structure 950. In one such embodiment, gate end cap isolation structure 950 also includes a third dielectric layer 956, such as a silicon oxide layer on a bottom portion and within the sidewalls of lower dielectric portion 952. Dielectric cap 954 is also on third dielectric layer 956. Dielectric cap 954 can be a dielectric such as a dielectric layer as described above. Figures 6A-6F In an embodiment, the sidewalls of the lower dielectric portion 952 have an uppermost surface that is approximately coplanar with the uppermost surface of the third dielectric layer 956, and the dielectric cap 954 has a substantially flat lowermost surface, such as Fig. 9B . In another embodiment, the sidewalls of the lower dielectric portion 952 have an uppermost surface below the uppermost surface of the third dielectric layer 956, and the dielectric cap 954 extends further downward above the sidewall location. In yet another embodiment, the sidewalls of the lower dielectric portion 952 have an uppermost surface above the uppermost surface of the third dielectric layer 956, and the dielectric cap 954 extends further downward above the third dielectric layer 956.

[0121] In an embodiment, the deposition process of the third dielectric layer 956 is a conformal process, which in one embodiment provides a vertical seam 958 within the third dielectric layer 956. However, in another embodiment, the seam 958 is not formed in the wider structure, but is formed in the narrower structure (e.g., the seam 932 described above). It should be understood that the lower dielectric portions 928 and 952 can be composed of the same material (such as silicon nitride) and formed simultaneously with each other. It should also be understood that the dielectric caps 930 and 954 can be composed of the same material (such as tantalum-doped hafnium oxide) and formed simultaneously with each other. The third dielectric layer 956 in the structure 950 but omitted from the structure 926 can be formed by conformal deposition across the entire structure, but is excluded from the structure 926 because the lower dielectric portion 928 substantially fills the gap 906 in the first deposition process that does not completely fill the gap 904.

[0122] refer to Fig. 9C , sacrificial spacers 916 are removed. In an embodiment, sacrificial spacers 916 are removed by a wet etch or dry etch process. In an embodiment, the patterned stacked layers above the fins are also removed to provide fins 900' and 902'.

[0123] Reference again Fig. 9C In an embodiment, the gate end cap isolation structure 926 or 950 is in a corresponding recess below the uppermost surface of the trench isolation layer. In an embodiment, the gate end cap isolation structure 926 or 950 includes a lower dielectric portion and a dielectric cap on the lower dielectric portion. In an embodiment, the gate end cap isolation structure 926 or 950 includes a vertical seam centered within the second gate end cap isolation structure. In an embodiment, the first gate end cap isolation structure 926 has a different overall composition than the overall composition of the second gate end cap isolation structure 950, for example, by including additional fill dielectric material.

[0124] In embodiments where the gate end cap isolation structure 926 or 950 includes a lower dielectric portion and a dielectric cap on the lower dielectric portion, the gate end cap isolation structure 926 or 950 may be formed by first depositing a first dielectric material (such as a SiN layer, a SiCN layer, a SiOCN layer, a SiOC layer, or a SiC layer) and then recessing the first dielectric material to provide the lower dielectric portion. In one embodiment, the first dielectric material is a silicon nitride layer. The gate end cap isolation structure 926 or 950 may include a dielectric cap such as a silicon nitride layer. Figures 6A-6F The dielectric cap material described. The dielectric cap material may be planarized to form a dielectric cap, or may be grown upwards to directly provide a dielectric cap.

[0125] One or more of the above embodiments relate to cap improvements for SAGE walls of FinFET devices. It should be understood that other embodiments may include applying this method to fins composed of alternating layers of two different semiconductor materials (e.g., Si and SiGe or SiGe and Ge). One of the different semiconductor material pairs can then be removed in the gate region to provide a nanowire / nanoribbon channel for a full-all-around gate device. In an embodiment, the method for a full-all-around gate device is similar to the method described above for FinFETs, with the addition of a nanowire / ribbon release operation in the gate region.

[0126] In an embodiment, as used throughout this specification, an interlayer dielectric (ILD) material consists of or includes a layer of a dielectric or insulating material. Examples of suitable dielectric materials include, but are not limited to, oxides of silicon (e.g., silicon dioxide (SiO 2 )), doped oxides of silicon, fluorinated oxides of silicon, carbon-doped oxides of silicon, various low-k dielectric materials known in the art, and combinations thereof. The interlayer dielectric material can be formed by conventional techniques (e.g., chemical vapor deposition (CVD), physical vapor deposition (PVD)) or by other deposition methods.

[0127] In an embodiment, as also used throughout this specification, metal lines or interconnect materials (and via materials) are composed of one or more metals or other conductive structures. A common example is a structure using a copper line and a barrier layer that may or may not be included between copper and the surrounding ILD material. As used herein, the term metal includes alloys, stacks, and other combinations of multiple metals. For example, a metal interconnect may include a barrier layer (e.g., a layer including one or more of Ta, TaN, Ti, or TiN), a stack of different metals or alloys, etc. Therefore, the interconnect may be a single material layer, or may be formed by several layers including a conductive liner layer and a filling layer. Any suitable deposition process (e.g., electroplating, chemical vapor deposition, or physical vapor deposition) may be used to form an interconnect. In an embodiment, the interconnect is composed of a conductive material, such as, but not limited to, Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Mo, Ag, Au, or an alloy thereof. Interconnects are sometimes also referred to as traces, wires, lines, metals, or simply interconnects in the art.

[0128] In an embodiment, as also used throughout this specification, a hard mask material, a cover layer or a plug is composed of a dielectric material different from the interlayer dielectric material. In one embodiment, different hard mask, cover or plug materials can be used in different regions to provide growth or etching selectivity different from each other and from the underlying dielectric layer and metal layer. In some embodiments, the hard mask layer, cover or plug layer comprises a silicon nitride layer (e.g., silicon nitride) or a silicon oxide layer, or both, or a combination thereof. Other suitable materials may include carbon-based materials. Depending on the specific implementation, other hard mask, cover or plug layers known in the art may be used. The hard mask, cover or plug layer may be formed by CVD, PVD or by other deposition methods.

[0129] In an embodiment, as also used throughout this specification, lithography operations are performed using 193nm immersion lithography (i193), EUV and / or EBDW lithography, etc. Positive tone or negative tone resists may be used. In one embodiment, the lithography mask is a three-layer mask consisting of a topography masking portion, an anti-reflective coating (ARC) layer, and a photoresist layer. In a specific such embodiment, the topography masking portion is a carbon hard mask (CHM) layer, and the anti-reflective coating is a silicon ARC layer.

[0130] The embodiments disclosed herein can be used to manufacture various types of integrated circuits and / or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, microcontrollers, etc. In other embodiments, semiconductor memories can be manufactured. In addition, integrated circuits or other microelectronic devices can be used in various electronic devices known in the art. For example, in computer systems (e.g., desktops, laptop computers, servers), cellular phones, personal electronic devices, etc. The integrated circuit can be coupled to buses and other components in the system. For example, a processor can be coupled to a memory, a chipset, etc. via one or more buses. Each of the processor, memory, and chipset can potentially be manufactured using the methods disclosed herein.

[0131] Fig.10 A computing device 1000 is shown in accordance with one implementation of an embodiment of the present disclosure. The computing device 1000 houses a board 1002. The board 1002 may include a number of components, including but not limited to a processor 1004 and at least one communication chip 1006. The processor 1004 is physically and electrically coupled to the board 1002. In some implementations, the at least one communication chip 1006 is also physically and electrically coupled to the board 1002. In other implementations, the communication chip 1006 is part of the processor 1004.

[0132] Depending on its application, the computing device 1000 may include other components that may or may not be physically and electrically coupled to the board 1002. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a cryptographic processor, a chipset, an antenna, a display, a touch screen display, a touch screen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as a hard drive, a compact disk (CD), a digital versatile disk (DVD), etc.).

[0133] The communication chip 1006 implements wireless communications for transmitting data to and from the computing device 1000. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can communicate data via a non-solid medium using modulated electromagnetic radiation. The term does not mean that the associated device does not contain any wires, although in some embodiments they may not. The communication chip 1006 may implement any of a variety of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives, and any other wireless protocols designated as 3G, 4G, 5G and thereafter. The computing device 1000 may include multiple communication chips 1006. For example, the first communication chip 1006 may be dedicated to shorter-range wireless communications such as Wi-Fi and Bluetooth, and the second communication chip 1006 may be dedicated to longer-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, etc.

[0134] The processor 1004 of the computing device 1000 includes an integrated circuit die packaged within the processor 1004. The integrated circuit die of the processor 1004 may include one or more structures, such as a self-aligned gate end cap (SAGE) structure constructed according to implementations of embodiments of the present disclosure. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory to transform the electronic data into other electronic data that may be stored in registers and / or memory.

[0135] The communication chip 1006 also includes an integrated circuit die packaged within the communication chip 1006. The integrated circuit die of the communication chip 1006 may include one or more structures, such as a self-aligned gate end cap (SAGE) structure constructed according to implementations of embodiments of the present disclosure.

[0136] In further implementations, another component housed within computing device 1000 may include an integrated circuit die that includes one or more structures, such as a self-aligned gate end cap (SAGE) structure constructed in accordance with implementations of embodiments of the present disclosure.

[0137] In various embodiments, computing device 1000 may be a laptop computer, a netbook, a notebook, an ultrabook, a smart phone, a tablet computer, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video camera. In other embodiments, computing device 1000 may be any other electronic device that processes data.

[0138] Fig.11 An interposer 1100 including one or more embodiments of the present disclosure is shown. Interposer 1100 is an intermediate substrate for bridging a first substrate 1102 to a second substrate 1104. The first substrate 1102 may be, for example, an integrated circuit die. The second substrate 1104 may be, for example, a memory module, a computer motherboard, or another integrated circuit die. Typically, the purpose of interposer 1100 is to extend connections to a wider spacing or to rewire connections to different connections. For example, interposer 1100 may couple an integrated circuit die to a ball grid array (BGA) 1106 that may then be coupled to the second substrate 1104. In some embodiments, the first substrate 1102 and the second substrate 1104 are attached to opposite sides of interposer 1100. In other embodiments, the first substrate 1102 and the second substrate 1104 are attached to the same side of interposer 1100. And in further embodiments, three or more substrates are interconnected through interposer 1100.

[0139] The interposer 1100 may be formed of epoxy, glass fiber reinforced epoxy, ceramic material, or polymer material such as polyimide. In further embodiments, the interposer 1100 may be formed of alternating rigid or flexible materials, which may include the same materials described above for the semiconductor substrate, such as silicon, germanium, and other III-V and IV materials.

[0140] The interposer may include metal interconnects 1108 and vias 1110, including but not limited to through silicon vias (TSVs) 1112. The interposer 1100 may also include embedded devices 1114, including both passive and active devices. Such devices include but are not limited to capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 1100. According to an embodiment of the present disclosure, the apparatus or process disclosed herein may be used to manufacture the interposer 1100 or to manufacture components included in the interposer 1100.

[0141] Thus, embodiments of the present disclosure include a self-aligned gate end cap (SAGE) architecture with an improved cap, and a method of fabricating a self-aligned gate end cap (SAGE) architecture with an improved cap.

[0142] The above description of the illustrated implementations of the embodiments of the present disclosure (including what is described in the Abstract) is not intended to be exhaustive or to limit the present disclosure to the precise forms disclosed. Although specific implementations and examples of the present disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the present disclosure as will be appreciated by those skilled in the relevant art.

[0143] These modifications may be made to the present disclosure in light of the above detailed description. The terms used in the appended claims should not be interpreted as limiting the present disclosure to the specific embodiments disclosed in the specification and claims. On the contrary, the scope of the present disclosure is determined entirely by the appended claims, which will be interpreted according to established principles of claim interpretation.

[0144] Example Embodiment 1: An integrated circuit structure includes a first gate structure over a first semiconductor fin. A second gate structure over the second semiconductor fin. A gate end cap isolation structure between the first gate structure and the second gate structure. The gate end cap isolation structure has a higher-k dielectric cap layer over a lower-k dielectric wall. The higher-k dielectric cap layer includes hafnium and oxygen and has a monoclinic crystallinity of 70% or greater.

[0145] Example Embodiment 2: The integrated circuit structure of Example Embodiment 1, wherein the higher-k dielectric cap layer further comprises tantalum.

[0146] Example Embodiment 3: The integrated circuit structure of Example Embodiment 1 or 2, wherein the higher-k dielectric cap layer is substantially composed of tantalum-doped hafnium oxide (Ta—HfO) having a monoclinic crystallinity of 70% or greater. 2 )composition.

[0147] Example Embodiment 4: The integrated circuit structure of Example Embodiment 1, 2 or 3, wherein the gate end cap isolation structure includes a vertical seam centered within the lower-k dielectric wall.

[0148] Example Embodiment 5: An integrated circuit structure includes a first gate structure on a first semiconductor fin. A second gate structure is on the second semiconductor fin. A gate end cap isolation structure is between the first gate structure and the second gate structure, the gate end cap isolation structure having a higher-k dielectric cap layer on a lower-k dielectric wall. The higher-k dielectric cap layer is substantially composed of tantalum-doped hafnium oxide (Ta-HfO) having a monoclinic crystallinity of 70% or greater. 2 A local interconnect is on the first gate structure, on the higher-k dielectric cap layer, and on the second gate structure, the local interconnect having a lowermost surface above an uppermost surface of the higher-k dielectric cap layer.

[0149] Example Embodiment 6: The integrated circuit structure of Example Embodiment 5, wherein the first gate structure and the second gate structure each have an uppermost surface that is coplanar with an uppermost surface of the higher-k dielectric cap layer of the gate end cap isolation structure.

[0150] Example Embodiment 7: The integrated circuit structure according to Example Embodiment 5 or 6, wherein the local interconnect electrically connects the first gate structure and the second gate structure.

[0151] Example Embodiment 8: The integrated circuit structure of Example Embodiment 5, 6 or 7, wherein the gate end cap isolation structure includes a vertical seam centered within the lower-k dielectric wall.

[0152] Example embodiment 9: A computing device includes a board and a component coupled to the board. The component includes an integrated circuit structure. The integrated circuit structure includes a first gate structure above a first semiconductor fin. A second gate structure is above the second semiconductor fin. A gate end cap isolation structure is between the first gate structure and the second gate structure. The gate end cap isolation structure has a higher-k dielectric cap layer on a lower-k dielectric wall. The higher-k dielectric cap layer includes hafnium and oxygen and has a monoclinic crystallinity of 70% or greater.

[0153] Example Embodiment 10: The computing device of Example Embodiment 9, further comprising a memory coupled to the board.

[0154] Example Embodiment 11: The computing device of Example Embodiment 9 or 10, further comprising a communication chip coupled to the board.

[0155] Example Embodiment 12: The computing device of Example Embodiment 9, 10 or 11, further comprising a camera coupled to the board.

[0156] Example Embodiment 13: The computing device of Example Embodiment 9, 10, 11 or 12, wherein the component is a packaged integrated circuit die.

[0157] Example Embodiment 14: The computing device of Example Embodiment 9, 10, 11, 12 or 13, wherein the computing device is selected from the group consisting of a mobile phone, a laptop computer, a desktop computer, a server, and a set-top box.

[0158] Example embodiment 15: A computing device includes a board and a component coupled to the board. The component includes an integrated circuit structure. The integrated circuit structure includes a first gate structure on a first semiconductor fin. A second gate structure is on the second semiconductor fin. A gate end cap isolation structure is between the first gate structure and the second gate structure, the gate end cap isolation structure having a higher-k dielectric cap layer on a lower-k dielectric wall. The higher-k dielectric cap layer is substantially composed of tantalum-doped hafnium oxide (Ta-HfO) having a monoclinic crystallinity of 70% or greater. 2 A local interconnect is on the first gate structure, on the higher-k dielectric cap layer, and on the second gate structure, the local interconnect having a lowermost surface above an uppermost surface of the higher-k dielectric cap layer.

[0159] Example Embodiment 16: The computing device of Example Embodiment 15, further comprising a memory coupled to the board.

[0160] Example Embodiment 17: The computing device of Example Embodiment 15 or 16, further comprising a communication chip coupled to the board.

[0161] Example Embodiment 18: The computing device of Example Embodiment 15, 16 or 17, further comprising a camera coupled to the board.

[0162] Example Embodiment 19: The computing device of Example Embodiment 15, 16, 17 or 18, wherein the component is a packaged integrated circuit die.

[0163] Example Embodiment 20: The computing device of Example Embodiment 15, 16, 17, 18 or 19, wherein the computing device is selected from the group consisting of a mobile phone, a laptop computer, a desktop computer, a server, and a set-top box.

Claims

1. An integrated circuit structure, comprising: a first pair of fins on a substrate; a second pair of fins on the substrate, the second pair of fins being laterally spaced apart from the first pair of fins; a first gate stack over upper portions of the first pair of fins; a second gate stack over an upper portion of the second pair of fins; a first gate end cap wall laterally disposed between the first pair of fins and the second pair of fins, the first gate end cap wall contacting the first gate stack and the second gate stack, and having an uppermost surface at the same level as an uppermost surface of the first gate stack and the second gate stack; a second gate end cap wall laterally spaced from a side of the second pair of fins opposite the first gate end cap wall and in contact with the second gate stack; as well as A trench isolation structure is laterally adjacent to a lower portion of the first pair of fins, a lower portion of the second pair of fins, a lower portion of the first gate end cap wall, and a lower portion of the second gate end cap wall, the lowermost surface of the trench isolation structure being below a lowermost surface of the first gate end cap wall and below a lowermost surface of the second gate end cap wall.

2. The integrated circuit structure according to claim 1, wherein: The first gate stack includes a first high-k dielectric layer in contact with a first sidewall of the first gate end cap wall, and wherein the second gate stack includes a second high-k dielectric layer in contact with a second sidewall of the second gate end cap wall, the second sidewall laterally opposing the first sidewall.

3. The integrated circuit structure according to claim 2, wherein: A first high-k dielectric layer is along a first sidewall of the first gate end cap wall, and wherein the second high-k dielectric layer is along a second sidewall of the second gate end cap wall.

4. The integrated circuit structure according to claim 1, wherein: The first gate stack has the same composition as the second gate stack.

5. The integrated circuit structure according to claim 1, further comprising: A dielectric cap layer is formed on the second gate end cap wall.

6. The integrated circuit structure according to claim 1, further comprising: A third gate end cap wall is laterally spaced apart from a side of the first pair of fins opposite the first gate end cap wall.

7. The integrated circuit structure according to claim 1, further comprising: A local conductive interconnect is formed on the first gate end cap wall.

8. An integrated circuit structure comprising: a first fin and a second fin on a substrate, the second fin being laterally spaced apart from the first fin; a third fin and a fourth fin on the substrate, the third fin being laterally spaced apart from the second fin, and the fourth fin being laterally spaced apart from the third fin; a first gate stack over an upper portion of the first fin and an upper portion of the second fin; a second gate stack over an upper portion of the third fin and an upper portion of the fourth fin; a first gate end cap wall laterally disposed between the second fin and the third fin, the first gate end cap wall contacting the first gate stack and the second gate stack, and having an uppermost surface at the same level as an uppermost surface of the first gate stack and the second gate stack; a second gate end cap wall laterally spaced from a side of the fourth fin opposite the first gate end cap wall and in contact with the second gate stack; a first trench isolation region located between a lower portion of the second fin and a lower portion of the first gate end cap wall; a second trench isolation region between the first gate end cap wall and a lower portion of the third fin, wherein a lowermost surface of the first gate end cap wall does not extend beyond a lowermost surface of the first trench isolation region and a lowermost surface of the second trench isolation region; and A third trench isolation region is located between a lower portion of the fourth fin and a lower portion of the second gate end cap wall, wherein a lowermost surface of the second gate end cap wall does not extend beyond a lowermost surface of the third trench isolation region.

9. The integrated circuit structure according to claim 8, wherein: The first gate stack includes a first high-k dielectric layer in contact with a first sidewall of the first gate end cap wall, and wherein the second gate stack includes a second high-k dielectric layer in contact with a second sidewall of the second gate end cap wall, the second sidewall laterally opposing the first sidewall.

10. The integrated circuit structure according to claim 9, wherein: A first high-k dielectric layer is along a first sidewall of the first gate end cap wall, and wherein the second high-k dielectric layer is along a second sidewall of the second gate end cap wall.

11. The integrated circuit structure according to claim 8, wherein: The first gate stack has the same composition as the second gate stack.

12. The integrated circuit structure of claim 8, further comprising: A dielectric cap layer is formed on the second gate end cap wall.

13. The integrated circuit structure of claim 8, further comprising: A local conductive interconnect is formed on the first gate end cap wall.

14. An integrated circuit structure comprising: a first pair of nanowires above a substrate; a second pair of nanowires on the substrate, the second pair of nanowires being laterally spaced apart from the first pair of nanowires; a first gate stack over upper portions of the first pair of nanowires; a second gate stack over upper portions of the second pair of nanowires; a first gate end cap wall laterally disposed between the first pair of nanowires and the second pair of nanowires, the first gate end cap wall contacting the first gate stack and the second gate stack, and having an uppermost surface at the same level as an uppermost surface of the first gate stack and the second gate stack; a second gate end cap wall laterally spaced from a side of the second pair of nanowires opposite the first gate end cap wall and in contact with the second gate stack; as well as A trench isolation structure is laterally adjacent to a lower portion of the first gate end cap wall and a lower portion of the second gate end cap wall, wherein a lowermost surface of the trench isolation structure is below a lowermost surface of the first gate end cap wall and below a lowermost surface of the second gate end cap wall.

15. The integrated circuit structure according to claim 14, wherein: The first gate stack includes a first high-k dielectric layer in contact with a first sidewall of the first gate end cap wall, and wherein the second gate stack includes a second high-k dielectric layer in contact with a second sidewall of the second gate end cap wall, the second sidewall laterally opposing the first sidewall.

16. The integrated circuit structure according to claim 15, wherein: A first high-k dielectric layer is along a first sidewall of the first gate end cap wall, and wherein the second high-k dielectric layer is along a second sidewall of the second gate end cap wall.

17. The integrated circuit structure according to claim 14, wherein: The first gate stack has the same composition as the second gate stack.

18. The integrated circuit structure of claim 14, further comprising: A dielectric cap layer is formed on the second gate end cap wall.

19. The integrated circuit structure of claim 14, further comprising: A third gate end cap wall is laterally spaced apart from a side of the first pair of nanowires opposite the first gate end cap wall.

20. The integrated circuit structure of claim 14, further comprising: A local conductive interconnect is formed on the first gate end cap wall.

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