Semiconductor device

Abstract

A semiconductor device includes: a substrate; an active region extending in a first direction on the substrate; a gate structure extending in a second direction on the active region and intersecting the active region; a source / drain region on the active region at one side of the gate structure; a separation pattern extending in the first direction and separating the gate structure; and a contact structure on and crossing the separation pattern, the contact structure electrically connected to the source / drain region, in which the contact structure includes a first portion and a second portion, the first portion contacting the separation pattern, the second portion contacting the source / drain region, a lower surface of the second portion being at a lower height than a lower surface of the first portion, and a lowermost end of the contact structure is spaced apart from the partition pattern.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices. Background Art

[0002] As the demand for high performance, high speed and / or multi-function of semiconductor devices increases, the integration of semiconductor devices is increasing. When finely patterned semiconductor devices are manufactured in response to the trend of high integration of semiconductor devices, it is necessary to realize patterns with fine widths or fine separation distances. In addition, in order to overcome the limitations in operating characteristics caused by the size reduction of planar metal oxide semiconductor field effect transistors (MOSFETs), efforts are being made to develop semiconductor devices including fin field effect transistors (Fin FETs) having three-dimensional channels. Summary of the invention

[0003] Provided is a semiconductor device that can have improved integration and reliability.

[0004] According to one aspect of an example embodiment, a semiconductor device includes: a substrate; an active region extending along a first direction on the substrate; a gate structure extending along a second direction on the active region and intersecting the active region; a source / drain region, the source / drain region being located on the active region on one side of the gate structure; a separation pattern extending in the first direction and separating the gate structure; and a contact structure located on the separation pattern and intersecting the separation pattern and electrically connected to the source / drain region, wherein the contact structure includes a first portion and a second portion, the first portion contacts the separation pattern, the second portion contacts the source / drain region, a lower surface of the second portion is at a lower height than a lower surface of the first portion, and a lowermost end of the contact structure is spaced apart from the separation pattern.

[0005] According to one aspect of an example embodiment, a semiconductor device includes: a substrate; an active region, the active region extending along a first direction on the substrate; a gate structure, the gate structure extending along a second direction on the active region and intersecting the active region; a source / drain region, the source / drain region being located on the active region on at least one side of the gate structure; and a contact structure, the contact structure being electrically connected to the source / drain region, wherein a lower surface of the contact structure includes a first surface, a second surface located at a height lower than the first surface, and an inner surface connecting the first surface and the second surface, the first surface being spaced apart from the source / drain region, the second surface contacting the source / drain region, and the inner surface being inclined so that a width of the contact structure becomes narrower toward the substrate.

[0006] According to one aspect of an example embodiment, a semiconductor device includes: a substrate; a plurality of active regions extending along a first direction on the substrate and spaced apart from each other in a second direction intersecting the first direction; a plurality of gate structures extending along the second direction on the plurality of active regions; a plurality of source / drain regions, the plurality of source / drain regions being located on the plurality of active regions on at least one side of the plurality of gate structures; a separation pattern extending along the first direction between the plurality of source / drain regions and penetrating at least one gate structure among the plurality of gate structures to separate the at least one gate structure; and a contact structure contacting the separation pattern on the separation pattern and contacting a first source / drain region and a second source / drain region among the plurality of source / drain regions, wherein a first lower surface of the contact structure contacting the separation pattern is at a height higher than a second lower surface of the contact structure contacting the first source / drain region and the second source / drain region, at least a portion of an inner side surface of the contact structure connecting the first lower surface and the second lower surface is spaced apart from the separation pattern, and the first source / drain region and the second source / drain region include impurities having different conductivity types. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The above and other aspects, features and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0008] Figure 1 is a top view illustrating a semiconductor device according to example embodiments;

[0009] FIG. 2A to FIG. 2D is a cross-sectional view illustrating a semiconductor device according to example embodiments;

[0010] FIG. 3A to FIG. 3B is a cross-sectional view illustrating a semiconductor device according to example embodiments;

[0011] Figure 4 is a cross-sectional view illustrating a semiconductor device according to example embodiments;

[0012] Figure 5 is a cross-sectional view illustrating a semiconductor device according to example embodiments;

[0013] Figure 6 is a cross-sectional view illustrating a semiconductor device according to example embodiments;

[0014] Figure 7 is a top view illustrating a semiconductor device according to example embodiments;

[0015] Figures 8 to 10 is a cross-sectional view illustrating a semiconductor device according to example embodiments; and

[0016] Figures 11 to 19 2 is a diagram illustrating a process sequence for explaining a method of manufacturing a semiconductor device according to example embodiments. DETAILED DESCRIPTION

[0017] Hereinafter, example embodiments of the present disclosure will be described with reference to the accompanying drawings. Hereinafter, unless otherwise indicated by a figure mark, terms such as "upper", "upper part", "upper surface", "lower", "lower part", "lower surface", "side surface" and the like may be understood as referring to the accompanying drawings.

[0018] Figure 1 FIG. 1 is a top view illustrating a semiconductor device according to an example embodiment. Figure 1 Some components of a semiconductor device are illustrated in FIG.

[0019] FIG. 2A to FIG. 2D is a cross-sectional view illustrating a semiconductor device according to example embodiments. Figure 2B Picture shows Figure 1 A cross section of the semiconductor device taken along line II-II'. Figure 2C Picture shows Figure 1 A cross section of the semiconductor device taken along line III-III'. Figure 2D Picture shows Figure 1 A cross section of the semiconductor device taken along line IV-IV'.

[0020] refer to Figures 1 to 2D , the semiconductor device 100 may include: a substrate 101 including an active region 105; a channel structure 140 including first to fourth channel layers 141, 142, 143 and 144 disposed to be vertically spaced apart from each other on the active region 105; a gate structure 160 extending across the active region 105 and including gate electrodes 165, respectively; a separation pattern 120 separating the gate structure 160; a source / drain region 130 contacting the channel structure 140; and a contact structure 180 connected to the source / drain region 130. The semiconductor device 100 may further include a device isolation layer 110, an interlayer insulating layer 170, an insulating region 175 and an upper insulating layer 190.

[0021] In the semiconductor device 100, the active region 105 may have a fin structure, and the gate electrode 165 may be disposed between the active region 105 and the channel structure 140, between the first to fourth channel layers 141, 142, 143, and 144 of the channel structure 140, and on the channel structure 140. Therefore, the semiconductor device 100 may include a multi-bridge channel FET (MBCFET). TM ) structure of a full-ring gate field effect transistor.

[0022] The substrate 101 may have an upper surface extending in the X direction and the Y direction. The substrate 101 may include a semiconductor material such as a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI compound semiconductor. For example, the Group IV semiconductor may include silicon, germanium, or silicon germanium. The substrate 101 may be provided as a bulk wafer, an epitaxial layer, a silicon on insulator (SOI) layer, or a semiconductor on insulator (SeOI) layer.

[0023] The substrate 101 may include an active region 105 disposed in, on, or above the substrate 101. The active region 105 may be surrounded by a device isolation layer 110 within the substrate 101, and may be disposed to extend in a first direction (e.g., the X direction). However, according to the description method of the present disclosure, the active region 105 may be described as being constructed separately from the substrate 101. A portion of the active region 105 may protrude onto the device isolation layer 110, and an upper surface of the active region 105 may be located at a height higher than the height of the device isolation layer 110. Throughout the present disclosure, "height" corresponds to a position in the Z direction (the third direction).

[0024] The active region 105 may be formed of a portion of the substrate 101 or may include an epitaxial layer grown from the substrate 101. However, at one side of the gate structure 160, the active region 105 may be partially recessed to form a recessed region, and the source / drain region 130 may be disposed in the recessed region.

[0025] In example embodiments, the active region 105 may or may not include a well region containing impurities. For example, in the case of a P-type transistor (pFET), the well region may include an N-type impurity such as phosphorus (P), arsenic (As), or antimony (Sb). In the case of an N-type transistor (nFET), the well region may include a P-type impurity such as boron (B), gallium (Ga), or indium (In). The well region may be located, for example, at a predetermined depth from the upper surface of the active region 105.

[0026] The device isolation layer 110 may define an active region 105 in the substrate 101. The device isolation layer 110 may surround the active region 105 in the substrate 101. For example, the device isolation layer 110 may be formed by a shallow trench isolation (STI) process. The device isolation layer 110 may expose the upper surface of the active region 105 and may partially expose the upper portion. In some example embodiments, the device isolation layer 110 may have a curved upper surface to have a higher height as it is closer to the active region 105. The device isolation layer 110 may be formed of an insulating material. The device isolation layer 110 may be, for example, an oxide, a nitride, or a combination of an oxide and a nitride.

[0027] The separation pattern 120 may be disposed adjacent to the active region 105 to extend in a first direction (e.g., the X direction) in which the active region 105 extends. The separation pattern 120 may be disposed to extend in a direction (e.g., the X direction) intersecting the gate structure 160. The separation pattern 120 may be disposed to be spaced apart from the active region 105, the source / drain region 130, and the substrate 101. The separation pattern 120 may be disposed to contact the gate structure 160, and the gate structure 160 may be separated by the separation pattern 120. For example, the gate structure 160 being separated by the separation pattern 120 may be understood as the gate structure 160 being divided into portions spaced apart from each other by the separation pattern 120. Reference Figure 2C , the upper surface of the separation pattern 120 may include a first upper surface 120U1 in contact with the lower surface of the first portion 180a of the contact structure 180 and a second upper surface 120U2 located at a height higher than the first upper surface 120U1. The first upper surface 120U1 and the second upper surface 120U2 may be located at a height higher than the upper end of the source / drain region 130 and the upper end of the gate electrode 165. The first upper surface 120U1 of the separation pattern 120 may be located at a height lower than the upper surface of the insulating region 175. The second upper surface 120U2 of the separation pattern 120 may be coplanar with the upper surface of the first portion 180a of the contact structure 180, and may be in contact with the lower surface of the upper insulating layer 190. The surface connecting the first upper surface 120U1 and the second upper surface 120U2 may contact the side surface of the first portion 180a of the contact structure 180. The lower surface of the separation pattern 120 may be located at a height lower than the lower end of the source / drain region 130, and the lower surface of the separation pattern 120 may be located at a height lower than the interface between the device isolation layer 110 and the interlayer insulating layer 170. That is, the separation pattern 120 may penetrate the interlayer insulating layer 170 and extend into the inside of the device isolation layer 110. The width of the separation pattern 120 may decrease toward the substrate 101. In the cross section of the separation pattern 120 in the first direction (see Figure 2C ), the separation pattern 120 may have a shape surrounding the lower surface and the side surface of the first portion 180a of the contact structure 180. In example embodiments, the side surface of the separation pattern 120 may be disposed perpendicular to the upper surface of the substrate 101 so that the width of the separation pattern 120 may be constant. The separation pattern 120 may include an insulating material, such as silicon nitride, silicon oxynitride, or a combination of silicon nitride and silicon oxynitride. The separation pattern 120 may have a material composition different from that of the interlayer insulating layer 170, and may include a material having an etching selectivity different from that of the interlayer insulating layer 170.

[0028] The gate structure 160 may intersect the active region 105 and the channel structure 140 on the active region 105 and the channel structure 140, and may be arranged to extend in the second direction (eg, in the Y direction). The gate structure 160 may be separated by the separation pattern 120, and in a cross-sectional view in the second direction (see Figure 2B ), one side of the gate structure 160 may be in contact with the separation pattern 120, and the other side of the gate structure 160 opposite to the one side may be in contact with the insulating region 175.

[0029] The functional channel region of the transistor may be formed in the active region 105 and / or the channel structure 140 intersecting with the gate electrode 165 of the gate structure 160. The gate structure 160 may include the gate electrode 165, a gate dielectric layer 162 between the gate electrode 165 and the first to fourth channel layers 141, 142, 143, and 144, and a gate spacer layer 164 on the side surface of the gate electrode 165. In example embodiments, the gate structure 160 may further include a capping layer on the upper surface of the gate electrode 165. Alternatively, the portion of the insulating region 175 located on the gate structure 160 may be referred to as a gate capping layer.

[0030] The gate dielectric layer 162 may be disposed between the active region 105 and the gate electrode 165 and between the channel structure 140 and the gate electrode 165, and may be disposed to cover at least a portion of the surface of the gate electrode 165. For example, the gate dielectric layer 162 may be disposed to surround all surfaces except the top surface of the gate electrode 165, the surface of the gate electrode 165 in contact with the separation pattern 120, and the surface in contact with the insulating region 175. The gate dielectric layer 162 may extend between the gate electrode 165 and the gate spacer layer 164, but the embodiments of the present disclosure are not limited thereto. The gate dielectric layer 162 may include an oxide, a nitride, or a high-κ material. The high-κ material may refer to a material that is in contact with silicon oxide (SiO 2 ) than a dielectric material having a higher dielectric constant. The high dielectric constant material may be, for example, aluminum oxide (Al 2 O 3 ), Tantalum Oxide (Ta 2 O 3 ), titanium oxide (TiO 2 ), yttrium oxide (Y 2 O 3 )、ZrO 2 ), zirconium oxide silicon (ZrSi x O y ), hafnium oxide (HfO 2 ), Hafnium Silicon Oxide (HfSi x O y ), lanthanum oxide (La 2 O3 ), lanthanum aluminum oxide (LaAl x O y ), lanthanum hafnium oxide (LaHf x O y ), Hafnium Aluminum Oxide (HfAl x O y ) and praseodymium oxide (Pr 2 O 3 According to example embodiments, the gate dielectric layer 162 may be formed of a multi-layer film.

[0031] The gate electrode 165 may be provided to fill the gaps between the first to fourth channel layers 141, 142, 143, and 144 on the active region 105 and extend onto the channel structure 140. The gate electrode 165 may be spaced apart from the first to fourth channel layers 141, 142, 143, and 144 by the gate dielectric layer 162. The gate electrode 165 may include a conductive material, and for example, include a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN) and / or a metal material such as aluminum (Al), tungsten (W), or molybdenum (Mo), or a semiconductor material such as doped polysilicon. According to an embodiment, the gate electrode 165 may be composed of two or more multilayer structures.

[0032] The gate spacer layer 164 may be disposed on both side surfaces of the gate electrode 165 on the channel structure 140. The gate spacer layer 164 may insulate the source / drain region 130 and the gate electrode 165. According to example embodiments, the gate spacer layer 164 may have a multilayer structure. The gate spacer layer 164 may be formed of at least one of oxide, nitride, and oxynitride, and may be formed of, for example, a low dielectric constant film.

[0033] The channel structure 140 may be disposed on the active region 105 in the region where the active region 105 intersects with the gate structure 160. Each channel structure 140 may include first to fourth channel layers 141, 142, 143, and 144, which are multiple channel layers that are disposed to be spaced apart from each other in the Z direction. The first to fourth channel layers 141, 142, 143, and 144 may be disposed sequentially from the bottom, and the first channel layer 144 may be a top channel layer. One side of the first to fourth channel layers 141, 142, 143, and 144 may be etched through the insulating region 175 and may be in contact with the insulating region 175. The channel structure 140 may be connected to the source / drain region 130. The channel structure 140 may have the same or similar width as the gate structure 160 in the X direction, and may have the same or smaller width as the active region 105 in the Y direction. In the cross section in the y direction, the width of the lower channel layer in the first to fourth channel layers 141, 142, 143 and 144 may be equal to or greater than the width of the upper channel layer in the first to fourth channel layers 141, 142, 143 and 144. In various embodiments, the number and shape of the channel layers forming one channel structure 140 may vary. For example, one channel structure 140 may include three channel layers, two channel layers, or five or more channel layers.

[0034] The channel structure 140 may be formed of a semiconductor material, and may include, for example, at least one of silicon (Si), silicon germanium (SiGe), and germanium (Ge). For example, the channel structure 140 may be formed of the same material as the active region 105. In some example embodiments, the channel structure 140 may include an impurity region positioned adjacent to the source / drain region 130. Each of the channel layers 141, 142, 143, and 144 of the channel structure 140 may include a semiconductor material and have a shape of a nanosheet having a thickness of several nanometers in the Z direction.

[0035] The source / drain region 130 may be disposed in a recessed region in which the upper portion of the active region 105 is partially recessed on one or both sides of the gate structure 160. The recessed region may extend along the side surface of the channel structure 140 and the side surface of the gate dielectric layer 162. The source / drain region 130 may be disposed to cover the side surface of each of the first to fourth channel layers 141, 142, 143, and 144 of the channel structure 140 in the X direction. The upper surface of the source / drain region 130 may be located at the same height as the lower surface of the gate electrode 165 on the channel structure 140 or higher than the lower surface of the gate electrode 165 on the channel structure 140, and the height may be changed differently in various example embodiments. In example embodiments, the side surface of the source / drain region 130 may be curved according to the first to fourth channel layers 141, 142, 143, and 144 and the gate structure 160. However, specific shapes of side surfaces of the source / drain regions 130 may be variously changed in various example embodiments.

[0036] The source / drain region 130 may include a semiconductor material, for example, at least one of silicon (Si) and germanium (Ge), and may further include a dopant. For example, when the semiconductor device 100 is a pFET, the dopant may be at least one of boron (B), gallium (Ga), and indium (In). The source / drain region 130 may be formed by an epitaxial layer.

[0037] The internal spacer layer 150 may be arranged to be parallel to the gate electrode 165 between the first to fourth channel layers 141, 142, 143 and 144 in the Z direction. The gate electrode 165 may be stably spaced apart from the source / drain region 130 by the internal spacer layer 150 and may be electrically separated. The internal spacer layer 150 may have a shape in which the side surface of the internal spacer layer 150 facing the gate electrode 165 is convexly rounded inwardly toward the gate electrode 165, but the embodiments of the present disclosure are not limited thereto. The internal spacer layer 150 may include at least one of an oxide, a nitride and an oxynitride, and may be made of, for example, a low dielectric constant film. However, in some example embodiments, the internal spacer layer 150 may be omitted.

[0038] The contact structure 180 may be disposed on the separation pattern 120 to extend in the second direction (e.g., the Y direction) across the separation pattern. The contact structure 180 may penetrate the interlayer insulating layer 170 and be connected to the source / drain region 130, and may apply an electrical signal to the source / drain region 130. The contact structure 180 may be disposed to recess a portion of the source / drain region 130.

[0039] The contact structure 180 may include a first portion 180a including a lower surface in contact with the separation pattern 120 and a second portion 180b including a lower surface in contact with the source / drain region 130. The lower surface of the first portion 180a may be referred to as a first surface, and the lower surface of the second portion 180b may be referred to as a second surface. The area of ​​the second surface may be greater than the area of ​​the first surface. The first portion 180a may be located between the second portions 180b along the second direction. The lower surface of the second portion 180b may be located at a height lower than the lower surface of the first portion 180a. The lower surface of the second portion 180b may be located at a height lower than the lower surface of the third channel layer 143. The lower surface of the first portion 180a may be located at a height higher than the upper end of the source / drain region 130. The upper surface of the first portion 180a and the upper surface of the second portion 180b may be coplanar, and the thickness H1 of the first portion 180a may be less than the thickness H2 of the second portion 180b. A portion of the second portion 180 b may overlap a portion of the separation pattern 120 in the second direction (eg, the Y direction).

[0040] The lower surface of the contact structure 180 may include an inner side surface connecting a first surface as the lower surface of the first portion 180a and a second surface as the lower surface of the second portion 180b. At least a portion of the inner side surface may be spaced apart from the separation pattern 120, and the inner side surface may be inclined so that the width of the contact structure 180 becomes narrower toward the substrate. The lowermost end of the contact structure 180 may be included in the second surface and may be spaced apart from the separation pattern 120. The space between the portion of the second portion 180b located at a height lower than the lower surface of the first portion 180a and the separation pattern 120 may be provided to be filled with the interlayer insulating layer 170. In example embodiments, the inner side surface may be perpendicular to the upper surface of the substrate 101. In example embodiments, at least a portion of the inner side surface may be in contact with the separation pattern 120, or the entire inner side surface of the inner side surface may be in contact with the separation pattern 120.

[0041] Among the gate structures 160 disposed adjacently in the y direction with the separation pattern 120 interposed therebetween, the transistor formed by one gate structure 160 may be a PMOS, and the transistor formed by the other gate structure 160 may be an NMOS. Therefore, the contact structure 180 may connect the source / drain region 130 of the PMOS and the source / drain region 130 of the NMOS. According to an embodiment, both sides of the gate structure 160 separated by the separation pattern 120 and disposed adjacent to the separation pattern 120 in the y direction may be the same PMOS transistor or NMOS transistor.

[0042] Such a semiconductor device 100 may have a structure in which the gate structure 160 is formed by forming a linear recessed region RS (see Fig.12 ) are separated, the separation pattern 120 fills a portion of the recessed region RS, and the first portion 180a of the contact structure 180 fills a portion of the recessed region RS on the separation pattern 120. Therefore, gate separation can be performed in the form of a line, thereby stably separating the gate structure 160 and forming the contact structure 180 through a self-aligned contact (SAC) process. By including the separation pattern 120 and the contact structure 180 in this form, a semiconductor device with improved integration and reliability can be provided.

[0043] The interlayer insulating layer 170 may be provided to cover the upper surface of the source / drain region 130 and the upper surface of the device isolation layer 110. The interlayer insulating layer 170 may include at least one of an oxide, a nitride, and an oxynitride, such as a low dielectric constant material. According to example embodiments, the interlayer insulating layer 170 may include a plurality of insulating layers. The interlayer insulating layer 170 may include a material having an etching selectivity different from that of the separation pattern 120.

[0044] The insulating region 175 may be provided to cover portions of the substrate 101 and the active region 105. The insulating region 175 may cover the remaining portion of the device isolation layer 110 that does not cover the substrate 101 and the active region 105. The insulating region 175 may cover at least a portion of the remaining portion of the active region 105, the source / drain region 130, and the contact structure 180 that is not covered by the interlayer insulating layer 170. The insulating region 175 may cover at least a portion of the source / drain region 130 that is not covered by the interlayer insulating layer 170. A side surface of the active region 105 adjacent to the separation pattern 120 may contact the device isolation layer 110 and the interlayer insulating layer 170, and a side surface of the active region 105 on a side opposite to the separation pattern 120 may contact the insulating region 175. That is, the insulating region 175 may cover one side surface of the contact structure 180, the source / drain region 130, and the active region 105. The insulating region 175 may be provided to be spaced apart from the separation pattern 120, and may be provided to contact the contact structure 180. The insulating region 175 may cover the upper surface and the side surface of the gate electrode 165, and the portion of the insulating region 175 covering the upper surface of the gate structure 160 may be referred to as a gate cover layer. The side surface of the insulating region 175 may be perpendicular to the upper surface of the substrate 101, but the embodiments of the present disclosure are not limited thereto. For example, the insulating region 175 may have a side surface that is inclined so that the width of the insulating region 175 decreases toward the substrate 101, and conversely, the insulating region 175 may have a side surface that is inclined so that the width of the insulating region 175 increases toward the substrate 101. The lower surface of the insulating region 175 may be located at substantially the same height as the lower surface of the device isolation layer 110, but the embodiments of the present disclosure are not limited thereto. For example, the lower surface of the insulating region 175 may be located at a height higher than the upper surface of the substrate 101, and the space between the lower surface of the insulating region 175 and the substrate 101 may be filled with the device isolation layer 110. In example embodiments, the insulating region 175 may have a shape extending into the interior of the substrate 101. The insulating region 175 may include at least one of oxide, nitride, and oxynitride, and may include, for example, a low dielectric constant material.

[0045] The upper insulating layer 190 may be disposed to cover the upper surface of the contact structure 180 and the upper surface of the insulating region 175. The upper insulating layer 190 may include at least one of oxide, nitride, and oxynitride, such as a low dielectric constant material. According to example embodiments, the upper insulating layer 190 may include a plurality of insulating layers.

[0046] In the following description of the exemplary embodiments, the above referenced Figures 1 to 2D Those described are repeated descriptions.

[0047] Figure 3A and Figure 3Bis a cross-sectional view illustrating a semiconductor device according to example embodiments. Figure 3A The diagram shows the Figure 1 The cross section corresponding to the cross section cut taken by the line II', and Figure 3B The diagram shows the Figure 1 The cross-sectional cut corresponding to the cross-sectional cut taken along the line II-II'.

[0048] refer to Figure 3A and Figure 3B In the semiconductor device 100a, the device isolation layer 110 may cover the side surface of the active region 105 adjacent to the separation pattern 120 and the side surface opposite to the separation pattern 120. The interlayer insulating layer 170 may cover at least a portion of the active region 105, the source / drain region 130, and the contact structure on the device isolation layer 110, and the interlayer insulating layer 170 may cover the upper surface of the gate electrode 165. The portion of the interlayer insulating layer 170 covering the upper surface of the gate electrode 165 may be referred to as a gate covering layer.

[0049] Figure 4 is a cross-sectional view illustrating a semiconductor device according to example embodiments. Figure 4 The diagram shows the Figure 1 The cross section corresponds to the cross section cut taken along line II'.

[0050] refer to Figure 4 , the separation pattern 120 of the semiconductor device 100b may be disposed to contact the source / drain region 130. The separation pattern 120 may be disposed to recess a portion of the source / drain region 130. Even in this case, the separation pattern 120 may be disposed to be spaced apart from the active region 105 and the substrate 101.

[0051] Figure 5 is a cross-sectional view illustrating a semiconductor device according to example embodiments. Figure 5 The diagram shows the Figure 1 The cross-sectional view corresponds to the cross-sectional cut taken along the line II' in FIG.

[0052] refer to Figure 5 , the separation pattern 120 of the semiconductor device 100c may extend in a third direction (e.g., Z direction) perpendicular to the upper surface (the second direction) of the substrate 101 to extend into the interior (inner region) of the substrate 101, and may penetrate the device isolation layer 110. Therefore, the separation pattern 120 may contact the contact structure 180, the interlayer insulating layer 170, the device isolation layer 110, and the substrate 101 at the same time. Figure 5As illustrated, the separation pattern 120 may be spaced apart from the source / drain region 130 , but embodiments of the present disclosure are not limited thereto. In example embodiments, the separation pattern 120 may also contact the source / drain region 130 .

[0053] Figure 6 is a cross-sectional view illustrating a semiconductor device according to example embodiments. Figure 6 The diagram shows the Figure 1 The cross section corresponds to the cross section cut taken along line II'.

[0054] refer to Figure 6 The inner surface of the contact structure 180 connecting the lower surface of the first part 180a and the lower surface of the second part 180b can cover the side surface of the separation pattern 120, and the lowermost end of the inner surface can be the lowermost end of the second part 180b and can contact the separation pattern 120.

[0055] Figure 7 is a cross-sectional view illustrating a semiconductor device according to example embodiments. Figures 8 to 10 is a cross-sectional view illustrating a semiconductor device according to an example embodiment. Figure 7 Some components of a semiconductor device are illustrated in FIG.

[0056] Figure 8 Picture shows Figure 7 A cross section of the semiconductor device taken along line VV'. Fig. 9 Picture shows Figure 7 A cross section of the semiconductor device taken along line VI-VI'. Fig.10 Picture shows Figure 7 A cross section of the semiconductor device taken along line VII-VII'.

[0057] refer to Figures 7 to 10 , the semiconductor device 100e may include a first active region 105a, a second active region 105b, a first gate structure 160a, a second gate structure 160b, a separation pattern 120, an insulating region 175, and contact structures 180, 181S, and 181G. Figure 7 Only portions of contact structures 180 , 181S, and 181G are illustrated.

[0058] The first active region 105a and the second active region 105b may extend in a first direction (e.g., X direction) and may be arranged to be spaced apart in a second direction (e.g., Y direction) intersecting the first direction. The first active region 105a may include impurities having a first conductivity type, and the second active region 105b may include impurities having a second conductivity type different from the first conductivity type. When the first conductivity type is a P type, the impurities of the first conductivity type may include at least one of boron (B), aluminum (Al), gallium (Ga), and indium (In), and in this case, the second conductivity type is an N type, and the impurities of the second conductivity type may include at least one of phosphorus (P), arsenic (As), and antimony (Sb).

[0059] The first source / drain region 130 a may be disposed on the first active region 105 a , and the second source / drain region 130 b may be disposed on the second active region 105 b .

[0060] The first and second gate structures 160a and 160b may extend along a second direction (eg, Y direction) intersecting the first and second active regions 105a and 105b on the first and second active regions 105a and 105b and may be disposed to be spaced apart in the first direction (eg, X direction).

[0061] The first gate structure 160a may be formed by a recessed region RS (see Fig.12 ) and may be disposed to contact the separation pattern 120 filling the recessed region (RS). According to an example embodiment, in the region, at least a portion of the first gate structure 160a and the second gate structure 160b may be separated by another recessed region. In an embodiment, the recessed region may be in a shape extending in one direction or in a hole shape. In an example embodiment, according to a process, the channel structures 140 disposed on both sides of the insulating region 175 may initially be configured as one body, but may be configured to be separated by the insulating region 175.

[0062] The separation pattern 120 may extend in a first direction (e.g., X direction) to separate the plurality of first gate structures 160a. Depending on the embodiment, the separation pattern 120 may further extend in the X direction to separate portions of the plurality of second gate structures 160b. Depending on the embodiment, the number of gate structures separated by the separation pattern 120 may vary, and there may be a plurality of separation patterns 120. In a cross section in the X direction (see Fig.10 ), the separation pattern 120 may further include a portion having a concave upper surface in addition to a portion where the first portion 180 a of the contact structure 180 is present, and the portion may be filled with the upper insulating layer 190.

[0063] The insulating region 175 may be disposed between adjacent first active regions 105a to contact the first active regions 105a, or may be disposed between adjacent second active regions 105b to contact the second active regions 105b. Each of the first active region 105a and the first source / drain region 130a may initially be formed integrally, but may be separated by the insulating region 175. Likewise, each of the second active region 105b and the second source / drain region 130b may initially be formed integrally, but may be separated by the insulating region 175. The insulating region 175 may be disposed to penetrate each of the first gate structure 160a and the second gate structure 160b. In example embodiments, the insulating region 175 may not exist, and in this case, the insulating region 175 may include a first gate structure 160a and a second gate structure 160b. Figure 3A and Figure 3B The semiconductor device 100a has the same structure as described in FIG.

[0064] The contact structures 180, 181S, and 181G may include a contact structure 180 that simultaneously contacts the separation pattern 120 and the first source / drain region 130a and the second source / drain region 130b, a (source / drain) contact structure 181S disposed on the source / drain regions 130a and 130b, and a (gate) contact structure 181G disposed on the gate structures 160a and 160b. Depending on the embodiment, the number, position, etc. of the contact structures 180, 181S, and 181G may vary.

[0065] Depending on the process, the upper insulating layer 190 may include a protrusion extending into the interior of the interlayer insulating layer 170. The upper insulating layer 190 may include a protrusion extending into the interior of the substrate 101 through the interlayer insulating layer 170 and the device isolation layer 110, and in the cross section in the y direction (see Figure 8 ), the protrusions may be disposed to be spaced apart from each other with the contact structure 180 and the insulating region 175 interposed therebetween.

[0066] In with Figures 7 to 10 The contents not specifically described in the relevant description may be understood as Figures 1 to 6 The configuration of the semiconductor device described in the accompanying drawings is the same as or similar to that of the semiconductor device described in the accompanying drawings.

[0067] Figures 11 to 19 2 is a diagram illustrating a process sequence for explaining a method of manufacturing a semiconductor device according to example embodiments. Figures 11 to 19 The corresponding cross-sectional view included in the diagram shows from the left side Figure 2A , Figure 2B and Figure 2C A cross-sectional view of a semiconductor device is shown in the process.

[0068] refer to Fig.11An active region 105, first to fourth channel layers 141, 142, 143 and 144, a gate structure 160, a device isolation layer 110, an interlayer insulating layer 170 and an insulating region 175 may be formed on a substrate 101. A preliminary protection layer 191 may be formed on the interlayer insulating layer 170.

[0069] The insulating region 175 may be formed by removing a portion of the sacrificial layer, the first to fourth channel layers 141, 142, 143, and 144, and the active region 105 stacked on the substrate 101 and filling the removed region. The insulating region 175 may be formed by removing a portion of the sacrificial layer, but the embodiments of the present disclosure are not limited thereto. In example embodiments, the insulating region 175 may be formed by removing a portion of the gate electrode 165 after the sacrificial layer is removed and the gate electrode 165 is formed.

[0070] refer to Fig.12 , a recessed region RS penetrating the interlayer insulating layer 170 and the gate structure 160 and extending into the inner portion of the device isolation layer 110 may be formed. The gate structure 160 may be separated by the recessed region RS. Figure 1 , the recessed region RS may be in the form of a line extending in a first direction (eg, X direction). The recessed region RS may be formed to be spaced apart from the substrate 101, the active region 105, and the source / drain region 130, but the embodiments of the present disclosure are not limited thereto. Figure 4 In the process of manufacturing the semiconductor device 100b, the recessed region RS may also be formed by removing a portion of the source / drain region 130. Figure 5 In the process of manufacturing the semiconductor device 100 c , the recess region RS may extend into the inside of the substrate 101 .

[0071] refer to Fig.13 , a separation pattern 120 may be formed to fill the recessed region RS. The separation pattern 120 may be formed of a material having an etch selectivity different from that of the interlayer insulating layer 170. For example, when the interlayer insulating layer 170 includes silicon oxide, the separation pattern 120 may include silicon nitride.

[0072] refer to Fig.14 , portions of the preliminary protection layer 191 and the separation pattern 120 located at a height higher than the upper surface of the interlayer insulating layer 170 may be removed. Fig.14 The subsequent process may be used to form Figure 2A The process shown has a structure including a first portion 180 a in contact with the separation pattern 120 and a second portion 180 b in contact with the source / drain region 130 .

[0073] refer to Fig.15, masks 81 and 82 may be formed on the upper surface of the interlayer insulating layer 170 and the upper surface of the separation pattern 120. The upper mask 82 may include a layer for opening the upper surface of the separation pattern 120 after etching. Figure 2A The first portion 180a has an opening.

[0074] refer to Fig.16 , you can use Fig.15 The openings of the upper mask 82 expose portions of the lower mask 81 to form openings of the lower mask 81 , and the upper mask 82 may be removed.

[0075] refer to Fig.17 , a portion of an upper portion of the separation pattern 120 having an etching selectivity different from that of the interlayer insulating layer 170 may be removed. The upper portion etched by the separation pattern 120 may be a portion exposed by the opening of the lower mask 81.

[0076] refer to Fig.18 , the space where the separation pattern 120 is removed may be filled with a material having the same etching selectivity as the interlayer insulating layer 170. Even if the separation pattern 120 is formed in the form of a line extending in one direction through this process, the contact structure 180 can be formed through a self-aligned contact (SAC) process.

[0077] refer to Fig.19 , a portion of the interlayer insulating layer 170 having an etching selectivity different from that of the separation pattern 120 may be removed. In this case, a portion of the source / drain region 130 may be removed together. Thereafter, a contact structure 180 may be formed to fill the removed region. Figure 2A , can be manufactured by removing a portion of the upper portion of the contact structure 180 Figure 2A A semiconductor device 100 is provided.

[0078] By removing Figures 16 to 18 Even if the upper portion of the contact structure 180 is removed, the first portion 180a may remain. In this process, even if the separation pattern 120 is formed in the form of a line extending in one direction, the contact structure 180 may be formed by a self-aligned contact (SAC) process, so that a semiconductor device with improved integration and reliability may be provided.

[0079] As explained above, by optimizing the structure of the contact structure connected to the source / drain regions, a semiconductor device with improved integration and electrical characteristics can be provided.

[0080] While example embodiments have been illustrated and described above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A semiconductor device, comprising: substrate; an active region extending along a first direction on the substrate; a gate structure extending along a second direction on the active region and intersecting the active region; a source / drain region, the source / drain region being located on the active region on at least one side of the gate structure; a separation pattern extending in the first direction and separating the gate structures; as well as a contact structure, the contact structure being located on the separation pattern, intersecting the separation pattern and electrically connected to the source / drain region, Wherein, the contact structure comprises a first part and a second part, wherein the first portion contacts the separation pattern, wherein the second portion contacts the source / drain region, wherein the lower surface of the second portion is at a lower height than the lower surface of the first portion, and Wherein, the lowermost end of the contact structure is spaced apart from the separation pattern.

2. The semiconductor device according to claim 1, wherein The separation pattern is spaced apart from the source / drain region.

3. The semiconductor device according to claim 1, wherein The width of the separation pattern decreases toward the substrate.

4. The semiconductor device according to claim 1, wherein: The separation pattern extends in a third direction perpendicular to an upper surface of the substrate and extends into the substrate.

5. The semiconductor device according to claim 1, wherein The upper surface of the separation pattern includes a first upper surface and a second upper surface, wherein the first upper surface contacts the lower surface of the first portion, and Wherein, the second upper surface is coplanar with an upper surface of the first portion.

6. The semiconductor device according to claim 1, wherein The lower surface of the first portion is at a height higher than an upper end of the source / drain region.

7. The semiconductor device according to claim 1, wherein The separation pattern is spaced apart from the substrate.

8. The semiconductor device according to claim 1, further comprising: a device isolation layer in the substrate and surrounding the active area; as well as an interlayer insulating layer, the interlayer insulating layer covering a portion of the source / drain region on the device isolation layer, The separation pattern penetrates the interlayer insulating layer and extends into the device isolation layer.

9. The semiconductor device according to claim 8, wherein: The interlayer insulating layer includes silicon oxide, and Wherein, the separation pattern comprises silicon nitride. 10 . The semiconductor device according to claim 1 , further comprising an insulating region covering a side surface of the contact structure, a side surface of the source / drain region, and a side surface of the active region.

11. The semiconductor device according to claim 1, wherein The separation pattern contacts the source / drain region.

12. The semiconductor device according to claim 1, wherein A first thickness of the first portion of the contact structure is less than a second thickness of the second portion of the contact structure.

13. The semiconductor device according to claim 1, further comprising: a plurality of channel layers, the plurality of channel layers being spaced apart from each other along a third direction perpendicular to the upper surface of the substrate on the active region and surrounded by the gate structure, The plurality of channel layers include a first channel layer, a second channel layer, a third channel layer and a fourth channel layer sequentially arranged along the third direction, and The lower surface of the second portion is at a height lower than that of the lower surface of the third channel layer.

14. A semiconductor device, comprising: substrate; an active region extending along a first direction on the substrate; a gate structure extending along a second direction on the active region and intersecting the active region; a source / drain region, the source / drain region being located on the active region on at least one side of the gate structure; as well as a contact structure electrically connected to the source / drain region, The lower surface of the contact structure includes a first surface, a second surface located at a height lower than the first surface, and an inner surface connecting the first surface and the second surface. wherein the first surface is spaced apart from the source / drain region, wherein the second surface contacts the source / drain region, and The inner surface is inclined so that the width of the contact structure becomes narrower toward the substrate.

15. The semiconductor device according to claim 14, further comprising a separation pattern contacting the first surface and extending in the first direction, in, The gate structures are separated by the separation patterns.

16. The semiconductor device according to claim 15, wherein: At least a portion of the inner side surface is spaced apart from the partition pattern.

17. The semiconductor device according to claim 15, wherein: The second surface is spaced apart from the separation pattern in the second direction.

18. A semiconductor device, comprising: substrate; a plurality of active regions extending along a first direction on the substrate and spaced apart from each other in a second direction intersecting the first direction; a plurality of gate structures extending along the second direction on the plurality of active regions; a plurality of source / drain regions, the plurality of source / drain regions being located on at least one side of the plurality of gate structures on the plurality of active regions; a separation pattern extending between the plurality of source / drain regions along the first direction and penetrating at least one gate structure among the plurality of gate structures to separate the at least one gate structure; as well as a contact structure, the contact structure contacting the separation pattern on the separation pattern and contacting a first source / drain region and a second source / drain region among the plurality of source / drain regions, The first lower surface of the contact structure is at a higher height than the second lower surface of the contact structure, the first lower surface of the contact structure contacts the separation pattern, and the second lower surface of the contact structure contacts the first source / drain region and the second source / drain region. wherein at least a portion of the inner side surface of the contact structure connecting the first lower surface and the second lower surface is spaced apart from the separation pattern, and The first source / drain region and the second source / drain region include impurities with different conductivity types.

19. The semiconductor device according to claim 18, wherein: The first source / drain region and the second source / drain region have symmetrical shapes with respect to the separation pattern.

20. The semiconductor device according to claim 18, wherein The contact structure extends in the second direction, and The length of the contact structure extending in the second direction is greater than the minimum distance between the plurality of active regions.

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