Semiconductor structure comprising substrate with silicon insulation

Abstract

A semiconductor structure including a silicon-coated insulating layer (SOI) substrate and a method of forming the same, the semiconductor structure including a silicon-coated insulating layer substrate including a silicon layer and an insulating layer stacked from bottom to top, a phosphate glass (PGS) on the insulating layer, and a fluosilicate glass on the insulating layer, the silicon layer and the insulating layer being stacked from bottom to top, the fluosilicate glass including a silicon layer and an insulating layer stacked from bottom to top, the silicon layer and the insulating layer being stacked from bottom to top, the silicon layer and the insulating layer being stacked from bottom to top, the silicon layer and the insulating layer being stacked from bottom to top, and the silicon layer and the insulating layer being stacked from bottom to top. FSG) is located on the phosphate glass.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a semiconductor structure including a silicon-on-insulator (SOI) substrate and a manufacturing method thereof. Background Art

[0002] With the advancement of semiconductor manufacturing technology, the number of components per unit area has gradually increased, and the semiconductor structure has begun to develop in the direction of three-dimensional stacking. In addition, in order to improve the yield of the manufacturing process and reduce the difficulty of the manufacturing process, different components may be made on different chips, and then the two chips are bonded to each other, which can greatly improve the efficiency of the manufacturing process.

[0003] When chips are bonded, the bonding quality at the interface between the two chips will affect the performance of the entire semiconductor device, and defects are more likely to occur on the chip interface surface before bonding. Therefore, how to reduce these defects to improve the quality of the semiconductor structure after bonding is one of the development directions in this field. Summary of the invention

[0004] The invention provides a semiconductor structure including a silicon-on-insulator (SOI) substrate, including a silicon-on-insulator substrate, wherein the silicon-on-insulator substrate includes a silicon layer and an insulating layer stacked from bottom to top, a phosphate glass (Phosphosilicate Glass, PGS) located on the insulating layer, and a fluorosilicate glass (Fluorosilicate Glass, FSG) located on the phosphate glass.

[0005] The present invention further provides a method for forming a semiconductor structure including a silicon-on-insulator (SOI) substrate, comprising providing a silicon-on-insulator substrate, wherein the silicon-on-insulator substrate includes a silicon layer and an insulating layer stacked from bottom to top, forming a phosphate glass (Phosphosilicate Glass, PGS) located on the insulating layer, and forming a fluorosilicate glass (Fluorosilicate Glass, FSG) located on the phosphate glass.

[0006] The present invention is characterized in that the applicant has found that if only fluorosilicate glass is formed on the back of the SOI substrate, then when the back surface planarization step is performed, the ions contained in the polishing liquid are easily infiltrated into the doped region of the transistor, thereby affecting the electrical properties of the transistor. Therefore, in addition to forming the fluorosilicate glass, the present invention further forms a phosphate glass between the SOI substrate and the fluorosilicate glass, wherein the phosphorus contained in the phosphate glass is good at grabbing the 1A group or 2A group ions (such as potassium ions) in the polishing liquid, thereby reducing the probability of ions penetrating into the transistor and improving the yield of the product. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1-2 is a schematic cross-sectional view of a semiconductor structure including a silicon-on-insulator (SOI) substrate according to an embodiment of the present invention;

[0008] Figure 3 FIG. 4 is a schematic cross-sectional view of a semiconductor structure including a silicon-on-insulator (SOI) substrate according to another embodiment of the present invention.

[0009] Explanation of symbols

[0010] 10: Base

[0011] 10A: Silicon layer

[0012] 10B: Silicon oxide layer

[0013] 10C: Silicon Oxynitride Layer

[0014] 12: Well region

[0015] 14: Dielectric layer

[0016] 16: Dielectric layer

[0017] 18: Dielectric layer

[0018] 20: Gap wall

[0019] 22: Fluorosilicate glass

[0020] 24: Phosphate glass

[0021] CT: Contact structure

[0022] D: Drain region

[0023] G: Gate

[0024] LDD: Lightly Doped Drain

[0025] M1: Metal layer

[0026] M2: Metal layer

[0027] S: Source region

[0028] T: Transistor

[0029] STI: Shallow Trench Isolation

[0030] V1: Contact column DETAILED DESCRIPTION

[0031] In order to enable a person skilled in the art to further understand the present invention, the preferred embodiments of the present invention are listed below, and the components and intended effects of the present invention are described in detail with reference to the accompanying drawings.

[0032] For the convenience of explanation, the drawings of the present invention are only for illustration to make it easier to understand the present invention, and the detailed proportions can be adjusted according to the design requirements. The upper and lower relationships of the relative elements in the drawings described in the text should be understood by those skilled in the art to refer to the relative positions of the objects, so they can be flipped to present the same components, which should all fall within the scope of the disclosure of this specification, and will be explained here first.

[0033] Figure 1 FIG. 4 is a cross-sectional view of a semiconductor structure including a silicon-on-insulator (SOI) substrate according to an embodiment of the present invention. Figure 1 As shown, a substrate 10 is provided. The substrate 10 is a silicon on insulator (SOI) substrate, which includes a silicon layer 10A located on an insulating layer, wherein the material of the silicon layer 10A is silicon, and the material of the insulating layer is, for example, silicon oxide, silicon nitride or silicon oxynitride. In this embodiment, the insulating layer is a composite layer, including a silicon oxide layer 10B located on a silicon oxynitride layer 10C, but the present invention is not limited thereto. Next, a transistor T is formed above the silicon layer 10A, wherein the transistor T includes a gate G, a source region S and a drain region D. In more detail, a well region 12, a source region S, a drain region D, and a lightly doped drain LDD are formed in the silicon layer 10A by doping, and a shallow trench isolation STI is formed outside the source region S and the drain region D. In addition, in this embodiment, if the transistor is an N-type transistor, the source region S, the drain region D and the lightly doped drain LDD are doped with N-type ions, and the well region 12 is doped with P-type ions. However, the present invention is not limited thereto. The material of the shallow trench isolation STI is, for example, silicon oxide, which is the same material as the silicon oxide layer 10B ( Figure 1 The interface between the two is represented by a dotted line).

[0034] A multilayer structure may be included above the silicon layer 10A, and these structures include a multilayer dielectric layer, and the dielectric layer may include a plurality of components, such as a gate of a transistor, a contact structure or a wire structure. In more detail, the dielectric layer 14, the dielectric layer 16 and the dielectric layer 18 are located on the silicon layer 10A, wherein the material of the dielectric layers 14, 16 and 18 is, for example, silicon oxide, silicon nitride, silicon oxynitride, ultra-low dielectric constant material (ULK), low dielectric constant material (low-k material), fluorosilicate glass (FSG), etc., but the present invention is not limited thereto. Spacers 20 are formed on both sides of the gate G, and the gate G and the spacers 20 are both located in the dielectric layer 14, and the material of the gate G may include polysilicon or metal, and the material of the spacers 20 is, for example, silicon oxide, silicon nitride or silicon oxynitride. In addition, the dielectric layer 14 also includes a contact structure CT, which electrically connects the source region S and the drain region D. The contact structure CT is further connected to the metal layer M1, the contact column V1 and the metal layer M2 included in the dielectric layers 16 and 18 located above. These metal layers and contact columns are used to connect the transistor T to other components, such as various active or passive components formed subsequently, or to other chips by means of heterogeneous contacts (hybrid bonds).

[0035] It is worth noting that other dielectric layers or metal layers and other components may be further formed on the metal layer M2 . Figure 1 Most of the transistor structures and other elements described above belong to the prior art of the present invention, so the parts not described in detail can refer to the existing transistor structures or related elements and will not be repeated here.

[0036] like Figure 1 As shown, Figure 1 The semiconductor structure shown defines a front side and a back side, wherein the front side is the side where the transistor T, metal layers M1, M2 and other components are formed as described above, and the back side is the bottom of the substrate 10, that is, the side where the silicon oxynitride layer 10C is exposed. As described above, in subsequent steps, the front side of the semiconductor structure may be connected to other components, or connected to other chips through hybrid bonds and other methods. Subsequently, in order to effectively increase the density of the semiconductor structure, the bonded chip is turned over, that is, some other components, such as inductors or various metal lines, are formed on the back side of the semiconductor structure.

[0037] like Figure 2 As shown, Figure 1The semiconductor structure shown is flipped (the reverse side of the flipped semiconductor structure faces upward and the front side faces downward), and a fluorosilicate glass (FSG) 22 is formed on the silicon oxynitride layer 10C. The fluorosilicate glass 22 can be used as the material of the first dielectric layer on the back side of the semiconductor, that is, other elements such as wires can be formed in the fluorosilicate glass 22, which are not drawn here for the sake of simplicity. In this embodiment, the fluorosilicate glass 22 is located on the back side of the SOI substrate 10 of the semiconductor structure, that is, the fluorosilicate glass 22 is in direct contact with the silicon oxynitride layer 10C of the SOI substrate 10. In this embodiment, the thickness of the fluorosilicate glass 22 is about 3500 angstroms, but is not limited thereto.

[0038] It is worth noting that in some other embodiments, the SOI substrate may also include a three-layer stacked structure of silicon layer-insulating layer-silicon layer, and when the components on the front side of the SOI substrate are formed, the SOI substrate is turned over to the back side, and then the top silicon layer (i.e., the original bottom silicon layer) after turning over is removed by a flattening step, so that the middle insulating layer (i.e., silicon oxide layer 10B) is exposed, and then the silicon oxynitride layer 10C is formed. In other words, the silicon oxynitride layer 10C is formed on the silicon oxide layer 10B after the back side manufacturing process, rather than being formed at the beginning. This implementation step also falls within the scope of the present invention.

[0039] Next, the back side device manufacturing process is performed, such as forming devices or wires and performing a planarization step. However, the applicant has found that the planarization step is, for example, chemical mechanical polishing (CMP), in which the polishing liquid contains ions that easily pass through the fluorosilicate glass. For example, the polishing liquid used in this embodiment contains potassium ions (K+), which act as a dispersant in the polishing liquid to prevent particle agglomeration, and potassium ions easily pass through the fluorosilicate glass. It is understandable that the present invention can use other types of polishing liquids, and other polishing liquids may contain, for example, 1A group (IA group) element ions: lithium (Li), sodium (Na), potassium (K), rubidium (Rb), cesium (Cs), francium (Fr) or 2A group (IIA group) element ions: beryllium (Be), magnesium (Mg), calcium (Ca), strontium (Sr), barium (Ba), radium (Ra), etc., and these ions also easily pass through the fluorosilicate glass. If the first dielectric layer on the back side of the SOI substrate 10 is a fluorosilicate glass 22, when the back side is subjected to chemical mechanical polishing, the 1A group ions or 2A group ions will easily pass through the fluorosilicate glass 22, and then penetrate into the channel region of the transistor T and affect the electrical properties of the transistor. In particular, when there is no back gate formed on the back side of the semiconductor structure, the ions that penetrate will affect the electrical properties of the transistor because there is no back gate to block them.

[0040] Therefore, in order to solve the above-mentioned ion penetration through fluorosilicate glass and affect the electrical properties, please refer to Figure 3 , Figure 3 A cross-sectional view of a semiconductor structure including a silicon-on-insulator (SOI) substrate according to another embodiment of the present invention is shown. Figure 3 and Figure 2 Most of the components are the same and will not be described in detail here. Figure 2 The structure of the present invention is different in that a phosphate glass (PGS) 24 is included between the silicon oxynitride layer 10C and the fluorosilicate glass 22. In this embodiment, the thickness of the phosphate glass 24 is about 1000 angstroms, while the thickness of the fluorosilicate glass 22 is about 2500 angstroms. Therefore, the total thickness of the phosphate glass 24 and the fluorosilicate glass 22 is about 3500 angstroms, which is roughly the same as the above-mentioned Figure 2 The thickness of the fluorosilicate glass 22 in FIG.

[0041] In this embodiment, the function of the phosphate glass 24 is to collect and block potassium ions. More specifically, the phosphate glass 24 contains phosphorus trioxide (P2O3), and phosphorus trioxide is easy to combine with potassium ions to form K2P2O3, which prevents potassium ions from continuing to penetrate through the fluorosilicate glass 22. Therefore, in this embodiment, a phosphate glass 24 is formed between the fluorosilicate glass 22 and the silicon oxynitride layer 10C, which can reduce the probability of potassium ions penetrating into the channel region of the transistor when the back of the semiconductor structure is subjected to chemical mechanical polishing, thereby improving the quality of the overall device.

[0042] In summary, the present invention provides a semiconductor structure including a silicon-on-insulator (SOI) substrate, including a silicon-on-insulator (SOI) substrate 10, wherein the silicon-on-insulator substrate 10 includes a silicon layer 10A and an insulating layer (a silicon oxide layer 10B and a silicon oxynitride layer 10C) stacked from bottom to top, a phosphate glass (Phosphosilicate Glass, PGS) 24 located on the insulating layer, and a fluorosilicate glass (Fluorosilicate Glass, FSG) 22 located on the phosphate glass 24 (please refer to Figure 3 ).

[0043] The present invention further provides a method for forming a semiconductor structure including a silicon-on-insulator (SOI) substrate, comprising providing a silicon-on-insulator substrate 10, wherein the silicon-on-insulator substrate 10 includes a silicon layer 10A and an insulating layer (a silicon oxide layer 10B and a silicon oxynitride layer 10C) stacked from bottom to top, forming a phosphate glass (Phosphosilicate Glass, PGS) 24 located on the insulating layer, and forming a fluorosilicate glass (Fluorosilicate Glass, FSG) 22 located on the phosphate glass 24 (please refer to Figure 3 ).

[0044] In some embodiments of the present invention, a thickness of the phosphate glass 24 is smaller than a thickness of the fluorosilicate glass 22 (eg, 1000 angstroms and 2500 angstroms, respectively).

[0045] In some embodiments of the present invention, the insulating layer includes a silicon oxide layer 10B and a silicon oxynitride layer 10C stacked from bottom to top (eg, Figure 3 ).

[0046] In some embodiments of the present invention, the phosphate glass 24 directly contacts the silicon oxynitride layer 10C.

[0047] In some embodiments of the present invention, a transistor T is further included, which is located below the silicon layer 10A.

[0048] In some embodiments of the present invention, the transistor T includes a source region S and a drain region D located in the silicon layer 10A, and a gate G located below the silicon layer 10A.

[0049] In some embodiments of the present invention, a dielectric layer 14 is further included below the silicon layer.

[0050] In some embodiments of the present invention, a plurality of contact structures CT are further included, which are located in the dielectric layer 14 and electrically connected to the source region S and the drain region D.

[0051] In some embodiments of the present invention, after the fluorosilicate glass 22 is formed, a planarization step (such as chemical mechanical polishing) is further included on the fluorosilicate glass 22 .

[0052] In some embodiments of the present invention, during the planarization step, a plurality of ions (eg, potassium ions) diffuse from a polishing liquid in the planarization step into the fluorosilicate glass 22 and are blocked by the phosphate glass 24 .

[0053] In some embodiments of the present invention, the types of the plurality of ions include Group 1A or Group 2A ions.

[0054] The present invention is characterized in that the applicant has found that if only fluorosilicate glass is formed on the back of the SOI substrate, then when the back surface planarization step is performed, the ions contained in the polishing liquid are easily infiltrated into the doped region of the transistor, thereby affecting the electrical properties of the transistor. Therefore, in addition to forming the fluorosilicate glass, the present invention further forms a phosphate glass between the SOI substrate and the fluorosilicate glass, wherein the phosphorus contained in the phosphate glass is good at grabbing the 1A group or 2A group ions (such as potassium ions) in the polishing liquid, thereby reducing the probability of ions penetrating into the transistor and improving the yield of the product.

[0055] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A semiconductor structure comprising a silicon-on-insulator (SOI) substrate, comprising: A silicon-coated insulating layer substrate, wherein the silicon-coated insulating layer substrate comprises a silicon layer and an insulating layer stacked from bottom to top; Phosphoglass (PGS), located on the insulating layer; as well as Fluorosilicate glass (FSG) is located on the phosphate glass. 2 . The semiconductor structure comprising a silicon-on-insulator substrate as claimed in claim 1 , wherein a thickness of the phosphate glass is smaller than a thickness of the fluorosilicate glass. 3 . The semiconductor structure comprising a silicon-on-insulator substrate as claimed in claim 1 , wherein the insulating layer comprises a silicon oxide layer and a silicon oxynitride layer stacked from bottom to top. 4 . The semiconductor structure comprising a silicon-on-insulator substrate as claimed in claim 3 , wherein the phosphate glass directly contacts the silicon oxynitride layer. 5 . The semiconductor structure comprising a silicon-on-insulator substrate as claimed in claim 1 , further comprising a transistor located below the silicon layer. 6 . The semiconductor structure comprising a silicon-on-insulator substrate as claimed in claim 5 , wherein the transistor comprises a source region and a drain region located in the silicon layer, and a gate is located below the silicon layer. 7 . The semiconductor structure comprising a silicon-on-insulator substrate as claimed in claim 6 , further comprising a dielectric layer located below the silicon layer. 8 . The semiconductor structure comprising a silicon-on-insulator substrate as claimed in claim 7 , further comprising a plurality of contact structures located in the dielectric layer and electrically connected to the source region and the drain region.

9. A method for forming a semiconductor structure including a silicon-on-insulator (SOI) substrate, comprising: Providing a silicon-coated insulating layer substrate, wherein the silicon-coated insulating layer substrate comprises a silicon layer and an insulating layer stacked from bottom to top; forming phosphate glass (PGS) on the insulating layer; as well as Fluorosilicate glass (FSG) is formed on the phosphate glass. 10 . The method for forming a semiconductor structure comprising a silicon-on-insulator substrate as claimed in claim 9 , wherein a thickness of the phosphate glass is smaller than a thickness of the fluorosilicate glass. 11 . The method for forming a semiconductor structure comprising a silicon-on-insulator substrate as claimed in claim 9 , wherein the insulating layer comprises a silicon oxide layer and a silicon oxynitride layer stacked from bottom to top. 12 . The method for forming a semiconductor structure comprising a silicon-on-insulator substrate as claimed in claim 11 , wherein the phosphate glass directly contacts the silicon oxynitride layer. 13 . The method for forming a semiconductor structure comprising a silicon-on-insulator substrate as claimed in claim 9 , further comprising forming a transistor located below the silicon layer. 14 . The method for forming a semiconductor structure comprising a silicon-on-insulator substrate as claimed in claim 13 , wherein the transistor comprises a source region and a drain region located in the silicon layer, and a gate is located below the silicon layer. 15 . The method for forming a semiconductor structure comprising a silicon-on-insulator substrate as claimed in claim 14 , further comprising forming a dielectric layer below the silicon layer. 16 . The method for forming a semiconductor structure comprising a silicon-on-insulator substrate as claimed in claim 15 , further comprising forming a plurality of contact structures located in the dielectric layer and electrically connecting the source region and the drain region. 17 . The method for forming a semiconductor structure comprising a silicon-on-insulator substrate as claimed in claim 9 , wherein after the fluorosilicate glass is completed, the method further comprises a step of planarizing the fluorosilicate glass.

18. The method for forming a semiconductor structure comprising a silicon-on-insulator substrate as claimed in claim 17, wherein during the planarization step, a plurality of ions diffuse from the polishing liquid in the planarization step into the fluorosilicate glass and are blocked by the phosphate glass. 19 . The method for forming a semiconductor structure comprising a silicon-on-insulator substrate as claimed in claim 18 , wherein the types of the plurality of ions include Group 1A or Group 2A ions.

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