Resistive memory structure

Abstract

The invention provides a resistive memory structure. The resistive memory structure includes a transistor device and a resistive memory device. The transistor device includes a gate. The resistive memory device is electrically connected to the gate of the transistor device. The resistive memory structure can have better electrical performance.

Description

Technical Field

[0001] The invention relates to a semiconductor structure, and in particular to a resistive memory structure. Background Art

[0002] Resistive memory (e.g., resistive random access memory (RRAM)) structures have the potential advantages of low power consumption, high-speed operation, and high density, and are therefore very suitable as the next generation of memory structures. However, how to further improve the electrical performance (e.g., endurance) of the resistive memory structure is currently a goal of continuous efforts. Summary of the invention

[0003] The invention provides a resistive memory structure which has better electrical performance.

[0004] The present invention provides a resistive memory structure, comprising a transistor device and a resistive memory device. The transistor device comprises a gate. The resistive memory device is electrically connected to the gate of the transistor device.

[0005] According to an embodiment of the present invention, in the resistive memory structure, the transistor device and the resistive memory device may share a gate.

[0006] According to an embodiment of the present invention, in the resistive memory structure, a substrate may be further included. The transistor device may be located on the substrate. The resistive memory device may be located on the transistor device.

[0007] According to an embodiment of the present invention, in the resistive memory structure, the transistor device may further include a gate dielectric layer, a first doped region, a second doped region and a spacer. The gate dielectric layer is located between the gate and the substrate. The first doped region and the second doped region are located in the substrate on both sides of the gate. The spacer is located on the sidewall of the gate and the sidewall of the gate dielectric layer.

[0008] According to an embodiment of the present invention, in the resistive memory structure, the gate dielectric layer may be a single-layer structure.

[0009] According to an embodiment of the present invention, in the resistive memory structure, the gate dielectric layer may be a multi-layer structure.

[0010] According to an embodiment of the present invention, in the resistive memory structure, the gate dielectric layer may include a first dielectric layer and a second dielectric layer. The first dielectric layer is located between the gate and the substrate. The second dielectric layer is located between the gate and the first dielectric layer.

[0011] According to an embodiment of the present invention, in the resistive memory structure, the material of the first dielectric layer may include silicon oxide, and the material of the second dielectric layer may include a high-k material.

[0012] According to an embodiment of the present invention, in the resistive memory structure, the resistive memory device may include a gate, an electrode and a variable resistance layer. The electrode is located on the gate. The variable resistance layer is located between the electrode and the gate.

[0013] According to an embodiment of the present invention, in the resistive memory structure, the electrode may be a single-layer structure.

[0014] According to an embodiment of the present invention, in the resistive memory structure, the electrode may be a multi-layer structure.

[0015] According to an embodiment of the present invention, in the resistive memory structure, the electrode may include a first conductive layer and a second conductive layer. The first conductive layer is located on the gate. The cross-sectional shape of the first conductive layer may include a U shape. The second conductive layer is located on the first conductive layer.

[0016] According to an embodiment of the present invention, in the resistive memory structure, the spacer may be further located on a sidewall of the variable resistance layer.

[0017] According to an embodiment of the present invention, in the resistive memory structure, the variable resistance layer may be a single-layer structure.

[0018] According to an embodiment of the present invention, in the resistive memory structure, the variable resistance layer may be a multi-layer structure.

[0019] According to an embodiment of the present invention, in the resistive memory structure, the cross-sectional shape of the variable resistance layer may include a U-shape.

[0020] According to an embodiment of the present invention, in the resistive memory structure, the material of the variable resistance layer may include metal oxide.

[0021] According to an embodiment of the present invention, in the resistive memory structure, the resistive memory device includes a first electrode, a second electrode and a variable resistance layer. The first electrode is located on the gate. The first electrode can be electrically connected to the gate. The second electrode is located on the first electrode. The variable resistance layer is located between the second electrode and the first electrode.

[0022] According to an embodiment of the present invention, the resistive memory structure may further include an interconnect structure. The interconnect structure is located between the first electrode and the gate. The interconnect structure may be electrically connected to the first electrode and the gate.

[0023] According to an embodiment of the present invention, in the resistive memory structure, the material of the variable resistance layer may include metal oxide.

[0024] Based on the above, in the resistive memory structure proposed by the present invention, the resistive memory device is electrically connected to the gate of the transistor device, thereby improving the electrical performance of the resistive memory structure. For example, when the above-mentioned resistive memory structure is read, since the read current does not pass through the resistive memory device, the durability of the resistive memory device can be improved. In addition, when the above-mentioned resistive memory structure is read, since the resistive memory structure has a higher ratio of the on current to the off current, the data discrimination capability can be improved. In addition, since the resistive memory device and the transistor device can be effectively integrated, the power consumption of the read operation can be further reduced. On the other hand, the above-mentioned resistive memory structure can effectively prevent the influence of the sneak path.

[0025] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is a cross-sectional view of a resistive memory structure according to some embodiments of the present invention;

[0027] Figure 2 sectional views of resistive memory structures according to some other embodiments of the present invention.

[0028] Description of Figure Numbers:

[0029] 10,20: Resistive memory structure

[0030] 100,200: Transistor devices

[0031] 102,202: Resistive memory devices

[0032] 104,204: Gate

[0033] 106,206: Substrate

[0034] 108,208: Gate dielectric layer

[0035] 110,112,210,212: doping area

[0036] 114,214: Spacer

[0037] 116,118,222: Dielectric layer

[0038] 120,216,218: Electrode

[0039] 122,220: variable resistance layer

[0040] 124,126: Conductive layer

[0041] IS1, IS2, IS3, IS4: Interconnection structure DETAILED DESCRIPTION

[0042] The following examples are listed and described in detail with reference to the accompanying drawings, but the examples provided are not intended to limit the scope of the present invention. For ease of understanding, the same components will be described with the same symbols in the following description. In addition, the drawings are for illustrative purposes only and are not drawn to their original size. In fact, the size of various features may be increased or decreased arbitrarily for the sake of clarity.

[0043] Figure 1 is a cross-sectional view of a resistive memory structure according to some embodiments of the present invention.

[0044] Please refer to Figure 1 , the resistive memory structure 10 includes a transistor device 100 and a resistive memory device 102. The transistor device 100 includes a gate 104. The gate 104 may be a single-layer structure or a multi-layer structure. In some embodiments, the material of the gate 104 may include titanium nitride (TiN), hafnium (Hf) or a combination thereof. The resistive memory device 102 is electrically connected to the gate 104 of the transistor device 100. In this embodiment, the transistor device 100 and the resistive memory device 102 may share the gate 104, so that the resistive memory device 102 may be electrically connected to the gate 104 of the transistor device 100.

[0045] The resistive memory structure 10 may further include a substrate 106. In some embodiments, the substrate 106 may be a semiconductor substrate, such as a silicon substrate. The transistor device 100 may be located on the substrate 106. In some embodiments, a portion of the transistor device 100 may be located in the substrate 106. The resistive memory device 102 may be located on the transistor device 100.

[0046] The transistor device 100 may further include a gate dielectric layer 108, a doped region 110, a doped region 112, and a spacer 114. The gate dielectric layer 108 is located between the gate 104 and the substrate 106. The gate dielectric layer 108 may be a single-layer structure or a multi-layer structure. In the present embodiment, the gate dielectric layer 108 is an example of a multi-layer structure, but the present invention is not limited thereto. For example, the gate dielectric layer 108 may include a dielectric layer 116 and a dielectric layer 118. The dielectric layer 116 is located between the gate 104 and the substrate 106. In some embodiments, the material of the dielectric layer 116 may include silicon oxide. The dielectric layer 118 is located between the gate 104 and the dielectric layer 116. In some embodiments, the material of the dielectric layer 118 may include a high dielectric constant material. In other embodiments, the transistor device 100 may not include the dielectric layer 118, and the gate dielectric layer 108 may be a single-layer structure.

[0047] The doped region 110 and the doped region 112 are located in the substrate 106 on both sides of the gate 104. The doped region 110 and the doped region 112 can serve as one of the source and the other of the drain, respectively. The spacer 114 is located on the sidewall of the gate 104 and the sidewall of the gate dielectric layer 108. The spacer 114 can be a single-layer structure or a multi-layer structure. In some embodiments, the material of the spacer 114 can include silicon oxide, silicon nitride, or a combination thereof.

[0048] The resistive memory device 102 may include a gate 104, an electrode 120, and a variable resistance layer 122. In some embodiments, the gate 104 may be used as a bottom electrode of the resistive memory device 102, and the electrode 120 may be used as a top electrode of the resistive memory device 102. The electrode 120 is located on the gate 104. The electrode 120 may be a single-layer structure or a multi-layer structure. In the present embodiment, the electrode 120 is taken as an example of a multi-layer structure, but the present invention is not limited thereto. For example, the electrode 120 may include a conductive layer 124 and a conductive layer 126. The conductive layer 124 is located on the gate 104. The cross-sectional shape of the conductive layer 124 may include a U-shape. The conductive layer 124 may be a single-layer structure or a multi-layer structure. In some embodiments, the material of the conductive layer 124 may include titanium nitride, tantalum nitride, titanium, tantalum, hafnium, or a combination thereof. The conductive layer 126 is located on the conductive layer 124. In some embodiments, the material of the conductive layer 126 may include a metal such as aluminum or tungsten.

[0049] The variable resistance layer 122 is located between the electrode 120 and the gate 104. The cross-sectional shape of the variable resistance layer 122 may include a U-shape. The spacer 114 may also be located on the sidewall of the variable resistance layer 122. The variable resistance layer 122 may be a single-layer structure or a multi-layer structure. In some embodiments, the material of the variable resistance layer 122 may include a metal oxide. In some embodiments, the material of the variable resistance layer 122 may include hafnium oxide (HfO), tantalum oxide (TaO), titanium oxide (TiO), nickel oxide (NiO), copper oxide (CuO) or a combination thereof.

[0050] Based on the above embodiments, it can be known that in the resistive memory structure 10, the resistive memory device 102 is electrically connected to the gate 104 of the transistor device 100, thereby improving the electrical performance of the resistive memory structure 10. For example, when the resistive memory structure 10 is read, since the read current does not pass through the resistive memory device 102, the durability of the resistive memory device 102 can be improved. In addition, when the resistive memory structure 10 is read, since the resistive memory structure 10 has a higher ratio of the on current to the off current, the data discrimination capability can be improved. In addition, since the resistive memory device 102 can be effectively integrated with the transistor device 100, the power consumption of the read operation can be further reduced. On the other hand, the resistive memory structure 10 can effectively prevent the influence of the sneak path.

[0051] Figure 2 2 are cross-sectional views of resistive memory structures according to some other embodiments of the present invention.

[0052] Please refer to Figure 2 , the resistive memory structure 20 includes a transistor device 200 and a resistive memory device 202. The transistor device 200 includes a gate 204. In some embodiments, the gate 204 includes a polysilicon gate or a metal gate. The resistive memory device 202 is electrically connected to the gate 204 of the transistor device 200. In this embodiment, the resistive memory structure 20 may further include an interconnect structure IS1. The interconnect structure IS1 is located between the resistive memory device 202 and the gate 204. The interconnect structure IS1 may be electrically connected to the resistive memory device 202 and the gate 204, so that the resistive memory device 202 may be electrically connected to the gate 204 of the transistor device 200. In some embodiments, the interconnect structure IS1 may include a plug, a wire, or a combination thereof. In some embodiments, the material of the interconnect structure IS1 may include tungsten, aluminum, copper, titanium, titanium nitride, tantalum, tantalum nitride, or a combination thereof.

[0053] The resistive memory structure 20 may further include a substrate 206. In some embodiments, the substrate 206 may be a semiconductor substrate, such as a silicon substrate. The transistor device 200 may be located on the substrate 206. In some embodiments, a portion of the transistor device 200 may be located in the substrate 206. The resistive memory device 202 may be located on the transistor device 200.

[0054] The transistor device 200 may further include a gate dielectric layer 208, a doped region 210, a doped region 212, and a spacer 214. The gate dielectric layer 208 is located between the gate 204 and the substrate 206. The gate dielectric layer 208 may be a single-layer structure or a multi-layer structure. In some embodiments, the material of the gate dielectric layer 208 may include silicon oxide, a high dielectric constant material, or a combination thereof. The doped region 210 and the doped region 212 are located in the substrate 206 on both sides of the gate 204. The doped region 210 and the doped region 212 may serve as one and the other of the source and the drain, respectively. The spacer 214 is located on the sidewall of the gate 204 and the sidewall of the gate dielectric layer 208. The spacer 214 may be a single-layer structure or a multi-layer structure. In some embodiments, the material of the spacer 214 may include silicon oxide, silicon nitride, or a combination thereof.

[0055] The resistive memory device 202 may include an electrode 216, an electrode 218, and a variable resistance layer 220. The electrode 216 is located on the gate 204. In some embodiments, the electrode 216 may serve as a bottom electrode of the resistive memory device 202, and the electrode 218 may serve as a top electrode of the resistive memory device 202. The electrode 216 may be electrically connected to the gate 204. The interconnection line structure IS1 is located between the electrode 216 and the gate 204. The interconnection line structure IS1 may be electrically connected to the electrode 216 and the gate 204, so that the resistive memory device 202 may be electrically connected to the gate 204 of the transistor device 200. The electrode 216 may be a single-layer structure or a multi-layer structure. In some embodiments, the material of the electrode 216 may include titanium nitride, tantalum nitride, titanium, tantalum, hafnium, or a combination thereof.

[0056] The electrode 218 is located on the electrode 216. The electrode 218 may be a single-layer structure or a multi-layer structure. In some embodiments, the material of the electrode 218 may include titanium nitride, tantalum nitride, titanium, tantalum, hafnium or a combination thereof.

[0057] The variable resistance layer 220 is located between the electrode 218 and the electrode 216. The variable resistance layer 220 may be a single layer structure or a multilayer structure. In some embodiments, the material of the variable resistance layer 220 may include a metal oxide. In some embodiments, the material of the variable resistance layer 220 may include hafnium oxide, tantalum oxide, titanium oxide, nickel oxide, copper oxide, or a combination thereof.

[0058] The resistive memory structure 20 may further include an interconnection structure IS2, an interconnection structure IS3, and an interconnection structure IS4. The interconnection structure IS2, the interconnection structure IS3, and the interconnection structure IS4 may be electrically connected to the doped region 210, the doped region 212, and the electrode 218, respectively. In some embodiments, the interconnection structure IS2, the interconnection structure IS3, and the interconnection structure IS4 may include a plug, a conductive line, or a combination thereof. In some embodiments, the material of the interconnection structure IS2, the material of the interconnection structure IS3, and the material of the interconnection structure IS4 may include tungsten, aluminum, copper, titanium, titanium nitride, tantalum, tantalum nitride, or a combination thereof.

[0059] The resistive memory structure 20 may further include a dielectric layer 222. The dielectric layer 222 may cover the transistor device 200. The resistive memory device 202, the interconnection structure IS1, the interconnection structure IS2, the interconnection structure IS3, and the interconnection structure IS4 may be located in the dielectric layer 222. In some embodiments, the dielectric layer 222 may be a multi-layer structure. In some embodiments, the material of the dielectric layer 222 may include silicon oxide.

[0060] Based on the above embodiments, it can be known that in the resistive memory structure 20, the resistive memory device 202 is electrically connected to the gate 204 of the transistor device 200, thereby improving the electrical performance of the resistive memory structure 20. For example, when the resistive memory structure 20 is read, since the read current does not pass through the resistive memory device 202, the durability of the resistive memory device 202 can be improved. In addition, when the resistive memory structure 20 is read, since the resistive memory structure 20 has a higher ratio of the on current to the off current, the data discrimination capability can be improved. In addition, since the resistive memory device 202 can be effectively integrated with the transistor device 200, the power consumption of the read operation can be further reduced. On the other hand, the resistive memory structure 20 can effectively prevent the influence of the sneak path.

[0061] In summary, in the resistive memory structure of the above embodiment, the resistive memory device is electrically connected to the gate of the transistor device, thereby improving the electrical performance of the resistive memory structure.

[0062] Although the present invention has been disclosed as above by embodiments, it is not intended to limit the present invention. Any person skilled in the art may make slight changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be based on the definition of the claims.

Claims

1. A resistive memory structure, characterized in that: include: A transistor device including a gate; and A resistive memory device is electrically connected to the gate of the transistor device.

2. The resistive memory structure according to claim 1, characterized in that: The transistor device shares the gate with the resistive memory device.

3. The resistive memory structure according to claim 1, characterized in that: Also includes: Substrate, where The transistor device is located on the substrate, and The resistive memory device is located on the transistor device.

4. The resistive memory structure according to claim 3, characterized in that: The transistor device further comprises: A gate dielectric layer, located between the gate and the substrate; A first doped region and a second doped region are located in the substrate on both sides of the gate; and The spacer is located on the sidewall of the gate and the sidewall of the gate dielectric layer.

5. The resistive memory structure according to claim 4, characterized in that: The gate dielectric layer includes a single-layer structure.

6. The resistive memory structure according to claim 4, characterized in that: The gate dielectric layer includes a multi-layer structure.

7. The resistive memory structure according to claim 4, characterized in that: The gate dielectric layer comprises: A first dielectric layer located between the gate and the substrate; and The second dielectric layer is located between the gate and the first dielectric layer.

8. The resistive memory structure according to claim 7, characterized in that: The material of the first dielectric layer includes silicon oxide, and the material of the second dielectric layer includes a high dielectric constant material.

9. The resistive memory structure according to claim 4, characterized in that: The resistive memory device comprises: the gate; an electrode located on the gate; and The variable resistance layer is located between the electrode and the gate.

10. The resistive memory structure according to claim 9, characterized in that: The electrode includes a single-layer structure.

11. The resistive memory structure according to claim 9, characterized in that: The electrode includes a multi-layer structure.

12. The resistive memory structure according to claim 9, characterized in that: The electrode comprises: A first conductive layer, located on the gate, wherein a cross-sectional shape of the first conductive layer includes a U shape; and The second conductive layer is located on the first conductive layer.

13. The resistive memory structure according to claim 9, characterized in that: The spacer is also located on a sidewall of the variable resistance layer.

14. The resistive memory structure according to claim 9, characterized in that: The variable resistance layer includes a single-layer structure.

15. The resistive memory structure according to claim 9, characterized in that: The variable resistance layer includes a multi-layer structure.

16. The resistive memory structure according to claim 9, characterized in that: A cross-sectional shape of the variable resistance layer includes a U-shape.

17. The resistive memory structure according to claim 9, characterized in that: The material of the variable resistance layer includes metal oxide.

18. The resistive memory structure according to claim 1, wherein: The resistive memory device comprises: A first electrode, located on the gate and electrically connected to the gate; a second electrode, located on the first electrode; and The variable resistance layer is located between the second electrode and the first electrode.

19. The resistive memory structure according to claim 18, characterized in that: Also includes: The interconnection line structure is located between the first electrode and the gate, and is electrically connected to the first electrode and the gate.

20. The resistive memory structure according to claim 18, wherein: The material of the variable resistance layer includes metal oxide.

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