Improved light source integration

Abstract

The present invention provides, among other things, a silicon-on-insulator (SOI) device for accommodating a light source device in a flip-chip arrangement, the device comprising, from bottom to top: a support layer; a BOX (buried oxide) layer comprising a BOX material; a BOX capping layer including a selective etch stop material; a cladding oxide layer including an optical interface; wherein the device comprises a plurality of recesses extending between the support layer and the BOX cover layer, the recesses defining pockets for receiving the light source device and a plurality of pedestals; wherein at least one of the bases is disposed at a side of the pocket opposite the other of the bases; wherein the susceptors each extend between the support layer and the BOX capping layer, thereby comprising a top portion comprising, preferably consisting of, a selective etch stop layer material.

Description

Technical Field

[0001] The present invention relates to improved light source integration. In particular, the present invention relates to vertical alignment involved when integrating devices requiring alignment (eg, light sources) with SOI devices (ie, devices based on silicon-on-insulator technology). Background Art

[0002] Integration of light sources on silicon has been a very popular research topic in the past few years. This ranges from very basic work attempting to epitaxially grow III-V on silicon, to heterogeneous integration by bonding III-V materials on silicon, to flip-chip and transfer printing approaches where fully or partially processed III-V sources are transferred to silicon and fixed by soldering or bonding.

[0003] When integrating light source devices in silicon devices, a significant challenge is the edge coupling between the light source (e.g., III-V device) on the one hand and the optical interface (e.g., silicon waveguide) on the other hand.

[0004] Related devices and methods are disclosed in US20200284978A1, US10677986B1 and US20180180826A1. However, these devices and methods are too complex and / or lack precision and / or cannot be well adapted to the requirements of integrating light sources on photonic chips.

[0005] The present invention is directed to solving problems inherent in light source integration, such as those described above. Summary of the invention

[0006] According to a first aspect, the present invention provides a silicon-on-insulator (SOI) device for accommodating a light source device in a flip-chip arrangement, the device comprising, from bottom to top:

[0007] - support layer;

[0008] -BOX (buried oxide) layer, including BOX material;

[0009] - a BOX capping layer, preferably a silicon layer, comprising a selective etch stop material, preferably comprising a silicon layer material;

[0010] - Encapsulating oxide layer, including optical interface;

[0011] Wherein, the device includes a plurality of recessed portions extending between a support layer and a BOX covering layer, wherein the recessed portions define a pocket for accommodating the light source device and a plurality of bases; wherein at least one of the bases is arranged at a side of the pocket opposite to another base of the bases; wherein each of the bases extends between the support layer and the BOX covering layer, thereby including a top portion, which includes the selective etching stop material, preferably consists of the selective etching stop material, and the selective etching stop material is preferably a silicon layer material.

[0012] In this document, the light source device may include, for example, a light source. However, the device that needs to be aligned may be any other device to be integrated on the SOI wafer, and the term "light source device" should not be understood as restrictive. The term "selective etching stop material" refers to any material that allows selective etching to stop, preferably selective to oxide, more preferably selective to silicon oxide. In an embodiment, the BOX cover layer is composed of a selective etching stop material, for example, the BOX cover layer is a silicon layer composed of silicon as an etching stop material. In an embodiment, the BOX cover layer includes another material in addition to the selective etching stop material. For example, the selective etching stop material may be provided as a sublayer, wherein one or more sublayers are arranged on and / or under the etching stop sublayer. In an exemplary embodiment, the BOX cover layer is a silicon layer including a silicon sublayer, which includes or consists of a selective etching stop material.

[0013] The main advantage of this device is that it allows precise vertical alignment when housing the light source device in a pocket. Thus, the base can act as a mechanical stop, whose dimensions (especially the height) can be a critical parameter for vertical alignment. The required accuracy can be advantageously provided by "reusing" the structure of a common commercially available SOI wafer. As is known, such a "common" SOI wafer comprises, from bottom to top:

[0014] (i) A very thick silicon support layer; this portion constitutes almost the entire wafer;

[0015] (ii) a thin intermediate layer of insulating silicon dioxide, the buried oxide (BOX) layer; and

[0016] (iii) BOX capping layer, which is the topmost silicon layer, specifically the thin top layer of single crystal silicon, in which the circuits are created.

[0017] Such SOI wafers or SOI substrates are typically manufactured by highly specialized companies in the form of ultra-thin disks of 200 mm to 300 mm diameter and less than 1 mm thickness, with very tight specifications. For example, the thickness non-uniformity of the thickness of the topmost layer and the BOX layer on a 200 mm wafer may be required to be less than 2%, or even less than 1%. This very high uniformity can be well used for devices and methods according to the present invention. By relying on the original dimensions of the SOI wafer, the dimensions of the device (including the base) can be accurately adjusted regardless of the etching type combination, thereby achieving precise alignment. Relatedly, the present invention can reuse any commercially available SOI wafer, including SOI wafers with a topmost layer that is not provided as consisting of silicon, but can include any selective etch stop material, preferably in the form of a selective etch stop layer or sublayer.

[0018] Relatedly, the present invention can enjoy high structural and mechanical integrity. The SOI wafer layer structure manufactured according to strict specifications ensures good structural adhesion between layers. This can be beneficial to the structural integrity of the base, especially in embodiments where the base consists only of layers that already exist in the original SOI wafer.

[0019] Relatedly, the present invention may advantageously "reuse" a selective etching step for a BOX capping layer, for example, a selective etching step that already exists in the manufacturing process due to another device (e.g., a modulator or a photodiode) being manufactured on the same SOI wafer at the same time as the device of the present invention, wherein the BOX capping layer may be, for example, a silicon layer including a silicon layer material. In this regard, the present invention does not require the introduction of new manufacturing steps, but rather may allow the reuse of existing manufacturing steps to define the pedestal, thereby more effectively solving the vertical alignment problem than devices and methods of the current state of the art.

[0020] In a preferred embodiment, at least each top of each base, preferably the entire base, is independent at the side facing away from the pocket. This may be advantageous in that by not being directly connected to the rest of the device, some (small) movement of the top of the base in the direction toward and / or away from the light source device under thermal expansion may be allowed. In addition, this may involve defining a base that is not "clamped" by the light source device at the top, which in some embodiments allows (small) movement in one direction in a plane perpendicular to the alignment direction under thermal expansion. Thus, this embodiment is contrasted with the device of WO2016202357A1, in which the base is clamped at its top in a (so-called) "groove", which is a recessed portion in the light source device. This clamping in the "groove" may be disadvantageous because it may over-restrict movement during manufacturing and / or operation. For example, it may over-restrict movement caused by thermal expansion during manufacturing and / or during operation.

[0021] In a preferred embodiment, the bottom surface of the pocket does not extend within the support layer. In such an embodiment, the depth H1 is equal to zero. Such an embodiment can advantageously achieve a reduction in size of the device during manufacturing and / or improved thermal properties of the bonding device and / or improved electrical properties of the bonding device and / or reduced cost of the bonding device and / or improved flow of the bonding device. Thus, the improved flow of the bonding device can involve an improved flow of any one of one or more than one thermally conductive layers included in the bonding device and / or an improved flow of the solder included in the bonding device. The reduced size can involve simpler manufacturing, without the need to etch beyond the depth H1, and / or using less bonding device material, because the pocket with H1 equal to zero can provide a pocket of reduced depth. On the other hand, cost reduction can involve an embodiment in which the bonding device includes gold (Au) as an expensive material. In addition, the improved electrical properties and / or improved thermal properties can involve having a reduced electrical resistance and / or thermal resistance on the bonding device in view of the bonding device having a smaller height. The improved flow can involve a reduced volume of the pocket, thereby allowing a more predictable manufacturing process. This embodiment is in contrast to the device according to US10649137B1, which does not enjoy any of these advantages. In fact, in US10649137B1, H1 cannot be zero, because the base always includes the so-called "handle wafer part", which means that the depth H1 is greater than zero.

[0022] According to a second aspect, the present invention provides an apparatus comprising a device of the present invention and a light source device, the device comprising an optical interface, the light source device comprising a light source; wherein the device and the light source device are in a flip-chip arrangement, the optical interface and the light source are aligned; and wherein the light source device is attached to the device via attachment between an attachment-related portion of the light source device and a top of a device base.

[0023] According to another aspect, the present invention provides a method of manufacturing an SOI device suitable for accommodating a light source device in a flip chip arrangement, the method comprising the steps of:

[0024] - providing an SOI wafer portion, the SOI wafer portion comprising, from bottom to top:

[0025] Support layer;

[0026] BOX (buried oxide) layer, including BOX material;

[0027] A BOX capping layer, preferably a silicon layer, comprising a selective etch stop material, preferably a silicon layer material;

[0028] - forming one or more structures in the BOX cover layer, the structures involving silicon structures and / or silicon nitride structures, the forming comprising each of the following: selectively etching the BOX cover layer, providing a cladding oxide layer on the BOX cover layer, and providing an optical interface in the cladding oxide layer;

[0029] - forming a plurality of recessed portions extending between the support layer and the BOX cover layer, the recessed portions defining pockets for accommodating light source devices and a plurality of bases;

[0030] Wherein, at least one of the pedestals is arranged at a side of the pocket opposite to another of the pedestals; wherein the height of the pedestals is defined by selective etching, whereby the selective etch stop material of the BOX covering layer, preferably the silicon layer material of the silicon layer, is included in the top of each pedestal and acts as an etch stop.

[0031] This approach may have similar advantages as the device according to the present invention, with better height definition and / or structural integrity of the base, which may result in improved vertical alignment accuracy.

[0032] Preferred embodiments and advantages thereof are provided in the description and in the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The present invention will be discussed in more detail below with reference to the accompanying drawings.

[0034] Figure 1 Several exemplary devices in production related to the present invention are shown.

[0035] Figure 2 Several example devices related to the present invention are shown.

[0036] FIG3 shows an example device according to the present invention. Thus, Figure 3A A cross-sectional view is shown, and Figure 3B A top view is shown.

[0037] Figure 4 An exemplary manufacturing method according to the present invention is shown. DETAILED DESCRIPTION

[0038] The following description depicts example embodiments only and is not to be considered limiting in scope.Any reference herein to the present disclosure is not intended to limit or restrict the disclosure to the precise features of any one or more exemplary embodiments disclosed in this specification.

[0039] In addition, the terms first, second, third, etc. in the specification and claims are used to distinguish similar elements and not necessarily to describe a sequential or chronological order. These terms are interchangeable under appropriate circumstances, and the embodiments of the invention can be operated in an order other than that described or illustrated herein.

[0040] Additionally, while various embodiments are referred to as "preferred," this should be construed as exemplary ways in which the invention can be implemented, rather than limiting the scope of the invention.

[0041] The term "comprising" used in the claims should not be interpreted as being limited to the elements or steps listed thereafter; it does not exclude other elements or steps. It needs to be interpreted as specifying the presence of the referenced features, integers, steps or components, but does not exclude the presence or addition of one or more other features, integers, steps or components or combinations thereof. Therefore, the scope of the expression "a device comprising A and B" should not be limited to a device consisting of only components A and B, but with respect to the present invention, only components A and B of the device are enumerated, and the claims should further be interpreted to include equivalents of these components.

[0042] In this document, the term "optical interface" may refer to any form of edge coupling, including waveguides for edge coupling, and may involve various geometries and materials. In an embodiment, the optical interface involves a trident structure or an inverted cone structure. In an embodiment, the optical interface involves a structure in a nitride layer, preferably an inverted cone structure. In an embodiment, the optical interface involves a structure using a nitride layer and an underlying silicon layer, preferably an inverted cone structure.

[0043] In this document, a "light source" may be any visible or invisible light source. In an embodiment, the light source may be any one of a laser, an LED, a SLED, a SOA, and a RSOA.

[0044] In this document, the term "SOI device" may refer to any silicon device or related device, preferably a silicon photonic chip, but is not limited to silicon in terms of material, amount of material or technology used. Similarly, the term "light source device" may refer to any device including a light source, preferably a III-V device, but is not limited to III-V in terms of material, amount of material or technology used.

[0045] When integrating light source devices in silicon devices, a significant challenge is the edge coupling between the light source and the optical interface (e.g. silicon waveguide). This can involve, for example, flip-chip integration of a III-V light source in a cavity (or pocket) on a silicon photonic chip. Thus, vertical alignment is a key challenge. One approach is to integrate the light source on a submount and actively align the submount to the silicon chip. However, this is complex as it requires the provision of a submount.

[0046] Vertical alignment is an integral part of the challenge of edge coupling. Thus, vertical alignment depends not only on the accuracy of the attachment process, but also on the process control of the wafer for the device and the light source device. Currently available commercial flip chip bonding machines can provide very high placement accuracy down to 500nm on the in-plane axis. However, the accuracy of post-bonding is generally lower, for example, with a tolerance of 1000nm. This should be contrasted with the stringent requirements imposed on wafer production, which can provide higher accuracy, which can be beneficial to vertical alignment according to the present invention.

[0047] The use of pedestals or columns inside pockets (or depressions) is critically dependent on a good definition of the pedestal height. Thus, not only the absolute size is important, but also the uniformity between different pedestals. Prior art devices and methods may rely primarily or entirely on timed etching to define the pedestal height, which makes it susceptible to process variations. Even if the local accuracy is high (for a given pedestal), there is no guarantee that this accuracy can be uniformly met (for all pedestals). This can be addressed by the present invention, providing at least one process step with selective etching rather than timed etching.

[0048] In an embodiment, each susceptor further comprises a middle portion, which comprises, preferably consists of, the BOX material; wherein the thickness of the middle portion is the same as the thickness of the BOX layer of the SOI wafer used to produce the device; this can advantageously achieve improved alignment accuracy and / or improved uniformity of height between susceptors and / or improved structural integrity of the susceptors.

[0049] In an embodiment, the thickness of the top portion is the thickness of the topmost layer of the SOI wafer used to produce the device, preferably at least 10%, preferably at least 50%, more preferably at least 80% of the thickness of the BOX capping layer of the SOI wafer used to produce the device.

[0050] In an embodiment, the number of pedestals is at least four, wherein a plurality of pedestals are arranged in groups at two opposite sides of a pocket. In a related embodiment, the grouping relates to at least three pedestals arranged in groups at two opposite sides of a pocket in two rows, for example, two, more than two, three, more than three, four, more than four, or five pedestals in two rows. In addition to other advantages, this arrangement in rows can also have the advantage of improving the attachment between the device and the light source device by allowing space for solder flow and / or allowing any adhesive or solder between each pedestal. This can, for example, relate to an embodiment in which solder is arranged between heat-conducting elements. In an alternative embodiment, in an embodiment, the number of pedestals is at least two, wherein a plurality of pedestals are arranged in groups at two opposite sides of a pocket, wherein the number of pedestals of one or two groups is one per group. In such an embodiment, at least on one side or both sides, a single corresponding pedestal is arranged. This can, for example, relate to a pedestal or two pedestals with a cubic shape, i.e. a beam-shaped pedestal or two beam-shaped pedestals.

[0051] In an embodiment, the bottom surface of the pocket extends within the support layer, wherein the depth H1 of the pocket relative to the BOX layer is at least 50 nm, preferably at least 100 nm. In an alternative embodiment, the depth H1 is 0. In such an embodiment, the bottom surface of the pocket extends above the top surface of the support layer.

[0052] In an embodiment, the attachment-related portion of the light source device is provided with a passivation layer having a thickness H2 selected based on the height of the base to ensure vertical alignment of the light source and the optical interface. The passivation layer is preferably made of a dielectric, more preferably of an oxide or a nitride. In a related embodiment, the thickness H2 of the passivation layer is between 50nm and 500nm, preferably between 100nm and 400nm.

[0053] In an embodiment, the apparatus comprises one or more further corresponding devices, preferably modulators and / or photodiodes, comprising respective further portions of said support layer, said BOX layer and said BOX cover layer, preferably said silicon layer, wherein respective further BOX cover layer portions are selectively etched in the same etching step as the top of the base.

[0054] In an embodiment, the method comprises the following further steps:

[0055] - providing a thermally conductive metal layer, preferably a layer based on a Ti / Au alloy, on the bottom surface of said recess, preferably by under bump metallization (UBM);

[0056] - Providing a solder layer on said thermally conductive metal layer, preferably a layer based on an Au / Sn alloy.

[0057] This may involve providing a good attachment between the device and the light source device. Thus, these materials may be advantageous because they have high conductivity for both heat and electricity, the latter preferably being at least related to the powering of the light source device, for example, the pumping of the light source included in the light source device. In addition, a thermally conductive metal layer (e.g., a layer based on a Ti / Au alloy) comprising Au may be advantageously combined with a solder layer based on an Au / Sn alloy to provide advantageous soldering properties. Specifically, the melting point of such a solder may be low when the solder is applied, for example, may be lower than 300°C or 290°C or about 280°C, but may be increased after the solder is applied by diffusion of Au present in the thermally conductive metal layer into the solder material. This may provide the advantage of relatively low temperature soldering, which may ensure minimal thermal impact on the device and the light source device, while giving the obtained device good heat resistance, because the melting temperature of the solder may be much higher than the melting temperature when the solder is applied, for example, may be increased by 5°C or 10°C or more than 10°C.

[0058] In an embodiment, the method comprises the following further steps:

[0059] - attaching a light source device to the device according to a flip chip arrangement, said attachment involving attachment between an attachment relevant part of the light source device and a top part of the base of the device.

[0060] In an embodiment, attaching comprises soldering by soldering, bonding the bonding relevant part of the light source device and the bonding relevant part of the device by solder, preferably Au / Sn gold based solder.In a preferred embodiment, the solder is a Au / Sn alloy based solder.

[0061] In an embodiment, the bonding related part of the device involves a thermally conductive metal layer, preferably a layer based on a TI / Au alloy, provided on the bottom surface of the pocket.

[0062] In an embodiment, the bonding related portion of the light source device involves a thermally conductive metal layer, preferably a layer based on a Ti / Pt / Au alloy, arranged on a surface of the light source device close to a light source comprised in the light source device.

[0063] In an embodiment, before the attaching, the method further comprises the following steps:

[0064] - providing a passivation layer on the attachment-related parts of the light source device;

[0065] The thickness H2 of the passivation layer is selected based on the height of the base to ensure vertical alignment of the light source included in the light source device and the optical interface.

[0066] In an embodiment, the light source involves an InP waveguide, and / or the optical interface involves a SiN waveguide.Thereby, preferably, the BOX capping layer is a silicon layer comprising a silicon layer material as a selective etch stop material.

[0067] In an embodiment, the light source includes GaAs and / or InGaAsP and / or other combinations from Group III (e.g., aluminum (Al), gallium (Ga) and / or indium (In)) and Group V (e.g., nitrogen (N), phosphorus (P), arsenic (As) and / or antimony (Sb)) of the periodic table.

[0068] In an embodiment, the optical interface involves a material different than SiN (eg, silicon oxynitride (SiON)) and / or another silicon layer.

[0069] In an embodiment, these method steps are performed collectively for respective SOI wafer parts belonging to the same wafer, wherein the method comprises the further step of dicing said wafer to obtain respective devices.

[0070] In an embodiment, the angle of the optical interface is between 2 degrees and 45 degrees, preferably between 5 degrees and 20 degrees. This may advantageously prevent back reflections.

[0071] The BOX cover layer and the selective etching stop material can be any material and material combination suitable for realizing selective etching stop by etching stop material (preferably suitable for realizing selective etching stop relative to oxide by etching stop material). In an embodiment, the BOX cover layer is a silicon layer including a silicon layer material as a selective etching stop material. In an embodiment, the BOX cover layer is a silicon layer composed of a silicon layer material as a selective etching stop material. In an embodiment, the BOX cover layer includes silicon nitride or lithium niobate as a selective etching stop material, wherein the selective etching stop material is preferably arranged in the entire BOX cover layer or within the range of a sublayer of the BOX cover layer. In an embodiment, the BOX cover layer includes germanium as a selective etching stop material, preferably including a germanium layer or sublayer. In an embodiment, the BOX cover layer includes two or more sublayers, wherein at least one or two or three sublayers involve a sublayer including a material suitable as a selective etching stop material, for example, two sublayers of different materials of silicon nitride, lithium niobate and germanium. This can advantageously allow the BOX cover layer to be used as a selective etching stop in different etching steps, wherein different pedestal heights can be obtained depending on the type of etching used.

[0072] Hereinafter, exemplary embodiments of the present invention will be described to illustrate the present invention but not to limit the scope of the present invention.

[0073] Example 1: Example devices and apparatus according to the present invention

[0074] In this example, an example device and associated apparatus are considered. It will be understood that in certain variations of this example, the device and apparatus of this example can be manufactured using the example manufacturing method of Example 2. In view of this, it is still indicated that Figure 4 exists but Figure 1 , Figure 2 Or some reference numerals not present on any of FIG. 3 .

[0075] Figure 1 A number of exemplary devices in production related to the present invention are shown. This may involve a stage in manufacturing, for example, one of the diagrams 400 of Example 2. On the one hand, this relates to an example of an SOI device 10 of the present invention, but also to further exemplary devices 80, 90 (specifically, a modulator 80 and a photodiode 90) all formed simultaneously within the same SOI wafer portion, which include, from bottom to top: a support layer 1; a BOX layer 2, including a BOX material; and a BOX capping layer 3, including a selective etching stop material. In this example, the BOX capping layer is a thin silicon layer 3 including a silicon layer material as a selective etching stop material. The various devices 10, 80, 90 have been formed to a certain extent, wherein parts of the silicon layer 3 have been removed by etching (e.g., by selective etching, or a combination of selective etching and timed etching). The remaining parts of the silicon layer 3 relate to modulator-related parts 3b', photodiode-related parts 3b and device-related parts 3a' having non-uniform thicknesses, from which the final top 3a of the base 8 can be obtained. Each of these portions 3b', 3b and 3a' may act as a waveguide layer of the device 10, 80, 90 in question, or as an etch stop layer in the case of the device 10. The formation of the device also involves the deposition of a cladding oxide, resulting in a cladding oxide layer 4, in several steps.

[0076] Modulators 80 and 90 further comprise vertical bond pad interconnects 82 and 92 extending within the capping oxide layer 4, with the actual bond pads at its top surface. Thus, the bond pad interconnect has a cross section that varies with length; this may involve a metal portion of larger cross section and a via of smaller cross section. Modulator 80 further comprises two respective contacts extending between the respective bond pad interconnects and the connection portion of the modulator-related portion 3b'. Photodiode 90 further comprises a contact extending between the bond pad interconnect 92 and the germanium portion, which in turn is connected to the photodiode-related portion 3b.

[0077] As for the device 10, the optical interface 5, which is a SiN waveguide, already exists within the cladding oxide layer. It is arranged at an appropriate height to allow for optimal vertical alignment with the light source device 20, which is not yet arranged in the pocket 40, which is not yet formed.

[0078] Figure 2A number of example devices related to the present invention are shown. This shows a device 10 of the present invention as well as devices 80, 90, and an example light source device 20 of the present invention. Thus, the device 10 and the light source device 20 together provide an example device according to the present invention, which is also shown in FIG. Figure 3A In the cross-sectional view above and Figure 3B Top view on.

[0079] from Figure 1 Steering Figure 2 , Figure 3A and Figure 3B In the device, a plurality of recesses have been provided. The recesses extend between the support layer 1 and the silicon layer 3. They define a pocket 40 for accommodating the light source device 20 and a plurality of bases 8. The bases are arranged along opposite sides of the pocket 40. Specifically, the bases are grouped into five bases 8 arranged in two rows at opposite sides of the pocket 40.

[0080] During the formation of the pocket 40, the top 3a of the pedestal 8 has already acted as an etch stop. This allows a more precise etching than forming the pocket and the pedestal 8 using timed etching. The thickness of the top 3a is at least 10% of the thickness of the topmost layer of the SOI wafer used to produce the device 10. This may involve further etching already performed on the top before the pedestal 8 in its final form is obtained. This does not jeopardize the accuracy of the alignment, since any type of etching (including timed etching) can be performed precisely in view of the limited depth of the device-related portion 3a' from which the top 3a is obtained. On the contrary, the pedestal must be formed at a greater depth (e.g., the entire stack and / or the entire depth of the pocket 40) by using timed etching, which will result in a less precise height of the pedestal 8 and therefore a less precise vertical alignment.

[0081] The susceptor 8 further comprises a middle portion 2a consisting of BOX material. Thus, the thickness of the middle portion 2a is the same as the thickness of the BOX layer of the SOI wafer used to produce the device 10. This allows for precise vertical alignment.

[0082] Furthermore, the recess further defines an optical interface related portion 4c of the cladding oxide layer 4 (comprising the optical interface 5) and a further portion 4b of the cladding oxide layer (associated with the further devices 80, 90).

[0083] The bottom surface of the pocket 40 extends within the support layer 1 , wherein the depth H1 of the pocket 40 relative to the BOX layer is at least 50 nm, preferably at least 100 nm. In an alternative example (not shown), H1 is zero.

[0084] The device and the light source device 20 together form the apparatus. The device 10 and the light source device 20 are in a flip chip arrangement. Thereby, alignment is achieved according to the alignment axis 6, thereby allowing light from the light source 22 of the light source device 20 to be transmitted to the optical interface 5 of the device 10 with minimal losses. Thereby, the light source 22 is an InP waveguide and the optical interface is a SiN waveguide.

[0085] The light source device 20 is attached to the device 10 via attachment between an attachment-related portion of the light source device 20 and the top 3 a of the base 8 of the device 10 .

[0086] The attachment-related portion of the light source device 20 is provided with a passivation layer 21 made of a dielectric as an oxide or nitride, the passivation layer 21 having a thickness H2 selected based on the height of the base 8 to ensure vertical alignment of the light source 22 and the optical interface 5. Figure 3A As shown (upper - i.e. light source device with initial passivation layer 21), the thickness of initial passivation layer 21 (i.e., the passivation layer just after deposition) may initially be greater than the desired thickness. This thickness may then be reduced to achieve the desired passivation layer thickness. This ensures interoperability as it allows various light source devices of various light sources to be used with the device of the present invention.

[0087] The thickness H2 of the passivation layer 21 is between 50 nm and 500 nm.

[0088] The device 10 and the light source device 20 are joined by a joining device 7. The joining device 7 includes heat conductive layers 71, 73 and solder 72. The joining is achieved by soldering the heat conductive layers 71, 73 of the device 10 and the light source device 20 together by the solder 72. The joining ensures attachment and allows heat from the light source device to be dissipated to another part of the device 10, such as the support layer 1. The solder 72 is a solder based on an Au / Sn alloy. The heat conductive metal layer 71 (also referred to as the joining-related portion of the device 10) is a layer based on a Ti / Au alloy disposed on the bottom surface of the pocket. On the other hand, the heat conductive layer 73 of the light source device 10 (also referred to as the joining-related portion of the light source device 20) is a layer based on a Ti / Pt / Au alloy. As Figure 2 and Figure 3A As shown, the heat-conducting layer 73 is arranged on the surface of the light source device close to the light source 22, so as to achieve good heat dissipation from the light source to the heat-conducting layer.

[0089] like Figure 3AAs shown, the base 8 is independent at the side facing away from the pocket. Specifically, an opening is defined between the base 8 and the other part 2c of the device, thereby defining the side of the base 8 facing away from the pocket. Such a base can be advantageous because by not being directly connected to other parts of the device 10, they can allow some (small) movement in the direction toward the light source device 20 and / or away from the light source device 20 under thermal expansion. In addition, this can involve defining a base that is not "clamped" by the light source device at the top of the base, which in some embodiments can achieve free movement in a direction along a plane perpendicular to the alignment direction under thermal expansion.

[0090] refer to Figure 3B , a metal sealing ring 14 is deposited around the device. Within the sealing ring 14, there are respective bonding pads 13 for connecting to the pocket portion of the device 10 on the one hand and to the pocket portion of the light source device 20 on the other hand. This involves a contact portion 11 and a pair of wire bonds 12 provided on the bottom of the pocket 40 of the device. A pair of wire bonds 12 extends between the contact portion 11 and the bonding pads 13 associated with the portion of the device 10 located in the pocket 40. Another pair of wire bonds 12 extends between the light source device 20 and the bonding pads 13 associated with the light source device 20.

[0091] like Figure 3B As shown, the waveguide 9 enters the device below the sealing ring and approaches the light source device 20 in a non-orthogonal direction. Thus, an angle between 5 degrees and 20 degrees is provided, resulting in an angled optical interface 5. This can be beneficial to prevent back reflections. Specifically, the angled edge can prevent reflections from being coupled back to the waveguide core that emits it, i.e., the light source. This is particularly beneficial for light sources such as lasers or semiconductor optical amplifiers, both of which are very sensitive to back reflections.

[0092] In by Figure 3B In the top view provided, an example light source device 20 is located on a portion of the device, thereby hiding the base 8 and a portion of the support layer top surface 1a extending around the base of the base 8. Thus, the light source device 20 is depicted as transparent for illustration purposes only, and is actually opaque (not shown).

[0093] Example 2: Example manufacturing method according to the present invention

[0094] Figure 4 An example manufacturing method according to the present invention is shown, which shows process steps 101 to 105. Thus, the process can advantageously provide more precise vertical alignment than methods that rely on timed etching. It will be understood that in some variations of this example, the devices and apparatuses manufactured can be the example devices and apparatuses of Example 1. In view of this, it is still indicated Figure 1 , 2or 3 but exists on Figure 4 Some reference numerals are not present.

[0095] The method begins with the production of an SOI device 10 suitable for accommodating a light source device 20 in a flip-chip arrangement, wherein a portion of the production of the device 10 is illustrated by method steps 101 and 102 .

[0096] First, the method comprises the step of providing an SOI wafer portion, which comprises, from bottom to top: a support layer 1; a BOX layer 2 comprising a BOX material and a BOX capping layer 3 comprising a selective etching stop material. In this example, the BOX capping layer is a thin silicon layer 3 comprising a silicon layer material as a selective etching stop material. Subsequently (not shown), several structures 80, 90 are formed in the silicon layer 3. This involves selectively etching the silicon layer 3 and providing a capping oxide layer 4, 4c on the silicon layer 3. These structures may involve silicon as well as silicon nitride structures. For example, this may involve the modulator 80 and / or the photodiode of Example 1. In addition, as Figure 4 As shown in the diagram 400 of FIG. 4 , this involves forming an integrated detector 16 in the cladding oxide layer 4 and a bonding pad 15 connected thereto. In addition, this includes (not shown) providing an optical interface 5 within the cladding oxide layer 4 .

[0097] Next, the method includes the step of forming 101 a plurality of recesses extending between the support layer 1 and the silicon layer 3. Thus, as shown in diagram 401, the recess defines a pocket 40 for accommodating the light source device 20. In addition, the recess defines a plurality of pedestals in number of ten. The pedestals 8 are grouped into two rows, five in each row, and are arranged in parallel at opposite sides of the pocket 40. Thus, the height of the pedestals 8 is defined by selective etching. Thus, the silicon layer material included in the top 3a of each pedestal 8 acts as an etching stop. Or, in other words, the silicon layer material of the silicon layer is included in the top 3a of each pedestal 8 and acts as an etching stop. The rest of the pedestal (i.e., the middle portion 3b) involves the BOX layer material.

[0098] Next, the method comprises the steps of providing 102 a thermally conductive metal layer 71 and a solder layer 72 and depositing a sealing ring 14 (in this example a metal sealing ring). This is shown in diagram 402. As for the thermally conductive metal layer 71, this involves providing a layer based on a Ti / Au alloy on the bottom surface of the pocket 40. This is performed by under bump metallization (UBM). As for the solder layer 72, this involves providing a layer based on an Au / Sn alloy as a solder layer on the thermally conductive metal layer 71. As for the attachment of the metal sealing ring 72, this may involve either soldering and / or UBM.

[0099] Next, the method comprises the step of providing 103 an attachment (including solder-based bonding and wire bonding) between the device 10 and the light source device 20 according to a flip chip arrangement. This achieves an apparatus comprising the device and the light source device, wherein vertical alignment is performed according to the alignment axis 6 or beam, as shown in diagram 403.

[0100] As for attachment according to the flip chip arrangement, this involves attaching the light source device 20 to the device 10. The attachment is performed between the attachment-related portion of the light source device 20 and the top 3a of the base 8 of the device 10. The attachment includes a solder-based joint, which is performed by joining the joint-related portion 73 of the light source device 20 and the joint-related portion 71 of the device 10 by solder 72. The solder is a solder based on an Au / Sn alloy. The joint-related portion 71 of the device 10 is a layer based on a Ti / Au alloy set in the previous method step. Complementary to this, the joint-related portion 73 of the light source device 20 involves another thermally conductive metal layer 73 arranged on the surface of the light source device 20 near the light source 22 included in the light source device 20, in this example a layer based on a Ti / Pt / Au alloy.

[0101] Still with regard to attachment, the light source device has been prepared for optimal vertical alignment by a pre-processing step. Specifically, a passivation layer 21 has been provided on the attachment-related portion of the light source device 20. Thus, the thickness H2 of the passivation layer 21 is selected based on the height of the base 8 to ensure optimal vertical alignment of the light source 22 included in the light source device 20 and the optical interface 5 included in the device 10. Thus, the thickness of the initial passivation layer 21 (i.e., the passivation layer just after deposition) can be reduced to achieve the desired passivation layer thickness. This ensures interoperability because it allows various light source devices of various light sources to be used with the device of the present invention. Thus, the light source 22 is an InP waveguide, and the optical interface is a SiN waveguide.

[0102] As for solder-based bonding, this involves laser-assisted spot size bonding, wherein the solder layer 72 reaches its transition temperature to ensure bonding between the thermally conductive layers 71, 73 of the device 10 and the light source device 20. This bonding can ensure attachment and simultaneously achieve thermal conduction, thereby allowing heat from the light source device to be dissipated to another portion of the device 10, such as the support layer 1.

[0103] As for the wiring bonds, this involves, on the one hand, forming at least one bonding pad 13 in the surface portion of the device 10 located within the sealing ring 14. In this example, this involves corresponding bonding pads for connecting to the pocket portion of the device 10 on the one hand and to the light source device 20 on the other hand. In this example, this also involves contacts 11 provided on the bottom of the pocket 40 of the device. Then, the actual wiring bonds 12 are provided. This involves, on the one hand, paired wiring bonds 12 between contacts 11 and pads 13 associated with the portion of the device 10 located in the pocket 40, and, on the other hand, paired wiring bonds 12 between the light source device 20 and pads 13 associated with the light source 20.

[0104] Next, the method includes a step 104 of providing a cover 18 on the pocket 40, as shown in diagram 404. The cover is made of silicon and has a U-shaped cross-section, as shown in diagram 404. The dimensions of the cover are such that the length and width match the dimensions of the metal sealing ring 14, while the height is such that the cover 18 can accommodate the portion of the light source device 20 that protrudes relative to the device 10 and the wiring connection. Preferably, the cover provides an airtight seal for one or more individual light source devices 20. This can involve providing 104 multiple covers 18 at the wafer level, wherein multiple covers are provided at a time. For example, this can involve providing covers for all light source devices 20 of a wafer at a time.

[0105] Next, the method comprises a step of cutting the portion 105 of the wafer 100. This is shown in diagram 405. Advantageously, these method steps are performed collectively for respective SOI wafer portions belonging to the same wafer, and the wafer is cut only at the end, thereby obtaining respective devices each comprising a respective device 10, 20. Thus, if further devices such as modulators and / or photodiodes are present, the wafer can advantageously be cut according to any device grouping and any further devices.

[0106] (End of Example 2)

[0107] In the above, several examples are given in which the light source device includes a light source. However, instead of the light source device, any device that requires alignment may be integrated with the SOI device, and the term "light source device" should not be understood as limiting.

Claims

1. A silicon-on-insulator (SOI) device (10) for accommodating a light source device (20) in a flip-chip arrangement, the device (10) comprising, from bottom to top: - support layer (1); - a BOX buried oxide layer (2), comprising BOX material; - a BOX cover layer (3), preferably a silicon layer, comprising a selective etch stop material, preferably a silicon layer material; - a coating oxide layer (4, 4c), including an optical interface (5); The device comprises a plurality of recessed portions extending between the support layer (1) and the BOX covering layer (3), the recessed portions defining a pocket (40) for accommodating the light source device (20) and a plurality of bases (8); wherein at least one of the bases (8) is arranged at a side of the pocket (40) opposite to another base of the bases (8); Wherein, each of the bases extends between the support layer (1) and the BOX cover layer (3), thereby comprising a top portion (3a), wherein the top portion (3a) comprises the selective etch stop material, preferably consists of the selective etch stop material, and the selective etch stop material is preferably a silicon layer material.

2. The SOI device (10) according to claim 1, wherein: At least the respective top portion (3a) of each base (8), preferably the entire base (8), is independent at the side facing away from the pocket (40).

3. The SOI device (10) according to claim 1 or 2, wherein: The bottom surface of the pocket (40) does not extend within the support layer (1), wherein the depth (H1) is zero.

4. The SOI device (10) according to claim 1 or 2, wherein: The bottom surface of the pocket (40) extends within the support layer (1), wherein the depth (H1) of the pocket (40) relative to the BOX layer is at least 50 nm, preferably at least 100 nm.

5. The SOI device (10) according to claims 1 to 4, wherein: Each pedestal (8) further comprises a middle portion (2a), said middle portion (2a) comprising said BOX material, preferably consisting of said BOX material; and wherein the thickness of said middle portion (2a) is the same as the thickness of the BOX layer of the SOI wafer used to produce said device (10); and / or The thickness of the top portion (3a) is at least 10%, preferably at least 50%, and more preferably at least 80% of the thickness of the topmost layer of the SOI wafer used to produce the device (10), preferably the thickness of the BOX cover layer of the SOI wafer used to produce the device (10).

6. The SOI device (10) according to claims 1 to 5, wherein: The number of the bases is at least four, and wherein the plurality of bases (8) are grouped and arranged at two opposite sides of the pocket (40); And preferably, Therein, the grouping involves grouping at least three bases (8) arranged in two rows at two opposite sides of the pocket (40).

7. An apparatus comprising the device (10) according to claims 1 to 6 and a light source device (20), the device (10) comprising an optical interface (8), the light source device comprising a light source (22); in, The device (10) and the light source device (20) are arranged in a flip chip manner, and the optical interface (8) and the light source (22) are aligned; and Wherein, the light source device (20) is attached to the device (10) via attachment between an attachment-related portion of the light source device (20) and a top portion (3a) of a base (8) of the device (10).

8. The device according to claim 7, wherein: The attachment-related portion of the light source device (20) is provided with a passivation layer (21), the passivation layer (21) having a thickness (H2) selected based on the height of the base (8) to ensure vertical alignment of the light source (22) and the optical interface (5), wherein, preferably, the thickness (H2) of the passivation layer (21) is between 50nm and 500nm, preferably between 100nm and 400nm, and the passivation layer (21) is preferably made of a dielectric, more preferably made of an oxide or a nitride.

9. The device according to claims 7 to 8, comprising one or more further corresponding devices, preferably a modulator (80) and / or a photodiode (81), said one or more further corresponding devices comprising further corresponding parts of said support layer (1), said BOX layer (2) and said BOX cover layer (3), preferably of said silicon layer (3), wherein The respective further BOX cover layer portions (3b, 3b') are selectively etched in the same etching step as the top portion (3a) of the base.

10. A method of manufacturing an SOI device suitable for accommodating a light source device (20) in a flip chip arrangement, the method comprising the steps of: - providing a SOI wafer portion, said SOI wafer portion comprising, from bottom to top: Support layer (1); · BOX buried oxide layer (2), including BOX material; A BOX cover layer (3), preferably a silicon layer, comprising a selective etch stop material, preferably a silicon layer material; - forming one or more structures in the BOX cover layer (3), preferably in the silicon layer, the structures involving silicon structures and / or silicon nitride structures, the forming comprising each of the following items: selectively etching the silicon layer (3), providing a cladding oxide layer (4, 4c) on the silicon layer (3), and providing an optical interface (5) in the cladding oxide layer (4c); - forming (101) a plurality of recessed portions extending between the support layer (1) and the BOX cover layer (3), the recessed portions defining a pocket (40) for accommodating the light source device (20) and a plurality of bases (8); wherein at least one of the bases (8) is arranged at a side of the pocket (40) opposite to another of the bases; Wherein, the height of the pedestals (8) is defined by selective etching, whereby the selective etch stop material of the BOX cover layer, preferably the silicon layer material of the silicon layer, is included in the top (3a) of each pedestal (8) and acts as an etch stop.

11. The method according to claim 10, further comprising the steps of: - providing a thermally conductive metal layer (71), preferably a layer based on a Ti / Au alloy, on the bottom surface of the pocket (40), preferably using under bump metallization (UBM); - Providing a solder layer (72), preferably a layer based on an Au / Sn alloy, on said thermally conductive metal layer (71).

12. The method according to claims 10 to 11, further comprising the steps of: - attaching a light source device (20) to the device (10) according to a flip chip arrangement, the attachment involving attachment between an attachment-related portion of the light source device (20) and a top portion (3a) of a base (8) of the device (10); Wherein, preferably, the attachment comprises soldering by soldering, wherein the bonding-related portion (73) of the light source device (20) and the bonding-related portion (71) of the device (10) are bonded by solder (72), preferably Au / Sn gold-based solder; wherein, preferably, the bonding-related portion (71) of the device (10) involves a thermally conductive metal layer (71), preferably a layer based on a TI / Au alloy, arranged on the bottom surface of the pocket (40); and / or Preferably, the bonding-related portion (73) of the light source device (20) involves a thermally conductive metal layer (73) arranged on a surface of the light source device (20) close to a light source (22) included in the light source device (20), preferably a layer based on a Ti / Pt / Au alloy.

13. The method according to claim 12, before the attaching, further comprising the following steps: - providing a passivation layer (21) on the attachment-related portion of the light source device (20); The thickness (H2) of the passivation layer (21) is selected based on the height of the base (8) to ensure vertical alignment of the light source (22) included in the light source device (20) and the optical interface (5).

14. The method according to claims 10 to 13, wherein: The light source (22) involves an InP waveguide, and wherein the optical interface involves a SiN waveguide.

15. The method according to claims 10 to 14, wherein: The steps of the method are collectively performed for respective SOI wafer parts belonging to the same wafer, wherein the method comprises the further step of dicing the wafer to obtain individual devices (10, 20).

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