Vacuum bake for EUV lithography

Abstract

A method and apparatus for performing a post-exposure bake operation is described herein. After exposure of the photoresist on the substrate, the substrate is heated during a baking process to promote protection of the photoresist. The baking process is performed in a vacuum environment at a pressure of sub-atmospheric pressure. After baking at the reduced pressure, the substrate is cooled. The cooling process is performed at a pressure of sub-atmospheric pressure. Further development of the resist is performed at ambient pressure.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to methods and apparatus for semiconductor processing. More specifically, the present disclosure relates to methods and apparatus for processing a substrate after exposure to radiation. Background Art

[0002] Integrated circuits have evolved into complex devices that can include millions of components (e.g., transistors, capacitors, and resistors) on a single chip. Photolithography is a process that can be used to form components on a chip. Generally speaking, the photolithography process involves several stages. Initially, a photoresist layer is formed on a substrate. Chemically amplified photoresists typically include a resist resin and a photoacid generator. When exposed to electromagnetic radiation in a subsequent exposure stage, the photoacid generator changes the solubility of the photoresist in the development process. The electromagnetic radiation can be generated by any suitable source, such as a laser, an electron beam, an ion beam, or other suitable electromagnetic radiation source. The electromagnetic radiation is also selected to have any desired wavelength, such as 193nm or other suitable wavelength.

[0003] During the exposure phase, a photomask or master photomask is used to selectively expose certain areas of the substrate to electromagnetic radiation. Other exposure methods include shieldless exposure methods or the like. Exposure decomposes the photoacid generator, which generates acid and forms a latent acid image in the resist resin. After exposure, the substrate is heated in a post-exposure bake process. During the post-exposure bake process, the acid generated by the photoacid generator reacts with the resist resin, thereby changing the solubility of the resist during the subsequent development process.

[0004] After post-exposure baking, the substrate (specifically the photoresist layer) is developed and rinsed to produce a patterned mask. Depending on the type of photoresist used, the areas of the substrate exposed to electromagnetic radiation are resistant to removal or more easily removed. After development and rinsing, the pattern of the mask is transferred to the substrate using a wet or dry etching process.

[0005] The evolution of chip design constantly pursues faster circuit systems and greater circuit density. The demand for greater circuit density usually takes advantage of the reduction in the size of integrated circuit components. As the size of integrated circuit components decreases, more components can be placed in a given area on a semiconductor integrated circuit. Therefore, the photolithography process transfers smaller features to the substrate, and the photolithography is performed precisely, accurately and without damage to meet the advanced chip design specifications. In order to accurately and accurately transfer features to the substrate, high-resolution lithography uses a light source that provides radiation of a small wavelength. Small wavelengths help to reduce the minimum printable size on the substrate. However, small wavelength lithography encounters problems, such as low throughput, increased line edge roughness and / or reduced resist sensitivity. In addition, it is difficult to use current photoresist materials and baking processes to reduce the print size on the substrate and maintain uniform critical dimensions of patterned features.

[0006] Therefore, there is a need for improved methods for patterning resists on substrates. Summary of the invention

[0007] In one embodiment, a method of processing a substrate is provided. The method includes exposing a photoresist disposed on a substrate to electromagnetic energy, transferring the substrate to a processing chamber and baking the substrate under sub-atmospheric pressure, and transferring the substrate from the processing chamber to a chill plate to cool the substrate.

[0008] In another embodiment, a substrate processing method includes exposing a chemically amplified photoresist disposed on a substrate to a photolithography exposure process under a sub-atmospheric pressure, transferring the substrate to a processing chamber having a processing space, baking the substrate under a sub-atmospheric pressure in the processing space, and cooling the substrate in the processing space of the processing chamber under a sub-atmospheric pressure.

[0009] In another embodiment, a substrate processing method includes exposing a chemically amplified photoresist disposed on a substrate to a photolithography exposure process under a sub-atmospheric pressure, transferring the substrate to a processing chamber having a processing space, baking the substrate under a sub-atmospheric pressure in the processing space, cooling the substrate to less than 30° C. under a pressure less than 100 Torr in the processing space of the processing chamber, and transferring the substrate from the processing chamber to a developing chamber and developing the photoresist. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Thus, the manner in which the above-described features of the present disclosure may be understood in detail, a more particular description of the present disclosure, briefly summarized above, may be obtained by reference to the embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the drawings illustrate only exemplary embodiments and, therefore, should not be considered limiting of the scope of the present disclosure, as the present disclosure may admit to other equally effective embodiments.

[0011] Figure 1 A schematic cross-sectional view of a processing chamber is depicted according to one embodiment.

[0012] Figure 2A According to one embodiment, Figure 1 Schematic cross-sectional view of a portion of a processing chamber.

[0013] Figure 2B A schematic cross-sectional view of a portion of a processing chamber is depicted according to one embodiment.

[0014] Figure 3 According to one embodiment, Figure 1 Schematic diagram of a processing chamber and a cooling chamber.

[0015] Figure 4 Operations of a method for baking a substrate in a vacuum pressure environment are depicted according to one embodiment.

[0016] Figure 5 Operations of a method for baking a substrate in a vacuum pressure environment are depicted according to one embodiment.

[0017] Figure 6 According to one embodiment, a substrate processing system is shown.

[0018] Figure 7 Operations of a method for processing a substrate in a vacuum pressure environment are depicted according to one embodiment.

[0019] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation. DETAILED DESCRIPTION

[0020] The present disclosure generally relates to apparatus and methods for use during post-exposure baking of semiconductor substrates. The methods and apparatus disclosed herein assist in reducing line edge / width roughness, improving critical dimension uniformity, and improving exposure resolution in photolithography processes for semiconductor processing applications. The methods and apparatus disclosed herein may also assist in reducing the dose of radiation (eUV exposure) used to achieve similar critical dimensions compared to conventional techniques. The apparatus described herein enables post-exposure baking or electric field guided baking of a resist layer on a substrate. The post-exposure baking or electric field guided baking may be performed prior to development of the substrate. The post-exposure baking process described herein exhibits improved dose sensitivity, reduced line width roughness, and improved critical dimension uniformity when compared to conventional techniques.

[0021] As used herein, "substrate" or "substrate surface" generally represents any suitable surface on which processing is performed. Processing includes deposition, etching, patterning, and other methods utilized during semiconductor processing. Processable substrates or substrate surfaces also include dielectric materials, such as silicon dioxide, silicon nitride, organic silicates, and carbon-doped silicon oxide or nitride materials. In certain embodiments, the substrate or substrate surface includes a photoresist material, a hard mask material, or other films or layers utilized in the patterning of the substrate. The substrate itself is not limited to any particular size or shape. Although the embodiments described herein are generally made with reference to circular 200mm or 300mm substrates, other sizes and shapes, such as polygonal, square, rectangular, curved or other non-circular workpieces, may be utilized according to the embodiments described herein. Other substrate sizes may include 100mm, 150mm, 250mm, 350mm, 400mm, 450mm, etc.

[0022] The methods and apparatus disclosed herein improve the photoresist sensitivity and productivity of the photolithography process. The random diffusion of charged species produced by the photoacid generator during the post-exposure baking process can cause line edge / width roughness and reduced resist sensitivity. Electrode assemblies (such as those described herein) are used to apply electric and / or magnetic fields to the photoresist layer during the photolithography process. Field application controls the diffusion of charged species produced by the photoacid generator. In addition, an intermediate medium is used between the photoresist layer and the electrode assembly to enhance the electric field generated therebetween. In some embodiments, the intermediate medium is a fluid, such as a liquid, a gas, or a plasma. In another embodiment, the intermediate medium is a non-liquid and non-solid medium.

[0023] The air gap defined between the photoresist layer and the electrode assembly results in a voltage drop applied to the electrode assembly, thereby adversely reducing the electric field strength desired to be generated and applied to the photoresist layer. Inaccurate (e.g., too small or too large voltage and / or current) and / or non-uniform electric field strength at the photoresist layer may result in insufficient or inaccurate voltage power to drive or generate charged species in the photoresist layer in certain desired directions, resulting in reduced line edge profile control of the photoresist layer. Generating a controlled or desired electric field strength increases the accuracy and sensitivity of the photoresist layer to the exposure and / or development process.

[0024] In embodiments where the intermediate medium is a non-gaseous medium (such as a slurry, gel, liquid solution, or solid medium), the applied voltage level can be effectively maintained within a determined range when transmitted from the electrode assembly to the photoresist layer disposed on the substrate. However, the use of non-gaseous phases (e.g., liquid or liquid-like materials) as intermediate media has several challenges that remain to be solved. For example, non-gaseous intermediate media have limited operating temperatures and can react with the resist layer disposed on the substrate.

[0025] The resistivity of the non-gas phase fluid is also difficult to control within a stable range. In some aspects and applications, the desired resistivity of the intermediate medium is about 6×10 10 Ohm·cm, but due to variations during semiconductor production, the actual resistivity is closer to 5×10 10 Ohm·cm. The resistivity and temperature of the intermediate dielectric change during the substrate bake operation and are affected by oxygen content, impurities within the dielectric, and possible polymerization of the dielectric. The purity of non-gaseous fluids is difficult to control and may cause defects on the processed substrate. Non-gaseous fluids interact with the photoresist differently at the exposed areas compared to the unexposed areas and may cause photoresist loss and roughness changes.

[0026] Therefore, a solution to the above-mentioned problem is provided herein by using a weakly ionized gas or a mixture of weakly ionized gases as an intermediate medium. By flowing one or more gases into a plasma formation region and forming a high ion density plasma (about 10 5 Ions / cm 3 to about 10 10 Ions / cm 3 ) to produce (some) weakly ionized gases. The high ion density plasma is then filtered and optionally combined with another gas to form a low ion density plasma (10 4 Ions / cm 3 Up to 10 7 Ions / cm 3 ). The low ion density plasma mixture includes, but is not limited to, free radicals and neutrons, and flows through the showerhead to be transported to the space between the substrate and the opposing electrode. When the low ion density plasma passes through the showerhead and enters the gap, the low ion density plasma mixture is filtered and leaves the showerhead as a charged material cloud. The low ion density plasma and the charged material cloud contain different types of ions and free radicals from the same gas or gas mixture. The charged material cloud includes a lower concentration of ions than the low ion density plasma, such as about 10 4 Ions / cm 3 to about 10 6 Ions / cm 3 .

[0027] Electron density is defined as the number of free electrons in space. The electron density of each plasma can be similar to the ion density, such that the electron density in a high ion density plasma is about 10 5 Electron / cm 3 to about 10 10 Electron / cm 3 The electron density in low ion density plasma is about 10 4 Electron / cm 3 Up to 10 7 Electron / cm 3 , and the electron density between the substrate and the electrode is about 10 4 Electron / cm 3 to about 10 10 Electron / cm 3 The electron and ion density directly above the substrate is selected to form a plasma medium through which the electric field passes, while not processing or reacting with or remaining substantially inert to the resist layer on top of the substrate. The electric field is coupled through the plasma medium, making the plasma medium a charge carrying medium through which the electric field is more efficiently maintained. The gas used to form the plasma medium and the electron / ion density within the plasma medium further affect whether the plasma medium reacts with the resist layer on top of the substrate. Therefore, the shape, density, position and composition of the plasma medium are controlled to increase the electric field coupling therethrough while reducing the reaction with the substrate.

[0028] In some embodiments, only one of a high ion density plasma or a low ion density plasma is formed before passing through a showerhead or diffuser into a processing space between the substrate and the counter electrode. In these embodiments, the ion density between the substrate and the counter electrode is about 10 4 Ions / cm 3 to about 10 6 Ions / cm 3 , and the electron density is about 10 4 Ions / cm 3 to about 10 6 Ions / cm 3 .

[0029] The gas and plasma within the processing chamber are selected and / or controlled with respect to resistivity, temperature, pressure, and composition. The pressure of the processing environment within the processing chamber is between about 10 mTorr and about 800 Torr. A voltage is applied between the substrate and the opposing electrode so that an electric field is formed through the gas phase or plasma phase medium between the substrate and the opposing electrode. The electric field is controlled by applying a constant voltage or a constant current to one or both of the substrate support or the electrode with a power supply. The direction of the current can be unipolar or bidirectional so that the electric field is directed upward or downward relative to the top surface of the substrate. In some embodiments, an alternating current is applied by the power supply.

[0030] The low ion density plasma / charged species cloud is delivered to the gap or space between the substrate and the counter electrode. In the embodiments described herein, the counter electrode is a secondary plasma injection (SPI) showerhead. The SPI showerhead has a plurality of holes for passing gas.

[0031] In one embodiment, the bottom surface of the SPI showerhead facing the substrate is formed of a conductive material, such as a metal or semiconductor material with a controlled resistivity. The top surface of the SPI showerhead faces away from the substrate and is coated with a dielectric layer to reduce or eliminate current or electric fields directed in the opposite direction (upward) to other parts of the plate stack, such as another showerhead maintained at ground potential.

[0032] In another embodiment, the SPI showerhead is formed of a dielectric material, such as a ceramic, quartz, or plastic material. In this embodiment, the bottom surface of the SPI showerhead is a metallized surface that faces the substrate. Having a SPI showerhead with a metallized surface formed of a dielectric material is beneficial because the hole formed through the SPI showerhead has an inner surface made of a dielectric material. When using a dielectric SPI showerhead with a metallized bottom surface, the voltage applied to the bottom metallized surface facing the substrate directs the current and the electric field to flow through the low ion density plasma to the substrate or from the substrate and through the low ion density plasma.

[0033] In yet another embodiment, the SPI showerhead is formed of a silicon material, such as a crystalline silicon material, and the resistivity across the thickness of the SPI showerhead is controlled by doping the substrate-facing surface.

[0034] Another arrangement to prevent or reduce the direction of current or electric field from the SPI showerhead in an upward direction includes increasing the resistance of a gap between the SPI showerhead and a grounded or floating showerhead above the SPI showerhead. In this embodiment, the gap is filled with a low ion density plasma permeable dielectric medium to enable the low ion density plasma to pass therethrough without complete recombination.

[0035] If it is desired to add a neutral or uncharged gas to the low ion density plasma, the neutral gas is added to the low density plasma through a dual channel showerhead located above the SPI showerhead. The dual channel showerhead includes at least one set of channels that completely pass through the thickness of the showerhead body and a second set of channels that have an opening only on one side of the showerhead body and are configured to provide one or more second gases / plasmas. The plasma generation source is placed on top of the SPI showerhead and includes one or more of a capacitively coupled plasma (CCP) arrangement, an inductively coupled plasma (ICP) arrangement, an ultraviolet (UV) arrangement, a microwave arrangement, or a remote plasma source (RPS) arrangement. In some embodiments, the lower electrode of the CCP architecture is a showerhead or diffuser, which acts as a plasma recombination component. Plasma recombination includes removing ions within the plasma to increase the ratio of free radicals to ions. In embodiments where the diffuser is placed on the bottom of the CCP architecture, the plate stack can be assembled on a pre-existing chamber architecture.

[0036] In one embodiment, the plate stacks described herein may be used in a 1000MW 1000MW 2 ... The diffuser may have a DC bias applied thereto relative to the substrate support. In this example, the diffuser is connected to a DC power source via an RF filter that implements an independent RF return path. The diffuser is electrically isolated from the chamber lid or body. The partially composite or low ion density plasma flows to a process region where a substrate is disposed and current / electric field flows between the substrate and the diffuser. In this embodiment, neither an SPI showerhead nor a dual channel showerhead is utilized.

[0037] In each of the embodiments described herein, a substrate is positioned on a substrate support pedestal when exposed to a low ion density plasma. The substrate support pedestal is either positively or negatively charged with reference to an SPI showerhead. The substrate support pedestal includes a vacuum clamping component and capability. The substrate support pedestal is a heated pedestal configured to control the temperature of the substrate. The heated pedestal is used to bake the substrate, and the process environment within the chamber is maintained at a sub-atmospheric pressure, for example, in a vacuum environment. Optionally, a current / electric field is applied to the substrate during the substrate baking process in the sub-atmospheric environment.

[0038] Figure 1A schematic cross-sectional view of a processing chamber 100 is depicted according to one embodiment. The processing chamber 100 is configured to perform a field directed post-exposure bake operation on a substrate having a photoresist or chemically modified resist layer disposed thereon. The processing chamber 100 described herein may be mirrored across a centerline C such that a second processing chamber (not shown) forms a single structure coupled to the same vacuum processing platform. In one embodiment, the platform is commercially available from Applied Materials, Inc. of Santa Clara, California. However, it is contemplated that other appropriately configured devices available from other manufacturers may benefit from the embodiments described herein.

[0039] The processing chamber 100 includes a mixing block 102, which acts as an RF electrode and / or a gas manifold. Processing gas is provided to the mixing block 102 from a gas source 136. The processing gas from the gas source 136 enters the mixing block 102 via a feedthrough member 103. In one embodiment, the feedthrough member 103 is formed of a polymeric material, such as polytetrafluoroethylene. The mixing block 102 includes a flow centering insert 140 disposed therein. The flow centering insert 140 may be an annular device having an opening 204 formed therein. The opening 204 is formed through the center of the flow centering insert 140, and the opening 204 may be a single aperture or may be a plurality of apertures. The flow centering insert 140 improves the concentric flow distribution of the processing gas within the plate stack of the processing chamber 100. The flow centering insert 140 further assists in reducing the backflow of plasma into the mixing block 102.

[0040] The mixing block 102 is electrically coupled to a first diffuser 104 and a faceplate 106, which are used to redirect the flow of the source gas to make the gas flow uniform (in Figure 1 ). It should be noted that all diffusers or meshes herein may be characterized as electrodes, since any such diffuser or mesh may be coupled to a particular potential. Insulator 108 electrically insulates mixing block 102 (including panel 106) from second diffuser 110. Second diffuser 110 acts as a second electrode opposite panel 106. In one embodiment, second diffuser 110 is a selectivity modulating device (SMD) and acts as an ion blocking plate. First diffuser 104 and panel 106 are formed of a conductive material, such as a metal. The conductive material as described herein may be aluminum or an aluminum alloy. Insulator 108 is an insulating material, such as a dielectric. The insulating material may be a ceramic, such as alumina, or a quartz material.

[0041] Each of the first diffuser 104, the face plate 106, and the second diffuser 110 has a plurality of holes disposed therethrough to enable the process gas to flow through the plate stack (e.g., the first diffuser 104, the face plate 106, the insulator 108, the second diffuser 110, the gas distribution device 112, the insulator plate 156, and the barrier screen 114). At least a portion of the mixing block 102, the face plate 106, and the second diffuser 110 are formed of a conductive material, such as aluminum or an aluminum alloy.

[0042] The surfaces of the faceplate 106 , the second diffuser 110 , and the insulator 108 define a first plasma generation region 210 in which a first plasma is generated when gas from the gas source 136 is present and energy is provided at the faceplate 106 via the mixing block 102 .

[0043] The surface of the faceplate 106 and the second diffuser 110 facing the first plasma generation region 210 may be directly coated with a ceramic layer of, for example, yttrium oxide (Y2O3) or aluminum oxide (Al2O3) for protection from bombardment by energetic plasma products generated in the first plasma generation region 210. The ceramic coating may be formed by an electron beam coating process, an anodizing process, and / or a non-porous anodizing process. Other suitable coatings include nickel plating and surface oxidation processes, for example, by exposure to a concentrated HNO3 solution. Other surfaces of the faceplate 106 and the second diffuser 110 that are not necessarily directly exposed to the plasma but are exposed to reactive gases and / or radicals generated by the plasma may be coated with a ceramic layer (e.g., yttrium oxide, aluminum oxide) or with a suitable passivation layer (e.g., an anodized layer, or a chemically generated aluminum oxide layer) to achieve chemical resistance. The insulator 108 may be any insulator, and in certain embodiments is formed of a ceramic material.

[0044] The plasma products generated in the first plasma generation region 210 pass through the second diffuser 110, which further promotes uniform distribution of the plasma products and assists in electron temperature control. After passing through the second diffuser 110, the plasma products pass through the gas distribution device 112. When the gas distribution device 112 and the second diffuser 110 contact each other at the edge, the gas distribution device 112 is also maintained at a voltage similar to the second diffuser 110. The aperture 216 ( Figure 2A) is at least three times the diameter of the pores in the second diffuser 110. The gas distribution device 112 includes a second and / or third set of gas channels 214, which can be used to introduce one or more additional gases into the plasma products as they enter the second plasma generation region 218. The second and / or third set of gas channels 214 are coupled to a second gas source 142. The second gas source 142 is configured to supply one or more inert or neutral gases, and can optionally assist in reducing the ionization of the plasma generated between the face plate 106 and the second diffuser 110. The one or more additional gases emerge from a side of the gas distribution device 112 away from the second diffuser 110. The gas distribution device 112 is made of aluminum or an aluminum alloy, and similar to the face plate 106 and the second diffuser 110 discussed above, can be coated with a passivation layer for chemical resistance, or can be coated with a ceramic layer.

[0045] The gas and plasma flowing through the gas distribution device 112 enter the second plasma generation region 218 ( Figure 2A ), the gas and the plasma are mixed in the second plasma generation region 218. The second plasma generation region 218 is a gas chamber formed between the gas distribution device 112 and the blocking screen 114. The gas distribution device 112 and the blocking screen 114 can both be maintained at different voltage potentials to control the ion density of the second plasma formed therebetween. In some embodiments, the gas distribution device 112 and the blocking screen 114 are grounded so that the second diffuser 110 and the gas distribution device 112 are connected to the first grounding member 253 while the blocking screen 114 is connected to the second grounding member 255. The gas distribution device 112 and the blocking screen 114 are separated by an insulator plate 156. The insulator plate 156 is formed of a ceramic or plastic material and can be similar to the insulator 108. In one embodiment, the insulator plate 156 is formed of an aluminum oxide material. In other embodiments, the insulator plate 156 is formed of a plastic material, such as a fluorine carbide-containing material. The plastic material may be polytetrafluoroethylene (PTFE) or polyether ether ketone (PEEK). The insulator plate 156 is selected to exhibit desirable electrical insulating properties such that the resistivity of the insulator plate 156 is greater than about 10 15 Ω·cm, such as greater than about 10 16 Ω·cm, such as greater than about 10 17 Ω·cm, such as greater than about 10 18Ω·cm. The insulator plate 156 enables control of the voltage difference between the gas distribution device 112 and the blocking mesh 114. The blocking mesh 114 is a plasma blocking mesh or an ion blocking mesh, so that the plasma is filtered out and the ion concentration is reduced when passing through the blocking mesh 114. The blocking mesh 114 may alternatively be described as a showerhead or a third diffuser plate.

[0046] The portion of the barrier screen 114 directly exposed to the plasma may be coated with a ceramic (e.g., alumina or yttrium oxide), while the surface not directly exposed to the plasma may also be coated with a ceramic. Both the exposed and unexposed surfaces are advantageously coated with a passivation layer to achieve chemical resistance to reactive gases and activated species.

[0047] The blocking screen 114 is composed of Figure 1 and Figure 2A The blocking mesh 114 is a showerhead configured to prevent the plasma from traveling back from the processing space 170 to the plate stack. The blocking mesh 114 is also configured to reduce the number of ions in the plasma that pass through the blocking mesh 114 and enter the processing space 170. The bottom surface of the blocking mesh 114 faces the processing space 170 and the substrate supporting surface 132 of the substrate support 130.

[0048] The substrate support 130 is an upper portion of the substrate support assembly 126. The substrate support assembly 126 further includes a shaft 128 and a bellows 154 connecting the substrate support assembly 126 to the lower chamber body 120. The bellows 154 forms a seal between the processing volume 170 and the external environment. One or more backside gas sources 152 are coupled to the substrate support assembly 126 to supply a backside gas to the substrate supporting surface 132 of the substrate support 130. The backside gas source 152 may also include a pump for forming a vacuum on the backside of the substrate 150.

[0049] A power source 146 and a motion device 148 are also coupled to the substrate support assembly 126. The power source 146 may be an AC or DC power source. The power source 146 is configured to supply power to the motion device 148 and / or one or more heating devices 228 ( Figure 2A ). The motion device 148 is configured to achieve movement of the substrate support assembly 126, such as raising or lowering the substrate support assembly 126, rotating the substrate support assembly 126 about the central axis A, or tilting the substrate support assembly 126. In some embodiments, the substrate support 130 is an aluminum substrate support 130. In other embodiments, the substrate support 130 is a ceramic, or a metal alloy.

[0050] The processing chamber 100 further includes an upper chamber body 116 coupled to the lower chamber body 120. The upper chamber body 116 and the lower chamber body 120 are coupled together to define at least a portion of the processing space 170. A plate stack as described herein is disposed on top of the upper chamber body 116. The lower chamber body 120 includes at least one transfer channel 160 disposed therethrough. A pumping liner 122 is disposed radially inward from the lower chamber body 120. The pumping liner 122 includes a plurality of openings 124 disposed therethrough. The openings 124 connect the exhaust plenum 134 and the processing space 170 so that gas is removed by the pump 144 via the exhaust plenum 134. The openings 124 are symmetrically disposed around the pumping liner 122. A showerhead spacer 118 is disposed radially inward from the upper chamber body 116 and is formed of a conductive material, such as an aluminum material. The showerhead spacer 118 further defines a portion of the processing space 170. The upper chamber liner 119 is disposed radially inward from the upper chamber body 116 and the showerhead spacer 118. The upper chamber liner 119 is an insulator. The upper chamber liner 119 is made of a ceramic material. In some embodiments, the upper chamber liner 119 is made of an aluminum oxide material or an aluminum nitride material.

[0051] A source match device 138, such as an RF matching circuit, is coupled to the plate stack such that the source match device 138 is configured to be in electrical communication with the face plate 106. The source match device 138 is configured to apply an RF current or voltage to the face plate 106. The source match device 138 is configured to generate a plasma between the face plate 106 and the second diffuser 110.

[0052] Figure 2A According to one embodiment, Figure 1 Schematic cross-sectional view of a portion of the processing chamber 100. Figure 2A Further depicted are the channels and plenums formed within the plate stack. As described herein, opening 204 is formed through flow centering insert 140. Opening 202 is formed through first diffuser 104 and is in fluid communication with first plenum 206. Opening 208 is formed through face plate 106 and is in fluid communication with first plasma generation region 210.

[0053] The second diffuser 110 also includes a plurality of openings to enable the process gas from the first plasma generation region 210 to flow through the second diffuser 110 and into a second plenum 212 formed between the second diffuser 110 and the gas distribution device 112 .

[0054] The aperture 216 through the gas distribution device 112 is in fluid communication with the second gas chamber 212 and the second plasma generation region 218. The gas distribution device 112 further includes one or more heaters 250 disposed therein to achieve controlled heating of the gas distribution device. The one or more heaters may include resistive heating elements, infrared heaters, or induction heaters. In some embodiments, the one or more heaters 250 may also be used to heat the substrate 150. The gas distribution device 112 and / or the second diffuser are electrically coupled to the first ground member 253. Alternatively, one of the gas distribution device 112 or the second diffuser 110 is coupled to a power source to achieve a voltage difference different from the voltage difference applied to either the face plate 106 or the blocking screen 114.

[0055] The opening 220 is formed in the insulator plate 156 to form a portion of the second plasma generation region 218. The blocking screen 114 further includes a plurality of apertures 222 that fluidly couple the second plasma generation region 218 and the processing volume 170. Due to the insulator plate 156, the blocking screen 114 and the gas distribution device 112 can be maintained at different potentials to enable control of the plasma intensity in the second plasma generation region 218. The apertures 222 through the blocking screen 114 are offset from the apertures through the second diffuser 110 so that the central axis extending parallel to the direction of each of the apertures in the blocking screen 114 is offset from any central axis of the aperture formed through the second diffuser 110. Offsetting the apertures reduces exposure of the photoresist on the substrate 150 to the high ion density plasma formed in the first plasma generation region 210. The blocking screen 114 includes a top surface 244 and a bottom surface 234. The barrier screen 114 may be coupled to the upper chamber body 116 via one or more fasteners 224 disposed through the barrier screen 114 .

[0056] The plurality of openings 124 of the pumping liner 122 may further include individual apertures 226 formed through the pumping liner 122. The individual apertures 226 surround the pumping liner 122 to enable uniform removal of gas from the processing volume 170 around the substrate support 130. In the embodiments described herein, the one or more heating devices 228 disposed within the substrate support 130 are resistive heating devices. The backside gas source 152 is fluidly coupled to the substrate supporting surface 132 of the substrate support 130 via one or more gas conduits 230. An edge ring 232 may also be disposed on the edge of the substrate support 130 around the substrate 150.

[0057] A plurality of sealing rings 240 are disposed between each plate within the plate stack, such as between the face plate 106 and the insulator 108, between the insulator 108 and the second diffuser 110, between the second diffuser 110 and the gas distributor 112, between the gas distributor 112 and the insulator plate 156, and between the insulator plate 156 and the barrier screen 114. The sealing rings 240 are configured to seal the various regions 210, 218 and plenums 206, 212 to prevent plasma products from escaping from the chamber 100 and to achieve vacuum integrity within the chamber 100.

[0058] As described above, the bottom surface 234 of the barrier screen 114 facing the substrate 150 is formed of a conductive material, such as a metal or semiconductor material with a controlled resistivity. The top surface 244 of the barrier screen 114 faces away from the substrate 150 and is coated with a dielectric layer (not shown) to reduce or eliminate the current or electric field being directed in the opposite direction (upward) to other parts of the plate stack, such as the gas distribution device 112.

[0059] In another embodiment, the barrier screen 114 is formed of a dielectric material, such as a ceramic, quartz, or plastic material. In this embodiment, the bottom surface 234 of the barrier screen 114 is a metallized surface facing the substrate 150. It is beneficial to form the barrier screen 114 from a dielectric material having a metallized surface because the apertures 222 formed through the barrier screen 114 have inner surfaces made of a dielectric material. When a dielectric barrier screen 114 having a metallized bottom surface is used, a voltage applied to the bottom metallized surface facing the substrate 150 directs the current and electric field to pass through the low ion density plasma in the processing space to the substrate 150 or from the substrate 150 and through the low ion density plasma.

[0060] In yet another embodiment, the barrier screen 114 is formed of a silicon material, such as a crystalline silicon material, and the resistivity across the thickness of the barrier screen 114 is controlled by doping the substrate-facing surface.

[0061] In some embodiments, coating the surface of the barrier screen 114 with a dielectric material is performed over the entire surface of the barrier screen 114. Similarly, it may be possible to form a metal coating over the entire ceramic barrier screen 114. The distance between the barrier screen 114 and other chamber components will then be controlled in other ways to account for changes in the electric field distribution within the plate stack.

[0062] A voltage supply 260 is connected between the blocking mesh 114 and the substrate support 130. The voltage 260 enables control of a voltage difference between the blocking mesh 114 and the substrate support 130. The voltage may be configured to cause a voltage difference of about 0V to about 2000V, such as about 10V to about 2000V. The voltage may further include AC / DC waveform control so that a DC voltage or an AC voltage having a frequency less than or equal to about 7.5kHz, such as about 0kHz to about 7.5kHz, may be applied. Controlling the voltage difference between the substrate support 130 and the blocking mesh 114 enables control of the electric field therebetween during baking of the resist disposed on the substrate 150. Either the blocking mesh 114 or the substrate support 130 may be grounded. Figure 2A In an embodiment of the present invention, the blocking mesh 114 is grounded and the substrate support 130 is positively or negatively charged to form an electric field between the substrate support 130 and the blocking mesh 114 .

[0063] The substrate support 130 also includes a cryogen conduit 280. The cryogen conduit 280 circulates a cryogen or cooling fluid through a cryogen line 281. The cryogen line 281 circulates a cryogen through the substrate support 130. In one embodiment, the cryogen line 281 is disposed within the substrate support 130 and below the support surface 132. The cryogen line 281 may be disposed in a pie pattern, a ring tube pattern, or other suitable pattern that achieves substantially consistent and uniform cooling of the entire substrate support. In one embodiment, the cryogen line 281 is disposed in the same plane as the heating device 228. Alternatively, the cryogen line 281 is disposed in a plane different from the plane occupied by the heating device 228. The cryogen line 281 enables cooling and temperature control of the substrate 150 and the substrate support 130 during operation. Suitable heat transfer fluids that may be circulated through the cryogen line 281 include, but are not limited to, water, glycol-based fluids, and polymer-based fluids, such as, or its equivalent.

[0064] The chamber 100 described above may be controlled by a processor-based system controller, such as the controller 270. For example, the controller 270 may be configured to control the flow of various precursor gases through the gas sources 136, 142, 152, and coordinate the operation of the source match device 138 to facilitate plasma generation and flow within the chamber 100. The controller 270 may also be configured to control all aspects of the generation of the electric field within the chamber 100 by modulating and controlling the voltage applied to one or more of the components of the plate stack and the pedestal to generate the electric field within the processing volume 170. The controller 270 further operates to control various stages of the substrate processing sequence.

[0065] The controller 270 includes a programmable central processing unit (CPU) 272 operable with a memory 274 and mass storage devices, an input control unit, and a display unit (not shown), such as power supplies, clocks, caches, input / output (I / O) circuits, and the like, coupled to various components of the chamber 100 to facilitate control of substrate processing. The controller 270 also includes hardware for monitoring substrate processing via sensors in the chamber 100, including sensors that monitor flow, RF power, voltage potentials, and the like. Other sensors that measure system parameters such as substrate temperature, chamber atmospheric pressure, and the like may also provide information to the controller 270.

[0066] To facilitate control of the chamber 100 and associated plasma and electric field formation processes, the CPU 272 may be one of any form of general purpose computer processor that may be used in an industrial environment to control various chambers and subprocessors, such as a programmable logic controller (PLC). A memory 274 is coupled to the CPU 272 and is non-transitory and may be one or more of readily accessible memory such as a random access memory (RAM), a read only memory (ROM), a floppy disk drive, a hard disk, or any other form of digital storage (local or remote). Support circuits 276 are coupled to the CPU 272 for supporting the processor in a conventional manner. Plasma and electric field generation and other processes are typically stored in the memory 274, typically as software routines. The software routines may also be stored and / or executed by a second CPU (not shown) that is located remotely from the hardware controlled by the CPU 272.

[0067] The memory 274 is in the form of a computer-readable storage medium containing instructions that, when executed by the CPU 272, facilitate the operation of the chamber 100. The instructions in the memory 274 are in the form of a program product, such as a program that implements the method of the present disclosure. The program code may conform to any of a number of different programming languages. In one example, the present disclosure may be implemented as a program product stored on a computer-readable storage medium for use with a computer system. The program(s) of the program product define implementation functions (including the methods described herein).

[0068] In certain embodiments, the program(s) embody machine learning capabilities. Various data features include process parameters such as processing time, temperature, pressure, voltage, polarity, power, gas species, precursor flow rate, and the like. Relationships between features are identified and defined so that analysis by a machine learning algorithm can ingest the data and adapt to the process performed by the chamber 100. The machine learning algorithm may employ supervised learning or unsupervised learning techniques. Examples of machine learning algorithms embodied by the program include, but are not limited to, linear regression, logistic regression, decision trees, state vector machines, neural networks, naive Bayes, k-nearest neighbors, k-means, random forests, dimensionality reduction algorithms, and gradient boosting algorithms, among others. In one example, a machine learning algorithm is utilized to modulate RF power and precursor gas flow to form a plasma, and then facilitate maintaining a low ion density plasma that includes a greater concentration of free radicals than ions. The formation of a charged species cloud may be refined and improved in this manner by identifying the components of the charged species cloud (e.g., radicals and / or ions) and modifying chamber process or equipment characteristics to form and maintain a charged species cloud that exhibits desirable properties as an electric field coupling medium between an electrode (e.g., mesh 114) and substrate support 130.

[0069] Illustrative computer-readable storage media include, but are not limited to: (i) non-writable storage media that permanently stores information (e.g., a read-only memory device within a computer, such as a CD-ROM disk that can be read by a CD-ROM drive, a flash memory, a ROM chip, or any type of solid-state non-volatile semiconductor memory); and (ii) writable storage media that stores changeable information (e.g., a floppy disk or hard disk drive within a floppy disk drive, or any type of solid-state random access semiconductor memory). Such computer-readable storage media, when carrying computer-readable instructions that direct the functions of the methods described herein, are embodiments of the present disclosure.

[0070] The distance between the perforated bottom surface 242 of the gas distribution device 112 and the top surface 244 of the blocking screen 114 is less than about 20 mm, such as less than about 20 mm, such as about 5 mm to about 18 mm, such as about 10 mm to about 18 mm, such as about 12 mm to about 17 mm. The distance D between the bottom surface 234 of the blocking screen 114 and the substrate support surface 132 is about 2 mm to about 60 mm, such as about 5 mm to about 56 mm, such as about 16 mm to about 56 mm, such as about 32 mm to about 56 mm. The gaps between the gas distribution device 112, the blocking screen 114, and the substrate support surface 132 are small enough to achieve good electric field uniformity, while being large enough to prevent breakdown and discharge of the gas in the second plasma generation region 218 and the processing space 170, respectively. The distance D between the blocking screen 114 and the substrate support surface 132 is configured to enable control of the plasma formed in the processing space 170 while reducing the interaction of the plasma with the substrate 150. The plasma is controlled to provide a uniform and unidirectional electric field therethrough to interact with the substrate 150. The plasma within the processing volume 170 serves to electrically couple the substrate 150 and the barrier screen 114 and enables better control of the electric field through the processing volume 170.

[0071] Figure 2B A schematic cross-sectional view of a processing chamber 100b is depicted according to one embodiment. The processing chamber 100b is configured to perform a field-directed post-exposure bake operation on a substrate 150 having a photoresist or chemically modified resist layer disposed thereon. However, it is contemplated that other appropriately configured processing chambers may benefit from the embodiments described herein.

[0072] The processing chamber 100b includes an upper chamber body 116 coupled to a lower chamber body 120. The upper chamber body 116 and the lower chamber body 120 are coupled together to define at least a portion of a processing space 170. The substrate support 130 is disposed in the processing space 170 and is used to support the substrate 150 thereon during processing. Figure 2B In an example, the cooling plate 265 is cooled using temperature control techniques, such as flowing a heat transfer fluid therethrough and / or through a thermoelectric device.

[0073] The lower chamber body 120 includes at least one substrate transfer channel 160 disposed therethrough. The transfer channel 160 may have a slit valve door configured to provide access to the processing volume 170 via a transfer robot to move substrates 150 into and out of the processing volume 170. A pumping liner may be disposed radially inward from the lower chamber body 120. The pumping liner includes a plurality of openings connecting an exhaust plenum and the processing volume 170 to allow gas to be removed by the pump through the exhaust plenum.

[0074] The cooling plate 265 is disposed proximate to the substrate support 130. The substrate 150 may be moved proximate to the cooling plate 265 to assist in conditioning (eg, cooling) the substrate 150 after a post bake process.

[0075] exist Figure 2B In the example depicted in FIG. 1 , the cooling plate 265 has a bottom surface 141 facing the processing space 170. Although Figure 2B In the example depicted in , the cooling plate 265 is cooled and in close proximity to the substrate support 130 , but in other embodiments, other types of cooling plates may be disposed a distance away from the substrate support 130 .

[0076] The cooling plate 265 has an integrated channel 267 connected to a source of coolant 266. The integrated channel 267 can spiral through the cooling plate 265. The source of coolant 266 can provide a cryogen, such as deionized water, glycol, an inert high-performance fluorinated heat transfer fluid, or other fluid suitable as a coolant. Alternatively or in addition, the cooling plate 265 can have a thermoelectric cooling device, such as a Peltier cooling element and the like. The thermoelectric cooling device can be electrically driven to provide cooling (or even heating) to the cooling plate 265.

[0077] The cooling plate 265 can be any conductive material. For example, the cooling plate 265 is aluminum. In another example, the cooling plate 265 is an aluminum alloy with a coating. In some embodiments, the source of coolant 266 supplies a cryogen to the integrated channel 267 during the baking operation and the cooling operation.

[0078] When exposed to the bake process, the substrate 150 is located on the substrate support 130 portion of the substrate support assembly 126. The substrate support 130 is a heated pedestal that is configured to control the temperature of the substrate. The substrate support assembly 126 further includes a shaft 128 and a bellows that connects the substrate support assembly 126 to the lower chamber body 120. The bellows forms a seal between the processing volume 170 and the external environment. One or more backside gas sources can be coupled to the substrate support assembly 126 to supply backside gas to the substrate supporting surface 132 of the substrate support 130.

[0079] A power source and a motion device are also coupled to the substrate support assembly 126. The power source may be an AC or DC power source. The power source is configured to supply power to the motion device 148 and / or the heating device 228 within the substrate support 130. The motion device 148 is configured to effect movement of the substrate support assembly 126, such as raising or lowering the substrate support assembly 126, rotating the substrate support assembly about a central axis, or tilting the substrate support 130.

[0080] The substrate support assembly 126 additionally has a substrate lift 137. The substrate lift 137 is coupled to the moving assembly 135 to raise and lower the substrate lift 137. The substrate lift 137 is raised to an upper position to receive a substrate 150 from a transfer robot. The substrate lift 137 is lowered to place the substrate 150 onto the substrate support surface 132 of the substrate support 130 for processing. The substrate lift 137 may be a lift pin, a hoop, an edge support ring, or any suitable device for receiving a substrate 150 from a robot blade and moving the substrate from the substrate support surface 132 of the substrate support 130 to an elevated position above the substrate support 130. In one example, the substrate lift 137 is a plurality of lift pins. The lift pins may be moved to an elevated position to pick up a substrate 150 and balance the substrate 150 thereon by the pins. The elevated position places the substrate 150 close to the cooling plate 265. For example, the elevated position places the substrate 150 less than 10 mm from the cooling plate 265. For example, the elevated position places the substrate 150 between about 1 mm and about 10 mm from the cooling plate 265. During processing, when the substrate 150 is engaged with the heated substrate support 130, the lifting pins can be moved under the substrate supporting surface 132 of the substrate support 130 into the lifting pin holes. In another example, the substrate lifting device 137 is a hoop with an opening for a robot blade. The hoop can be moved to the elevated position to pick up the substrate 150 and hold the substrate 150 along its edge. During processing, when the substrate 150 is engaged with the heated substrate support 130, the hoop can be moved into the groove in the substrate supporting surface 132 of the substrate support 130.

[0081] Figure 3 Draw Figure 1 Schematic diagram of the processing chamber 100 and cooling chamber 302 of the photoresist. As previously described, one aspect of processing the substrate includes heating or baking the substrate to promote the reaction of the chemically amplified resist and promote resist deprotection. In some embodiments, a low ion density plasma is used as a charge transfer medium to couple current / electric field to the substrate and promote directional migration of species within the resist during the resist deprotection process. In other embodiments, baking the substrate is performed without applying or generating current or electric field to the photoresist.

[0082] In another embodiment, the substrate is heated and baked without applying a current / electric field to the substrate in the chamber 100. For example, the substrate is heated to between about 50°C and about 250°C for a time period between about 20 seconds and about 90 seconds. For example, between about 90°C and about 135°C for a time period between about 20 seconds and about 90 seconds. In another example, between about 110°C and about 120°C for a time period between about 20 seconds and about 90 seconds. The baking process is performed at a sub-atmospheric pressure in a vacuum environment. For example, the processing space 170 of the processing chamber 100 is maintained at a pressure between about 0.5 Torr and about 100 Torr in a vacuum environment. For example, the processing space 170 of the processing chamber 100 is maintained at a pressure between about 1 Torr and about 55 Torr, for example, between about 10 Torr and about 50 Torr. The sub-atmospheric pressure in the chamber 100 is generated by the pump 144. The sub-atmospheric pressure during the bake process may remain constant or vary during the bake process. In one embodiment, an inert gas is delivered to the processing volume 170 during the bake process. Suitable inert gases include, but are not limited to, nitrogen, helium, argon, and other sufficiently non-reactive gases.

[0083] It is believed that utilizing a vacuum environment during the bake process reduces the possibility of micro contamination (e.g., particle contamination) of the substrate that can lead to non-uniformity in critical dimensions of features such as contact holes and the like. Thus, the vacuum bake process improves substrate-to-substrate uniformity, and it is further believed that the vacuum bake environment provides additional benefits of reducing line edge and width roughness, reducing device defectivity, and improving device yield.

[0084] After the baking process is completed, the substrate 150 is cooled. In one embodiment, the substrate 150 cools from the elevated baking temperature to about room temperature, for example, between about 20° C. and about 30° C., within a time period between about 20 seconds and about 60 seconds. The substrate 150 can be cooled in the processing chamber 100 while still under vacuum. In another embodiment, to facilitate cooling, the substrate is transferred from the processing chamber 100 to the cooling chamber 302. In one embodiment, the cooling chamber 302 is a transfer chamber or a load lock chamber. In one embodiment, the cooling chamber 302 is coupled to the processing chamber 100. Alternatively, the transfer chamber 320 is disposed between the processing chamber 100 and the cooling chamber 302. In some embodiments, a robot 322 is disposed in the transfer chamber 320, and the robot 322 includes a substrate transfer blade to facilitate the movement of the substrate 150 from the processing chamber 100 to the cooling chamber 302.

[0085] In some embodiments, baking and cooling of substrate 150 occur at approximately the same pressure. In some embodiments, baking occurs at a higher pressure than cooling, and both pressures are subatmospheric. In some embodiments, baking occurs at a lower pressure than cooling, and both pressures are still subatmospheric.

[0086] The cooling chamber 302 defines a space 304. A chill plate 306 is disposed within the space 304, and the substrate 150 is positioned on the chill plate 306 to facilitate cooling of the substrate 150 after a bake process is performed in the processing chamber 100. The chill plate 306 is a substrate support capable of cooling the substrate by flowing a refrigerant through an internal cavity within the chill plate. In one embodiment, the temperature of the chill plate is controlled by flowing a fluid through a channel 308 in the chill plate 306. The channel 308 is in fluid communication with a fluid source 310, and a fluid flows from the fluid source 310 through the channel 308 to cool the substrate 150 disposed on the chill plate 306. In one embodiment, the fluid supplied from the fluid source 310 is a heat transfer liquid, such as water, or other suitable liquid.

[0087] In one embodiment, the cooling of the substrate 150 in the cooling chamber 302 is performed in a vacuum environment. For example, the space 304 is maintained at a sub-atmospheric pressure between about 0.5 Torr and about 100 Torr. The pressure maintained in the space 304 can be constant or varied during the cooling process. A pump 312 or other suitable vacuum generating device is in fluid communication with the space 304 and is responsible for reducing the pressure in the space 304. In one embodiment, an inert gas is delivered to the space 304 during the cooling process. Suitable inert gases include, but are not limited to, nitrogen, helium, argon, and other sufficiently non-reactive gases.

[0088] Figure 4 The operations of a method 400 for baking a substrate in a vacuum pressure environment are depicted according to one embodiment. At operation 410, masking features on a photoresist disposed on a substrate are exposed to a lithography scanner. Depending on the type of exposure process utilized, the lithography exposure process may be performed at ambient pressure or at vacuum pressure. At operation 420, the substrate is transferred to a post-exposure bake chamber and placed onto a substrate support 130. The pressure maintained in the processing space in the post-exposure bake chamber is reduced to a sub-atmospheric pressure, and the substrate is heated in a vacuum pressure environment. Figure 3 An example of substrate baking parameters in a vacuum pressure environment is described.

[0089] At operation 430, the substrate is transferred to a chill plate and cooled. Figure 3, the substrate 150 is transferred from the processing chamber 100 to the cooling chamber 302, wherein the substrate 150 is positioned on the chill plate 306 to facilitate cooling of the substrate after the bake process is performed in the processing chamber 100. At operation 440, the substrate is transferred from the chill plate to the developing chamber and the photoresist pattern is developed. In some embodiments, at least operations 420, 430, and 440 are all completed and the substrate is maintained at a sub-atmospheric pressure. In one embodiment, the substrate is transferred back to the lithography track equipment and a wet development process is performed at ambient pressure to further develop the resist.

[0090] Figure 5 The operations of a method 500 for baking a substrate in a vacuum pressure environment are depicted according to one embodiment. At operation 510, masking features on a photoresist disposed on a substrate are exposed in a lithography scanner. Depending on the type of exposure process utilized, the lithography exposure process may be performed at ambient pressure or at vacuum pressure. At operation 520, the substrate is transferred to a post-exposure bake chamber and placed on a substrate support. The processing space in the post-exposure bake chamber is brought to a sub-atmospheric pressure, and the substrate is heated in a vacuum pressure environment. In embodiments in which the substrate is maintained at a sub-atmospheric pressure while being transferred to a post-exposure bake chamber between lithography exposure processes, the post-exposure bake chamber maintains a sub-atmospheric pressure. About Figure 3 An example of substrate baking parameters in a vacuum pressure environment is described.

[0091] At operation 530, the substrate 150 is cooled in the post-exposure bake chamber while on the substrate support. Figure 2A , a substrate 150 is in a processing chamber 100, wherein the substrate 150 is positioned on a substrate support 130. In some embodiments, a refrigerant is circulated through a refrigerant line 281 within the substrate support 130 to facilitate cooling of the substrate 150 after a bake process is performed in the processing chamber 100. In other embodiments, cooling of the substrate is allowed without the use of a refrigerant. In other words, the heating device 228 in the processing chamber 100 stops receiving power and the substrate 150 cools as the processing chamber 100 cools. In some embodiments, at least operations 520, 530, and 540 are all completed and the substrate is maintained at a sub-atmospheric pressure. At operation 540, the substrate is transferred from the processing chamber 100 to a developing chamber and the photoresist pattern is developed. In one embodiment, the substrate is transferred back to the lithography track equipment and a wet development process is performed at ambient pressure to further develop the resist. In some embodiments, reference Figure 2B, the substrate 150 is in the processing chamber 100, wherein the substrate 150 is positioned on the substrate support 130. In some embodiments, the substrate 150 is elevated from the substrate support 130 to prevent residual heat from being transferred from the substrate support 130 to the substrate 150. While elevated, a cryogen is circulated through the integrated channels 267 within the cooling plate 265 to facilitate cooling the substrate 150 after a bake process is performed in the processing chamber 100. In some embodiments, during operation 530, the substrate 150 is under vacuum, but an inert gas is still provided in the processing volume 170.

[0092] By performing in-situ cooling, cooling can be performed more quickly when compared to conventional processes that transport the substrate 150 over long distances or allow passive cooling. Rapid cooling of the substrate 150 is enhanced by flowing a cryogen into the cooling plate 265 while active cooling is maintained in the processing chamber 100. Methods and apparatus for rapidly cooling a substrate 150 are provided.

[0093] Figure 6 A representative processing system that can be used to process substrates according to embodiments disclosed herein is depicted. As shown, processing system 600 includes a load port 610, a coating chamber 620, a processing chamber 100, an exposure chamber 630 (such as a scanner), a second processing chamber 100, a developing chamber 660, and a post-processing chamber 650. Each chamber of processing system 600 is coupled to each adjacent chamber by a transfer chamber 605 or a transfer chamber 615. Transfer chamber 605 and transfer chamber 615 can be substantially similar or different. Processing system 600 can be under vacuum. In some embodiments, one or more of chambers 100, 605, 615, 620, 630, 650, 660 are under vacuum so that when a substrate is transferred between chambers 100, 605, 615, 620, 630, 650, 660, the substrate is always under vacuum.

[0094] Load port 610 may be used to introduce a substrate into or remove a substrate from processing system 600. Coating chamber 620 may be used, for example, to apply photoresist to a substrate. Coating chamber 620 may be, for example, a spin coater. Exposure chamber 630 includes a photolithography scanner and may be used to expose a substrate to extreme ultraviolet (EUV) light under vacuum to form a latent acid image in a photoresist layer on the substrate. Processing chamber 100 is the chamber previously described.

[0095] The development chamber 660 can be used, for example, to remove portions of a photoresist layer. The development chamber 660 can be a wet development chamber, a dry development chamber. The development chamber 660 can develop the photoresist at a temperature between about 15° C. and about 30° C. and at atmospheric or sub-atmospheric pressures. For example, wet development can occur at about 0.5 Torr to about 760 Torr. For example, wet development can occur between 100 Torr and about 700 Torr. In yet another example, wet development can occur at less than 750 Torr.

[0096] The post-processing chamber 650 can be used, for example, to perform various post-processing steps on the substrate. In some embodiments, the post-processing chamber 650 can be the same as the processing chamber 100. The processing chamber 100 can be used for pre-exposure baking, post-exposure baking, pre-development baking, post-development baking, and / or other processing steps.

[0097] Figure 7 The operations of a method 700 for processing a substrate in a vacuum pressure environment are depicted according to one embodiment. At operation 710, a substrate is loaded into the processing system 600 and a photoresist is applied to the substrate by a coating chamber 620. The photoresist may be applied by a spin coating process, such as a wet spin coating process.

[0098] At operation 720, the substrate is transferred to the exposure chamber 630 and exposed to an EUV process to pattern the photoresist on the substrate. Depending on the type of exposure process utilized, the photolithography exposure process may be performed at ambient pressure or at vacuum pressure. For example, the photolithography exposure may be a 193nm photolithography process. The EUV process is performed at a temperature between about 15°C and about 30°C and under vacuum. For example, the EUV process occurs at about 0.5 torr to about 760 torr. For example, between 100 torr to about 700 torr. In another example, less than 750 torr.

[0099] At operation 730, the substrate is transferred to the processing chamber 100 / 100b, and the previously described post-exposure baking method 400 / 500 is performed. The substrate is maintained at a sub-atmospheric pressure while being transferred to the processing chamber 100 / 100b between photolithography exposure processes, and the post-exposure baking chamber maintains a sub-atmospheric pressure. During the baking operation, the processing space and the substrate in the processing chamber 100 / 100b are heated in a vacuum pressure environment. An example of substrate baking parameters in a vacuum pressure environment is described above.

[0100] At operation 740, the substrate 150 is cooled in the processing chamber 100 / 100b. Figure 2B, when the substrate 150 is lifted from the substrate support 130 and positioned adjacent the cooling plate 265, the substrate 150 is rapidly cooled in situ. In some embodiments, a cryogen is circulated through an integrated channel 267 within the cooling plate 265 to facilitate cooling the substrate 150 after the bake process is performed in the processing chamber 100. In some embodiments, at least operations 720, 730, and 740 are all completed and the substrate is maintained at a sub-atmospheric pressure. In some embodiments, as Figure 3 As described in , a substrate is moved to a specific cooling chamber so that another substrate can be processed.

[0101] At operation 750, the substrate is transferred from the processing chamber 100 / 100b to the development chamber 660 and the photoresist pattern is developed. In one embodiment, the substrate is transferred back to the photolithography track and a wet development process is performed at ambient pressure to further develop the resist.

[0102] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the present disclosure may be devised without departing from the basic scope of the present disclosure, the scope of which is to be determined by the claims that follow.

Claims

1. A substrate processing method, comprising the following steps: exposing a photoresist disposed on a substrate to electromagnetic energy; transferring the substrate to a substrate support disposed in a processing chamber; baking the substrate on the substrate support at a sub-atmospheric pressure in a first vacuum environment; and The substrate is cooled in a second vacuum environment at a second atmospheric pressure.

2. The method of claim 1, wherein the first atmospheric pressure has a pressure between about 0.5 Torr and about 100 Torr.

3. The method of claim 2, wherein the pressure of the first atmosphere is constant during the baking.

4. The method of claim 2, wherein the pressure of the first atmosphere varies during the baking.

5. The method of claim 1, wherein the substrate is heated to a temperature between about 50°C and about 250°C during the baking.

6. The method of claim 1, wherein the cooling is performed in a chamber different from the processing chamber.

7. The method of claim 6, wherein the second atmosphere has a pressure between about 0.5 Torr and about 100 Torr.

8. The method of claim 7, wherein the pressure of the second atmosphere is constant during cooling of the substrate.

9. The method of claim 7, wherein the pressure of the second atmosphere varies during cooling of the substrate.

10. The method of claim 1, wherein the step of baking the substrate is performed without applying or generating an electric current or an electric field to the photoresist.

11. A substrate processing method, comprising the following steps: exposing a chemically amplified photoresist disposed on a substrate to a photolithography exposure process under a sub-atmospheric pressure; transferring the substrate to a substrate support disposed in a processing chamber having a processing space; baking the substrate in a vacuum environment at a sub-atmospheric pressure in the processing space; and The substrate in the processing volume of the processing chamber is cooled at the sub-atmospheric pressure.

12. The method of claim 11, wherein the sub-atmospheric pressure is between about 1 Torr and about 55 Torr.

13. The method of claim 11, wherein the substrate is heated to a temperature between about 90°C and about 135°C during the baking.

14. The method of claim 11, wherein the substrate is maintained at the sub-atmospheric pressure during the exposing, transferring, baking, and cooling.

15. The method of claim 11, wherein the step of cooling the substrate further comprises the steps of: The base plate is raised into proximity with a cooling plate.

16. The method of claim 15, wherein the substrate is less than 10 mm from the cooling plate.

17. A substrate processing method, comprising the following steps: applying a photoresist to a substrate in a coating chamber; Transferring the substrate to an exposure chamber and performing an EUV exposure process under vacuum; transferring the substrate onto a substrate support in a processing chamber having a processing space; baking the substrate on the substrate support at a sub-atmospheric pressure in the processing volume; cooling the substrate to less than 30° C. in the process volume of the process chamber at a pressure less than 100 Torr by raising the substrate toward a cooling plate opposite the substrate support; and The substrate is transferred from the processing chamber to a developing chamber and the photoresist is developed.

18. The method of claim 17, wherein the substrate is heated to a temperature between about 90°C and about 135°C during the baking.

19. The method of claim 17, wherein the sub-atmospheric pressure is maintained between the exposing and the baking of the substrate.

20. The method of claim 17, wherein cooling the substrate is performed at a pressure lower than a pressure during the baking.

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