Reducing overhead in processor array search

Abstract

A processor (100) has: an instruction memory (114) configured to store processor instructions; a data memory (120) configured to store processor data representing an array, the array comprising a plurality of data elements; a controller (102); and an instruction pipeline (104). The instruction pipeline includes: a load stage circuit (126) configured to load array elements from the data memory; a comparison stage circuit (128) configured to compare the array elements to a reference value; a storage stage circuit (130) configured to store a result set comprising a result of the comparison of the array element with the reference value; and a loop hit detection stage circuit (132) configured to determine whether any of the set of results is associated with a hit for the reference value.

Description

Background Art

[0001] The described examples relate to electronic processors and more particularly to improving hardware or processor performance in processor array searches, such as reducing overhead.

[0002] Computational programming and processing often require searching for values ​​in an array, usually by comparing a predetermined value to each element in the array. Once a search match (hit) occurs, the position (index) of the matching array element is often returned or stored, usually for subsequent actions. Alternatively, the search can be completed when only the element being searched is identified somewhere in the array. Searching can be performed in various forms, examples of which include linear (sequential) and interval (e.g., binary) searches. Data array value searches can be used in a large number of applications, including, for example, digital data processing and image / speech processing.

[0003] The processor architecture can be programmed to search for elements in an array in a higher-level language, and the programming is compiled into some lower-language level instructions (object code) that are processed by the processor pipeline at the machine-level instructions. Generally speaking, the lower-language level instructions include three functions: (i) first, load one or more instructions and operands, the operands including the value to be searched and the array element; (ii) second, execute the instruction to compare the value to be searched with the array element; and (iii) in response to the search result, if a comparison mismatch (miss) occurs, then the branch control causes the flow to loop and repeat the three functions for the next array element, however, if there is a comparison match (hit), then the branch control ends the search sequence and any loops, and takes the next action if the search is complete. Therefore, when a miss occurs and the branch needs to repeat or loop those same steps, the resource penalty incurred is sometimes called loop overhead, which may include repeating the loop until the search is completed. In addition, in many contemporary processors (e.g., reduced instruction set computers and their variants), the processor includes a pipeline design with multiple stages, often involving instruction fetch, operand reading, execution, and writeback. As successive instructions pass through the pipeline, the efficiency of processing later instructions in the sequence often depends on processing earlier instructions in the sequence, such as pauses, pipeline refreshes, branch predictions, and otherwise managing pipeline artifacts. The depth of the pipeline (meaning the number of its stages) creates pipeline overhead. Therefore, array searches can be resource intensive in terms of both loop overhead and pipeline overhead. Examples that can be improved on various of the above considerations as well as other concepts are provided herein, as further detailed below. Summary of the invention

[0004] In one example, there is a processor comprising: an instruction memory configured to store processor instructions; a data memory configured to store processor data representing an array, the array comprising a plurality of data elements; a controller; and an instruction pipeline. The instruction pipeline comprises: a load stage circuit configured to load array elements from the data memory; a compare stage circuit configured to compare the array elements with a reference value; a store stage circuit configured to store a result set comprising a result of the comparison of the array elements with the reference value; and a loop hit detection stage circuit configured to determine whether any of the result sets is associated with a hit on the reference value.

[0005] Other aspects are disclosed and claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 A block diagram of the processor.

[0007] Figure 2 Shown by Figure 1 The instruction process implemented by the object code in the processor.

[0008] 3A to 3C illustrate the use of the Figure 2 The corresponding array search instance of the instruction process.

[0009] Figure 4 Shown in a larger array Figure 2 Extension of instruction processing and concurrent instructions across a large number of clock cycles.

[0010] Figure 5 shows the use of Figure 4 Search instance of the instruction process.

[0011] Figure 6 Instruction processing with additional concurrency by operating simultaneously with respect to two different array elements is shown.

[0012] FIG. 7 shows the use of Figure 6 Array search instance of the instruction process.

[0013] Figure 8 An instruction progression is shown with instructions directed to four different array elements simultaneously.

[0014] FIG. 9 shows the use of Figure 8 Search instance of the instruction process.

[0015] Fig.10 Flowchart of the example array search method. DETAILED DESCRIPTION

[0016] Figure 11 is an example block diagram of a processor 100 including structures and operable to perform an array search. The processor 100 may take various forms, such as a general purpose microprocessor, a special purpose processor, a digital signal processor, a microcontroller, or the like. The processor 100 includes a controller 102, which may be coupled to control various other blocks of the processor 100, including at least one instruction pipeline 104. The instruction pipeline 104 represents control logic that manages the flow of operations and interacts with the various operation blocks, and it includes a number of different stages that are logically characterized as being functionally associated with each stage when instructions are processed by the corresponding stage. Each of the stages has some form of physical circuit representation, such as control logic to complete the stage functionality alone or in combination with other blocks shown (or understanding blocks that are not shown separately). For example, the stage includes a number of application specific integrated circuits, including: an instruction fetch stage 106, an instruction decode stage 108, an operand fetch stage 110, and an execution stage 112. Conceptually, the stages are generally sequential, and each occurs in a separate clock cycle (or cycles), with functionality occurring in the stage's hardware, or in combination with one or more other blocks of the processor 100. However, the functionality / timing of one stage may overlap with another, and each stage may be further subdivided physically or operationally in different architectures and different processor models. Thus, in general, the discussion of the instruction pipeline 104 is not intended to be limiting, as the concepts described and claimed in this document may be implemented in a variety of pipelined processors.

[0017] The instruction fetch stage 106 is coupled to an instruction buffer 114, and it fetches one or more instructions at a time from the instruction buffer 114. The instruction buffer 114 is coupled to a system bus 116, and it temporarily stores instructions received by it from the system bus 116. The system bus 116 is coupled to various blocks, including a system memory 118, from which instructions are transferred to the system bus 116. The system memory 118 may alternatively include one or more levels of cache memory. The transfer of instructions from the system memory 118 to the instruction buffer 114 via the system bus 116 may be under the operation of the controller 102, which may include a dedicated structure to participate in such instruction transfer, such as a direct memory access (DMA) controller. Thus, through these various structures and paths, the system memory 118 acts as a processor (or computer) readable storage medium in which instructions are stored and then readable for execution by the processor 100. Each fetched instruction is in a format compatible with the specifications of the processor 100, such as representing object code level instructions resulting from compiling higher level language programming instructions. In one example, the code may be provided directly to the processor 100 in object code form (and compiled elsewhere, such as on a general purpose computer). In the context of the current example, the higher level language programming instructions include one or more array search instructions intended to cause an array to be searched to determine whether a reference value matches any element within the array, and optionally also to identify the location (index) within the array where a match is identified (if any). Therefore, unless otherwise stated, it should be understood that the instructions at the levels discussed below are those object code instructions resulting from compiling such one or more higher level array search instructions.

[0018] The instruction decode stage 108 receives one or more instructions at a time and then decodes them according to the binary state and position of the bits in each instruction. In general, an instruction may include one or more fields, such as an instruction opcode indicating the function of the instruction, and one or more operands on which the operation of the instruction directly acts or indicates the location of something to be acted upon. More than one instruction may be decoded at a time. For example, a very long instruction word (VLIW) architecture may include some form of instruction concurrency, where more than one instruction may be processed by one or more of the pipeline 104 stages, including the instruction decode stage 108. The VLIW may be formatted, for example, as one larger instruction or fixed instruction packet. In any case, a program may explicitly provide multiple instructions at the same time, where the instructions may be decoded and subsequent steps may be taken at the same time, provided that there are no dependencies among the instructions that prevent one or more from being executed simultaneously or otherwise taken out of order.

[0019] Operand extraction stage 110 is controlled to read one or more values ​​for subsequent corresponding instruction execution based on one or more instruction functions identified by instruction decoding stage 108, wherein such value retrieval is referred to as extraction from registers or data memory elements. The extracted values ​​may represent data, such as one or more data elements in an array to be searched. Typically, the read values ​​come from a block of adjacent and fast data storage, such as registers 120. Registers 120 may also be coupled to system bus 116 via system bus 116, wherein values ​​are also provided between registers 120 and system memory 118. Thus, the extracted values ​​may be immediate register values ​​in registers 120, such as already valid in registers according to the execution of previous instructions, or may be transferred from a storage location in system memory 118. In addition, to the extent that processor 100 supports concurrency, operand extraction stage 110 may then extract multiple values ​​simultaneously, such as corresponding to multiple instructions to be executed, respectively.

[0020] The execution stage 112 executes one or more instructions, and to the extent that the execution of the instructions provides a data result, the result is written to an appropriate target destination, such as a register 120 or a write buffer 122, which is also coupled to the system bus 116. The execution of the execution stage 112 is typically implemented in conjunction with additional circuitry in addition to the control logic of the stage, including, for example, dedicated functional units 124, each of which is operable to perform certain types of operations on a unit basis (e.g., integer operations, floating point operations, video processing, etc.). As described later, in the present example, the execution stage 112 also includes additional structure and / or functionality implemented to provide and complete concurrent operations for the array search function, including a LOAD_EX stage 126 for loading array elements, a COMPARE_EX stage 128 for comparing the loaded array elements to a reference value, a STORE_COMP_HIS_EX stage 130 for storing / aggregating a history of each comparison as the array is processed, and a LOOPDECISION_EX stage 132 for periodically looking at the history and determining subsequent actions from the history, such as continuing the search function or causing it to end. The stored historical and periodically reviewed results may be indicated in one or more of registers 120, so for illustration purposes, additional cycle processing registers 134 are shown as part of registers 120. Of course, execution stage 112 and functional units 124 may include and provide a variety of other structures and functionality, such as associated with conventional or yet to be developed processor architectures. In any case, when execution stage 112 executes its corresponding instruction for a result, the result may be represented by a value written to write buffer 122, from which the value may be further read or transmitted to some other destination, such as via system bus 116.

[0021] Processor 100 may also include other structures and functionalities. For example, Figure 1Certain such items are included, including an input / output (I / O) block 136 and peripheral devices 138. The I / O block 136 may be coupled to the system bus 116 and provide an interface (not explicitly shown) to one or more other devices external to the processor 100 to facilitate communication between the I / O block 136 (and the system bus 116) and such devices. The peripheral devices 138 may have various formations known in the art. Other structures and functionality, such as those existing or developed in the art, may also be included, but are not shown for simplicity. For example, in a secure processor architecture, additional safety and / or security structures may be included between the system bus 116 and the physical layer interface, such as an I / O block 136 interface to an external connection, or even an interface to the system memory 118 and the peripheral devices 138. Other structures are also anticipated and will be determined by those skilled in the art.

[0022] For example, consider the higher-level programming pseudocode in Table 1 below.

[0023] Instruction sequence number instruction INS0 For i=0, N INS1 COMPARE, REF, ARRAY[i] INS2 If you miss INS3 i=i+1 INS4 Go to INS1 INS5 Otherwise, if it is a hit, store i and set HIT_FLAG

[0024] Table 1

[0025] In general, the pseudocode of Table 1 is intended to illustrate an example loop that compares a reference value REF to each value in an array ARRAY having a total of N+1 elements. The comparison conditional loop index [i] shown by the pseudocode and as executed by the corresponding target code in the processor 100 starts from index [i=0] until [i=N], as controlled by the initialization and various conditional instructions at INS0 and advancing the index through INS3. Thus, the collective code compares the ARRAY values ​​at one index [i] at a time until a comparison hit is found, after which the index [i] from the hit is stored and the flag HIT_FLAG is set, or loops to evaluate the next ARRAY value at an increasing index [i] on each miss until every element in the entire ARRAY is compared to REF.

[0026] In some alternative architectures, the pseudo code of Table 1 typically requires a number N clock cycles for each loop iteration until a hit is found. Each such iteration includes at least loading, comparison, and then a branch decision based on the result of the comparison, so N represents the total number of clock cycles to implement these steps for a given iteration. In general, for each comparison miss, the branch decision repeats the loop, thus repeating N clock cycles. Therefore, for an array search with a total of M misses and with a resulting loop, then at least M*N clock cycles are consumed to complete the array search. In other words, the loop overhead for each miss is essentially compound, so for searching a relatively large number of elements, the loop overhead penalty can be quite large. In contrast, the processor 100 implements structure and functionality to greatly reduce this overhead, as described in detail below.

[0027] Figure 2 The instruction process 200 is shown, as indicated by Figure 1 The target code in the processor 100 is implemented and used to realize the functionality corresponding to the pseudo code of Table 1. Figure 2 The first example is shown and also introduces and simplifies additional examples provided later. Figure 2 In the example shown in FIG. 1 , and in contrast to later examples, the LOAD_EX stage 126 of the execution stage 112 supports a single comparison operation per clock cycle, while other portions of the execution stage 112 may perform other functions concurrently with the comparison. Figure 2 , the vertical axis shows consecutive clock cycles (downward), where the example process spans a total of six clock cycles, numbered 0 to 5. In addition, Figure 2 The horizontal axis shows the sequence to which a particular execution instruction belongs. In the first example, Figure 2 The first row indicates clock cycle 0, during which only a single instruction (LOAD A[0] from instruction sequence 0) is executed through LOAD_EX stage 126 and the first array element is loaded into the register. In the second example, Figure 2 The second row indicates clock cycle 1 during which two instructions are executed, namely instruction sequence 0, COMPARE A[0], REF is executed by COMPARE_EX stage 128 and compares the register value loaded in clock cycle 0 with a reference value REF, which may have been previously stored in a separate register, however in the same clock cycle 1, for instruction sequence 1, an additional load (as shown as LOAD A[1]) is performed by LOAD_EX stage 126 to load the next ARRAY element into the register. The load instruction may be initiated earlier in the instruction pipeline 104, such as as part of the operand fetch stage 110, but it is completed in LOAD_EX stage 126 and is separate from other stages, such as COMPARE_EX stage 128. Therefore, during clock cycle 1, portions of two different instruction sequences 0 and 1 are executed simultaneously, one in LOAD_EX stage 126 and the other in COMPARE_EX stage 128. The remaining examples will be further understood below.

[0028] although Figure 2 The overall example compares three array elements to REF in a total of four clock cycles (0, 1, ..., 3), but for each instruction sequence (0, 1, 2), an additional target code instruction is executed after the comparison and storage of the history associated with the comparison results, this additional instruction is identified herein as STORE_COMP_HIS, and it is executed by STORE_COMP_HIS_EX stage 130. In this example and other examples described below, the history stores a hit / miss indicator of the comparison results. The hit / miss indicator can be stored in a temporary or dedicated storage location, such as in a one-bit HIS_FLAG register or in a value that is a portion of a larger number of bits, which can be Figure 1 The loop processes portions of register 134. For example, in clock cycle 2, STORE_COMP_HIS stores the hit / miss indicator for instruction sequence 0, that is, COMPARE A[0], REF for the immediately preceding clock cycle 1. Similarly, in clock cycle 3, STORE_COMP_HIS stores the hit / miss indicator for instruction sequence 1, that is, COMPARE A[1], REF for the immediately preceding clock cycle 2. Finally, in clock cycle 4, STORE_COMP_HIS stores the hit / miss indicator for instruction sequence 2, that is, COMPARE A[2], REF for the immediately preceding clock cycle 3. Thus, multiple instances of STORE_COMP_HIS store and provide an aggregate history of successive comparisons, each comparison associated with a different array element, and facilitate the additional functionality described below.

[0029] Figure 2 Instruction process 200 also shows in clock cycle 5 that following several instruction sequences (three such sequences (0, 1, 2) in the example provided), additional LOOP DECISION instructions are executed by LOOP DECISION_EX stage 132 with respect to the data loaded and compared in the aforementioned comparison group. In the example, the LOOP DECISION instruction processes the aggregated history information (from multiple prior executions of STORE_COMP_HIS) of sequences 0 to 2 to determine whether a comparison hit has occurred, and if so, at which array index position the hit occurred. The hit position index may be stored in a temporary or dedicated storage location, such as in a HIT_INDEX register, which may also be part of loop processing registers 134. If such a hit has not occurred, then as shown by the following additional examples, LOOP DECISION may direct that additional array elements may be processed. Conversely, if a hit has occurred, then the loop may draw a conclusion and branch to one or more other instructions involving functions other than array searching. Therefore, and as further demonstrated below, aggregating loop histories (STORE_COMP_HIS) and processing of such histories (LOOP DECISION) can significantly reduce loop overhead during array searches compared to the prior art.

[0030] 3A to 3C illustrate the use of Figure 2Corresponding array search instances 300_A, 300_B, and 300_C of instruction process 200. Each of these figures shows the first three ARRAY elements (indexes [0], [1], [2]) having instances of stored values ​​and a search reference of value REF=30. Generally speaking, in FIG. 3A, a hit occurs at A[2] (i.e., the location of value 30), in FIG. 3B, a hit occurs at A[1], and in FIG. 3C there is no hit. Additional details below relate to aggregate loop history and its processing.

[0031] For the example values ​​in FIG. 3A and according to Figure 2Process, in clock cycle 0, A[0]=16 is loaded into the register, in clock cycle 1, the register value is compared with REF=30, thereby generating a miss, and in clock cycle 2, the corresponding miss history is stored by HIS_FLAG, for example, where HIS_FLAG=0 indicates a miss. Partially overlapping the above, in clock cycle 1, A[1]=62 is loaded into the register, in clock cycle 2, the register value is compared with REF=30, thereby generating a miss, and in clock cycle 3, the corresponding miss history is stored by HIS_FLAG=0. Also partially overlapping the above, in clock cycle 2, A[2]=30 is loaded into the register, in clock cycle 3, the register value is compared with REF=30, thereby generating a hit, and in clock cycle 4, the corresponding hit history is stored, for example, where HIS_FLAG=1 indicates a hit (where, of course, complementary miss / hit values ​​can be used for HIS_FLAG, such as a one-bit value). In clock cycle 5, when LOOP DECISION is executed, the stored HIS_FLAG is processed and the HIT_INDEX location of the hit (at [2]) is identified; in an example, the identification may be implemented as a count, starting at count zero, with HIS_FLAG being incremented at the earliest in time and thereafter for each clean flag, but incrementing and stopping once a hit is encountered (HIS_FLAG=1). It should be noted that the HIT_INDEX value is only considered valid when a hit occurs, because before then it is essentially an increasing miss count rather than identifying the location where the hit occurred. In FIG. 3A , for example, for HIS_FLAG=0 from clock cycle 2, the count is equal to 0, for HIS_FLAG=0 from clock cycle 3, the count is incremented to 1, and at clock cycle 4, for HIS_FLAG=1, it increments but stops at the next valid count of 2, meaning that at that time HIT_INDEX=2 accordingly identifies array element A[2] as the location where the comparison hit occurred. 3A , the count evaluates three such flags (corresponding to A[0], A[1], and A[2]), and may be incremented from 0 to 2 in a single clock cycle. Additional examples are provided below, with other potential increment values ​​in a single cycle.

[0032] In FIG. 3B , again in clock cycle 0, A[0]=16 is loaded into the register, in clock cycle 1, the register value is compared with REF=30, thereby generating a miss, and in clock cycle 2, the corresponding miss history is stored by HIS_FLAG=0. Partially overlapping the above, in clock cycle 1, A[1]=30 is loaded into the register, in clock cycle 2, the register value is compared with REF=30, thereby generating a hit, and in clock cycle 3, the corresponding hit history is stored by HIS_FLAG=1. Also partially overlapping the above, in clock cycle 2, A[2]=62 is loaded into the register, in clock cycle 3, the register value is compared with REF=30, thereby generating a miss, and in clock cycle 4, the corresponding miss history is stored by HIS_FLAG=0. In clock cycle 5, when LOOP DECISION is executed, the stored HIS_FLAG is processed, and the HIT_INDEX of the hit (at [i=1]) is identified. Thus, although a hit was detected at clock cycle 2, at least one additional comparison occurs after the hit in clock cycle 3, but the history of all comparisons is stored and evaluated after all three comparisons are completed. The index position of the hit may again be implemented as a count indicated as HIT_INDEX, starting with the earliest HIS_FLAG in time, and continuing to increment with each flag, while stopping and being valid once a set (HIS_FLAG=1) is encountered. In FIG. 3B , for example, the count is equal to 0 for HIS_FLAG=0 from clock cycle 2, increments to 1 for HIS_FLAG=1 from clock cycle 3, and stops when the first hit is encountered without changing any later stored history information, including HIS_FLAG=0 from clock cycle 4 in this example. Thus, by completing clock cycle 5, LOOP DECISION determines that a hit has occurred at index [i=1].

[0033] In FIG. 3C , generally speaking, the above process is applied again, where in clock cycle 0, A[0]=16 is loaded into the register, resulting in a miss in clock cycle 1, and the miss is stored as HIS_FLAG=0 in clock cycle 2. Similarly, but delayed by one corresponding clock cycle, in clock cycle 1, A[0]=62 is loaded into the register, resulting in a miss in clock cycle 2, and the miss is stored as HIS_FLAG=0 in clock cycle 3, and with another clock delay, the same delay occurs for A[2]=22. Thus, in clock cycle 5, LOOP DECISION evaluates the three stored HIS_FLAGs and determines that a hit did not occur because each has a value of zero. This determination would indicate a count of zero, for example, in the counting manner described above. Specifically, the HIT_INDEX count is equal to 0 for HIS_FLAG=0 from clock cycle 2, increments to 1 for HIS_FLAG=0 from clock cycle 3, and increments again to 2 for HIS_FLAG=0 from clock cycle 4; however, because a hit did not occur, the HIT_INDEX value of 2 is invalid because it does not identify the location of an array hit at that time when a hit has not occurred. Therefore, by completing clock cycle 5, LOOP DECISION determines that a hit did not occur, e.g., based on all history flags being cleared, thereby invalidating the HIT_INDEX value. However, as shown in a later example, additional array search instructions may be used for larger arrays, in which case the HIT_INDEX counter may continue to increment from its current (e.g., HIT_INDEX=2) value if and until verified when a hit is detected.

[0034] In view of the foregoing, for example, Figure 1 Processor 100 and Figure 2 Instruction process 200 provides a structure and method by which an array can be searched with at least one comparison per each of consecutive clock cycles. This can be contrasted with an alternative technique that does not load elements for subsequent iterations until all step sets for prior iterations are completed, the alternative technique comprising loading, comparing, and the resulting action taken for the prior iteration, in which case the delayed loading for subsequent iterations causes additional clock cycles compared to processor 100. The described example can greatly reduce loop overhead, especially for larger arrays or where hits occur anywhere outside the first few positions in the array, because the prior art has three times the clock cycles per array index and also three times the aggregation for each miss, yet the described example can compare per clock cycle. In addition, and as further shown below, additional examples can be implemented in additional scaling or concurrent situations to achieve even greater performance and / or efficiency.

[0035] Figure 4Shows the same axis convention and contains Figure 2 The instruction process 200 is the instruction process 400. Figure 4 However, additional target code instructions are provided, such as to indicate the additional benefits of array searches in larger arrays and concurrent instructions spanning a large number of clock cycles, as further considered in an example later in conjunction with FIG. 5. For example, Figure 2 The diagram and corresponding description show the LOOP DECISION in clock cycle 5; Figure 4 Add additional instruction sequences in the same clock cycle and before it. For example, in clock cycle 3, Figure 2 indicates a history store (STORE_COMP_HIS) for instruction sequence 1 and a reference compare (COMPARE A[1],REF) for instruction sequence 2. While those two instructions are being executed, Figure 4 A load (LOAD A[3]) for the next consecutive instruction sequence 3 is also added. As another example, in clock cycle 4, Figure 2 Indicates the history storage (STORE_COMP_HIS) for instruction sequence 2; when the instruction is executed, Figure 4 A comparison (COMPARE A[3], REF) for the next consecutive instruction sequence 3 and a load (LOAD A[4]) for the next consecutive instruction sequence 4 are also added. Therefore, although Figure 2 Depicts a single execution of LOOP DECISION in clock cycle 5, but Figure 4 The depiction of clock cycle 5 presents simultaneous execution of instructions and a larger array, such that the LOOP DECISION of instruction sequences 0 through 2 occurs concurrently with partial processing of all three of the above instruction sequences (3, 4, and 5) in different stages during the same clock cycle. If the LOOP DECISION in clock cycle 5 determines that no hit has occurred in any of array elements A[0], A[1], or A[2] (equivalent to FIG. 3C search example 300_C), then an array search has begun with respect to additional array elements A[3], A[4], and A[5].

[0036] The above process continues for the entire instruction process 400 until the entire process is completed without a hit, or as long as a hit is not encountered and detected in the three array element sets preceding the LOOP DECISION example. For example, in clock cycle 8, another LOOP DECISION is executed, and then the stored history of array comparisons for array elements A[3], A[4], or A[5] is processed. If a hit has occurred, it will be indicated by HIS_FLAG=1, the index of the hit will be identified, and the instruction process 400 can then branch elsewhere without executing some or all of the instructions shown after clock cycle 8. Conversely, if a hit has occurred, the instruction process 400 continues through clock cycle 11, at which time another LOOP DECISION is executed, and then the stored history of array comparisons for array elements A[6], A[7], or A[8] is processed, its stored history is evaluated and a hit and its corresponding index is detected, or it continues again through the remaining clock cycles to clock cycle 14. Thus, in any of the foregoing, comparisons can be performed in successive clock cycles for a large number of array elements, thereby inferring whether and when a hit is found in this set of array elements, where the set size is determined by the frequency of the LOOP DECISION. And, by completing clock cycle 14, a total of 12 array elements have been loaded, compared, and potential hits therein and their indices have been detected.

[0037] Figure 5 shows the use of Figure 4Search instance 500 of instruction process 400. Overall, search instance 500 includes twelve array elements (indexes [0], [1], ...,

[11] ), wherein instruction process 400 executes LOOP DECISION for three consecutive sets of array elements corresponding to three instruction sequences at a time. Thus, across clock cycles 0 to 5, the first three sets of array elements are loaded, compared to reference REF, and the hit history including the aggregate value of HIS_FLAG is stored and then evaluated with LOOP DECISION. In the illustrated example, the first set does not produce a hit, i.e., HIS_FLAG=0 for each corresponding comparison, and if implemented by a counter, LOOP DECISION is incremented for each HIS_FLAG=0, thereby until the HIT_INDEX count is 2. Furthermore, during those clock cycles 0 to 5, i.e., in clock cycle 3, instruction processing of a second consecutive set of three array elements is started, and ends with the evaluation of LOOP DECISION in clock cycle 8. In the example shown, the second set also does not produce a hit, so a flag of no hit (miss) is stored or appended to the flags from the first set, and if implemented by a counter, LOOPDECISION increments for each HIS_FLAG=0, thereby until the HIT_INDEX count is 5. The same process continues for the third consecutive set of three array elements, where the counter then counts to 8 at clock cycle 11, and then continues for the fourth consecutive set of three array elements starting, thus ending in clock cycle 14. In clock cycle 14, LOOP DECISION increments the HIT_INDEX count from 8 to 9 due to the miss of comparing array element A[9], and then increments the count from 9 to 10 due to the hit of comparing array element A

[10] and stops any additional increments, thereby verifying the HIT_INDEX count at that time. Therefore, of the 14 clock cycles in instruction process 400, most of those clock cycles include consecutive comparisons following the comparison of the immediately previous clock cycle, thereby effectively reducing the loop overhead when performing array searches.

[0038] Figure 6 Shows the same axis convention and contains Figure 2 The instruction process 200 is the instruction process 600. Figure 6 In, however, additional concurrency is provided because each target code instruction operates simultaneously with respect to two different array elements, as will be further considered in an example later in conjunction with FIG. 7. This concurrency may be achieved, for example, in Figure 1The structure and functionality of the instruction pipeline 104 are implemented in an appropriate stage of the instruction pipeline 104, such as where each of the LOAD, COMPARE, and STORE_COMP_HIS instructions has multiple operands corresponding to corresponding multiple array elements. For example, in clock cycle 0, LOAD A[1], A[0] is shown, which is intended to illustrate pipeline processing of the instruction such that when executed, both array elements A[1] and A[0] are loaded into corresponding registers (or corresponding portions of the same register) in the same clock cycle. Thereafter and as a next example, in clock cycle 1, COMPARE: A[1], REF; A[0], REF is shown, which is intended to illustrate pipeline execution where each of array elements A[1] and A[0] is compared to REF in the same clock cycle. Thereafter and as a final example, in clock cycle 2, STORE_COMP_HIS stores the history of the two compared array elements. For example, where the earlier example used a single bit for HIS_FLAG, in Figure 6 In an example, HIS_FLAG may use two bits, one for each value compared in the same instruction sequence in the immediately preceding clock cycle; for reference to such multi-bit implementations, the flags may be represented as HIS_FLAG{mse,lse}, where operand mse is the more significant array element compared (A[1] in the current example), and operand lse is the less significant array element compared (A[0] in the current example). This convention is by way of example, as an alternative to considering / implementing each bit as a separate flag (e.g., HIS_FLAG1 and HIS_FLAG2). After storing the history, for example, as shown in clock cycle 5, LOOP DECISION evaluates those flags consistent with the prior description to determine whether a hit occurred, and if so, also determines the index of the hit, as further shown by the following example.

[0039] Figure 7 shows the use of Figure 6 The instruction process 600 and array search example 700 again searches for array value 30. Overall, search example 700 includes six array elements (indexes [0], [1], ..., [5]). However, using Figure 6Concurrency, processing two array elements at a time. For example, in clock cycle 0, A[1]=16 and A[0]=65 are loaded, then in clock cycle 1, each loaded element is compared to REF=30, and then in clock cycle 2, the match history of each comparison is stored. In the example shown, the two cycle 1 comparisons produce a miss, so clock cycle 2 stores HIS_FLAG{A[1], A[0]}=00. Partially overlapping clock cycles process A[1] and A[0], in clock cycle 1, A[3]=62 and A[2]=83 are loaded, then in clock cycle 2, each loaded array element is compared to REF=30, and then in clock cycle 3, the match history of each comparison is stored (so the flags are stored with or appended to the flags from clock cycle 2), producing two corresponding misses for these example values, so clock cycle 3 stores HIS_FLAG{A[3], A[2]}=00. Partially overlapping clock cycles process A[3] and A[2], in clock cycle 2, A[5]=30 and A[4]=29 are loaded, in clock cycle 3, each is compared to REF=30, and in clock cycle 3, the match history of each comparison is stored (thus, the flags are stored with or appended to the flags from clock cycle 3), resulting in one corresponding hit and one corresponding miss for these instance values, so clock cycle 4 stores HIS_FLAG{A[5], A[4]}=10. Finally, in clock cycle 5, LOOP DECISION determines that a hit has occurred and identifies index [i=5], again using the counter instance for hit index detection, starting with the earliest HIS_FLAG in time (least significant order) and incrementing once a set (HIS_FLAG=1) is encountered but stopping at the then-verify count.

[0040] Figure 8 Show that following Figure 2 , 4 The same axis convention as 6 is used for the instruction process 800. Figure 8 However, in the example above, target code instructions are provided in additional clock cycles, and each instruction (and instruction sequence) targets four different array elements, thereby further extending the capacity, for example with Figure 2 and 4 A single array element instruction in Figure 6 The double array element instruction comparison in . Additional element capacity can also be implemented in Figure 11 , and the structure and functionality of the appropriate stages of the instruction pipeline 104. For example, for the first instruction sequence, in clock cycle 0, LOAD A[3-0] illustrates a pipeline process that, when executed, loads all four array elements A[3], A[2], A[1], and A[0] into corresponding registers (or corresponding portions of the same register) in the same clock cycle. Thereafter and as a next example, in clock cycle 1, COMPARE: A[3-0], REF illustrates a pipeline process that compares REF to each of the four load array elements A[3], A[2], A[1], and A[0] in the same clock cycle. Thereafter and as a final example, in clock cycle 2, STORE_COMP_HIS stores the history of all four compare array elements, thus storing a total of four bits, which may be contiguous bits stored in order of positional significance or four separate flags as described above. Furthermore, partially overlapping with the above steps taken with respect to the first set of four array elements, in clock cycle 1, a comparable set of steps is taken with respect to the second set of four array elements, and this process is repeated in Figure 8 A total of nine instruction sequences are repeated in , processing nine sets, each set having four array elements. Also occasionally, for example, in a fixed cycle starting at clock cycle 5 and repeated every three clock cycles, a LOOP DECISION is executed for the history associated with the 12 previously loaded array elements compared to REF, and a hit / miss history is stored for the array elements. For example, in clock cycle 5, LOOP DECISION evaluates flags corresponding to array elements A[0] through A

[11] , while in clock cycle 8, LOOP DECISION evaluates flags corresponding to array elements A

[12] through A

[23] , and finally in clock cycle 11, LOOP DECISION evaluates flags corresponding to array elements A

[24] through A

[35] . Furthermore, each LOOP DECISION may end (branch away) the search if a hit is found in an array element processed before the LOOP DECISION, and consistent with the foregoing description, if a hit is ultimately located, the index of the hit is determined, as further illustrated by the example below.

[0041] FIG. 9 shows the use of Figure 8Search example 900 of instruction process 800. Overall, search example 900 includes thirty-six array elements (indexes [0], [1], ...,

[35] ), wherein instruction process 800 executes LOOP DECISION for twelve consecutive sets of elements corresponding to three instruction sequences at a time, and wherein each instruction sequence involves four different array elements. Thus, across clock cycles 0 to 5, the first set of 12 array elements is loaded, compared to reference REF, and the hit history is stored and then evaluated with LOOP DECISION. In the illustrated example, the first set does not produce a hit, i.e., HIS_FLAG=0 for each corresponding comparison (shown collectively as 0000 from index [3] to index [0]), and if implemented by a counter, LOOP DECISION is incremented for each HIS_FLAG=0, thereby until the value is 11. Furthermore, during those clock cycles 0 to 5, i.e., in clock cycle 3, instruction processing of a second consecutive set of 12 array elements is started, and ends with evaluation of LOOP DECISION in clock cycle 8. In the example shown, the second set also does not produce a hit, and if implemented by a counter, LOOP DECISION increments for each HIS_FLAG=0, thereby until the value is 23. The same process continues for the third set of 12 consecutive array elements. However, when LOOP DECISION is executed in clock cycle 11, a hit is detected in the third set of 12 array elements, namely at index 25, which is the count value of the count incremented from 23 after clock cycle 8 LOOP DECISION, corresponding to the next most significant HIS_FLAG miss value of A

[24] =82 followed by the next most significant hit value of HIS_FLAG of A

[25] =30. Thus, in 11 clock cycles in instruction process 700, a total of 32 array values ​​are evaluated for hit / miss, again effectively reducing the loop overhead when performing the array search.

[0042] Fig.10Flowchart of an example array search method 1000 consistent with and summarizing certain principles described above. In the array search method 1000, step 1002 converts (e.g., compiles) an array search (e.g., indicated in a higher-level computing language) into target code instructions to be processed in a processor pipeline. The target code instructions provide multiple simultaneous flows 1004A, 1004B, ..., 1004Z, wherein the previous example described describes three such simultaneous flows, and the target code instructions further include loop decisions that then execute the flow set. Each of the multiple simultaneous flows has the same set of steps and operates simultaneously, wherein each flow is time-shifted relative to the other flows and is processed through the processor pipeline. For example, a first flow 1104A includes loading 1006A one or more array elements, then comparing 1008A one or more loaded elements with a search reference value, then historically storing 1010A one or more comparison results. At the same time, a second flow 1104B has the same steps, but partially overlaps, but starts and ends later in time relative to the first flow 1104A, such as having a load 1106B that occurs simultaneously with the compare 1108A of the first flow 1104A, and a compare 1008B that occurs simultaneously with the history save 1010A of the first flow 1004A. Finally, the second flow also has a history store 1010B, followed by its compare 1008B and also after the completion of the history store 1010A of the first flow 1004A. The same pattern and time delays will repeat for any additional flows, such as flow 1004Z. In addition, at a time subsequent to the completion of the set of steps of the first flow 1004A, a conditional step 1012 evaluates the history of multiple flows, wherein the history represents an aggregation at a point in time of multiple array elements that have been compared to a reference value, wherein the comparison results have been stored as an aggregate comparison history. If conditional step 1012 determines that the aggregate comparison history only reveals a miss in the comparison, and the array has not been fully searched, then conditional step 1012 directs control to a continue step 1014, thereby providing control to multiple flows 1004A, 1004B, ..., 1004Z so that each flow continues to loop and process one or more additional array elements. Conversely, if conditional step 1012 determines that the aggregate comparison history reveals a hit from the comparison or the array is fully searched, then it directs control to a complete step 1016, wherein if a hit is detected, the index of the first array element that hits in the comparison is determined, and method 1000 is also completed without requiring any additional processing by any of multiple flows 1004A, 1004B, ..., 1004Z.

[0043] As can be seen from the above, the described examples provide electronic processor structures and methods for reducing overhead in processor array searches. The example processor includes a pipeline with stages that can operate with respect to one or more array elements in different examples. For example, array search instructions from a higher-level computing language are converted to machine-level instructions that include certain steps that can reduce or even significantly reduce overhead in a pipeline architecture that performs array searches. A large number of examples are provided and teachings from which other examples can be found are also provided. Therefore, within the scope of the claims, additional modifications to the described embodiments are still possible, and other embodiments are also possible.

Claims

1. A processor, comprising: an instruction memory configured to store processor instructions; a data store configured to store processor data representing an array, the array comprising a plurality of data elements; Controller; The instruction pipeline, which contains: a load stage circuit configured to load array elements from said data memory; a comparison stage circuit configured to compare the array element with a reference value; a storage stage circuit configured to store a result set comprising results of said comparison of said array elements with said reference values; and A loop hit detection stage circuit is configured to determine whether any one of the result sets is associated with a hit on the reference value. 2 . The processor of claim 1 , wherein the loop hit detection stage circuit is further configured to determine, in response to a processor instruction, whether any of the result sets is associated with a hit on the reference value.

3. The processor of claim 1, wherein the loop hit detection stage circuit is further configured to determine an index of an array element that provides a matching result in a comparison of the loaded array element to a reference value. 4 . The processor of claim 1 , wherein the loop hit detection stage circuit is configured to determine whether any of three result sets is associated with a hit on the reference value.

5. The processor of claim 1 , wherein the load stage circuit is configured to load a third array element from the data memory while the storage stage circuit is configured to store a result set including a result of a comparison of a first array element with a reference value and while the compare stage circuit is configured to compare a second array element with a reference value.

6. The processor of claim 1, wherein the load stage circuit is configured to load a plurality of array elements from the data memory during a same first clock cycle.

7. The processor of claim 6, wherein the comparison stage circuit is configured to compare each of the plurality of array elements with the reference value during a same second clock cycle.

8. The processor of claim 7, wherein the storage stage circuit is configured to store a result of the comparison of each of the plurality of array elements with the reference value during a same third clock cycle.

9. The processor of claim 6, wherein the plurality of array elements consists of two array elements.

10. The processor of claim 6, wherein the plurality of array elements consists of four array elements.

11. The processor of claim 1, wherein the loop hit detection stage circuit is configured to determine whether any of a plurality of result sets is associated with a hit on the reference value.

12. The processor of claim 1, wherein the storage stage circuitry is configured to append a comparison history to a history corresponding to one or more prior executions performed by the storage stage circuitry.

13. A method of operating a processor to search for a value in an array comprising a plurality of elements, comprising: For each element in the plurality of elements: loading the corresponding array element; comparing the corresponding array element with a reference value; storing a result of said comparison of said corresponding array element with said reference value; and It is determined from a result set including the corresponding result associated with each element of the plurality of elements whether any one of the plurality of elements matches the reference value.

14. The method of claim 13, and further comprising determining an index of an array element matching the reference value.

15. The method of claim 14, wherein the step of determining an index comprises, for each step of comparing the corresponding array element to a reference value, advancing a counter from a first comparison until a comparison comprising an indication of a match between an array element and a reference value.

16. The method of claim 13, wherein the storing step comprises storing a result of comparing the first array element with the reference value while the loading step loads the third array element and while the comparing step compares the second array element with the reference value.

17. The method according to claim 16: wherein the step of loading the corresponding array elements comprises loading a corresponding plurality of array elements; wherein the step of comparing the corresponding array elements with a reference value comprises comparing a corresponding plurality of array elements with a reference value; and Wherein the step of storing results comprises storing a respective plurality of results of the comparison corresponding to the respective plurality of array elements.

18. The method according to claim 13: wherein the step of loading the corresponding array elements comprises loading a corresponding plurality of array elements; wherein the step of comparing the corresponding array element with a reference value comprises comparing a corresponding plurality of array elements with a reference value; and Wherein the step of storing results comprises storing a respective plurality of results of the comparison corresponding to the respective plurality of array elements.

19. A computer-readable storage medium having instructions stored therein and executable by a processor to search for a value in an array comprising a plurality of elements, wherein execution of the instructions by the processor results in the following steps: For each element in the plurality of elements: loading the corresponding array element; comparing the corresponding array element with a reference value; storing a result of said comparison of said corresponding array element with said reference value; and It is determined from a result set including the corresponding result associated with each element of the plurality of elements whether any one of the plurality of elements matches the reference value.

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