Uniform epitaxial growth on crystal templates

Abstract

A processing system includes one or more processing chambers, and a system controller configured to cause the processing system to perform (a) a pre-cleaning process on an exposed surface of a semiconductor structure, the semiconductor structure including a first semiconductor region, a second semiconductor region separated from the first semiconductor region by a trench, and a dielectric layer over at least a portion of the first semiconductor region and the second semiconductor region, (b) a first deposition process to form an amorphous silicon-containing layer on the exposed surface of the semiconductor structure, (c) a recrystallization annealing process to recrystallize at least a portion of the amorphous silicon-containing layer to form a silicon-containing crystalline layer within the trench, (d) an etching process, and (e) a second deposition process to remove the remainder of the amorphous silicon-containing layer, and (e) a second deposition process to epitaxially form a source / drain region over the silicon-containing crystalline layer within the trench.

Description

Technical Field

[0001] Embodiments described herein relate generally to semiconductor device fabrication, and more particularly, to systems and methods for uniform epitaxial growth within semiconductor structures. Background Art

[0002] MOSFETs (such as double-gate field-effect transistors (FinFETs), silicon-on-insulator (SOI) tri-gate MOSFETs, and gate all around (GAA) FETs), which incorporate more than one gate into a single device and are therefore more scalable than conventional planar bulk multi-gate metal-oxide-semiconductor field-effect transistors (MOSFETs), present challenges to manufacturability due to their three-dimensional (3D) design and small size. In architectures for technology nodes below 10-15 nm where gates are placed on both or all four sides of a silicon-based channel (such as GAA FETs), parasitic or external resistances significantly affect device performance. In such devices, source / drain regions can be formed within the trenches by an epitaxial process. However, due to the different materials (e.g., silicon (Si) and silicon nitride (Si3N4)) on the inner surface of the trench during the epitaxial process, increased variations in critical dimensions (e.g., line width) have been observed in these devices. This non-uniformity leads to varying growth rates over the inner surface of the trench during the epitaxial process and to the formation of defects in the source / drain regions, such as twins, stacking defects, or voids. The presence of defects in the source / drain regions can dramatically increase contact resistance.

[0003] Therefore, there is a need for methods and systems that can form uniform epitaxial source / drain regions. Summary of the invention

[0004] Embodiments of the present disclosure provide a processing system. The processing system includes one or more processing chambers, and a system controller configured to cause the processing system to perform in the one or more processing chambers (a) a pre-cleaning process on an exposed surface of a semiconductor structure, the semiconductor structure including a first semiconductor region, a second semiconductor region separated from the first semiconductor region by a trench, and a dielectric layer on at least a portion of the first semiconductor region and the second semiconductor region, (b) a first deposition process to form an amorphous silicon-containing layer on the exposed surface of the semiconductor structure, (c) a recrystallization annealing process to recrystallize at least a portion of the amorphous silicon-containing layer to form a silicon-containing crystalline layer in the trench, (d) an etching process to remove the remaining portion of the amorphous silicon-containing layer, and (e) a second deposition process to epitaxially form a source / drain region on the silicon-containing crystalline layer in the trench.

[0005] Embodiments of the present disclosure provide a method for filling a trench in a semiconductor structure. The method includes performing a first deposition process to form an amorphous silicon-containing layer on an exposed surface of the semiconductor structure, the semiconductor structure including a first semiconductor region, a second semiconductor region separated from the first semiconductor region by a trench, and a dielectric layer on at least a portion of the first semiconductor region and the second semiconductor region; performing a recrystallization annealing process to recrystallize at least a portion of the amorphous silicon-containing layer to form a silicon-containing crystalline layer in the trench; performing an etching process to remove the remaining portion of the amorphous silicon-containing layer; and performing a second deposition process to epitaxially form a source / drain region on the silicon-containing crystalline layer in the trench.

[0006] An embodiment of the present disclosure provides a method for filling a trench in a semiconductor structure. The method includes performing a pre-cleaning process on an exposed surface of a semiconductor structure, the semiconductor structure including a first semiconductor region, a second semiconductor region separated from the first semiconductor region by a trench, and a dielectric layer on at least a portion of the first semiconductor region and the second semiconductor region; performing a first deposition process to form an amorphous silicon-containing layer on the exposed surface of the semiconductor structure; performing a recrystallization annealing process to recrystallize at least a portion of the amorphous silicon-containing layer to form a silicon-containing crystalline layer in the trench; performing an etching process to remove the remaining portion of the amorphous silicon-containing layer; and performing a second deposition process to epitaxially form a source / drain region on the silicon-containing crystalline layer in the trench. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Thus, the manner in which the above-described features of the present disclosure may be understood in detail, a more particular description of the present disclosure, briefly summarized above, may be obtained by reference to the embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the drawings illustrate only typical embodiments of the present disclosure and, therefore, should not be considered limiting of the scope of the present disclosure, as the disclosure may admit to other equally effective embodiments.

[0008] Figure 1 is a schematic top view of a multi-chamber processing system according to one or more embodiments of the present disclosure.

[0009] Figure 2A is a cross-sectional view of a processing chamber according to one or more embodiments.

[0010] Figure 2B for Figure 2A An enlarged view of a portion of a processing chamber.

[0011] Figure 3 is a cross-sectional view of a processing chamber according to one or more embodiments.

[0012] Figure 4 is a cross-sectional view of a processing system according to one or more embodiments.

[0013] Figure 5 It is a process flow chart of a method for forming a contact layer in a semiconductor structure according to a first embodiment of the present disclosure.

[0014] Fig. 6A , Figure 6B , Figure 6C , Fig.6D and Fig. 6E For the corresponding Figure 5 A cross-sectional view of a portion of a semiconductor structure at various states of the method.

[0015] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation. DETAILED DESCRIPTION

[0016] Embodiments described herein provide methods and systems for epitaxial growth to fill trenches in semiconductor structures. The methods and systems may be particularly useful for forming source / drain regions in trenches, in gate-all-around (GAA) FETs. Unlike conventional processes that require epitaxial growth of source / drain regions on a rough surface of a trench, embodiments described herein include epitaxial growth of source / drain regions on a crystalline template formed on the surface of the trench. Thus, the formed source / drain regions are uniform, high quality, and free of defects or voids.

[0017] Figure 1 1 is a schematic top view of a multi-chamber processing system 100 according to one or more embodiments of the present disclosure. The processing system 100 generally includes a factory interface 102, load lock chambers 104, 106, transfer chambers 108, 110 with corresponding transfer robots 112, 114, holding chambers 116, 118, and processing chambers 120, 122, 124, 126, 128, 130. As described in detail herein, substrates in the processing system 100 can be processed in various chambers and transferred between various chambers without exposing the substrates to an ambient environment external to the processing system 100 (e.g., such as an atmospheric ambient environment that may exist in a wafer fab). For example, substrates can be processed in various chambers maintained at a low pressure (e.g., less than or equal to about 300 Torr) or a vacuum environment and transferred between various chambers without breaking the low pressure or vacuum environment between various processes performed on the substrates in the processing system 100. Thus, the processing system 100 can provide an integrated solution for some substrate processing.

[0018] Examples of processing systems that may be appropriately modified in accordance with the teachings provided herein include the ATTACH®, commercially available from Applied Materials, Inc., located in Santa Clara, California. or Integrated processing system or other suitable processing system. It is contemplated that other processing systems, including those from other manufacturers, may be adapted to benefit from the aspects described herein.

[0019] exist Figure 1 In the illustrated example of , the factory interface 102 includes a docking station 132 and a factory interface robot 134 to facilitate the transfer of substrates. The docking station 132 is adapted to receive one or more front opening unified pods (FOUPs) 136. In some examples, each factory interface robot 134 generally includes a blade 138 disposed on one end of the respective factory interface robot 134, which is adapted to transfer substrates from the factory interface 102 to the load lock chambers 104, 106.

[0020] The load lock chambers 104, 106 have respective ports 140, 142 coupled to the factory interface 102 and respective ports 144, 146 coupled to the transfer chamber 108. The transfer chamber 108 further has respective ports 148, 150 coupled to the holding chambers 116, 118 and respective ports 152, 154 coupled to the processing chambers 120, 122. Similarly, the transfer chamber 110 has respective ports 156, 158 coupled to the holding chambers 116, 118 and respective ports 160, 162, 164, 166 coupled to the processing chambers 124, 126, 128, 130. The ports 144, 146, 148, 150, 152, 154, 156, 158, 160, 162, 164, 166 may be, for example, slit valve openings having slit valves for allowing substrates to pass therethrough by the transfer robots 112, 114 and for providing a seal between the respective chambers to prevent gas from passing therethrough. In general, any port is opened for transferring a substrate therethrough. Otherwise, the port is closed.

[0021] The load lock chambers 104, 106, transfer chambers 108, 110, holding chambers 116, 118, and processing chambers 120, 122, 124, 126, 128, 130 may be fluidly coupled to a gas and pressure control system (not specifically shown). The gas and pressure control system may include one or more gas pumps (e.g., turbo pumps, cryopumps, roughing pumps), gas sources, various valves, and conduits fluidly coupled to the various chambers. In operation, the factory interface robot 134 transfers the substrate from the FOUP 136 to the load lock chamber 104 or 106 via the port 140 or 142. The gas and pressure control system then evacuates the load lock chamber 104 or 106. The gas and pressure control system further maintains the transfer chambers 108, 110 and the holding chambers 116, 118 with an internal low pressure or vacuum environment (which may include an inert gas). Thus, evacuating the load lock chamber 104 or 106 facilitates transferring substrates between the atmospheric pressure environment of the factory interface 102 and the low pressure or vacuum environment of the transfer chamber 108 , for example.

[0022] With the substrate in the evacuated load lock chamber 104 or 106, the transfer robot 112 transfers the substrate from the load lock chamber 104 or 106 into the transfer chamber 108 via the port 144 or 146. The transfer robot 112 can then transfer the substrate to and / or between any of the processing chambers 120, 122 via the respective ports 152, 154 for processing and to the holding chambers 116, 118 via the respective ports 148, 150 for holding to await further transfer. Similarly, the transfer robot 114 is capable of accessing substrates in the holding chamber 116 or 118 via the port 156 or 158 and is capable of transferring the substrates to any of the processing chambers 124, 126, 128, 130 via the respective ports 160, 162, 164, 166 and / or transferring the substrates between any of the processing chambers 124, 126, 128, 130 for processing and transferring to the holding chamber 116, 118 via the respective ports 156, 158 for holding to await further transfer. The transferring and holding of substrates within and between the various chambers may be in a low pressure or vacuum environment provided by the gas and pressure control system.

[0023] The processing chambers 120, 122, 124, 126, 128, 130 may be any suitable chamber for processing a substrate. In some examples, the processing chamber 120 may be capable of performing an etching process, the processing chamber 122 may be capable of performing a cleaning process, the processing chamber 124 may be capable of performing a selective removal process, and the processing chambers 126, 128, 130 may be capable of performing a corresponding epitaxial growth process. The processing chamber 120 may be a Selectra® chamber available from Applied Materials, Inc. of Santa Clara, California. TM The processing chamber 122 may be a SiCoNi etch chamber available from Applied Materials, Inc., Santa Clara, California. TM Pre-clean chamber. The processing chamber 126, 128, or 130 may be a Centura TM Epitaxial chamber.

[0024] The system controller 168 is coupled to the processing system 100 to control the processing system 100 or components thereof. For example, the system controller 168 may control the operation of the processing system 100 using direct control of the chambers 104, 106, 108, 110, 116, 118, 120, 122, 124, 126, 128, 130 of the processing system 100 or by controlling controllers associated with the chambers 104, 106, 108, 110, 116, 118, 120, 122, 124, 126, 128, 130. In operation, the system controller 168 enables data collection and feedback from the respective chambers to coordinate the execution of the processing system 100.

[0025] The system controller 168 generally includes a central processing unit (CPU) 170, a memory 172, and support circuits 174. The CPU 170 may be one of any form of general purpose processor that may be used in an industrial environment. The memory 172 or non-transitory computer readable medium may be accessed by the CPU 170 and may be one or more of memories such as random access memory (RAM), read only memory (ROM), a floppy disk, a hard disk, or any other form of digital storage, whether local or remote. The support circuits 174 are coupled to the CPU 170 and may include caches, clock circuits, input / output subsystems, power supplies, and the like. The various methods disclosed herein may be implemented by the CPU 170 executing computer instruction codes stored in the memory 172 (or in the memory of a particular processing chamber) as, for example, a software routine, generally under the control of the CPU 170. When the computer instruction codes are executed by the CPU 170, the CPU 170 controls the chamber to perform processes according to the various methods.

[0026] Other processing systems may have other configurations. For example, more or fewer processing chambers may be coupled to the transfer device. In the illustrated example, the transfer device includes transfer chambers 108, 110 and holding chambers 116, 118. In other examples, more or fewer transfer chambers (e.g., one transfer chamber) and / or more or fewer holding chambers (e.g., no holding chambers) may be implemented as a transfer device in a processing system.

[0027] Figure 2A FIG. 2 is a cross-sectional view of a processing chamber 200 adapted to perform a pre-cleaning process as described in detail below, according to one or more embodiments. The processing chamber 200 may be Figure 1 The processing chamber 122 is shown in FIG. Figure 2B for Figure 2A An enlarged view of a portion of the processing chamber 200 is shown.

[0028] The processing chamber 200 can be particularly useful for performing thermal or plasma-based cleaning processes and / or plasma-assisted dry etching processes. The processing chamber 200 includes a chamber body 202, a lid assembly 204, and a support assembly 206. The lid assembly 204 is disposed at an upper end of the chamber body 202, and the support assembly 206 is at least partially disposed within the chamber body 202. A vacuum system can be used to remove gases from the processing chamber 200. The vacuum system includes a vacuum pump 208, which is coupled to a vacuum port 210 disposed in the chamber body 202. The processing chamber 200 also includes a controller 212 for controlling processes within the processing chamber 200.

[0029] The lid assembly 204 includes a stack of components adapted to provide precursor gases and / or plasma to a processing region 214 within the processing chamber 200. A first plate 216 is coupled to a second plate 218. A third plate 220 is coupled to the second plate 218. The lid assembly 204 may be connected to a power source (not shown) for supplying plasma to a conical cavity 222 formed in the lid assembly 204. The lid assembly 204 may also be connected to a remote plasma source 224 that generates plasma upstream of the lid stack. The remote plasma cavity (e.g., FIG. 2A to FIG. 2B The processing region 214, the first plate 216, and the second plate 218 in the processing chamber 200 are coupled to the gas source 226 via the remote plasma source 224 (or the gas source 226 is directly coupled to the lid assembly 204 in the absence of the remote plasma source 224). The gas source 226 may include a gas source adapted to provide helium, argon, or other inert gas. In some configurations, the gas provided by the gas source 226 may be energized into a plasma that is provided to the lid assembly 204 using the remote plasma source 224. In alternative embodiments, the gas source 226 may provide a processing gas that may be activated by the remote plasma source 224 before being introduced to a surface of a substrate disposed within the processing chamber 200. Reference Figure 2B The conical chamber 222 has an opening 228 that allows formed plasma to flow from the remote plasma source 224 into a space 230 formed in a fourth plate 232 of the lid assembly 204 .

[0030] In some configurations of the lid assembly 204, a plasma is generated within the conical chamber 222 by applying energy delivered from a plasma source. In one example, energy may be provided by biasing the lid assembly 204 to capacitively couple RF, VHF, and / or UHF energy to a gas positioned within the conical chamber 222. In this configuration of the lid assembly 204, the remote plasma source 224 may not be used or mounted within the lid assembly 204.

[0031] The central conduit 234 formed in the fourth plate 232 is adapted to provide the plasma-generated material provided from the space 230 to the mixing chamber 238 formed in the sixth plate 240 of the lid assembly 204 via the fifth plate 236. The central conduit 234 communicates with the mixing chamber 238 via an opening 242 in the fifth plate 236. The opening 242 may have a diameter that is smaller than, larger than, or the same as the diameter of the central conduit 234. Figure 2B In the embodiment of the present invention, the opening 242 has the same diameter as the central conduit 234.

[0032] The fourth plate 232 also includes inlets 244 and 246 adapted to provide gas to the mixing chamber 238. The inlet 244 is coupled to a first gas source 248, and the inlet 246 is coupled to a second gas source 250. The first gas source 248 and the second gas source 250 may include a process gas and an inert gas used as a carrier gas, for example, an inert gas such as argon and / or helium. The first gas source 248 may include ammonia (NH3) and argon (Ar). The second gas source 250 may contain a fluorine-containing gas, a hydrogen-containing gas, or a combination thereof. In one example, the second gas source 250 may contain hydrogen fluoride (HF) and argon (Ar).

[0033] like Figure 2B , in some configurations, the inlet 244 is coupled to the mixing chamber 238 via a cylindrical passage 252 (shown in phantom) and a hole 254 formed in the fifth plate 236. The inlet 246 is coupled to the mixing chamber 238 via a cylindrical passage 256 (shown in phantom) and a hole 258 formed in the fifth plate 236. The holes 254, 258 formed in the fifth plate 236 are generally sized so that they enable a uniform flow of gas into the mixing chamber 238, the gas being provided from its respective gas source 248, 250. In one configuration, the diameter of the hole 258 is less than the width of the opening defined by the opposing sidewalls of the cylindrical passage 256 formed in the fourth plate 232. The holes 258 are generally distributed around the circumference of the centerline of the cylindrical passage 256 to provide a uniform flow of fluid into the mixing chamber 238. In one configuration, the holes 254 have a diameter that is less than the width of the opening defined by the opposing sidewalls of the cylindrical passage 252 formed in the fourth plate 232. The holes 254 are generally distributed around the circumference of the centerline of the cylindrical passage 252 to provide uniform fluid flow into the mixing chamber 238.

[0034] Inlets 244 and 246 provide respective fluid flow paths that transversely pass through fourth plate 232, turn and pass through fifth plate 236 to mixing chamber 238. Cover assembly 204 also includes a seventh plate or first gas distributor 260, which may be a gas distribution plate, such as a showerhead, wherein the various gases mixed in cover assembly 204 flow through perforations 262 formed therein. Perforations 262 are in fluid communication with mixing chamber 238 to provide a flow path from mixing chamber 238 through first gas distributor 260. Return to Reference Figure 2A A baffle plate 264 and a second gas distributor 266 (which may be a gas distribution plate, such as a showerhead) are disposed below the cover assembly 204 .

[0035] Alternatively, a different cleaning process may be utilized to clean the substrate surface. For example, a remote plasma containing helium (He) and ammonia (NH3) may be introduced into the processing chamber 200 via the lid assembly 204, while ammonia (NH3) may be directly injected into the processing chamber 200 via a separate gas inlet 268 disposed at a side of the chamber body 202 and coupled to a gas source (not shown).

[0036] The support assembly 206 may include a substrate support 270 to support a substrate 272 thereon during processing. The substrate support 270 may be coupled to an actuator 274 via a shaft 276 that extends through a centrally located opening formed in the bottom of the chamber body 202. The actuator 274 may be flexibly sealed to the chamber body 202 by a bellows (not shown) that prevents vacuum from leaking around the shaft 276. The actuator 274 allows the substrate support 270 to move vertically within the chamber body 202 between a processing position and a loading position. The loading position is slightly below the opening of a tunnel (not shown) formed in the sidewall of the chamber body 202.

[0037] The substrate support 270 has a flat or substantially flat substrate support surface for supporting a substrate 272 to be processed thereon. The substrate support 270 can be moved vertically within the chamber body 202 by an actuator 274 coupled to the substrate support 270 by a shaft 276. For some process operations, the substrate support 270 can be raised to a position very close to the lid assembly 204 to control the temperature of the substrate 272 being processed. In this way, the substrate 272 can be heated via radiation emitted from the second gas distributor 266 or another radiation source or by convection or conduction through an intervening gas from the second gas distributor 266. In some process steps, the substrate can be placed on lift pins 278 to perform additional thermal processing operations, such as performing an annealing step.

[0038] Figure 3FIG. 3 is a cross-sectional view of a processing chamber 300 adapted to perform an epitaxial (Epi) deposition process as described in detail below, according to one or more embodiments. The processing chamber 300 may be Figure 1 The processing chamber 126, 128 or 130 shown in FIG.

[0039] The processing chamber 300 includes a housing structure 302 made of a process resistant material such as aluminum or stainless steel (e.g., 316L stainless steel). The housing structure 302 encloses various functional elements of the processing chamber 300, such as a quartz chamber 304, which includes an upper quartz chamber 306 and a lower quartz chamber 308, containing a processing space 310. Reactive substances are provided to the quartz chamber 304 by a gas distribution assembly 312, and processing byproducts are removed from the processing space 310 by an outlet port 314, which is generally connected to a vacuum source (not shown).

[0040] The substrate support 316 is adapted to receive a substrate 318 that is transferred to the processing space 310. The substrate support 316 is disposed along the longitudinal axis 320 of the processing chamber 300. The substrate support 316 may be made of a ceramic material or a graphite material coated with a silicon material (such as silicon carbide) or other process-resistant material. Reactive species from the precursor reactant material are applied to a surface 322 of the substrate 318, and byproducts may then be removed from the surface 322 of the substrate 318. Heating of the substrate 318 and / or the processing space 310 may be provided by a radiation source (such as an upper lamp module 324A and a lower lamp module 324B).

[0041] In one embodiment, the upper lamp module 324A and the lower lamp module 324B are infrared (IR) lamps. Non-thermal energy or radiation from the lamp modules 324A and 324B travels through the upper quartz window 326 of the upper quartz chamber 306 and through the lower quartz window 328 of the lower quartz chamber 308. Cooling gas for the upper quartz chamber 306 enters through the inlet 330 and exits through the outlet 332 as needed. Precursor reactant materials for the processing chamber 300, as well as diluent, purge and exhaust gases, enter through the gas distribution assembly 312 and exit through the outlet port 314. Although the upper quartz window 326 is shown as curved or convex, the upper quartz window 326 can be planar or concave because the pressure on both sides of the upper quartz window 326 is substantially the same (i.e., atmospheric pressure).

[0042] The low wavelength radiation in the processing volume 310 (which is used to excite reactive species and assist in the adsorption of reactants and the desorption of process byproducts from the surface 322 of the substrate 318) typically ranges from about 0.8 μm to about 1.2 μm, for example, between about 0.95 μm and about 1.05 μm, with various wavelength combinations being provided depending on the composition of the film being epitaxially grown, for example.

[0043] The component gases enter the processing space 310 via the gas distribution assembly 312. The gases flow from the gas distribution assembly 312 and exit via the outlet port 314, as generally shown by the flow path 334. The combination of component gases used to clean / passivate the substrate surface or to form an epitaxially grown silicon and / or germanium-containing film is typically mixed before entering the processing space 310. The total pressure in the processing space 310 can be adjusted by a valve (not shown) at the outlet port 314. At least a portion of the inner surface of the processing space 310 is covered by a liner 336. In one embodiment, the liner 336 includes an opaque quartz material. In this way, the chamber wall is insulated from the heat in the processing space 310.

[0044] The surface temperature in the processing space 310 may be controlled within a temperature range of about 200° C. to about 600° C. or more by the flow of cooling gas (which enters through the inlet 330 and exits through the outlet 332) in combination with radiation from the upper lamp module 324A (positioned above the upper quartz window 326). The temperature in the lower quartz chamber 308 may be controlled within a temperature range of about 200° C. to about 600° C. or more by adjusting the speed of a blower unit (not shown) and by radiation from the lower lamp module 324B disposed below the lower quartz chamber 308. The pressure in the processing space 310 may be between about 0.1 Torr and about 600 Torr, such as between about 5 Torr and about 30 Torr.

[0045] The temperature on the surface 322 of the substrate 318 can be controlled by adjusting the power of the lower lamp module 324B in the lower quartz chamber 308 or by adjusting the power of the upper lamp module 324A overlying the upper quartz window 326 and the lower lamp module 324B in the lower quartz chamber 308. The power density in the processing space 310 can be about 40 W / cm 2 To about 400W / cm 2 between, such as about 80W / cm 2 To about 120W / cm 2 .

[0046] In one aspect, the gas distribution assembly 312 is disposed perpendicular to or relative to the longitudinal axis 320 of the processing chamber 300 or substrate 318 in a radial direction 338. In this orientation, the gas distribution assembly 312 is adapted to flow the processing gas across or parallel to the surface 322 of the substrate 318 in the radial direction 338. In one processing application, the processing gas is preheated when introduced into the processing chamber 300 to initiate preheating of the gas prior to introduction into the processing volume 310, and / or to break specific bonds in the gas. In this way, the surface reaction kinetics can be modified independent of the thermal temperature of the substrate 318.

[0047] In operation, precursors for forming blanket or selective epitaxial films of silicon (Si) and silicon germanium (SiGe) are provided to the gas distribution assembly 312 from one or more gas sources 340A and 340B. Figure 3 334) can be used to heat the precursor within the gas distribution assembly 312 and along the flow path 334. The gas sources 340A, 340B can be coupled to the gas distribution assembly 312 in a manner adapted to facilitate introduction regions within the gas distribution assembly 312, such as, when viewed from a top plan view, radially outer regions and radially inner regions between the outer regions. The gas sources 340A, 340B can include valves (not shown) to control the rate of introduction into the regions.

[0048] Gas sources 340A, 340B may include silicon precursors, such as silanes, including silane (SiH4), disilane (Si2H6), dichlorosilane (SiH2Cl2), hexachlorodisilane (Si2Cl6), dibromosilane (SiH2Br2), higher order silanes, derivatives thereof, and combinations thereof. Gas sources 340A, 340B may also include germanium-containing precursors, such as germanium (GeH4), digermane (Ge2H6), germanium tetrachloride (GeCl4), dichlorogermane (GeH2Cl2), derivatives thereof, and combinations thereof. Precursors containing silicon and / or germanium may be used in combination with hydrogen chloride (HCl), chlorine (Cl2), hydrogen bromide (HBr), and combinations thereof. Gas sources 340A, 340B may include one or more of silicon- and germanium-containing precursors in one or both of gas sources 340A, 340B.

[0049] The precursor material in this excited state passes through the opening or hole 344 in the perforated plate 346 (at Figure 3The perforated plate 346 (only one shown) enters the processing volume 310 and is a quartz material in one embodiment having holes 344 formed therethrough. The perforated plate 346 is transparent to IR energy and can be made of a clear quartz material. In other embodiments, the perforated plate 346 can be any material that is transparent to IR energy and resistant to process chemicals and other process chemicals. The excited precursor material passes through the holes 344 in the perforated plate 346 and through the channel 348 (at Figure 3 310. A portion of the photons and non-thermal energy from the IR lamp 342 also passes through the holes 344, the perforated plate 346, and the channel 348, facilitated by the reflective materials and / or surfaces disposed on the inner surface of the gas distribution assembly 312, thereby illuminating the flow path 334 of the precursor material. In this way, the vibrational energy of the precursor material can be maintained along the flow path from the introduction point into the processing volume 310.

[0050] Figure 4 FIG. 4 is a cross-sectional view of a processing system 400 adapted to perform a recrystallization anneal or oxidation process as described in detail below according to one or more embodiments. The processing system 400 may be a rapid thermal processing (RTP) apparatus such as, but not limited to, an RTP available from Applied Materials, Inc. of Santa Clara, California. Other types of thermal reactors (such as EPI, available from Applied Materials, Inc., Santa Clara, California) ) can replace the RTP device. Other suitable plasma reactors can also be used, including Remote Plasma Oxidation (RPO) reactors available from Applied Materials, Inc., Santa Clara, California.

[0051] The processing system 400 includes a thermal processing chamber 402 and a precursor activator 404 coupled to the thermal processing chamber 402 and used to remotely provide radicals of a plasma to a processing region 406 of the thermal processing chamber 402. The precursor activator 404 can also be used to provide an activated plasma gas mixture, for example, by applying energy to the gas to form a radical-rich mixture with negligible ions. The processing region 406 is enclosed by one or more sidewalls 408 (e.g., four sidewalls) and a base 410. The upper portion of the sidewall 408 can be sealed to a window assembly 412 (e.g., using an "O" ring). A radiant energy assembly 414 is positioned above and coupled to the window assembly 412. The radiant energy assembly 414 has a plurality of lamps 416, which can be tungsten halogen lamps, each mounted in a container 418 and positioned to emit electromagnetic radiation into the processing region 406. Figure 4The window assembly 412 of FIG. 4 has a plurality of light pipes 420, but the window assembly 412 may have only a straight, solid window without light pipes. The window assembly 412 has an outer wall 422 (e.g., a cylindrical outer wall) that forms a rim that closes the window assembly 412 around its circumference. The window assembly 412 also has a first window 424 that covers a first end of the plurality of light pipes 420, and a second window 426 that covers a second end (opposite the first end) of the plurality of light pipes 420. The first window 424 and the second window 426 extend to and engage with the outer wall 422 of the window assembly 412 to close and seal the interior volume of the window assembly 412, which includes the plurality of light pipes 420. In such cases, when light pipes are used, a vacuum can be created in the plurality of light pipes 420 by applying a vacuum to one of the plurality of light pipes 420 via a conduit 428 passing through the outer wall 422, which in turn is fluidly connected to the others of the light pipes.

[0052] The substrate W is supported in the thermal processing chamber 402 by a support ring 430 within the processing region 406. The support ring 430 is mounted on a rotatable cylinder 432. By rotating the rotatable cylinder 432, the support ring 430 and the substrate W are rotated during processing. The base 410 of the thermal processing chamber 402 has a reflective surface 434 for reflecting energy onto the back side of the substrate W during processing. Alternatively, a separate reflector (not shown) may be positioned between the base 410 of the thermal processing chamber 402 and the support ring 430. The thermal processing chamber 402 may include a plurality of temperature probes 436 that are disposed through the base 410 of the thermal processing chamber 402 to detect the temperature of the substrate W. In the case of using a separate reflector, as described above, the temperature probes 436 are also disposed through the separate reflector to optically receive electromagnetic radiation from the substrate W.

[0053] The rotatable cylinder 432 is supported by a magnetic rotor 438, which is a cylindrical component having a flange 440 on which the rotatable cylinder 432 rests when the two components are installed in the thermal processing chamber 402. The magnetic rotor 438 has a plurality of magnets in a magnet region 442 below the flange 440. The magnetic rotor 438 is disposed in an annular well 444 located at a peripheral region of the thermal processing chamber 402 along the base 410. A cover 446 rests on a peripheral portion of the base 410 and extends beyond the annular well 444 toward the rotatable cylinder 432 and the support ring 430, such that a tolerance gap is left between the cover 446 and the rotatable cylinder 432 and / or the support ring 430. The cover 446 generally protects the magnetic rotor 438 from exposure to process conditions in the processing region 406.

[0054] The magnetic rotor 438 is rotated by magnetic energy from a magnetic stator 448 disposed around the base 410. The magnetic stator 448 has a plurality of electromagnets 450, which are powered according to a rotation pattern during processing of the substrate W to form a rotating magnetic field that provides magnetic energy to rotate the magnetic rotor 438. The magnetic stator 448 is coupled to a linear actuator 452 by a support 454. Operating the linear actuator 452 moves the magnetic stator 448 along an axis 456 of the thermal processing chamber 402, which in turn moves the magnetic rotor 438, the rotatable cylinder 432, the support ring 430, and the substrate W along the axis 456.

[0055] Process gas is provided to the thermal processing chamber 402 through the chamber inlet 458 and exhausted through the chamber outlet, which is directed out of the page and generally along the direction parallel to the chamber inlet 458 and the support ring 430 ( Figure 4 The substrate enters and exits the thermal processing chamber 402 via an access port 460 formed in the side wall 408 and at Figure 4 Presented in the back.

[0056] The precursor activator 404 has a body 462 surrounding an interior space 464 in which a plasma 466 of ions, radicals, and electrons may be formed. An inner liner 468 made of quartz or sapphire protects the body 462 from chemical attack by the plasma. The interior space 464 is preferably free of any potential gradient that may attract charged particles (e.g., ions). A gas inlet 470 is disposed at a first end 472 of the body 462 and is opposite a gas outlet 474, which is located at a second end 476 of the body 462. When the precursor activator 404 is coupled to the thermal processing chamber 402, the gas outlet 474 is in fluid communication with the thermal processing chamber 402 via a delivery line 478 to the chamber inlet 458 so that radicals of the plasma 466 generated within the interior space 464 are supplied to the processing region 406 of the thermal processing chamber 402. The gas inlet 474 may have a larger diameter than the gas inlet 470 to allow efficient discharge of excited radicals at a targeted flow rate and to minimize contact between the radicals and the liner 468. If targeted, a separate orifice may be inserted into the liner 468 at the gas outlet 474 to reduce the internal dimensions of the interior space 464 at the gas outlet 474. The diameter of the gas outlet 474 (or orifice, if used) may be selected to provide a pressure differential between the processing region 406 and the precursor activator 404. The pressure differential may be selected to produce a composition of ions, radicals, and molecules flowing into the thermal processing chamber 402 that is suitable for the process performed in the thermal processing chamber 402.

[0057] To provide gas for plasma processing, a first gas source 480 is coupled to the gas inlet 470 via a first input of a four-way valve 482 and a valve 484, which is used to control the flow rate of the gas released from the first gas source 480. A second input of the four-way valve 482 can be coupled to a second gas source 486. A third input of the four-way valve can be coupled to a third gas source 488. Each of the first gas source 480, the second gas source 486, and the third gas source 488 can be or include one or more of a nitrogen-containing gas, an oxygen-containing gas, a silicon-containing gas, a hydrogen-containing gas, or a plasma-forming gas such as argon or helium. A flow controller 490 is connected to the four-way valve 482 to switch the valve between its different positions depending on the process to be performed. The flow controller 490 also controls the switching of the four-way valve 482.

[0058] In some implementations, a second hydrogen source (not shown) is fluidly coupled to the thermal processing chamber 402. The second hydrogen source delivers hydrogen gas to the processing region 406 where the hydrogen gas is activated by a remote plasma comprising oxygen and argon that is delivered to the processing region 406 from the precursor activator 404. In some implementations where a high percentage of hydrogen gas is desired, hydrogen gas may be supplied to the processing region 406 via the third gas source 488 and the second hydrogen source.

[0059] In some implementations, a second argon gas source (not shown) is coupled to the thermal processing chamber 402. The second argon gas source delivers argon gas to the processing region 406, where the argon gas is activated by a remote plasma delivered from the precursor activator 404 to the processing region 406. In some implementations where a high percentage of argon gas is desired, argon gas can be supplied to the processing region 406 via the second gas source 486 and the second argon gas source.

[0060] Figure 5 A process flow diagram depicts a method 500 of forming source / drain regions in a semiconductor structure 600 according to a first embodiment of the present disclosure. Fig. 6A , Figure 6B , Figure 6C , Fig.6D and Fig. 6E 5 is a cross-sectional view of a portion of a semiconductor structure 600 corresponding to various states of method 500. It should be understood that Fig. 6A , Figure 6B , Figure 6C , Fig.6D and Fig. 6E Only a partial schematic diagram of the semiconductor structure 600 is shown, and the semiconductor structure 600 may contain any number of transistor portions and additional materials having aspects as shown in the figures. It should also be noted that although the sequential description Figure 5Other process sequences that are consistent with the methods depicted in , but include one or more operations that have been omitted and / or added, and / or rearranged in another desired order are within the scope of embodiments of the present disclosure provided herein.

[0061] refer to Fig. 6A , Figure 6B , Figure 6C , Fig.6D and Fig. 6E , the semiconductor structure 600 may include a first semiconductor region 602 and a second semiconductor region 604 formed on a substrate 606. The first semiconductor region 602 and the second semiconductor region 604 are separated by a trench 608 in which a source / drain (SD) region is formed.

[0062] As used herein, the term "substrate" refers to a layer of material that serves as a foundation for subsequent processing operations and includes a surface to be cleaned. The substrate may be a silicon-based material or any suitable insulating or conductive material, as desired. The substrate may include materials such as: crystalline silicon (e.g., Si <100> or Si <111> ), silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers and patterned or unpatterned wafers, silicon on insulator (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass or sapphire.

[0063] like Fig. 6A As shown in , the first semiconductor region 602 and the second semiconductor region 604 each include a first semiconductor layer 610 and a second semiconductor layer 612 alternately and repeatedly stacked on a substrate 606. The first semiconductor layer 610 is formed of a first material that has an etching selectivity to a second material forming the second semiconductor layer 612 (i.e., the etching rate of the first material is higher than the etching rate of the second material). The etching selectivity (i.e., the ratio of the etching rate of the first material to the etching rate of the second material) is between about 10:1 and 200:1. Example combinations of the first material and the second material include silicon germanium (SiGe) / silicon (Si), silicon germanium (SiGe) / germanium (Ge), and germanium tin (GeSn) / silicon (Si). The first semiconductor layer 610 can be selectively etched to form a dent at the end of the first semiconductor layer 610 facing the trench 608, and a spacer layer 614 is formed in each of the dents. These spacers 614 can be formed of a dielectric material, such as silicon nitride (Si3N4), silicon oxynitride (SiON), or silicon oxycarbide (SiOCN).

[0064] The second semiconductor layer 612 may function as a channel having a width between several nanometers and tens of nanometers.

[0065] The first semiconductor layer 610 and the second semiconductor layer 612 may be formed using any suitable deposition technique, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD), and the trench 608 may be formed by a patterning technique, such as photolithography and etching processes. The first semiconductor layer 610 and the second semiconductor layer 612 may each have a thickness between about 3 nm and about 15 nm, for example, about 10 nm. The selective etching of the first semiconductor layer 610 may be performed by any suitable etching process, such as a dry plasma etching process.

[0066] The semiconductor structure 600 further includes a dummy gate layer (also referred to as a "dielectric layer") 616 formed over at least a portion of each of the first semiconductor region 602 and the second semiconductor region 604. The dummy gate layer 616 may be formed of a dielectric material, such as silicon dioxide (SiO2).

[0067] The method 500 begins with a pre-cleaning process in block 510. The pre-cleaning process may be performed in a processing chamber, such as, Figure 1 2, or the processing chamber 122 shown in FIG. Figure 3 . In some embodiments, the pre-cleaning process in block 510 and the first deposition process in block 520 may be performed in-situ in the same processing chamber to minimize the regrowth of the oxide layer.

[0068] The pre-cleaning process is configured to remove contaminants (such as a native oxide layer) or patterning residues (eg, fluorocarbons) on the exposed surfaces of the first semiconductor region 602 and the second semiconductor region 604 formed within the trench 608 .

[0069] The pre-clean etch process may be a wet etch process using a cleaning solution such as a hydrofluoric acid (HF)-last type cleaning solution, an ozone water cleaning solution, a HF and hydrogen peroxide (H2O2) solution, and / or other suitable cleaning solutions. The cleaning solution may be heated.

[0070] The pre-cleaning process may include an isotropic plasma etch process such as SiCoNi TMA dry chemical etching process using a plasma formed from a gas including ammonia (NH3), nitrogen trifluoride (NF3), hydrogen fluoride (HF), or a combination thereof, and a carrier gas such as nitrogen (N2), hydrogen (H2), or a combination thereof. The dry chemical etching process is selective to oxide layers, and therefore does not readily etch silicon, germanium, or nitride layers, whether the layers are amorphous, crystalline, or polycrystalline. The dry chemical etching process has a selectivity of at least about 3:1 for oxide to silicon or germanium, and is typically 5:1 or better, and sometimes 10:1. The dry chemical etching process is also highly selective for oxide to nitride. The dry chemical etching process has a selectivity of at least about 3:1 for nitride, and is typically 5:1 or better, and sometimes 10:1.

[0071] The pre-cleaning process may include an anisotropic remote plasma assisted dry etching process, such as a reactive ion etching (RIE) process, using a plasma formed from a gas including argon (Ar), helium (He), or a combination thereof. The plasma effluents directionally bombard and remove contaminants on the exposed surfaces of the first semiconductor region 602 and the second semiconductor region 604 within the trench 608.

[0072] The pre-cleaning process may include an inductively coupled plasma (ICP) etching process using a plasma formed from gases including chlorine (Cl2) and hydrogen (H2) and a carrier gas including argon (Ar) and helium (He). The ICP etching process is used to form deep ridges with smooth sidewalls in silicon.

[0073] At block 520, a first deposition process is performed to form an amorphous silicon-containing layer 618 on the exposed surface of the semiconductor structure 600 (ie, the exposed surface of the first semiconductor region 602 and the second semiconductor region 604 within the trench 608, and the dummy gate layer 616). Figure 6B The first deposition process may include a first deposition process in a processing chamber (such as Figure 1 The processing chamber 126, 128 or 130 shown in FIG. Figure 3 The process chamber 300 shown in FIG. 3 may be any suitable deposition process such as plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), an epitaxial process, or the like.

[0074] Depending on the desired conductive properties of the S / D regions to be formed in the trenches 608, the amorphous silicon-containing layer 618 may be doped with a p-type dopant such as boron (B) or gallium (Ga) at a concentration of about 10 19 cm -3 With about 5x 10 21 cm -3 The p-type amorphous silicon-containing layer 618 may be formed of silicon germanium (SiGe) having a high germanium (Ge) concentration (e.g., between about 5% and about 60%) to minimize parasitic resistance. The amorphous silicon-containing layer 618 may contain carbon (C) at a concentration of less than about 1%, which may be used for subsequent dopant diffusion control in the S / D regions to be formed.

[0075] Depending on the desired conductive properties of the S / D regions to be formed in the trenches 608, the amorphous silicon-containing layer 618 may be doped with n-type dopants such as phosphorus (P), antimony (Sb), with a concentration of about 10 19 cm -3 With 5x 10 21 cm -3 The n-type amorphous silicon-containing layer 618 may be formed of silicon germanium (SiGe) having a low germanium (Ge) concentration (eg, less than about 5%) to facilitate recrystallization of the amorphous silicon-containing layer 618 in a subsequent recrystallization annealing process in block 530 .

[0076] In the first deposition process, the semiconductor structure 600 is exposed to a silicon-containing deposition gas at a low temperature between about 200° C. and about 500° C. to ensure that the formed layer 618 is amorphous. The deposition gas includes a silicon-containing precursor, a germanium-containing precursor, and a dopant source. The silicon-containing precursor may include silane (SiH4), disilane (Si2H6), trisilane Si3H8, tetrasilane (Si4H 10 ), methylsilane (CH6Si), dimethylsilane (C2H8Si) or a combination thereof. The germanium-containing precursor may include germane (GeH4), germanium tetrachloride (GeCl4) and digermane (Ge2H6). In order to form the n-type amorphous silicon-containing layer 618, the dopant source may include an n-type dopant, such as phosphorus (P), antimony (Sb), arsenic (As). The dopant source may include the precursor phosphine (PH3), phosphorus trichloride (PCl3), triisobutylphosphine ([(CH3)3C]3P), antimony trichloride (SbCl3), Sb(C2H5)5, arsine (AsH3), arsenic trichloride (AsCl3), tert-butylarsine (AsC4H 11 ). To form the p-type amorphous silicon-containing layer 618, the dopant source may include a p-type dopant, such as boron (B) or gallium (Ga). The dopant source may include a precursor diborane (B2H6) or trimethylgallium Ga(CH3)3. It should be noted that the dopant may enhance the recrystallization of the amorphous silicon-containing layer 618 in a subsequent recrystallization process in block 530.

[0077] At block 530, a recrystallization annealing process is performed to recrystallize at least a portion of the amorphous silicon-containing layer 618, such as Figure 6C In some embodiments, a recrystallization annealing process is performed in-situ in the same chamber as the subsequent epitaxial deposition process in block 550, such as, Figure 3 In some other embodiments, the recrystallization annealing process is a rapid thermal annealing process and is performed in a rapid thermal processing (RTP) apparatus such as, Figure 4 The recrystallization annealing process may be a laser annealing process.

[0078] The recrystallization annealing process may be performed at a temperature between about 400° C. and about 700° C. for a duration between about 1 minute and about 15 minutes, or at a temperature between about 700° C. and about 900° C. for a duration of several milliseconds. In some embodiments, the temperature is fixed at, for example, about 600° C. for the duration of the thermal annealing. In some embodiments, the temperature is increased from, for example, about 300° C. to about 600° C., and then decreased back to about 300° C., and this temperature change is repeated for the duration of the thermal annealing.

[0079] During the recrystallization annealing process, the amorphous silicon-containing layer 618 begins to crystallize at a surface 612S of the second semiconductor layer 612 (e.g., silicon (Si)) facing the trench 608, extends laterally along the width of the trench 608, and extends vertically over a surface 614S of the spacer layer 614 facing the trench 608 along the length of the trench 608. Portions of the amorphous silicon-containing layer 618 are thus crystallized within the trench 608 and form a silicon-containing crystalline layer 620, covering the surface 612S of the second semiconductor layer 612 and the surface 614S of the spacer layer 614. Portions of the amorphous silicon-containing layer 618 over the dummy gate layer 616 (e.g., silicon dioxide (SiO2)) remain amorphous.

[0080] At block 540, an etching process is performed to remove the remaining portion of the amorphous silicon-containing layer 618, such as Fig.6D The etching process may include any suitable etching process and is performed in-situ in the same chamber as the subsequent epitaxial deposition process in block 550, such as, Figure 3 In some embodiments, the etching process may be performed in a different processing chamber (such as, Figure 1 In these embodiments, the etching process is followed by a pre-cleaning process as in block 510 prior to a subsequent epitaxial deposition process in block 550 .

[0081] In the etching process, portions of the amorphous silicon-containing layer 618 above the dummy gate layer 616 (e.g., silicon dioxide (SiO2)) and any portions of the amorphous silicon-containing layer 618 that were not crystallized during the recrystallization annealing process in block 530 are removed by a suitable etching gas. The amorphous silicon-containing layer 618 may be etched at a faster rate than the silicon-containing crystalline layer 620, and thus may be selectively etched relative to the silicon-containing crystalline layer 620. The etching process in block 540 may also remove polysilicon or defective material, if present.

[0082] At block 550, a second deposition process is performed to epitaxially form S / D regions 622 in trench 608, such as Fig. 6E The second deposition process may include an epitaxial deposition process in a processing chamber, such as, Figure 1 The processing chamber 126, 128 or 130 shown in FIG. Figure 3 The processing chamber 300 is shown in FIG.

[0083] The S / D regions 622 are formed of the same material as the silicon-containing crystalline layer 620 and thus the same material as the amorphous silicon-containing layer 618. In the second deposition process, the silicon-containing crystalline layer 620 is used as a crystalline template for epitaxial growth of the S / D regions 622. The S / D regions 622 formed in the block 550 may thus be uniform, of high quality, and free of twin or stacking defects.

[0084] The epitaxial deposition process may be performed at a temperature between about 400° C. and about 700° C. and at a pressure between 5 Torr and 300 Torr.

[0085] Embodiments described herein provide methods and systems for epitaxial growth to fill trenches in semiconductor structures, wherein the inner surface of the trench includes a silicon-containing portion and a silicon nitride-containing portion. According to embodiments described herein, epitaxial growth of source / drain regions is performed on a crystalline template formed on the surface of the trench, covering the silicon-containing portion and the silicon nitride-containing portion, and thus the formed source / drain regions are uniform, high quality and free of defects or voids. The crystalline template is formed by recrystallizing an amorphous silicon-containing layer deposited on the inner surface of the trench.

[0086] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the present disclosure may be devised without departing from the basic scope of the present disclosure, the scope of which is determined by the claims that follow.

Claims

1. A processing system comprising: one or more processing chambers; and A system controller configured to cause the processing system to perform in the one or more processing chambers: (a) a pre-cleaning process on an exposed surface of a semiconductor structure, the semiconductor structure comprising a first semiconductor region, a second semiconductor region separated from the first semiconductor region by a trench, and a dielectric layer over at least a portion of the first semiconductor region and the second semiconductor region; (b) a first deposition process to form an amorphous silicon-containing layer on the exposed surface of the semiconductor structure; (c) a recrystallization annealing process to recrystallize at least a portion of the amorphous silicon-containing layer to form a silicon-containing crystalline layer in the trench; (d) an etching process to remove the remaining portion of the amorphous silicon-containing layer; and (e) a second deposition process to epitaxially form source / drain regions on the silicon-containing crystalline layer in the trench.

2. The processing system of claim 1, wherein The one or more processing chambers include a first processing chamber and a second processing chamber, (a) and (b) are performed in the first processing chamber, and (c) to (e) are performed in the second processing chamber.

3. The processing system of claim 1, wherein The one or more processing chambers include a first processing chamber, and (a) to (e) are performed in the first processing chamber.

4. The processing system of claim 1, wherein the first deposition process is performed at a temperature between 200°C and 500°C.

5. The processing system of claim 1, wherein the recrystallization annealing process is performed at a temperature between 400°C and 700°C.

6. The processing system of claim 1, wherein Each of the first semiconductor region and the second semiconductor region includes first semiconductor layers and second semiconductor layers that are alternately and repeatedly stacked, each of the first semiconductor layers comprises a spacer layer at an end of the each of the first semiconductor layers facing the trench, The first semiconductor layer includes silicon (Si), The second semiconductor layer includes silicon germanium (SiGe), and The spacer layer includes a dielectric material selected from the group consisting of silicon nitride (Si3N4), silicon oxynitride (SiON), and silicon oxycarbide (SiOCN).

7. A method for filling a trench in a semiconductor structure, comprising the steps of: performing a first deposition process to form an amorphous silicon-containing layer on an exposed surface of a semiconductor structure, the semiconductor structure comprising a first semiconductor region, a second semiconductor region separated from the first semiconductor region by a trench, and a dielectric layer over at least a portion of the first semiconductor region and the second semiconductor region; performing a recrystallization annealing process to recrystallize at least a portion of the amorphous silicon-containing layer to form a silicon-containing crystalline layer within the trench; performing an etching process to remove a remaining portion of the amorphous silicon-containing layer; and A second deposition process is performed to epitaxially form source / drain regions on the silicon-containing crystalline layer within the trench.

8. The method of claim 7, wherein the first deposition process is performed at a temperature between 200°C and 500°C.

9. The method of claim 7, wherein the recrystallization annealing process is performed at a temperature between 400°C and 700°C.

10. The method of claim 7, wherein the amorphous silicon-containing layer, the silicon-containing crystalline layer, and the source / drain regions are doped with n-type dopants.

11. The method of claim 7, wherein the amorphous silicon-containing layer, the silicon-containing crystalline layer, and the source / drain regions are doped with p-type dopants.

12. The method of claim 7, wherein Each of the first semiconductor region and the second semiconductor region includes first semiconductor layers and second semiconductor layers that are alternately and repeatedly stacked, and Each of the first semiconductor layers includes a spacer layer at an end of the each of the first semiconductor layers facing the trench.

13. The method of claim 12, wherein The first semiconductor layer includes silicon (Si), The second semiconductor layer includes silicon germanium (SiGe), and The spacer layer includes a dielectric material selected from the group consisting of silicon nitride (Si3N4), silicon oxynitride (SiON), and silicon oxycarbide (SiOCN).

14. The method of claim 7, further comprising the steps of: Prior to the first deposition process, a pre-cleaning process is performed on the exposed surface of the semiconductor structure.

15. A method for filling a trench in a semiconductor structure, comprising the steps of: performing a pre-cleaning process on an exposed surface of a semiconductor structure, the semiconductor structure comprising a first semiconductor region, a second semiconductor region separated from the first semiconductor region by a trench, and a dielectric layer over at least a portion of the first semiconductor region and the second semiconductor region; performing a first deposition process to form an amorphous silicon-containing layer on the exposed surface of the semiconductor structure; performing a recrystallization annealing process to recrystallize at least a portion of the amorphous silicon-containing layer to form a silicon-containing crystalline layer within the trench; performing an etching process to remove a remaining portion of the amorphous silicon-containing layer; and A second deposition process is performed to epitaxially form source / drain regions on the silicon-containing crystalline layer within the trench.

16. The method of claim 15, wherein the first deposition process is performed at a temperature between 200°C and 500°C.

17. The method of claim 15, wherein the recrystallization annealing process is performed at a temperature between 400°C and 700°C.

18. The method of claim 15, wherein the amorphous silicon-containing layer, the silicon-containing crystalline layer, and the source / drain regions are doped with n-type dopants.

19. The method of claim 15, wherein the amorphous silicon-containing layer, the silicon-containing crystalline layer, and the source / drain regions are doped with p-type dopants.

20. The method of claim 15, wherein Each of the first semiconductor region and the second semiconductor region includes first semiconductor layers and second semiconductor layers that are alternately and repeatedly stacked, each of the first semiconductor layers comprises a spacer layer at an end of the each of the first semiconductor layers facing the trench, The first semiconductor layer includes silicon (Si), The second semiconductor layer includes silicon germanium (SiGe), and The spacer layer includes a dielectric material selected from the group consisting of silicon nitride (Si3N4), silicon oxynitride (SiON), and silicon oxycarbide (SiOCN).

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