Micro device with sheared pads

Abstract

An example method includes forming and patterning an etch assist layer on a first dielectric layer such that the etch assist layer is not over a first bond pad (504); forming and patterning a first photoresist layer on a second patterned conductive layer on the first dielectric, wherein the first photoresist layer is not over the first bond pad (506); and etching a second dielectric layer to a depth of 5% to 15% of the thickness of the first dielectric layer and the second dielectric layer (514); etching the first dielectric layer and the second dielectric layer to a depth of 20% to 25% using a second photoresist layer; and exposing the first bond pad by etching the first dielectric layer using a patterned third photoresist layer such that a thickness of a region of the dielectric layer exposed by a third opening adjacent to the bond pad is between 3 and 5 [mu] m.

Description

Technical Field

[0001] The present invention relates generally to microdevices and, more particularly, to testing functionality in microelectrical devices. Background Art

[0002] Electrical and electronic devices used in harsh environments have significant testing requirements to avoid operational failures as much as possible. Examples of such harsh environments are automotive, military, and aerospace applications. These harsh environments increase the likelihood of device failure due to vibration, thermal stress, and other forces. In addition to the additional stress on the device, these environments often require a high level of durability to avoid safety issues.

[0003] In order to solve these harsh environments and safety issues, device customers usually need test solutions to ensure that the manufacturing process remains within the specified tolerances. For micro-electrical and microelectronic devices (collectively referred to as "micro devices"), the structure of concern is the wire bond. In an example, the wire bond uses a conductive material (e.g., gold) ball physically bonded to a bonding pad of a conductive material (e.g., aluminum). The wire bonding equipment applies heat and vibration energy to produce a bond between the ball and the bonding pad. The wire bonding between two micro devices is usually started by briefly heating one end of the lead to just above the melting point of the material containing the lead to form a surface tension induction ball, which is cooled to a solid state and physically pressed against the preheated bonding pad on the micro device, while applying vibration energy to the lead to provide friction heat to the interface between the pad and the lead tip to achieve thermomechanical bonding. The lead is then cut just above the bonded ball, leaving a ball and a small amount of residual lead bonded to the pad. The bonder then similarly creates a ball on the cut wire and bonds the ball to a bond pad of another microdevice. The bonder guides the bonded wire back to the previously formed bond ball on the original pad and applies heat and vibration energy to the wire as it is pressed into the previously bonded ball to form a so-called stitch bond. The bonder then cuts the wire near the stitch bond and repeats this cycle between the next two pads to couple between the microdevices, repeating until all desired pads between the microdevices are coupled.

[0004] The strength of the wire bond to the microdevice bond pad is a reliability issue. Insufficient bonding pressure and / or contamination are some of the problems that may occur. In order to ensure proper bonding, a shear test may be required. In a shear test, the device is sampled from the manufacturing process after ball bonding. The shear blade is lowered to the side of the ball and then moved laterally into the bond, at which time the force required for shear bonding is reported. If the force is within the specification, the test passes. If not, the test fails and manufacturing must be stopped to determine what caused the insufficient ball bonding. In general, the bond pad is recessed relative to the dielectric surface that provides passivation for the microdevice. In order to facilitate shear testing, an enlarged opening is provided at the selected bond pad, which allows space for the shear blade to be lowered far enough to contact the side of the ball. After compression, the height of the ball is about 4 to 10 microns. In order to be able to shear the ball, there may be no structure thicker than a few microns in the enlarged opening. Otherwise, the blade will shear the wire instead of the ball, giving an erroneous test result. Summary of the invention

[0005] In an example, a method includes forming a first patterned conductive layer on a substrate, the first patterned conductive layer including a first bonding pad, and forming a first dielectric layer on the first patterned conductive layer. The method also includes forming an etch assist layer on the first dielectric layer and patterning the etch assist layer so that the etch assist layer is not above the first bonding pad. The method also includes forming a second dielectric layer on the first dielectric layer and the etch assist layer, and forming a second patterned conductive layer on the dielectric layer. The method also includes forming and patterning a first photoresist layer on the second patterned conductive layer, wherein the first photoresist layer does not cover the first bonding pad, and etching the dielectric layer to a depth of 5% to 15% of the thickness of the first dielectric layer and the second dielectric layer using the first photoresist layer as a mask. The method also includes forming and patterning a second photoresist layer having a pattern for a second opening leading to the first bonding pad, and etching the first dielectric layer and the second dielectric layer to a depth of 20% to 25% of the exposed portions of the first dielectric layer and the second dielectric layer using the second photoresist layer as a mask. The method also includes forming and patterning a third photoresist layer, wherein the third photoresist layer has a third opening that is smaller than the first opening and larger than the second opening, and etching the first dielectric layer using the third photoresist layer as a mask so that the first bonding pad is exposed in the form of the second opening, and so that the thickness of the area of ​​the dielectric layer exposed by the third opening but not exposed by the second opening is between 3 and 5 μm. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1A and 1B (collectively referred to as "FIG. 1") are top and side views, respectively, of an example "shear pad."

[0007] Figure 2is a plan view of an example microelectrical device.

[0008] Figure 3 yes Figure 2 The transformer follows Figure 2 Cross-sectional view of the cutting line indicated in .

[0009] Figure 4A 4 through 5 (collectively “FIG. 4”) are side views showing an example process for fabricating an example device having a shear pad.

[0010] Figure 5A and 5B (collectively referred to as “ FIG. 5 ”) is a flow chart showing a process outlining features of the process described in FIG. 4 . DETAILED DESCRIPTION

[0011] In the drawings, corresponding numerals and symbols generally refer to corresponding parts unless otherwise indicated. The drawings are not necessarily drawn to scale.

[0012] In this specification, the term "coupled" may include connections made with intervening elements, and additional elements and various connections may exist between any elements that are "coupled." Additionally, as used herein, the terms "on," "over," and "covering" may include layers or other elements with intervening or additional elements between an element and an element that is "on," "over," or "covering" the element.

[0013] Figure 1A and 1B (collectively, “FIG. 1”) are top and side views, respectively, of an example “shear pad.” A “shear pad” is a bond pad that is configured to facilitate shear testing of wire bonds. In this example, the polyimide layer 106 is approximately 4 to 10 μm thick. For bond pads that are not configured as shear pads (not shown), the openings in the polyimide layer 106 are within five to ten microns of the bond pad. However, for a shear pad, this would be unacceptable because the polyimide layer 106 would not allow the shear test blade 110 to descend low enough to make proper contact through the wire 114 near the ball bond 102, as indicated by the thickness of the polyimide layer 106. Figure 1B. The shadow shear blade 112 in the figure is shown. The shadow shear blade 112 will contact the lead 114 above the ball and will therefore provide erroneous data, which can be attributed to the unnecessary waste of scrapped devices that have passed this test. To avoid this problem, the opening 116 in the polyimide layer 106 is widened in at least two directions to allow space for the shear test blade 110 to be lowered to the appropriate height adjacent to the ball bond 102, and then to shear the bond laterally without colliding with the polyimide on the back side of the bond. In this example, the edge of the opening 116 is at least 80 μm away from the bond pad 104 in the lateral direction relative to the page. This type of shear pad allows accurate test results. However, some microdevices have an inorganic dielectric passivation layer for which the surface of the bond pad 104 is recessed more than 5 μm from the passivation layer surface. In the case of these devices, more complex integration schemes are required to produce an appropriate shear window.

[0014] Figure 22 is a plan view of an example micro-electric device. Transformer 200 is an example passive micro-electric device. In some environments, sensitive semiconductor devices must operate with higher voltage devices. For example, in the automotive field, battery packs in electric vehicles can operate at up to 800V or higher, but lower voltage processors must monitor and control the operation of the vehicle. Devices similar to transformer 200 are used to isolate high voltage devices from low voltage devices while transmitting necessary signals between them. In addition, transformers are used to isolate circuits to avoid transmitting undesired signals. In the example of transformer 200, the first coil 202 rotates counterclockwise from the first bonding pad 204 to the first center tap bonding pad 206. The second coil 208 rotates clockwise from the first center tap bonding pad 206 to the second bonding pad 210. A matching set of coils (not shown) is below the first coil 202 and the second coil 208. The third bonding pad 212 is coupled to a coil matching the first coil 202, and the fourth bonding pad 214 is coupled to a coil matching the second coil 208. The second center tap bonding pad 216 is coupled to the center tap between the lower coils. In this example, the high voltage input is coupled to the first coil 202 and the second coil 208. Therefore, this is referred to as a high voltage level. Therefore, the lower coil is referred to as a low voltage level. Field band 218 is arranged in an area without coils and bonding pads. The field band 218 at the low voltage level minimizes stray fields and helps to alleviate stress that may cause cracking. As further described below, there is a thick insulating layer between the high voltage level and the low voltage level. A portion of this thick insulating layer is retained above the lower voltage metal to provide passivation and prevent lateral breakdown between the high voltage coil and the low voltage field band. The bonding pad surfaces of the third bonding pad 212, the fourth bonding pad 214 and the second center tap bonding pad 216 are recessed less than 6 μm from the surrounding passivation layer surface to enable shear bonding to be formed on these pads.

[0015] Figure 3 The transformer is 200 Figure 2 Cross-sectional view of the cutting line indicated in . Figure 2 The cutting line will not pass through Figure 3 Specifically, the connection between the third bonding pad 212 and the third coil 302 will not be connected to the Figure 2 However, for completeness of explanation, these components are included in Figure 3. The first coil 202 is separated from the third coil 302 by a silicon oxynitride layer 304, a silicon dioxide layer 306, a silicon oxynitride layer 308, a silicon dioxide layer 310, a silicon oxynitride layer 312, and a silicon nitride layer 314. In this example, the total thickness of these layers is approximately 17 μm. An insulating layer 316, which is a combination of a silicon dioxide layer, a silicon oxynitride layer, and a silicon nitride layer, covers the first coil 202. A polyimide layer 318 provides additional protection by keeping the package molding compound away from areas of extremely high electric fields. A ball bond 320 is coupled to the first bonding pad 204, and a first bonding wire 322 is coupled to the ball bond 320. A through hole 330, a through hole 332, and a first metal layer 334 couple the third bonding pad 212 to the third coil 302. The first metal layer 334 is formed on the substrate 201. A stitch bond 340 is coupled to the third bonding pad 212 , and a second bonding wire 342 is coupled to the stitch bond 340 .

[0016] The functions of silicon oxynitride layer 304, silicon dioxide layer 306, silicon oxynitride layer 308, silicon dioxide layer 310, silicon oxynitride layer 312, and silicon nitride layer 314 are described more fully below with respect to FIG. 4. However, in order to explain the difficulty of using the third bonding pad 212 as a shear pad, the function of the silicon oxynitride layer as an etch stop layer when etching the thick layers above it is important. In order to open the third bonding pad 212, the silicon dioxide layer 306 and the silicon dioxide layer 310 must be etched. These thick layers require a stable etch stop layer. Therefore, in this example, the silicon oxynitride layer 304 is 1 μm thick. In addition, the silicon nitride layer 314 above the third bonding pad 212 is 1 μm thick. to Even though the opening for the third bond pad 212 is enlarged above the silicon oxynitride layer 304, portions of the silicon oxynitride layer 312 and the silicon nitride layer 314 are still too thick for the shear test blade to properly contact the stitch bond 340. Therefore, for low voltage bond pads similar to the third bond pad 212, a simple shear pad window is not possible, and a process and structure that allows the necessary opening to use one or more of the low voltage bond pads as a shear test bond pad needs to be provided.

[0017] Figure 4A 4 through 5 (collectively “FIG. 4”) are side views showing an example process for fabricating an example device having a shear pad. Figure 4A A substrate 402 is shown having a first patterned metal layer 404 deposited to approximately 0.5 μm thick using sputtering, electroplating, and / or chemical vapor deposition (CVD). In this example, the substrate 402 is a crystalline silicon substrate approximately 700 μm thick. In an example, the CVD forms a thin insulating layer (not shown), such as a silicon dioxide layer approximately 0.85 μm thick, on the substrate 402 prior to depositing the first patterned metal layer 404. Figure 4B A first insulating layer 406 formed by CVD and planarized by, for example, chemical mechanical polishing (CMP) to a thickness of approximately 0.7 μm is shown over the first patterned metal layer 404. After CMP, an additional 2.3 μm plasma enhanced CVD (PECVD) TEOS layer is deposited to complete the first insulating layer 406. In this example, approximately 67% of the first insulating layer 406 is a low stress silicon dioxide layer formed by deposition from tetraethyl orthosilicate (TEOS). In this example, the low stress TEOS is formed at a pressure of approximately 3 Torr, and the high stress TEOS is formed at a pressure of approximately 3.2 Torr.

[0018] The first through hole 408 and the second through hole 410 are formed by etching the first insulating layer 406 and filling the openings with a suitable conductor such as tungsten. The second layer of metal is deposited or sputtered to a thickness of 1.3 to 1.8 μm. The second layer of metal in this example is a stack of titanium, titanium nitride, aluminum and titanium nitride. The second metal layer is photolithographically patterned and then etched to form the third coil 302 and the third bonding pad 212. Other coils and bonding pads at low voltage levels are also formed at this time, but are not shown in Figure 4. In addition, in this example, field straps (not shown) are also formed in this metal layer using this step.

[0019] Figure 4C A composite layer 412 including a silicon nitride layer, a silicon oxynitride layer, and a silicon dioxide layer formed on the third coil 302 and the third bonding pad 212 using CVD is shown. The composite layer is planarized and CVD forms an etch stop layer 414 including silicon oxynitride on the composite layer 412. CVD forms a first dielectric layer 416 on the etch stop layer 414. In this example, the first dielectric layer is formed with alternating layers of high stress TEOS and low stress TEOS to reduce sensitivity to cracking during subsequent processing. In this example, the first dielectric layer 416 is approximately 9.6 μm, but can be in the range of 1 to 15 μm. CVD forms an etch assist layer 418 including silicon oxynitride. A first photoresist layer 420 is formed and patterned on the etch assist layer 418. Plasma etching removes the exposed portion of the etch assist layer 418 and due to over-etching to ensure removal of the etch assist layer 418, a portion of the first dielectric layer 416 is also removed, as shown. Figure 4C As described further below, after patterning, etch assist layer 418 introduces a surface topography that allows alignment of subsequent masks in the process.

[0020] Figure 4DThe steps for forming the first coil 202 and the first bonding pad 204 are shown. CVD forms the second dielectric layer 422 by alternately forming high stress TEOS layers and low stress TEOS layers. The second dielectric layer 422 is approximately 5.7 μm thick, but can be in the range of 2 to 8 μm. CVD forms a sealing layer, which is a combination of a silicon nitride layer 424 and a silicon oxynitride layer 425, wherein the total thickness is approximately 1 μm, but can be in the range of 0.5 to 2 μm. CVD and / or sputtering forms an approximately 3 μm thick aluminum layer on the silicon oxynitride layer 425, which is patterned and etched to form the first bonding pad 204 and the first coil 202 concentric with the third coil 302. This step uses the non-planarity caused by the etching auxiliary layer 418. Without this non-planarity, the top surface of the aluminum layer would be flat and the photolithography tool would not be able to align the pattern with the bottom layer. Additionally, the openings in the etch assist layer define openings for low voltage bonding pads including shear pads, as further described below. Thus, the first coil 202 and the third coil 302 may be properly aligned to provide concentric coils utilizing the topography 426 produced by patterning of the etch assist layer 418.

[0021] Figure 4E The patterned second photoresist layer 428 is shown so that the end of the second photoresist layer 428 is approximately 14 μm from the nearest coil of the first coil 202. However, this distance can be in the range of 10 to 25 μm. Using the second photoresist layer 428, plasma etching is used to remove the exposed portions of the sealing layer, the silicon nitride layer 424 and the silicon oxynitride layer 425, and the approximately 1.6 μm second dielectric layer 422. The second photoresist layer 428 is patterned so that this etching occurs at the lower voltage bonding pads that are expected to be shear pads, and not at other lower voltage bonding pads. In an example, in some configurations, the etching is performed to begin defining scribe lanes between devices in the wafer. For efficiency, this scribe lane etching can be performed at the same time as the scribe lane etching. Figure 4E The etching combination shown in FIG.

[0022] Figure 4F Display for Figure 4E Step of forming a protective layer on the structure. Figure 4F In the embodiment, the second photoresist layer 428 is removed and a protective layer 432 is formed. In an example, the protective layer 432 includes high density plasma (HDP) CVD deposited silicon dioxide, high stress TEOS and silicon oxynitride. The protective layer 432 is approximately 3.2 μm thick.

[0023] Figure 4GSteps for forming an opening to the first bonding pad 204 and beginning to form an opening to the third bonding pad 212 are shown. A third photoresist layer 434 is deposited and patterned on the protective layer 432. It is noteworthy that the edge of the second photoresist layer above the third bonding pad 212 is approximately 9 μm to the right (in the perspective of the page) of the etching auxiliary layer 418. As further described below, this 9 μm gap ultimately leads to a dielectric thickness region with a sufficiently low morphology defined relative to the exposed surface of the third bonding pad 212 to enable cutting to the final wire bond of the third bonding pad 212. The protective layer 432 is etched to open the first bonding pad 204. Since the first bonding pad 204 is a different material from the material of the protective layer 432, the etching stops at the first bonding pad 204. In an example, the etchant used in this step is a plasma of CF4+CHF3+Ar. However, in the area above the third bond pad 212, the etchant will remove all of the protective layer 432 and etch approximately 1.1 μm into the second dielectric layer 422. In an example, this etching step removes approximately 20% to 25% of the combination of the protective layer, the second dielectric layer 422, the first dielectric layer 416, the etch stop layer 414, and the composite layer 412.

[0024] Figure 4H The step of forming and patterning a fourth photoresist layer 436 on the protective layer 432 and the first bonding pad 204 is shown. For example, the fourth photoresist layer 436 is 15 μm thick. Therefore, the fourth photoresist layer 436 is thick enough to withstand etching through the dielectric layer above the third bonding pad 212 to expose the third bonding pad 212, the dielectric layer including the remaining portion of the second dielectric layer 422, the first dielectric layer 416, the etch stop layer 414 and the composite layer 412. Figure 4H The use of a low selectivity etchant such as C5F8+O2 is shown to etch through the second dielectric layer 422. Next, an etchant such as C4F8+O2 that is selective to the material in the etch assist layer 418 is used, followed by a non-selective etchant to etch through most of the first dielectric layer 416, and then back to selective etching to stop in layer 414. Figure 4E The previous etching steps, such as Figure 4G The etching protection layer 432 and the Figure 4CThe effect of etching the etching auxiliary layer 418 in the first step 438 and the second step 440 is used to form a two-step structure. Specifically, the etching of the exposed portion of the protective layer 432, which partially includes silicon oxynitride, is slower than the etching of the second dielectric layer 422 including silicon dioxide. In addition, when the etching of the second dielectric layer 422 reaches the etching auxiliary layer 418, the etching is slowed down by the etching auxiliary layer 418 but continues at a normal rate into the first dielectric layer 416. The height of the first step 438 and the second step 440 is determined by the difference in the etching rates of the corresponding materials, and importantly, by the difference in the etching rates of the first step 438 and the second step 440. Figure 4C is determined by previously removing layer 418 during the etching.

[0025] Fig. 4I Continuation of the etching of the first dielectric layer 416 is shown, with the portion of the etch stop layer 414 over the third bond pad 212 being removed. Figure 4J Continuation of etching of the first dielectric layer 416, the etch stop layer 414, and the composite layer 412 is shown. Figure 4J As shown in FIG. 4 , this step exposes the third bonding pad 212. Importantly, etching continues at the first step 438 and the second step 440 such that the first step 438 enters the etch stop layer 414. Thus, the composite layer 412 and the portion of the etch stop layer 414 at the first step 438 are significantly thinned to 3 to 5 μm, which is consistent with the embodiment of FIG. Figure 3 6μm or larger relative.

[0026] Figure 4K The formation of a polyimide layer 442 is shown. An uncured photosensitive polyimide layer is deposited using a spin coating technique. Using a standard binary mask, portions of the polyimide are exposed to broad spectrum light, which causes the material to crosslink in such a way that during subsequent exposure to a chemical developer, the irradiated areas remain and the non-irradiated areas dissolve away.

[0027] Figure 4L Ball bond 320 is shown coupled to first bond pad 204, and first bond wire 322 is coupled to ball bond 320. Additionally, stitch bond 340 is coupled to third bond pad 212, and second bond wire 342 is coupled to stitch bond 340. Since composite layer 412 and etch stop layer 414 are significantly thinned at first step 438, shear blade 110 has a substantially 85 μm wide region from second step 440 to stitch bond 340, thus allowing third bond pad 212 to act as a shear pad. Notably, shear test blade 110 moves in a direction perpendicular to the page. Figure 4L The position of the shear test blade 110 in FIG. 1 is only used to illustrate its position relative to the stitch bond 340 .

[0028] Figure 5A and 5B(collectively referred to as "FIG. 5") is a flow chart showing a process 500 that summarizes the features of the process described in FIG. 4. Step 502 is to form a first patterned conductive layer on a substrate, the first patterned conductive layer including a first bonding pad. An example of the first patterned conductive layer is the third coil 302 and the third bonding pad 212 ( Figure 4L Step 504 is to form a dielectric layer and an etching auxiliary layer on the first patterned conductive layer. An example of the dielectric layer is the first dielectric layer 416. An example of the etching auxiliary layer is the etching auxiliary layer 418 ( Figure 4L Step 506 is to use the first photoresist layer to pattern the etching auxiliary layer so that the etching auxiliary layer does not cover the cut window above the first bonding pad. Figure 4C An example of the first photoresist layer is the first photoresist layer 420 ( Figure 4C Step 508 is to form a second dielectric layer on the etching auxiliary layer and the first dielectric layer. An example of the second dielectric layer is the second dielectric layer 422 ( Figure 4D Step 510 is to form a second patterned conductive layer on the dielectric layer. An example of the second patterned conductive layer is the first coil 202 and the first bonding pad 204 ( Figure 4L Step 512 is to form and pattern a second photoresist layer on the second patterned conductive layer, wherein the second photoresist layer has a second opening corresponding to the first shear window. An example of the second photoresist layer is the second photoresist layer 428 ( Figure 4E Step 514 is to use the second photoresist layer as a mask to etch the second dielectric layer to a depth of 3% to 10% of the thickness of the first dielectric layer and the second dielectric layer. An example of this step is Figure 4E Step 516 is to form and pattern a third photoresist layer, wherein the third photoresist layer has a pattern for a third opening leading to the first shear window. An example of the third photoresist layer is the third photoresist layer 434 ( Figure 4G Step 518 is to etch the second dielectric layer to a depth of 20% to 25% of the exposed portions of the first dielectric layer and the second dielectric layer using the third photoresist layer as a mask. An example of this step is Figure 4G Step 520 is to form and pattern a fourth photoresist layer, wherein the fourth photoresist layer has a fourth opening corresponding to the first shear window, wherein the fourth opening is larger than the first opening and the third opening, but smaller than the second opening. An example of the fourth photoresist layer is the fourth photoresist layer 436 ( Figure 4H Step 522 is to etch the first dielectric layer and the second dielectric layer to a depth of 15% to 30% of the thickness of the dielectric layer using the fourth photoresist layer as a mask. Figure 4HStep 524 is to etch the first dielectric layer using the fourth photoresist layer as a mask so that the first bonding pad is exposed in the form of a third opening, and the thickness of the dielectric layer exposed by the first opening and enclosing the exposed second bonding pad is between 2 and 5 microns above the surface of the metal layer. An example of this step is Fig. 4I and 4J Shown in the middle.

[0029] Modifications are possible in the described examples, and other examples are possible, within the scope of the claims.

Claims

1. A method comprising: forming a first patterned conductive layer on a substrate, wherein the first patterned conductive layer includes a first bonding pad; forming a first dielectric layer on the first patterned conductive layer; forming an etching auxiliary layer on the first dielectric layer; patterning the etch assist layer so that the etch assist layer is not above the first bonding pad; forming a second dielectric layer on the first dielectric layer and the etching auxiliary layer; forming a second patterned conductive layer on the dielectric layer; forming and patterning a first photoresist layer on the second patterned conductive layer, wherein the first photoresist layer does not cover the first bonding pad; etching the dielectric layer to a depth of 5% to 15% of the thickness of the first dielectric layer and the second dielectric layer using the first photoresist layer as a mask; forming and patterning a second photoresist layer having a pattern for a second opening leading to the first bonding pad; etching the first dielectric layer and the second dielectric layer to a depth of 20% to 25% of the exposed portions of the first dielectric layer and the second dielectric layer using the second photoresist layer as a mask; forming and patterning a third photoresist layer, wherein the third photoresist layer has a third opening that is smaller than the first opening and larger than the second opening; and The first dielectric layer is etched using the third photoresist layer as a mask so that the first bonding pad is exposed in the form of the second opening and the thickness of the dielectric layer in the area exposed by the third opening but not by the second opening is between 3 and 5 μm. 2 . The method of claim 1 , wherein the first dielectric layer comprises silicon dioxide and the second dielectric layer comprises silicon dioxide. The method of claim 2 , wherein the etch assist layer comprises silicon nitride. 4 . The method of claim 1 , wherein the first patterned conductive layer comprises a first coil, the second patterned conductive layer comprises a second coil, and the first coil and the second coil are concentric and aligned with each other. The method of claim 1 , wherein the dielectric layer comprises silicon dioxide.

6. The method according to claim 1, further comprising: After etching the dielectric layer using the first photoresist layer, a protection layer is formed on the second patterned conductive layer.

7. The method of claim 6, wherein the second photoresist layer includes a fourth opening corresponding to a second bonding pad in the second patterned conductive layer, and wherein etching the dielectric layer using the second photoresist layer provides an opening in the protective layer that exposes the second bonding pad.

8. The method according to claim 1, further comprising: A ball bond is bonded to the first bond pad.

9. A method comprising: forming a first patterned conductive layer on a substrate, wherein the first patterned conductive layer includes a first bonding pad; forming a composite layer on the first patterned conductive layer; forming an etch stop layer on the composite layer; forming a first dielectric layer on the first patterned conductive layer; forming an etching auxiliary layer on the first dielectric layer; patterning the etching auxiliary layer so that the etching auxiliary layer has an edge; forming a second dielectric layer on the etch assist layer and the exposed portion of the first dielectric layer; forming a second patterned conductive layer on the second dielectric layer; forming and patterning a first photoresist layer on the second patterned conductive layer, wherein the first photoresist layer does not cover the first bonding pad; etching the second dielectric layer to a depth of 5% to 15% of the thickness of the first dielectric layer and the second dielectric layer using the first photoresist layer as a mask; forming and patterning a second photoresist layer having a pattern for a second opening leading to the first bond pad, wherein the second opening is a selected distance from the edge; etching the first dielectric layer and the second dielectric layer to a depth of 20% to 25% of the exposed portion of the second dielectric layer using the second photoresist layer as a mask; forming and patterning a third photoresist layer, wherein the third photoresist layer has a third opening that is smaller than the first opening and larger than the second opening; and The first dielectric layer, the etch stop layer and the composite layer are etched using the third photoresist layer as a mask, so that the first bonding pad is exposed in the form of the second opening, and the thickness of the etch stop layer and the composite layer in the area exposed by the third opening but not exposed by the second opening is between 3 and 5 μm.

10. The method of claim 9, wherein the first dielectric layer and the second dielectric layer are silicon dioxide, and the etch assist layer comprises silicon oxynitride. 11 . The method of claim 9 , wherein the first patterned conductive layer comprises a first coil, the second patterned conductive layer comprises a second coil, and the first coil and the second coil are concentric and aligned with each other.

12. The method of claim 9, wherein the first dielectric layer and the second dielectric layer comprise silicon dioxide.

13. The method of claim 9, further comprising: After etching the second dielectric layer using the first photoresist layer, a protection layer is formed on the second patterned conductive layer.

14. The method of claim 13, wherein the second photoresist layer includes a fourth opening corresponding to a second bonding pad in the second patterned conductive layer, and wherein etching the dielectric layer using the second photoresist layer provides an opening in the protective layer that exposes the second bonding pad.

15. The method of claim 9, further comprising: A ball bond is bonded to the first bond pad.

16. An apparatus comprising: A first patterned conductive layer, located on the substrate, wherein the first patterned conductive layer includes a first bonding pad; a dielectric layer on the first patterned conductive layer, wherein the dielectric layer exposes an opening of the first bonding pad and a portion adjacent to the opening having a thickness between 3 and 5 μm thick; and The second patterned conductive layer is located on the dielectric layer.

17. The device of claim 16, wherein the dielectric layer comprises: a first dielectric layer; an etching auxiliary layer, which is located on the first dielectric layer; and A second dielectric layer is located on the etching auxiliary layer.

18. The device of claim 17, wherein the first dielectric layer and the second dielectric layer are silicon dioxide, and the etch assist layer comprises silicon oxynitride.

19. The device of claim 17, wherein the first patterned conductive layer comprises a first coil, the second patterned conductive layer comprises a second coil, and the first coil and the second coil are aligned with each other.

20. The device of claim 16, further comprising: A ball bond is bonded to the first bonding pad.

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