Self-aligned backside contact for 3DIC applications

Abstract

Integrated circuit structures with through substrate vias (TSVs) processed by self-aligned contact modules are disclosed. Thus, much smaller and / or much densified TSVs are formed with low mechanical stresses. The denser TSVs allow for more flexible routing options.

Description

Technical Field

[0001] The present disclosure generally relates to novel self-aligned backside contacts for three-dimensional integrated circuit (3DIC) applications. Background Art

[0002] Integrated circuit technology has made great progress in increasing computing power by miniaturizing components such as semiconductor transistors. The development of semiconductors has evolved from bulk substrates and planar CMOS, FinFET, nanowires or nanoribbons, FinFET 3D stacking to nanowire or nanoribbon 3D stacking. 3DIC is one of the main trends in very large scale integration (VLSI) devices in the More Moore era. Silicon vias are an important process module that allows 3D stacking.

[0003] Unfortunately, conventional TSVs are limited by size, aspect ratio, mechanical stress, and alignment on the other side.Therefore, there is a need for systems, apparatus, and methods that enable fabrication of TSVs that address one or more issues with conventional TSVs and their fabrication. Summary of the invention

[0004] A simplified overview of one or more aspects and / or examples associated with each device and method disclosed herein is presented below. As such, the following overview should neither be considered an exhaustive overview of all considered aspects and / or examples, nor should the following overview be considered to identify key or decisive elements associated with all considered aspects and / or examples or to depict the scope associated with any particular aspect and / or example. Accordingly, the sole purpose of the following overview is to present certain concepts related to one or more aspects and / or examples of the device and method disclosed herein in a simplified form prior to the detailed description presented below.

[0005] An exemplary integrated circuit (IC) structure is disclosed. The IC structure may include a substrate. The IC structure may also include a front insulator located on the front surface of the substrate. The IC structure may also include a transistor located on the substrate and in the front insulator. The IC structure may also include one or more front metal layers located in the front insulator on the front side of the transistor. At least one front metal layer may be electrically coupled to the transistor. The IC structure may also include a through substrate via (TSV) located in the substrate and in the front insulator. The TSV may include a front contact located in the front insulator and electrically coupled to the front metal layer. The TSV may also include a back contact located in the substrate and electrically coupled to the front contact.

[0006] An exemplary method of manufacturing an integrated circuit (IC) structure is disclosed. The method may include forming a substrate. The method may also include forming a front insulator on a front surface of the substrate. The method may also include forming a transistor on the substrate and in the front insulator. The method may also include forming one or more front metal layers in the front insulator on the front side of the transistor. At least one front metal layer may be electrically coupled to the transistor. The method may also include forming a through substrate via (TSV) in the substrate and in the front insulator. The TSV may include a front contact located in the front insulator and electrically coupled to the front metal layer. The TSV may also include a back contact located in the substrate and electrically coupled to the front contact.

[0007] Other features and advantages associated with the various devices and methods disclosed herein will be apparent to those skilled in the art based on the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] A more complete appreciation thereof will be readily obtained as various aspects of the present disclosure and many of its attendant advantages become better understood by reference to the following detailed description when considered in conjunction with the accompanying drawings, which are presented for purposes of illustration only and do not constitute a limitation of the present disclosure in any way.

[0009] Figure 1 An example of a conventional 3DIC is illustrated.

[0010] Figure 2 Another example of a conventional 3DIC is illustrated.

[0011] Figure 3 Examples of integrated circuit structures according to one or more aspects of the present disclosure are illustrated.

[0012] FIG. 4A to FIG. 4J An example of stages in fabricating an integrated circuit structure according to one or more aspects of the present disclosure is illustrated.

[0013] Figures 5 to 7B A flow chart illustrating an example method of fabricating an integrated circuit structure according to one or more aspects of the present disclosure.

[0014] Figure 8 Various electronic devices are illustrated that may utilize one or more aspects of the present disclosure.

[0015] Based on the drawings and detailed description, other purposes and advantages associated with the various aspects disclosed herein will be apparent to those skilled in the art. According to convention, the features depicted in the drawings may not be drawn to scale. Accordingly, for the sake of clarity, the size of the features depicted may be arbitrarily enlarged or reduced. According to convention, for the sake of clarity, some drawings are simplified. Therefore, the drawings may not depict all components of a particular device or method. In addition, similar reference numerals are used throughout the specification and the drawings to indicate similar features. DETAILED DESCRIPTION

[0016] Various aspects of the present disclosure are illustrated in the following description and related drawings for specific embodiments. Alternative aspects or embodiments may be designed without departing from the scope of the present teachings. In addition, well-known elements of the exemplary embodiments herein will not be described in detail or will be omitted to avoid obscuring the relevant details of the teachings in the present disclosure.

[0017] In some of the described example implementations, the following examples are identified where various component structures and portions of operations may be obtained from known conventional techniques and then arranged according to one or more exemplary embodiments. In such examples, internal details of portions of known conventional component structures and / or operations may be omitted to help avoid potential confusion of the concepts illustrated in the exemplary embodiments disclosed herein.

[0018] The terminology used herein is for the purpose of describing specific embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the term "comprising", when used herein, specifies the presence of stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0019] As noted above, TSVs can be an important process module that allows 3D stacking in 3DIC to occur. However, conventional TSVs are limited by size, aspect ratio, mechanical stress, and alignment on the other side. Figure 1 An example of a conventional 3DIC is illustrated. The conventional 3DIC 100 is an example illustrating TSVs on a bulk silicon (Si) substrate.

[0020] As shown, conventional 3DIC 100 includes a bulk silicon (Si) substrate 110 and a dielectric 120 located on the front surface of the substrate 110. In this case, the front surface of the substrate 110 is the upper surface. Before continuing, it should be noted that terms such as "upper", "lower", "left", "right", etc. are used for convenience and are not intended to indicate an absolute orientation unless otherwise explicitly indicated.

[0021] As shown, transistor 130 is formed in substrate 110 and in dielectric 120. Source silicide 132 contacts the source of transistor 130, drain silicide 134 contacts the drain of transistor 130, and gate silicide 136 contacts the gate of transistor 130. Source contact 133 contacts source silicide 132, drain contact 135 contacts drain silicide 134, and gate contact 137 contacts gate silicide 136.

[0022] Metal layers 160-1, 160-2, 160-2 (individually or in combination referred to as metal layers 160) are formed in dielectric 120. In this case, first metal layer 160-1 (also referred to as M1) is electrically coupled to transistor 130 through source contact 133, drain contact 135, and / or gate contact 137.

[0023] 3DIC 100 also includes silicon vias 150 formed in dielectric 120, shallow trench isolation (STI) 140, and substrate 110. STI 140 is located in an upper portion of substrate 110 to isolate transistor 130. As shown, silicon vias 150 contact first metal layer 160-1 and extend through dielectric 120, STI 140, and substrate 110.

[0024] The size of TSV 150 is large. For example, the width and height of TSV 150 may be about 10um and about 150um, respectively. The large size of TSV 150 may exert stress on nearby devices. Moreover, the density of TSV is reduced due to the large size. This means that the wiring options are limited.

[0025] Figure 2 Another example of a conventional 3DIC 200 is illustrated, which is an example of TSV on silicon on insulator (SOI). As shown, the conventional 3DIC 200 includes a buried oxide (BOX) layer 215, a front dielectric 220 located on the front (upper) surface of the BOX layer 215, and a back dielectric 225 located on the back (lower) surface of the BOX layer 215.

[0026] As shown, transistor 230 is formed on BOX layer 215 and in front dielectric 220. Source silicide 232 contacts the source of transistor 230, drain silicide 234 contacts the drain of transistor 230, and gate silicide 236 contacts the gate of transistor 230. Source contact 233 contacts source silicide 232, drain contact 235 contacts drain silicide 234, and gate contact 237 contacts gate silicide 236.

[0027] Front side metallization layers 260-1, 260-2, 260-2 (individually or in combination referred to as front side metallization layers 260) are formed in front side dielectric 220. In this case, first front side metallization layer 260-1 (also referred to as M1) is electrically coupled to transistor 230 through source contact 233, drain contact 235, and / or gate contact 237.

[0028] Back side metal layers 270 - 1 , 270 - 2 (individually or in combination referred to as back side metal layers 270 ) are formed in the back side dielectric 225 .

[0029] 3DIC 200 also includes silicon vias 250 formed in front dielectric 220 and BOX layer 215. As shown, silicon vias 250 contact first front metal layer 260-1, extend through front dielectric 220 and BOX layer 215, and contact first back metal layer 270-1.

[0030] The size of TSV 250 is still large. For example, the width and height of TSV 250 may be about 0.5um and about 0.3um, respectively. The large size of TSV 250 may exert stress on nearby devices. Moreover, the density of TSV is reduced due to the large size. This means that the wiring options are limited. Moreover, aligning TSV 250 with the first front metal layer 260-1 and / or aligning TSV 250 with the first back metal layer 270-1 may become a problem.

[0031] To solve one or more problems of conventional 3DIC, it is proposed to provide a self-aligned contact module for TSV, which enables much smaller and denser TSVs with much lower stress. The proposed TSV is fully compatible with standard manufacturing (eg, complementary metal oxide semiconductor (CMOS) technology).

[0032] Figure 3 An example of an integrated circuit (IC) structure according to one or more aspects of the present disclosure is illustrated. A 3DIC may be Figure 3 An example of an integrated circuit structure 300 is illustrated in FIG. Although an SOI structure is illustrated, it should be noted that the concepts described herein are not limited thereto.

[0033] IC structure 300 may include substrate 315 and front side insulator 320 located on the front surface of substrate 315. Substrate 315 may be a buried oxide (BOX) layer, and front side insulator 320 may be a dielectric. The front side of substrate 315 may be the surface where active devices (e.g., transistors) are located. Figure 3 In the embodiment of the present invention, the upper surface of the substrate 315 can be referred to as the front surface. The lower surface of the substrate 315 can be regarded as the back surface.

[0034] The surfaces of other elements, such as the front insulator 320, may be in the same orientation. That is, the upper surface and the lower surface of the front insulator 320 may be referred to as the front surface and the back surface, respectively. Thus, in this case, the back surface of the front insulator 320 may be on the front surface of the substrate 315 or in contact with the front surface of the substrate.

[0035] Transistor 330 may be formed on substrate 315 and in front insulator 320. Source connector 332 may be electrically coupled to the source of transistor 330. For example, source connector 332 may be formed in the source of transistor 330 and / or in physical contact with the source of the transistor. Drain connector 334 may be electrically coupled to the drain of transistor 330. For example, drain connector 334 may be formed in the drain of transistor 330 and / or in physical contact with the drain of the transistor. Gate connector 336 may be electrically coupled to the gate of transistor 330. For example, gate connector 336 may be in physical contact with the gate of transistor 330. Source connector 332, drain connector 334, and / or gate connector 336 may be formed of silicide.

[0036] A source contact 333, a drain contact 335, and a gate contact 337 may be formed in the front side insulating member 320. The source contact 333 may be electrically coupled to the source of the transistor 330. For example, the source contact 333 may be in physical contact with the source connector 332. The drain contact 335 may be electrically coupled to the drain of the transistor 330. For example, the drain contact 335 may be in physical contact with the drain connector 334. The gate contact 337 may be electrically coupled to the gate of the transistor 330. For example, the gate contact 337 may be in physical contact with the gate connector 336.

[0037] One or more front metal layers 360 may be formed in the front insulating member 320. Figure 3, three front metal layers 360-1, 360-2, 360-3 are illustrated. However, there may be any number of front metal layers 360. At least one front metal layer 360 may be electrically coupled to the transistor 330. For example, one or more front metal layers 360 may contact any one or more of the source contact 333, the drain contact 335, and the gate contact 337. The front metal layer 360 may be formed of one or more metals including one or more of the following: tungsten (W), copper (Cu), aluminum (Al), cobalt (Co), palladium (Pd), nickel (Ni), gold (Au), tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), bismuth (Bi), antimony (Sb), molybdenum (Mo), ruthenium (Ru), etc.

[0038] The IC structure 300 may include a through substrate via 350 formed in the substrate 315 and in the front insulator 320. The TSV 350 may include a front contact 354 and a back contact 356. The front contact 354 may be formed in the front insulator 320, and the back contact 356 may be formed in the substrate 315. The front contact 354 and / or the back contact 356 may be formed of a metal including any one or more of the following: W, Cu, Al, Co, Pd, Ni, Au, Ta, TaN, Ti, TiN, Bi, Sb, Mo, Ru, etc. In one aspect, the front contact 354 and / or the back contact 356 may be formed of the same material as the source contact 333, the drain contact 335, and the gate contact 337.

[0039] The back contact 356 may extend from the back surface of the substrate 315 toward the front surface of the substrate 315. Also, the back surface of the back contact 356 may be coplanar with the back surface of the substrate 315. That is, the back contact 356 may be exposed at the back surface of the substrate 315.

[0040] The front contact 354 and the back contact 356 may be electrically coupled to each other. For example, the TSV 350 may also include a through-connector 352 located (physically and / or electrically) between the front contact 354 and the back contact 356. In particular, the front surface of the through-connector 352 may be in physical contact with the back surface of the front contact 354. Moreover, the back surface of the through-connector 352 may be in physical contact with the front surface of the back contact 356. The through-connector 352 may be partially located in the front insulating member 320 and partially located in the substrate 315. The through-connector 352 may be formed of the same material as the source connector 332, the drain connector 334, and the gate connector 336. For example, the through-connector 352 may be formed of silicide.

[0041] The sizes of the front contact 354 and the back contact 356 may be different. For example, the width and height of the front contact 354 may be 0.05um and 0.09um, and the width and height of the back contact 356 may be 0.1um and 0.1um. These values ​​may be typical, but the dimensions are not limited to these values. Therefore, it can be seen that the TSV 350 is larger than the Figure 1 and Figure 2 The conventional TSVs 150, 250 are much smaller. This can result in a much denser TSV 350, which is desirable. Note that in one aspect, the width of the front contact 354 can be narrower than the width of the back contact 356.

[0042] IC structure 300 may further include a back side insulator 325 located on a back side surface (opposite to the front side surface) of substrate 315. Back side insulator 325 may be a dielectric. That is, back side insulator 325 and front side insulator 320 may be formed of the same material.

[0043] The IC structure 300 may also include one or more back metal layers 370 located in the back insulator 325. Figure 3 , two back metal layers 370-1, 370-2 are illustrated. However, there may be any number of back metal layers 370. The back contact 356 may be electrically coupled to the back metal layer 370. For example, at least one back metal layer 370 may be in physical contact with the back contact 356. The back metal layer 370 may be formed of the same material as the front metal layer 360. That is, the back metal layer 370 may be formed of any one or more of the following: W, Cu, Al, Co, Pd, Ni, Au, Ta, TaN, Ti, TiN, Bi, Sb, Mo, Ru, etc.

[0044] FIG. 4A to FIG. 4J An example of stages in fabricating an integrated circuit structure according to one or more aspects of the present disclosure is illustrated. In this example, these stages may be applied to the fabrication of IC structure 300.

[0045] Figure 4A The stage is illustrated in which the substrate 315 is disposed on the substrate handle 405. In one aspect, the substrate handle 405 can be a silicon substrate. Doped silicon 410 can be formed on the substrate 315 near its front surface. The doped silicon 410 can be lightly doped, for example, the doping level can be 10 12 / cm 3 and 10 17 / cm 3 A shallow trench isolation (STI) region 415 may also be formed in the substrate 315 .

[0046] Figure 4BIllustrated is a stage where trench 420 is formed in STI region 415 of substrate 315. In one aspect, trench 420 can be deep enough to expose the front surface of substrate handle 405.

[0047] Figure 4C The stage is illustrated in which the trench 420 is partially filled with a trench insulator 430 (e.g., a dielectric) on the front surface of the substrate handle 405. The remaining portion of the trench 420 can then be filled with a first sacrificial trench fill 425. In one aspect, the first sacrificial trench fill 425 can be a first doped polysilicon, which can be a lightly doped polysilicon, also with a doping level of about 10 12 / cm 3 and 10 17 / cm 3 The first sacrificial trench filling 425 may then be polished (eg, by chemical mechanical polishing (CMP)). After polishing, the first sacrificial trench filling 425 and the front surface of the substrate 315 may be coplanar.

[0048] Figure 4D A stage is illustrated in which a gate oxide layer 435 is grown on the front surface of the substrate 315, the first sacrificial trench fill 425, and the doped silicon 410. Then, a polysilicon layer 440 may be grown or otherwise formed on the front surface of the gate oxide layer 435. The polysilicon layer 440 may be a second doped polysilicon, which may be lightly doped.

[0049] Figure 4E The stage in which the transistor 330, one or more front metal layers 360, the front contact 354 and the through-connection 352 are formed is illustrated. This can be done by standard CMOS front end of line (FEOL), middle of line (MOL) and back end of line (BEOL) processes. Through the FEOL, MOL and BEOL processes, the polysilicon layer 440 can be replaced with the front insulator 320, the transistor 330, one or more front metal layers 360, the front contact 354 and the through-connection 352. Moreover, the first sacrificial trench fill 425 in the trench 420 can be replaced with the second sacrificial trench fill 456, which can be a third doped silicon or polysilicon, which can be heavily doped, for example, the doping level can be above 10 19 / cm 3 and 10 21 / cm 3 between.

[0050] Figure 4F The stage in which the IC structure is turned over is illustrated.

[0051] Figure 4GA stage is illustrated where the substrate handle 405, the trench insulator 430 and a portion of the substrate 315 are removed, for example by grinding and / or etching. After removal, the second sacrificial trench fill 456 may be exposed.

[0052] Figure 4H A stage is illustrated in which the second sacrificial trench fill 456 is removed from the trench 420 by selective etching. Because a selective etchant is used, no mask needs to be used. After the selective etching, the through connector 352 may be exposed.

[0053] Fig. 4I Illustrated is a stage where trenches 420 may be filled with metal to form back contacts 356. Back contacts 356 may then be polished (e.g., by CMP) such that the back surface of substrate 315 is coplanar with back contacts 356. Back contacts 356 may serve as alignment marks for forming back metal layer 370.

[0054] Figure 4J A stage is illustrated in which a back side insulating member 325 and a back side metal layer 370 are formed.

[0055] Figure 5 A flow chart illustrating an example method 500 of fabricating an integrated circuit (IC) structure (eg, IC structure 300 ) in accordance with one or more aspects of the present disclosure. In block 510 , a substrate 315 may be formed.

[0056] In block 520 , the front-side insulating member 320 may be formed on the front surface of the substrate 315 .

[0057] In block 530 , transistor 330 may be formed on substrate 315 and in front side insulator 320 .

[0058] In block 540, one or more front side metallization layers 360 may be formed in the front side insulator 320 at the front side of the transistor 330. The at least one front side metallization layer 360 may be electrically coupled to the transistor 330.

[0059] In block 550, through substrate vias (TSVs) 350 may be formed in the substrate 315 and in the front side insulator 320. The TSVs 350 may include front side contacts 354 in the front side insulator 320. The front side contacts 354 may be electrically coupled to the front side metal layer 360. The TSVs 350 may also include back side contacts 356 in the substrate 315 and electrically coupled to the front side contacts 354.

[0060] Figure 6 A flow chart illustrating an example method 600 of fabricating an integrated circuit structure, such as integrated circuit structure 300 , according to one or more aspects of the present disclosure. Figure 6 Can be Figure 5 More comprehensive view. Therefore, blocks 610-650 may be similar to blocks 510-550. Therefore, for the sake of brevity, a detailed description of blocks 610-650 will be omitted.

[0061] Fig. 7A and Figure 7B Demonstrates the implementation Figure 5 Frames 530, 540, 550 and Figure 6 Flowchart of an example process of blocks 630, 640, and 650 of FIG. 710. In block 710, a substrate handle 405 may be provided, and a substrate 315 may be disposed on a front surface of the substrate handle 405, and doped silicon 410 may be disposed on the substrate 315. The front surfaces of the doped silicon 410 and the substrate 315 may be coplanar. A shallow trench isolation (sTI) region 415 may be formed in a portion of the substrate 315 not covered by the doped silicon 410. Block 710 may correspond to Figure 4A The stages illustrated in .

[0062] In block 715, a trench 420 may be etched in the STI region 415 of the substrate 315. The trench 420 may expose a portion of the front surface of the substrate handle 405. Block 715 may correspond to Figure 4B The stages illustrated in .

[0063] In block 720 , the trench 420 may be partially filled with a trench insulator 430 on the front surface of the substrate handle 405 .

[0064] In block 725 , the remaining portion of the trench 420 may be filled with a first sacrificial trench fill 425 .

[0065] In block 730, the first sacrificial trench filling 425 may be polished. After polishing, the front surface of the first sacrificial trench filling 425 may be coplanar with the front surface of the substrate 315. Blocks 720, 725, and 730 may correspond to Figure 4C The stages illustrated in .

[0066] In block 740 , a gate oxide layer 435 may be formed on the front surface of the substrate 315 , the front surface of the first sacrificial trench fill 425 , and the front surface of the doped silicon 410 .

[0067] In block 745, polysilicon layer 440 may be formed on the front surface of gate oxide layer 435. Blocks 740 and 745 may correspond to Figure 4D The stages illustrated in .

[0068] In block 750, transistor 330, one or more front metal layers 360, front contacts 354, and through-connectors 352 may be formed, for example, by standard CMOS FEOL, MOL, and BEOL processes. Polysilicon layer 440 may be replaced with front insulator 320, transistor 330, one or more front metal layers 360, front contacts 354, and through-connectors 352. Also, first sacrificial trench fill 425 in trench 420 may be replaced with second sacrificial trench fill 456. Block 750 may correspond to Figure 4E The stages illustrated in .

[0069] At block 755, IC structure 300 may be flipped over. Block 755 may correspond to Figure 4F The stages illustrated in .

[0070] In block 760, the substrate handle 405, the trench insulator 430, and a portion of the substrate 315 may be removed. The second sacrificial trench fill 456 may be exposed after removal. Block 760 may correspond to Figure 4G The stages illustrated in .

[0071] In block 765, the second sacrificial trench fill 456 may be selectively etched from the trench 420. After the selective etching, the through connector 352 may be exposed within the trench 420. Block 765 may correspond to Figure 4H The stages illustrated in .

[0072] In block 770 , the trenches 420 may be filled with metal to form the backside contacts 356 .

[0073] In block 775, the back contact 356 may be polished, for example, by CMP. After polishing, the back surface of the back contact 356 may be coplanar with the back surface of the substrate 315. Blocks 770, 775 may correspond to Fig. 4I The stages illustrated in .

[0074] Re-reference Figure 6 In block 660 , a back insulating member 325 may be formed on a back surface of the substrate 315 , which is opposite to the front surface of the substrate 315 .

[0075] In block 670, one or more back metal layers 370 may be formed in the back insulator 325. The back contacts 356 may be electrically coupled to the back metal layers 370. Blocks 660, 670 may correspond to Figure 4J The stages illustrated in .

[0076] It will be understood that the foregoing manufacturing processes and related discussions are provided only as general illustrations of some aspects of the present disclosure and are not intended to limit the present disclosure or the appended claims. Further, many details of the manufacturing processes known to those skilled in the art may be omitted or combined in each overview process section to facilitate understanding of the various aspects disclosed without having to present each detail and / or all possible process variations in detail. In addition, it will be understood that the illustrated configurations and descriptions are provided merely to help illustrate the various aspects disclosed herein. Accordingly, the above illustrative examples and associated drawings should not be construed as limiting the various aspects disclosed and claimed herein.

[0077] Figure 8 Various electronic devices 800 are illustrated that may be integrated with any of the aforementioned devices in accordance with various aspects of the present disclosure. For example, mobile phone device 802, laptop device 804, and fixed location terminal device 806 may each be generally considered as user equipment (UE) and may include electronic device 800 that includes one or more IC structures (e.g., IC structure 300) as described herein. Figure 8 The devices 802, 804, and 806 illustrated in the figure are merely exemplary. Other electronic devices may also include the IC structure, including but not limited to a group of devices (e.g., electronic devices) including the following: mobile devices, handheld personal communication systems (PCs) units, portable data units (such as personal digital assistants), devices enabled with a global positioning system (GPS), navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units (such as meter reading equipment), communication devices, smart phones, tablet computers, computers, wearable devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous vehicles), Internet of Things (IoT) devices, or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0078] The devices and functionality disclosed above may be designed and configured in computer files (e.g., RTL, GDSII, GERBER, etc.) stored on computer readable media. Some or all of such files may be provided to manufacturing processors that manufacture devices based on such files. The resulting products may include semiconductor wafers that are then cut into semiconductor dies and packaged into IC devices. The IC devices may then be used in the devices described herein.

[0079] Specific implementation examples are described in the following numbered clauses:

[0080] Item 1: An integrated circuit (IC) structure, comprising: a substrate; a front side insulator, the front side insulator being located on a front surface of the substrate; a transistor, the transistor being located on the substrate and in the front side insulator; one or more front side metal layers, the one or more front side metal layers being located in the front side insulator on the front side of the transistor, at least one front side metal layer being electrically coupled to the transistor; and a through substrate via (TSV), the through substrate via (TSV) being located in the substrate and in the front side insulator, the TSV comprising: a front side contact, the front side contact being located in the front side insulator and being electrically coupled to the front side metal layer; and a back side contact, the back side contact being located in the substrate and being electrically coupled to the front side contact.

[0081] Item 2: An IC structure according to item 1, wherein the front contact is formed by one or more of the following items: tungsten (W), copper (Cu), aluminum (Al), cobalt (Co), palladium (Pd), nickel (Ni), gold (Au), tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), bismuth (Bi), antimony (Sb), molybdenum (Mo) and ruthenium (Ru), or wherein the back contact is formed by one or more of the following items: W, Cu, Al, Co, Pd, Ni, Au, Ta, TaN, Ti, TiN, Bi, Sb, Mo and Ru, or both.

[0082] Clause 3: The IC structure of any of clauses 1 to 2, wherein a width of the front contact is narrower than a width of the back contact.

[0083] Clause 4: The IC structure of any of clauses 1 to 3, wherein the TSV further comprises: a through-connection between the front contact and the back contact, the through-connection electrically coupling the front contact and the back contact.

[0084] Item 5: The IC structure of Item 4, wherein a front surface of the through-connector is in physical contact with a back surface of the front contact, and wherein a back surface of the through-connector is in physical contact with a front surface of the back contact.

[0085] Clause 6: The IC structure of any of clauses 4 to 5, wherein the through-connector is formed of silicide.

[0086] Clause 7: The IC structure of any of clauses 4 to 6, wherein the through-connector is located partially in the front side insulator and partially in the substrate.

[0087] Item 8: An IC structure according to any one of items 4 to 7, the IC structure further comprising: a source connector, a drain connector, a gate connector, or any combination thereof, wherein the source connector is electrically coupled to the source of the transistor, wherein the drain connector is electrically coupled to the drain of the transistor, and wherein the gate connector is electrically coupled to the gate of the transistor.

[0088] Item 9: The IC structure of Item 8, wherein any one or more of the source connector, the drain connector, and the gate connector are formed of the same material as the through connector.

[0089] Item 10: An IC structure according to any one of items 1 to 9, wherein the IC structure also includes: a source contact, a drain contact, a gate contact or any combination thereof, wherein the source contact is formed in the front insulating member and is electrically coupled to the source of the transistor, wherein the drain contact is formed in the front insulating member and is electrically coupled to the drain of the transistor, and wherein the gate contact is formed in the front insulating member and is electrically coupled to the gate of the transistor.

[0090] Item 11: The IC structure of Item 10, wherein any one or more of the source contact, the drain contact, and the gate contact are formed of the same material or materials as the front contact.

[0091] Item 12: An IC structure according to any one of items 1 to 11, wherein the IC structure further includes: a back side insulating member, wherein the back side insulating member is located on a back surface of the substrate opposite to the front surface of the substrate; and one or more back side metal layers, wherein the one or more back side metal layers are located in the back side insulating member, wherein the back side contact is electrically coupled to the back side metal layer.

[0092] Item 13: The IC structure of Item 12, wherein the back side metal layer is in physical contact with the back side contact.

[0093] Clause 14: An IC structure according to any one of clauses 12 to 13, wherein the back side insulator is formed of the same material or materials as the front side insulator, or wherein the one or more back side metal layers are formed of the same material or materials as the one or more front side metal layers, or both.

[0094] Clause 15: The IC structure of any of clauses 1 to 14, wherein the substrate comprises a buried oxide (BOX) layer, or wherein the front side insulator comprises a front side dielectric layer, or both.

[0095] Clause 16: The IC structure of any of clauses 1 to 15, wherein the backside contact extends from a backside surface of the substrate toward the frontside surface of the substrate.

[0096] Clause 17: The IC structure of Clause 16, wherein a back surface of the back contact is coplanar with the back surface of the substrate.

[0097] Clause 18: An IC structure according to any one of clauses 1 to 17, wherein the one or more front metal layers are formed from one or more of the following: tungsten (W), copper (Cu), aluminum (Al), cobalt (Co), palladium (Pd), nickel (Ni), gold (Au), tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), bismuth (Bi), antimony (Sb), molybdenum (Mo) and ruthenium (Ru).

[0098] Clause 19: The IC structure of any of clauses 1 to 18, wherein the IC structure is a three-dimensional integrated circuit (3DIC).

[0099] Clause 20: An IC structure according to any one of clauses 1 to 19, wherein the IC structure is incorporated into a device selected from the group consisting of: a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, an Internet of Things (IoT) device, a laptop computer, a server, and a device in a motor vehicle.

[0100] Item 21: A method of manufacturing an integrated circuit (IC) structure, the method comprising: forming a substrate; forming a front side insulator on a front surface of the substrate; forming a transistor on the substrate and in the front side insulator; forming one or more front side metal layers in the front side insulator on the front side of the transistor, at least one front side metal layer being electrically coupled to the transistor; and forming a through substrate via (TSV) in the substrate and in the front side insulator, the TSV comprising: a front side contact located in the front side insulator and electrically coupled to the front side metal layer; and a back side contact located in the substrate and electrically coupled to the front side contact.

[0101] Clause 22: The method of clause 21, wherein the TSV further comprises: a through-connection between the front contact and the back contact, the through-connection electrically coupling the front contact and the back contact.

[0102] Item 23: A method according to Item 22, wherein forming the transistor, forming the one or more front metal layers, and forming the TSV include: providing a substrate handle and doped silicon on the substrate, the substrate being located on a front surface of the substrate handle, the front surface of the doped silicon being coplanar with the substrate; etching a trench in a shallow trench isolation (STI) region of the substrate, the trench exposing a portion of the front surface of the substrate handle; partially filling the trench with a trench insulator on the front surface of the substrate handle; filling the remaining portion of the trench with a first sacrificial trench fill; polishing the first sacrificial trench fill, wherein the front surface of the first sacrificial trench fill is coplanar with the front surface of the substrate; forming a gate oxide layer on the front surface of the substrate, the front surface of the first sacrificial trench fill, and the front surface of the doped silicon ; forming a polysilicon layer on the front surface of the gate oxide layer; forming the transistor, the one or more front metal layers, the front contact and the through-connection, wherein the polysilicon layer is replaced by the front insulator, the transistor, the one or more front metal layers, the front contact and the through-connection, and wherein the first sacrificial trench fill in the trench is replaced by a second sacrificial trench fill; flipping the IC structure; removing the substrate handle, the trench insulator and a portion of the substrate, wherein the second sacrificial trench fill is exposed; selectively etching the second sacrificial trench fill from the trench, wherein the through-connection is exposed in the trench; filling the trench with metal to form the back contact; and polishing the back contact, wherein the back surface of the back contact is coplanar with the back surface of the substrate.

[0103] Item 24: A method according to item 23, wherein the substrate handle is a silicon substrate, wherein the first sacrificial trench fill is a first doped polysilicon, wherein the polysilicon layer is a second doped polysilicon, wherein the second sacrificial trench fill is a third doped polysilicon, wherein the trench insulator is a dielectric, or any combination of the above.

[0104] Clause 25: The method of any of clauses 22 to 24, wherein the front surface of the through-connector is in physical contact with the back surface of the front contact, and wherein the back surface of the through-connector is in physical contact with the front surface of the back contact.

[0105] Item 26: A method according to any one of items 22 to 25, wherein the front contact is formed by one or more of the following items: tungsten (W), copper (Cu), aluminum (Al), cobalt (Co), palladium (Pd), nickel (Ni), gold (Au), tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), bismuth (Bi), antimony (5b), molybdenum (Mo) and ruthenium (Ru), wherein the back contact is formed by one or more of the following items: W, Cu, Al, Co, Pd, Ni, Au, Ta, TaN, Ti, TiN, Bi, Sb, Mo and Ru, wherein the through-connector is formed by silicide, or any combination of the above.

[0106] Clause 27: The method of any of clauses 21 to 26, wherein a width of the front contact is narrower than a width of the back contact.

[0107] Item 28: A method according to any one of items 21 to 27, the method further comprising: forming a back insulating member on a back surface of the substrate opposite to the front surface of the substrate; and forming one or more back metal layers in the back insulating member, wherein the back contact is electrically coupled to the back metal layer.

[0108] Clause 29: The method of clause 28, wherein the back metal layer is in physical contact with the back contact.

[0109] Clause 30: The method of any of clauses 28 to 29, wherein the back contact is used as an alignment mark when forming the one or more back metal layers.

[0110] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any detail described herein as "exemplary" is not to be construed as trumping other examples. Likewise, the term "example" does not imply that all examples include the discussed features, advantages, or modes of operation. Furthermore, particular features and / or structures may be combined with one or more other features and / or structures. Furthermore, at least a portion of the apparatus described herein may be configured to perform at least a portion of the methods described herein.

[0111] It should be noted that the terms "connected", "coupled" or any variations thereof mean any connection or coupling, direct or indirect, between elements, and may encompass the presence of intermediate elements between two elements via which the two elements are "connected" or "coupled" together, unless the connection is explicitly disclosed as a direct connection.

[0112] Any reference to an element herein using designations such as "first," "second," etc., does not limit the quantity and / or order of those elements. Rather, these designations are used as a convenient method of distinguishing between two or more elements and / or element instances. Furthermore, unless otherwise stated, a set of elements may include one or more elements.

[0113] Nothing described or illustrated in this application is intended to confer upon the public any component, act, feature, benefit, advantage, or equivalent, regardless of whether such component, act, feature, benefit, advantage, or equivalent is recited in the claims.

[0114] In the above specific embodiments, it can be seen that different features are grouped together in each example. This disclosure should not be understood as reflecting the intention that the examples claimed for protection have more features than the features explicitly mentioned in the corresponding claims. On the contrary, the present disclosure may include less than all the features of the disclosed examples. Therefore, the attached claims should be considered to be incorporated into this specification, wherein each claim itself may be a separate example. Although each claim itself may be a separate example, it should be noted that although the dependent claims in the claims may be cited in a specific combination with one or more claims, other examples may also cover or include a combination of the subject matter of the dependent claim with any other dependent claim or any feature with other dependent and independent claims. Such combinations are proposed herein unless it is explicitly expressed that a specific combination is not intended to be used. In addition, it is also intended that the features of the claims may be included in any other independent claim, even if the claim is not directly subordinate to the independent claim.

[0115] It should also be noted that the methods, systems and apparatuses disclosed in the description or claims may be implemented by devices including components for performing the corresponding actions and / or functionalities of the disclosed methods.

[0116] In addition, in some examples, a single action can be subdivided into or include one or more sub-actions. Such sub-actions can be included in and can be part of the disclosure of a single action.

[0117] Although the foregoing disclosure shows illustrative examples of the present disclosure, it should be noted that various changes and modifications may be made therein without departing from the scope of the present disclosure as defined in the appended claims. The functions and / or actions in the method claims of each example of the present disclosure described herein do not necessarily have to be performed in any particular order. In addition, well-known elements will not be described in detail or may be omitted to avoid blurring the relevant details of the various aspects and examples disclosed herein. In addition, although the elements of the present disclosure may be described or claimed in the singular, unless explicitly stated to be limited to the singular, the plural form may also be considered.

Claims

1. An integrated circuit (IC) structure, the integrated circuit (IC) structure comprising: substrate; A front insulating member, the front insulating member being located on the front surface of the substrate; a transistor, the transistor being located on the substrate and in the front insulating member; one or more front side metal layers, the one or more front side metal layers being located in the front side insulating member at a front side of the transistor, at least one front side metal layer being electrically coupled to the transistor; and A through substrate via (TSV), the through substrate via (TSV) being located in the substrate and in the front side insulator, the TSV comprising: a front contact disposed in the front insulating member and electrically coupled to the front metal layer; and A back side contact is located in the substrate and is electrically coupled to the front side contact.

2. The IC structure according to claim 1, wherein the front contact is formed of one or more of: tungsten (W), copper (Cu), aluminum (Al), cobalt (Co), palladium (Pd), nickel (Ni), gold (Au), tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), bismuth (Bi), antimony (Sb), molybdenum (Mo) and ruthenium (Ru), or wherein the back contact is formed of any one or more of: W, Cu, Al, Co, Pd, Ni, Au, Ta, TaN, Ti, TiN, Bi, Sb, Mo and Ru, or Both situations occur. 3 . The IC structure of claim 1 , wherein a width of the front contact is narrower than a width of the back contact.

4. The IC structure of claim 1 , wherein the TSV further comprises: A through-connection is located between the front contact and the back contact, the through-connection electrically coupling the front contact and the back contact.

5. The IC structure according to claim 4, wherein the front surface of the through connector is in physical contact with the back surface of the front contact, and Wherein a back surface of the through-connector is in physical contact with a front surface of the back contact.

6. The IC structure of claim 4, wherein the through-connector is formed of silicide.

7. The IC structure of claim 4, wherein the through-connector is partially located in the front side insulator and partially located in the substrate.

8. The IC structure according to claim 4, further comprising: a source connector, a drain connector, a gate connector, or any combination thereof, wherein the source connector is electrically coupled to a source of the transistor, wherein the drain connector is electrically coupled to the drain of the transistor, and The gate connector is electrically coupled to the gate of the transistor.

9. The IC structure of claim 8, wherein any one or more of the source connector, the drain connector, and the gate connector are formed of the same material as the through connector.

10. The IC structure according to claim 1, further comprising: a source contact, a drain contact, a gate contact or any combination thereof, wherein the source contact is formed in the front side insulating member and is electrically coupled to the source of the transistor, wherein the drain contact is formed in the front side insulating member and is electrically coupled to the drain of the transistor, and The gate contact is formed in the front side insulating member and is electrically coupled to the gate of the transistor.

11. The IC structure of claim 10, wherein any one or more of the source contact, the drain contact, and the gate contact are formed of the same material or materials as the front contact.

12. The IC structure according to claim 1, further comprising: a back insulating member, the back insulating member being located on a back surface of the substrate opposite to the front surface of the substrate; and one or more back metal layers, the one or more back metal layers being located in the back insulating member, The back contact is electrically coupled to the back metal layer.

13. The IC structure of claim 12, wherein the back metal layer is in physical contact with the back contact.

14. The IC structure according to claim 12, wherein the back insulating member is formed of one or more materials that are the same as the front insulating member, or wherein the one or more back metal layers are formed of the same material or materials as the one or more front metal layers, or Both situations occur.

15. The IC structure according to claim 1, wherein the substrate comprises a buried oxide (BOX) layer, or wherein the front insulating member comprises a front dielectric layer, or Both situations occur.

16. The IC structure of claim 1 wherein the backside contact extends from a backside surface of the substrate toward the frontside surface of the substrate.

17. The IC structure of claim 16, wherein a back surface of the back contact is coplanar with the back surface of the substrate.

18. An IC structure according to claim 1, wherein the one or more front metal layers are formed by one or more of the following items: tungsten (W), aluminum (Al), cobalt (Co), copper (Cu), palladium (Pd), nickel (Ni), gold (Au), tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), bismuth (Bi), antimony (Sb), molybdenum (Mo) and ruthenium (Ru).

19. The IC structure of claim 1, wherein the IC structure is a three-dimensional integrated circuit (3DIC).

20. The IC structure of claim 1, wherein the IC structure is incorporated into a device selected from the group consisting of: a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, an Internet of Things (IoT) device, a laptop computer, a server, and a device in a motor vehicle.

21. A method of manufacturing an integrated circuit (IC) structure, the method comprising: forming a substrate; forming a front insulating member on the front surface of the substrate; forming a transistor on the substrate and in the front insulating member; forming one or more front metal layers in the front insulating member at a front side of the transistor, at least one front metal layer being electrically coupled to the transistor; as well as A through substrate via (TSV) is formed in the substrate and in the front side insulator, the TSV comprising: a front contact disposed in the front insulating member and electrically coupled to the front metal layer; and A back side contact is located in the substrate and is electrically coupled to the front side contact.

22. The method according to claim 21, wherein the TSV further comprises: A through-connection is located between the front contact and the back contact, the through-connection electrically coupling the front contact and the back contact.

23. The method of claim 22, wherein forming the transistor, forming the one or more front side metal layers, and forming the TSV comprises: providing a substrate handle and doped silicon on the substrate, the substrate being located on a front surface of the substrate handle, the front surface of the doped silicon being coplanar with the substrate; etching a trench in a shallow trench isolation (STI) region of the substrate, the trench exposing a portion of the front surface of the substrate handle; partially filling the trench with a trench insulator on the front surface of the substrate handle; filling a remaining portion of the trench with a first sacrificial trench fill; polishing the first sacrificial trench filling, wherein a front surface of the first sacrificial trench filling is coplanar with the front surface of the substrate; forming a gate oxide layer on the front surface of the substrate, the front surface of the first sacrificial trench fill, and the front surface of the doped silicon; forming a polysilicon layer on a front surface of the gate oxide layer; forming the transistor, the one or more front metal layers, the front contact, and the through-connector, wherein the polysilicon layer is replaced with the front insulator, the transistor, the one or more front metal layers, the front contact, and the through-connector, and wherein the first sacrificial trench fill in the trench is replaced with a second sacrificial trench fill; flipping the IC structure; removing the substrate handle, the trench insulator, and a portion of the substrate, wherein the second sacrificial trench fill is exposed; selectively etching the second sacrificial trench fill from the trench, wherein the through-connector is exposed within the trench; filling the trench with metal to form the back contact; as well as The back contact is polished, wherein a back surface of the back contact is coplanar with a back surface of the substrate.

24. The method according to claim 23, wherein the substrate handle is a silicon substrate, wherein the first sacrificial trench filler is a first doped polysilicon, wherein the polysilicon layer is a second doped polysilicon layer, wherein the second sacrificial trench filler is a third doped polysilicon, wherein the trench insulator is a dielectric, or Any combination of the above.

25. The method according to claim 22, wherein the front surface of the through connector is in physical contact with the back surface of the front contact, and Wherein a back surface of the through-connector is in physical contact with a front surface of the back contact.

26. The method according to claim 22, wherein the front contact is formed of one or more of: tungsten (W), copper (Cu), aluminum (Al), cobalt (Co), palladium (Pd), nickel (Ni), gold (Au), tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), bismuth (Bi), antimony (Sb), molybdenum (Mo), and ruthenium (Ru), wherein the back contact is formed of one or more of: W, Cu, Al, Co, Pd, Ni, Au, Ta, TaN, Ti, TiN, Bi, Sb, Mo and Ru, wherein the through connector is formed of silicide, or Any combination of the above.

27. The method of claim 21, the front contact having a width narrower than the back contact.

28. The method according to claim 21, further comprising: forming a back insulating member on a back surface of the substrate opposite to the front surface of the substrate; as well as forming one or more back metal layers in the back insulating member, The back contact is electrically coupled to the back metal layer.

29. The method of claim 28, wherein the back metal layer is in physical contact with the back contact.

30. The method of claim 28, wherein the back side contacts serve as alignment marks when forming the one or more back side metal layers.

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