Integrated electronic device and corresponding manufacturing method

Abstract

The invention relates to an integrated electronic device (1) comprising at least one component he interconnection trace (8), the component being manufactured on a carrier structure (2) comprising a semiconductor substrate, the interconnection trace (8) extending on the carrier structure from the component to a side face (9) of the device, the interconnection trace comprising a layer (12) of oxidizable material supporting a continuous layer (13) of electrically conductive material, the oxidizable material layer is discontinuous. The invention also relates to a method for manufacturing such a device.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, in particular to integrated circuits comprising one or more components connected to interconnect traces. The present invention is advantageously applicable to the field of integrated circuits made of III-V semiconductor materials.

[0002] In particular, the present invention relates to an integrated electronic device and a method of manufacturing such a device. Background Art

[0003] In the field of integrated circuits, taking as an example (without limitation) integrated circuits operating at microwave frequencies or MMICs (Monolithic Microwave Integrated Circuits), it is known practice to protect components manufactured on a substrate by encapsulating these components in a polymer material.

[0004] The input and output signals transmitted or received by these components pass through interconnect traces that extend from the components parallel to the substrate to the sides (or edges) of the integrated circuit along the component cutting lines, which are referred to as dicing streets by those skilled in the art. At this point, the interconnect traces are therefore exposed to the external environment of the component and may oxidize due to moisture.

[0005] Specifically, it has been found that oxidation originating from the component cut lines can migrate along the interconnect traces, possibly as far as the component. This migration of oxidation is significantly facilitated by the electric fields generated by the signals circulating on the traces, and has been particularly observed on the interconnect traces of the transistor drains of the final amplifier stage of the MMIC component.

[0006] This oxidation leads to delamination of the interconnect traces and, if it reaches the component, changes the semiconductor surface under the passivation layer at the interface with the interconnect traces, creating electron traps that are responsible for a drop in current density in the component. This significantly affects the performance of the component. Summary of the invention

[0007] To overcome the above disadvantages, a means for preventing oxidation from propagating along interconnect traces to the active areas of the component has been proposed.

[0008] According to one aspect of the present invention, an integrated electronic device is proposed, which includes at least one component, which is manufactured on a carrier structure including a semiconductor substrate, and an interconnect trace, which extends from the component to the side of the device on the carrier structure, and the interconnect trace includes an oxidizable material layer supporting a continuous layer of conductive material, wherein the oxidizable material layer is discontinuous.

[0009] The oxidizable portion has discontinuous interconnecting traces, which advantageously makes it possible to prevent oxidation of the sides from propagating towards the component.

[0010] According to one embodiment, the device includes a barrier structure disposed between a carrier structure and a portion of an interconnect trace, the barrier structure extending laterally from one edge of the interconnect trace to the other edge (to the interconnect trace) and having an upper face facing away from the carrier structure, the oxidizable material layer including a first portion extending on the upper face and at least a second portion extending along the interconnect trace upstream or downstream of the barrier structure, the second portion having no material continuity with the first portion.

[0011] A barrier structure placed between the carrier structure and the interconnect trace is a simple way to achieve a discontinuity in the oxidizable layer of the interconnect trace. Furthermore, this solution is compatible with conventional interconnect trace manufacturing methods.

[0012] According to one embodiment, the second portion extends partially between the carrier structure and the first portion; in other words, the first portion extends over the second portion.

[0013] According to one embodiment, the barrier structure has a lower face in contact with the carrier structure, the dimension of the lower face along the interconnect trace (ie considered in a plane normal to the substrate and parallel to the direction in which the interconnect trace extends) being smaller than or equal to the dimension of the upper face along the interconnect trace.

[0014] According to one embodiment, the barrier structure has a trapezoidal cross-section having a plane parallel to the extension direction of the interconnect trace and orthogonal to the substrate.

[0015] According to one embodiment, the blocking structure comprises or is made of a dielectric material or a polymer.

[0016] According to one embodiment, the thickness of the blocking structure is smaller than the thickness of the conductive material layer. Preferably, if the method of manufacturing the conductive material layer comprises manufacturing a conductive material sublayer (or adhesive layer), the thickness of the blocking structure is smaller than the thickness of the conductive material sublayer.

[0017] According to one embodiment, the blocking structure is fabricated at a distance greater than 200 microns from any feature positioned along the interconnect trace.

[0018] The component is manufactured using a III-V material.For example, an integrated circuit may include an active layer, the active layer including the component and manufactured by epitaxy of a III-V material.

[0019] The component may be an active component, such as a high electron mobility transistor.

[0020] According to another aspect, a method for producing an integrated electronic device is provided, the integrated electronic device comprising at least one component on a carrier structure, the carrier structure comprising a semiconductor substrate, the method comprising

[0021] - a step of producing a barrier structure on the carrier structure, the barrier structure having an upper face facing away from the carrier structure,

[0022] - a step of making interconnect traces extending from the component to the side of the device, the step comprising:

[0023] - a sub-step of producing a layer of oxidizable material comprising a first portion extending on the upper face and at least a second portion extending along the interconnect trace upstream or downstream of the barrier structure, such that the first portion does not have any material continuity with the second portion,

[0024] - A sub-step of producing a continuous layer of conductive material on the layer of oxidizable material, so as to form an interconnection track comprising the layer of oxidizable material and the layer of conductive material.

[0025] Naturally, the various features, variants and embodiments of the present invention can be combined with one another in various combinations, as long as they are not mutually exclusive or incompatible. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Furthermore, various other features of the present invention will become apparent from the accompanying description provided with reference to the accompanying drawings, which illustrate non-limiting embodiments of the present invention, in which:

[0027] [ Figure 1 ] is a top view of a device according to an embodiment of the present invention,

[0028] [ Figure 2 ]yes Figure 1 A cross-sectional view of the device in

[0029] [ Figure 3 ] shows the first step of the method for manufacturing a device according to the present invention,

[0030] [ Figure 4 ] is the second step of the method for manufacturing a device according to the present invention,

[0031] [ Figure 5 ] is the third step of the method for manufacturing the device according to the present invention,

[0032] [ Figure 6 ] is the fourth step of the method for manufacturing the device according to the present invention,

[0033] [ Figure 7 ] shows a variant embodiment of a device according to the invention,

[0034] Note that in these figures, structural and / or functional elements common to various variants may have the same reference numerals. DETAILED DESCRIPTION

[0035] It goes without saying that an integrated circuit can be oriented in different ways, particularly depending on the way in which the integrated circuit is integrated into an electronic device, and furthermore, an electronic device does not always have a specific orientation (or reference orientation). However, for the sake of simplifying the present disclosure, the reference orientation will be the orientation commonly used in the reference literature and most patent literature, i.e., the carrier substrate will be considered to be at the bottom, the side of the substrate on which the various layers and components of the integrated circuit are fabricated is generally referred to as the "front side", which will be considered to be the upper side of the substrate. Therefore, relative terms such as "above", "below", "upper", "lower", "side", "lower" and "upper" should be interpreted according to the reference orientation. This orientation is consistent with the present application Figures 2 to 7 The orientation is consistent.

[0036] Figure 1 is a schematic top view of an integrated electronic device 1, in this case a monolithic microwave integrated circuit (MMIC), in this example a high power amplifier. The integrated electronic device 1 is made of, for example, III-V semiconductor materials.

[0037] The integrated circuit 1 comprises a carrier structure 2 on which components and interconnection tracks are manufactured, and a protective layer, in this case made of a dielectric material, which is manufactured on the carrier structure 2 in such a way as to encapsulate the components and interconnection tracks. For greater clarity in the figures, the integrated circuit 1 is shown here without its protective layer.

[0038] In this case, the carrier structure 2 comprises a carrier substrate, for example made of silicon carbide SiC, sapphire, silicon Si or gallium nitride GaN, on which there is a heterojunction formed by a first layer of a wide bandgap material (for example gallium nitride GaN) and a second layer of a wider bandgap material (for example aluminum-gallium nitride AlGaN). A nucleation layer or buffer layer, for example comprising gallium nitride, is present between the carrier substrate and the first layer, making it possible to ensure the grid adaptability of the heterojunction grown on the carrier substrate. For the sake of simplicity, these layers will not be shown in the figure.

[0039] Components, in this case transistors, here in particular high electron mobility transistors (HEMTs), are manufactured on a carrier structure 2. In this case, these transistors belong to two radio frequency power amplifier stages 3, 4.

[0040] The device 1 also comprises interconnect traces extending from the side faces of the device 1 and electrically connected to the electrodes of the transistors of the two levels 3 and 4. Within the meaning of the present invention, the side faces of the device 1 are understood to be faces orthogonal to the front face of the substrate and corresponding to the cutting lines of the device 1 before its individualization.

[0041] In this case, a first interconnect trace 6 extends from a first side 7 of the device 1 towards the component to contact the gate lines of the transistors of the two stages 3 and 4. The first interconnect trace 6 forms an input electrode for the device 1 at the first side 7.

[0042] A second interconnect trace 8 extends from the second side 9 of the device 1 towards the component to contact the drains of the transistors of the two stages 3 and 4. The second interconnect trace 6 forms an output electrode for the device 1 at the second side 9.

[0043] The third interconnect trace connects the sources of the two-stage transistors to ground, for example, by an air bridge structure, or by connecting the various sources by a benzocyclobutene bridge structure, a BCB-bridge structure. For example, in this case the device 1 is a microstrip device, and the ground plane is made on the back side (or the lower side opposite to the front side) of the substrate. The bridge (air or BCB) is connected to the ground plane via a via.

[0044] The various passive components 5 enable in particular impedance matching on the interconnection tracks 6 and 8 .

[0045] In this case, the interconnection tracks 6 and 8 on the sides 7 and 9, respectively, are exposed to the environment outside the device 1, in particular to moisture, and thus the interconnection tracks 6 and 8 may oxidize. This risk is particularly high for the second interconnection track 8, which here forms the output terminal of the high power amplifier. The current density flowing therein is particularly high, and the electromagnetic field generated promotes oxidation migration along the second interconnection track 8 towards the second transistor level 4.

[0046] The device 1 comprises a barrier structure 11 close to the second side 9, which barrier structure 11 is able to prevent oxidation from migrating along the second interconnect trace 8. Preferably, the barrier structure 11 is located at a distance from the passive component 5 greater than 200 micrometers.

[0047] In this case, the barrier structure 11 is disposed between the carrier structure 2 and the second interconnection trace 8. Here, the barrier structure 11 extends from one edge of the second interconnection trace 8 to the other, laterally to the second interconnection trace 8 and in particular in this case beyond the edge of the second interconnection trace 8.

[0048] The blocking structure 11 can be Figure 2 More clearly seen in Figure 2 It is along Figure 1 sectional view of the electronic device 1 along the section line II in FIG.

[0049] The barrier structure 11 has a first face 14 or lower face in contact with the carrier structure 2, and a second face 15 or upper face opposite to the first face and the carrier structure 2. The dimension of the first face 14 along the interconnection trace (i.e. considered parallel to the upper face of the carrier structure and in a plane parallel to the extension direction of the interconnection trace, in this case a plane parallel to the cross-sectional plane II) is smaller than or equal to the dimension of the second face 15 along the interconnection trace (i.e. considered in the same plane). The cross section of the carrier structure 2 (here also in a plane parallel to the cross-sectional plane II) is called an "undercut" (according to the usual terminology).

[0050] Specifically, in this case, the cross section of the carrier structure 2 in a plane parallel to the cross-sectional plane II is a trapezoid. The first base of the trapezoid formed by the cross section belongs to the first face 14, and the second base of the trapezoid belongs to the second face 15. The length of the first base is smaller than the length of the second base, and in this example, the trapezoid is an isosceles trapezoid.

[0051] In this case, the blocking structure 11 is made of a dielectric material.

[0052] The second interconnect trace 8 comprises at least two layers, including an oxidizable material layer 12 and a conductive material layer 13. In this case, the oxidizable material layer 12 is a supporting layer or adhesive layer, which supports the conductive material layer 13 and allows it to adhere better to the carrier structure 2.

[0053] In this case, the layer 12 of oxidizable material is a titanium-based alloy layer, here an alloy of titanium and tungsten, and is produced directly on the carrier structure 2. The layer 13 of electrically conductive material is in this case a gold layer.

[0054] In this case, the thickness of the barrier structure 11 (the distance between the first face 14 and the second face 15) is greater than the thickness of the oxidizable material layer 12, and much smaller than the thickness of the conductive material layer 13. The barrier structure 11 has a thickness of, for example, 60 nanometers to 80 nanometers, the oxidizable material layer 12 has a thickness of, for example, 20 nanometers to 30 nanometers, and the conductive material layer 13 has a thickness of, for example, equal to or greater than 1 micrometer (or even equal to or greater than 5 micrometers).

[0055] The oxidizable material layer 12 is discontinuous; in this case, the oxidizable material layer 12 comprises three parts. A first part 16 is located on the second face 15 of the barrier structure, and a second part 17 and a third part 18 are located on the carrier structure 2, respectively upstream and downstream along the interconnect trace (relative to the propagation direction of the signal).

[0056] As described above, the dimension of the second face 15 along the interconnect trace (i.e., here in a plane parallel to the section II) is greater than the dimension of the first face 14 along the interconnect trace. Therefore, the first portion 16 extends partially above the second portion 17 and partially above the third portion 18. In other words, the first portion 16 extends at a distance from the carrier structure 2, and a portion of the second portion 17 and a portion of the second portion 18 are placed (not in direct contact) between the first portion 16 and the substrate. More specifically, the ends of the second portion 17 and the third portion 18 extend between the carrier structure 2 and the ends of the first portion 16.

[0057] Taking into account the difference in thickness between the support structure 11 and the oxidizable material layer 12 , the first portion 16 is discontinuous with the second portion 17 and the third portion 18 (which themselves are not continuous with each other because they are separated by the barrier structure 11 ).

[0058] In contrast, the continuity of the conductive material layer 13 is not affected by the presence of the barrier structure 11 , since the thickness of the conductive material layer 13 is greater than the thickness of the barrier structure 11 .

[0059] Therefore, the barrier structure 11 can advantageously disrupt the continuity of the oxidizable material layer 12 without disrupting the continuity of the conductive material layer 13. Thus, electrical connection to the component is ensured. In addition, the barrier structure 11 does not affect the mechanical integrity of the second interconnect trace, because the conductive material layer 13 is well supported by the oxidizable material trace 12 over its entire length.

[0060] Figures 3 to 6 An integrated device (eg Figure 1 and Figure 2 The various steps of the manufacturing method of the device shown in FIG.

[0061] In manufacturing the device according to the present invention ( Figure 3 In a first step of the process of manufacturing the barrier structure 11 on the carrier structure 2, for example by depositing a layer of dielectric material, in particular a resin, on the carrier structure 2 and then defining the barrier structure 11 in the resin layer by photolithography and impregnation. The technique for manufacturing a cross section, in particular a trapezoidal cross section, called "undercut" for the barrier structure 11 will not be described in more detail here, since the technique itself is conventional and known. It is mainly used in methods for metal deposition by removal of layers (or generally known "lift-off" methods).

[0062] The second step of the method includes fabricating interconnect traces.

[0063] The first sub-step of making interconnect traces ( Figure 4 ) comprises depositing a layer 12' of an oxidizable material on the carrier structure 2 and the barrier structure 11 by sputtering.

[0064] The second sub-step ( Figure 5 ) comprises part of the manufacture of the layer of conductive material 13 and comprises depositing by sputtering a first sub-layer of conductive material 13', in this case gold, on the layer of oxidizable material. The third sub-step ( Figure 6 ) comprises another part of the manufacture of the conductive material layer 13 and comprises the electrolytic growth of a second sublayer 13″ of conductive material, in this case gold, on the oxidizable material layer 12′. Manufacturing the first sublayer 13′ by sputtering allows a uniform growth of the second sublayer 13″ and thus improves the adhesion of the conductive material to the oxidizable material layer 12′. In this example, the first sublayer 13′ has a thickness of 100 nanometers and the second sublayer 13″ has a thickness of 6 micrometers.

[0065] In a fourth sub-step (not shown), the conductive tracks of the device 1 , in particular the tracks 6 and 7 , are defined (or defined) in these three layers by photolithography and dipping.

[0066] Thus, the second interconnect trace 8 is manufactured by conventional methods, but advantageously comprises a discontinuity in the layer of oxidizable material 12 caused by the presence of the barrier structure 11 .

[0067] The present invention is not limited to the above combination Figure 1 and 2 In particular, although a trapezoidal cross-section barrier structure has been described, other shapes are also conceivable, such as a T-shape or an inverted platform shape, such as Figure 7 As shown, the barrier structure 11 comprises a first portion 19 of rectangular shape in contact with the substrate and a second portion 20 of rectangular shape, the second portion 20 being manufactured on the first parallelepiped portion 19 and having a dimension along the interconnection trace greater than the dimension along the interconnection trace of the first parallelepiped portion 19. Such a profile is obtained, for example, by a double layer of resin, each sub-layer having a different development speed (in this case, the layer in contact with the carrier structure 2 has a higher development speed).

[0068] More generally, the present invention is applicable to any device having an undercut profile (i.e., Figure 1 The blocking structure is compatible with the cross-sectional plane II (cross-sectional plane in the plane).

[0069] Furthermore, the invention is particularly advantageously applicable in the field of integrated circuits comprising III-V semiconductors and in the field of monolithic microwave integrated circuits. However, the invention is not limited to these applications and is compatible with any integrated circuit comprising interconnect traces comprising two layers, one of which is susceptible to oxidation.

[0070] Herein, a barrier structure 11 has been described which is manufactured at a distance from the second side 9 (the dicing line) of the integrated device 1. The invention also covers embodiments in which the barrier structure 11 is flush with the second side 9. Thus, the first portion 16 of the layer of oxidizable material extends to the second side 9, and the layer of oxidizable material 12 has no third portion but only a second portion extending upstream of the barrier structure, in other words, between the component and the barrier structure 11.

[0071] Finally, the present invention is not limited to embodiments comprising only one barrier structure, and encompasses embodiments comprising a plurality of barrier structures, for example, as many barrier structures as interconnect traces that may be oxidized.

[0072] Various other modifications may be made to the invention within the scope of the appended claims.

Claims

1. An integrated electronic device comprising at least one component and an interconnection trace (8), the component being manufactured on a carrier structure (2) comprising a semiconductor substrate, the interconnection trace (8) extending on the carrier structure from the component to a side (9) of the device (1), the interconnection trace (8) comprising a layer (12) of oxidizable material supporting a continuous layer (13) of conductive material, It is characterized in that The oxidizable material layer (12) is discontinuous.

2. A device as claimed in claim 1, comprising a barrier structure (11), the barrier structure (11) being interposed between the carrier structure (12) and a portion of the interconnection trace (8), the barrier structure (11) extending laterally from one edge of the interconnection trace to the other edge and having an upper face (15) facing away from the carrier structure (2), the oxidizable material layer comprising a first portion (16) extending on the upper face (15), and at least a second portion (17, 18) extending along the interconnection trace upstream or downstream of the barrier structure (11), the second portion (17, 18) having no material continuity with the first portion (16).

3. The integrated electronic device of claim 2, wherein: The second portion (17, 18) extends partially between the carrier structure (2) and the first portion (16).

4. The integrated electronic device according to claim 2 or 3, wherein: The barrier structure (11) has a lower face (14) in contact with the carrier structure (2), the dimension of the lower face (14) along the interconnection trace being smaller than or equal to the dimension of the upper face (15) along the interconnection trace.

5. The electronic device according to any one of claims 2 to 4, wherein: The barrier structure (11) has a trapezoidal cross section having a plane (II) parallel to the extension direction of the interconnect trace (8) and orthogonal to the substrate.

6. The integrated electronic device according to any one of claims 2 to 5, wherein: The barrier structure (11) comprises a dielectric material or a polymer.

7. The integrated electronic device according to any one of claims 2 to 6, wherein: The thickness of the blocking structure (11) is smaller than the thickness of the conductive material layer (13).

8. The integrated electronic device according to any one of claims 2 to 7, wherein: The blocking structure (11) is fabricated at a distance greater than 200 microns from any component (4, 5) located along the interconnect trace (8).

9. The integrated electronic device according to any one of claims 1 to 8, wherein: The components and the substrate are manufactured using III-V materials.

10. The integrated electronic device according to any one of claims 1 to 9, wherein: The component is a high electron mobility transistor.

11. A method for manufacturing an integrated electronic device (1), the integrated electronic device (1) comprising at least one component on a carrier structure (2), the carrier structure comprising a semiconductor substrate, the method comprising - a step of producing a blocking structure (11) on the carrier structure, the blocking structure having an upper face (15) facing away from the carrier structure, - a step of making interconnect traces (8) extending from the component to the side surfaces (9) of the device, the step comprising: - a sub-step of producing a layer (12) of oxidizable material comprising a first portion (16) extending on said upper face (15) and at least a second portion (17, 18) extending along said interconnection trace (8) upstream or downstream of said barrier structure (11), such that said first portion (16) does not have any material continuity with said second portion (17, 18), - A sub-step of producing a continuous layer (13) of electrically conductive material on said layer (12) of oxidizable material.

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