Current limiter circuit with adjustable response time

Abstract

A current limiter (104) includes a gain adjustment circuit (208) designed to vary a response time (e.g., mode of operation) of the current limiter. The current limiter may be designed to operate in different selectable speed modes (e.g., slow speed mode, fast speed mode) that affect the degree of quickness to which the current limiter responds to an over-current stimulus. The speed mode may be selected by selecting between different current mirror arrangements in the gain adjustment circuit. An acceleration circuit (210) including a switch (M5) to initiate a non-linear acceleration of the response time upon receipt of a certain overcurrent stimulus may also be implemented regardless of which mode of operation is selected for the current limiter.

Description

Technical Field

[0001] The present description relates to overcurrent protection in circuits, and more particularly, to current limiter circuits with tunable response times. Background Art

[0002] For example, when a given power rail is connected to a load via an external port or some other component, protection against voltage drops on the rail is an issue. In some cases, current limiting circuits are used to prevent the potential on the rail from deteriorating when a faulty load is applied. The response time of the current limiting circuit is typically very fast in order to limit the amount of power drop during, for example, a hard fault condition. However, an overly fast current limiting circuit may not be able to restore normal operation after certain transient soft fault conditions or other transient events that may cause the output current to rise above the current limit value. There are still many important issues in developing current limiter circuits. Summary of the invention

[0003] A current limiter is described that includes a gain adjustment circuit designed to change the response time (e.g., operating mode) of the current limiter. According to some embodiments, a given speed mode of the current limiter can be implemented based on a circuit layout of various transistors, and different sets of transistors can be selected to select between different speed modes.

[0004] An example current limiter includes: a gain stage; and a power switch having a control terminal and a current output, and configured to control a current at the current output in response to a signal at the control terminal. The gain stage includes: an amplifier having an amplifier output and a first amplifier input and a second amplifier input, wherein the first amplifier input is coupled to the current output and the second amplifier input is coupled to a reference terminal; a first current mirror; a first switch coupled between the first current mirror and the control terminal of the power switch; a second current mirror; and a second switch coupled between the second current mirror and the control terminal of the power switch. The first current mirror is configured to pull down a current from the control terminal of the power switch at a first rate in response to the first switch closing, and the second current mirror is configured to pull down a current from the control terminal of the power switch at a second rate in response to the second switch closing. The second rate is different from the first rate.

[0005] In some embodiments, the current limiter further includes a speed adjustment circuit having at least a resistor and a switch. The resistor is coupled between a control terminal of the power switch and an output of the gain stage, and the switch has a first terminal coupled to the control terminal of the power switch and a second terminal coupled to the output of the current limiter.

[0006] In another example, a printed circuit board (PCB) includes: a current limiter coupled to a power terminal and having a power output; and a peripheral output port coupled to the power output. The current limiter includes a gain stage and a power switch having a control terminal and a current output coupled to the power output, wherein the power switch is configured to control a current applied to the power output in response to a signal at the control terminal. The gain stage includes: an amplifier having an amplifier output and a first amplifier input and a second amplifier input, wherein the first amplifier input is coupled to the current output and the second amplifier input is coupled to a reference terminal; a first current mirror; a first switch coupled between the first current mirror and the control terminal of the power switch; a second current mirror; and a second switch coupled between the second current mirror and the control terminal of the power switch. The first current mirror is configured to pull down a current from the control terminal of the power switch at a first rate in response to the first switch closing, and the second current mirror is configured to pull down a current from the control terminal of the power switch at a second rate in response to the second switch closing. The second rate is different from the first rate.

[0007] In another example, a circuit includes a power switch, an amplifier, a first field effect transistor (FET) and a second field effect transistor (FET) having a first current mirror arrangement, and a third field effect transistor (FET) and a fourth field effect transistor (FET) having a second current mirror arrangement. The power switch has a first terminal or node, a second terminal or node, and a control terminal. The amplifier has an output and a first input and a second input, wherein the first input is coupled to the first terminal of the power switch and the second input is coupled to a reference voltage terminal. The first terminal of the first FET is coupled to the output of the amplifier via a first switch, and the first terminal of the second FET is coupled to the current mirror output. The first terminal of the third FET is coupled to the output of the amplifier via a second switch, and the first terminal of the fourth FET is coupled to the current mirror output. The W / L ratio between the first FET and the second FET is different from the W / L ratio between the third FET and the fourth FET. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a block diagram of an electrical device or system including a current limiter in an example.

[0009] Figure 2 is a block diagram of the current limiter in the example.

[0010] Figure 3 For example Figure 2 Schematic diagram of the current limiter.

[0011] Figure 4A For example Figure 2 Schematic diagram of a portion of a current limiter.

[0012] Figure 4B For another example Figure 2 Block diagram of a portion of a current limiter.

[0013] Figure 5 Graph showing different gain bandwidth (GBW) products for different operating modes of a current limiter in an example.

[0014] Figure 6 is a graph showing the response time of various operating modes of a current limiter having a non-linear acceleration response in an example. DETAILED DESCRIPTION

[0015] A current limiter is described that includes a gain adjustment circuit designed to change the response time (e.g., operating mode) of the current limiter. In some embodiments, the current limiter also includes an acceleration circuit designed to cause a relatively rapid reduction in rail current regardless of the operating mode of the current limiter. According to some embodiments, the current limiter can be designed to operate in different speed modes that affect how quickly the current limiter responds to an overcurrent stimulus. For example, in a slow mode, the current limiter can have a slower response time for lower overcurrent stimuli to withstand transients that may occur. In a fast mode, the current limiter can react quickly to even low overcurrent stimuli to pull down the rail current. Regardless of which operating mode is selected for the current limiter, the acceleration circuit can include a switch to enable a nonlinear acceleration of the response time after receiving a certain overcurrent stimulus. According to some embodiments, a given speed mode can be implemented based on a circuit layout of various transistors (e.g., based on transistor sizing, as further described below), and different groups of transistors can be selected to select between different speed modes.

[0016] General Overview

[0017] As described above, a number of important issues are associated with developing current limiters. For example, the response time of the current limiter circuit to different overcurrent stimuli (e.g., rail current amplitudes above a reference current amplitude) dictates how quickly the circuit can prevent high rail currents from damaging a connected load, or the ability of the current limiter to not react too quickly to transient changes in rail current. Current limiter circuits are designed to operate in one mode or another. For example, a current limiter circuit may be designed to react very quickly to any overcurrent stimulus, which may provide a high level of safety, but may be more likely to unnecessarily degrade the rail current. In contrast, a current limiter designed to react more slowly may be able to withstand transient situations that do not require a rail current to be pulled down, but may be more susceptible to current spikes that damage the load or power supply.

[0018] Thus, described herein is a current limiter that can operate in any of a variety of different response modes. In an example, one or more power switches (e.g., power field effect transistors or FETs) can be used to regulate the rail current, and an amplifier is used to compare the rail current to a reference current. If the rail current rises above the reference current, the output of the amplifier activates a current mirror to produce a current that helps pull down the rail current. According to some embodiments, the size ratio between the FETs of the current mirror determines the operating mode of the current limiter (e.g., whether it responds quickly or slowly to an overcurrent stimulus). In some examples, different groups of FETs can be used to form various current mirrors (e.g., a first group of FETs can be used for a fast operating mode, and a second group of FETs can be used for a slow operating mode, and a third group of FETs can be used for an intermediate operating mode). According to some such embodiments, one of the current mirrors can be selected to pick the operating mode of the current limiter.

[0019] In some embodiments, the current limiter includes an acceleration circuit that can provide a rapid increase in circuit response time even when the current limiter is operating in a slower mode. The output of a gain stage including various current mirrors is coupled to the acceleration circuit, which includes a resistor in a current path between the gain stage output and one or more power switches to allow a selected one of the current mirrors to pull down a control terminal of the power switch and thereby regulate the rail current. According to some embodiments, the acceleration circuit also includes an acceleration switch coupled to the rail. If there is a sufficiently high overcurrent stimulus, the acceleration switch can be activated. Activating the acceleration switch provides a path for the selected current mirror to limit the rail current very quickly. According to some embodiments, the acceleration circuit maintains circuit protection against large overcurrent transients while allowing a slower operating mode to withstand transients. Although the embodiments herein are described with reference to a current limiter for regulating rail current, such embodiments may also be applicable to any electronic device using any type of current regulation.

[0020] Electronic device or system

[0021] Figure 1 At least a portion of an example electronic device or system 100 is illustrated having a power supply 102 and a current limiter 104. In some embodiments, a load 106 (or load circuit) is part of or coupled to the electronic device or system 100. In some cases, the electronic device or system 100 is implemented as a system on a chip, or a chipset populated on a printed circuit board (PCB), which in turn may be populated into a chassis of a multi-chassis system or other higher-level system, although any number of implementations may be used.

[0022] The power supply 102 may represent any type or number of current and / or voltage generators. In some embodiments, the power supply 102 generates a rail voltage (e.g., VDD, VCC, or HVDD) for powering any number of integrated circuits. According to some embodiments, the supplied current may be regulated by the current limiter 104. As further described below, the current limiter 104 may be designed to operate in any number of different speed modes (relative to the current limit response time) to limit the rail current when the rail current rises above a threshold, and to limit the rail current very quickly when the rail current rises above a higher threshold. In this way, the current limiter circuit may have a tunable nonlinear response time. The current limiter 104 may be provided to protect the load 106, the power supply 102, and / or any other circuit connected to the power supply 102 from receiving a dangerously high or otherwise excessive rail current.

[0023] According to some embodiments, the power supply 102 and the current limiter 104 may be disposed together on a PCB 108. In the illustrated example, the load 106 is coupled to the PCB 108 via an output port 110 to receive power and possibly other data signals from various devices on the PCB 108. The output port 110 may be a dedicated output voltage port, or any other port that can pass an output voltage to a peripheral device, such as a serial port, a parallel port, a USB port, or an HDMI port, to name a few examples, and is coupled to an output power line or terminal (or more generally, a power output) of the current limiter 104. In some other examples, the load 106 is included on the PCB 108. The load 106 may represent another circuit or another device that receives at least the rail power that has passed through the current limiter 104.

[0024] Current Limiter Design

[0025] Figure 2A more detailed diagram illustrating a current limiter 104 according to some embodiments. A conductive power rail 202 carries current from the power source 102 to the load 106. In this example, the power rail 202 is shown as a straight conductive run (e.g., copper or other suitable metal conductor), but it may have any number of configurations capable of carrying current from the power source 102 to the load 106. The current on the power rail 202 may be regulated via a power switch 204 in coordination with an amplifier 206, a gain adjustment circuit 208, and an acceleration circuit 210. Current regulation may involve reducing the current on the power rail 202 if the current rises above a given threshold, and strongly pulling down the current magnitude if the current magnitude rises significantly above a given threshold (or above a second, higher threshold). Such staggered or graded over-current threshold techniques may be used to distinguish between temporary or relatively transient over-current conditions that may be safely tolerated without causing any damage to the overall system, and more severe fault mode-based over-current conditions that require a fast current limit response time.

[0026] Power switch 204 may represent any number of switches along rail 202. In some embodiments, power switch 204 comprises a power FET, wherein the rail current is configured to flow through a source and a drain of the power FET.

[0027] The rail current on rail 202 is sampled at a first input of amplifier 206, where it can be compared to a reference current (REF) received at a second input of amplifier 206. The reference current (REF) can be predetermined, for example, based on a given application or type of load 106. A low reference current (REF) causes the current limiter 104 to react to an overcurrent exceeding a low reference threshold, while a higher reference current (REF) causes the current limiter 104 to react to an overcurrent exceeding a higher threshold. In some instances, the reference current (REF) is fixed, while in other instances, the reference current (REF) can be adjusted by a user, or by an automatic process that dynamically determines an appropriate reference current. Amplifier 206 can include one or more operational amplifiers arranged as a transconductance amplifier with a gain gm (e.g., a voltage input with a current output). Any number of amplifiers and / or comparator circuits capable of comparing a current or voltage to a given threshold current or voltage can be used.

[0028] According to some embodiments, the output of amplifier 206 is coupled to a gain adjustment circuit 208. One or more current mirrors may be used within the gain adjustment circuit 208 to reduce the current by a given ratio determined by the size difference between the FETs of the one or more current mirrors. According to some embodiments, a current mirror is selected from a plurality of current mirrors within the gain adjustment circuit 208. The operating mode of the current limiter 104 (e.g., fast mode, slow mode, or any intermediate mode) may be determined based on which current mirror is selected. According to some embodiments, each current mirror includes a different gain adjustment factor (e.g., current ratio) based on the size difference between the FETs used in the current mirrors. An example gain adjustment circuit 208 includes a first current mirror for a fast mode and a second current mirror for a slow mode. In one such case, the gain adjustment circuit 208 includes a third current mirror for an intermediate mode (having a response time between the fast mode and the slow mode).

[0029] According to some embodiments, the speed-up circuit 210 is coupled to the output of the gain adjustment circuit 208. The speed-up circuit 210 can be configured to control the process of pulling down the current from the gate (or more generally, the control terminal) of the power switch 204 (e.g., using the mirror current from the gain adjustment circuit 208) to ultimately reduce the rail current. In some examples, the rail current can be reduced below the REF current to dynamically disable the gain adjustment circuit 208. The speed at which this occurs can be affected by the size ratio between the FETs in the selected current mirror of the gain adjustment circuit 208.

[0030] According to some embodiments, the speed-up circuit 210 includes a speed-up switch designed to activate if the pull-down current from the gain adjustment circuit 208 is too large (e.g., above a second threshold higher than REF). According to some examples, activation of the speed-up switch directly disconnects the path to the rail 202, allowing the power switch 204 to be quickly disabled and the rail current to be pulled down to a low level very quickly. The speed-up switch can be implemented, for example, using a single FET or as its own circuit with any number of FETs.

[0031] Figure 3 An example circuit diagram of the current limiter 104 is shown. Figure 3 Other elements than those described in can be included as part of the current limiter 104, such as various buffers, resistors, and / or capacitors. In addition, any of the described elements can be implemented in a variety of different ways to achieve similar outputs or functions.

[0032] According to some embodiments, the first voltage source 302 provides a rail voltage and an associated current on the power rail PPV. For some example applications, the PPV is set to a voltage amplitude of about 5 volts, but any voltage may be used, including low, medium, and high voltages. One or more power switches (e.g., power FETs M1 and M2) are provided on the rail and regulate the rail current that is ultimately output on VBUS (and may be connected to a load 106). The second voltage source 304 may be provided with any number of charge pumps (e.g., charge pumps 306a and 306b) to bias the gates of the power FETs M1 and M2 and activate each of the power FETs M1 and M2. In some examples, an equal number of charge pumps 306a and 306b (e.g., one variable pump coupled to the gate of one power switch) is provided for an equal number of power switches. In some embodiments, the power FET M1 may be replaced by any current sensing element, such as a resistor.

[0033] As further described below, the gate potential of the power FET M2 may be modulated or otherwise affected by the gain adjustment circuit 208 and the speed-up circuit 210, thereby regulating the rail current on VBUS. In some embodiments, the rail current is sampled at a location between one or more power switches on the rail (e.g., between the power FETs M1 and M2) and fed to a first input of the amplifier 208. A reference source 308 may be used to generate a reference current (or threshold current) that is fed to a second input of the amplifier 206. As described above, the reference source 308 may be a fixed source to provide a fixed reference current at a reference terminal, or it may be dynamically configurable.

[0034] According to some embodiments, the output of amplifier 206 is fed to gain adjustment circuit 208. For example, the output of amplifier 206 may be received by a current mirror selected from a plurality of current mirrors. For clarity, the illustrated example uses a single current mirror, but the description extends equally to any number of other current mirrors. In response to the rail current being less than (or equal to) the reference current, the output of amplifier 206 does not enable FETs M3 and M4 that form a given current mirror arrangement within gain adjustment circuit 208. However, in response to the rail current rising above the reference current, a current is provided output from amplifier 206 that is proportional to the difference between the rail current and the reference current (multiplied by the gain factor gm). The difference between the rail current and the reference current may be referred to as an overcurrent stimulus or simply an overcurrent.

[0035] According to some embodiments, FETs M3 and M4 have a current mirror arrangement, wherein the gates of FETs M3 and M4 are coupled together, the source nodes of FETs M3 and M4 are coupled together, and the drain node of FET M3 is coupled to the gates of both FETs M3 and M4. The ratio of the drain current through FET M3 and the drain current through FET M4 is proportional to the size ratio of FETs M3 and M4 (e.g., the width / length ratio of the semiconductor channels). Thus, according to some embodiments, the amount of gain adjustment that occurs within the gain adjustment circuit 208 depends on the size ratio between FETs M3 and M4. A relatively large difference in the size ratio (e.g., W / L of M4 to W / L of M3) produces a larger drain current through FET M4 and a faster pull-down of the rail current (e.g., a fast mode). In contrast, a relatively small or zero difference in the size ratio (e.g., W / L of M4 to W / L of M3) produces a smaller drain current through FET M4 and a slower pull-down of the rail current (e.g., a slow mode). In the case of only a single current mirror arrangement, the current limiter 104 operates in only one mode (eg, a slow mode, a fast mode, or some intermediate mode). However, according to some embodiments and as described in reference Figure 4A and 4B Describing in more detail, a particular current mirror may be selected from among more than one current mirror within the gain adjustment circuit 208 to select between different speed modes.

[0036] According to some embodiments, regardless of the mode in which the current limiter 104 operates, the current through the FET M4 also passes through the speed-up circuit 210. The speed-up circuit 210 includes a speed-up switch M5 and one or more other elements coupled between the gate of the speed-up switch M5 and the source terminal or node of the speed-up switch M5. In this example, the speed-up switch M5 is implemented as a p-channel FET. According to some embodiments, the speed-up circuit 210 includes a diode 310 coupled between the gate of the speed-up switch M5 and the gate of the power switch M2 (which is the same node as the source node of the speed-up switch M5 in this example). The diode 310 can be used to provide circuit protection in the event that very high current is drawn through the mirror FET M4, and can be optional in some implementations. According to some embodiments, the speed-up circuit 210 includes a resistor 312 coupled between the gate of the speed-up switch M5 and the gate of the power FET M2. The resistor 312 provides a dissipative element across the current path between the gate of the power FET M2 and the drain node of the mirror FET M4 (part of the current mirror). Therefore, the current generated across mirror FET M4 pulls down the gate of power FET M2 to regulate the rail current on VBUS.In some examples, a feedback loop is created to regulate the rail current on VBUS by balancing the current through resistor 312 with the current fed from charge pump 306b.

[0037] According to some embodiments, the acceleration switch M5 is coupled to VBUS. For example, the drain node of the acceleration switch M5 can be coupled to VBUS to provide a current pull-down path that bypasses the power FET M2 when the acceleration switch M5 is activated. According to some embodiments, the acceleration switch M5 is activated when the overcurrent stimulus is high enough, and the pull-down current through the mirror FET M4 correspondingly pulls the gate of the acceleration switch M5 down enough to activate the acceleration switch M5. For example, in response to the pull-down current (I PD ) and the resistance (R 312 ) is equal to or greater than the threshold voltage (V T_M5 )(For example, I PD *R 312 =>V T_M5 ), the acceleration switch M5 turns on and quickly discharges the gate to the source. When this occurs, the rail current on VBUS can be pulled down very quickly from the current passing through the mirror FET M4 and also passing through the acceleration switch M5. In some examples, the overcurrent stimulus that causes the activation of the acceleration switch M5 can be considered a second current threshold (e.g., a rail current amplitude that is higher than the reference current that causes the activation of the acceleration switch M5). According to some embodiments, the acceleration switch M5 can be used to cause a fast pull-down of the rail current regardless of the operating speed of the current limiter 104 (e.g., regardless of the size ratio used between the FETs M3 and M4). In this way, a slow operating mode can be used while still having the ability to quickly pull down current via the acceleration switch M5 if necessary.

[0038] The illustrated FETs may be shown as either n-channel (NFET) or p-channel (PFET) devices, but either n-channel or p-channel devices may be used to perform similar functions with some associated reconfiguration of the circuit layout. Similarly, any designation of a source node for a given transistor may also refer to a drain node, and vice versa, depending on the transistor channel type. Although FET devices are used in these examples, in some embodiments, any number of bipolar junction transistors (BJTs) may be used in place of FET devices.

[0039] As described above, the gain adjustment circuit 208 may include more than one current mirror arrangement to allow for multiple operating mode speeds. Figure 4AAn example circuit diagram illustrating at least a portion of a gain adjustment circuit 208 having two different current mirror arrangements according to some embodiments. An amplifier output is received by a first current mirror arrangement 402 and a second current mirror arrangement 404. Although only two current mirror arrangements are shown, one for a relatively fast or first mode of operation and one for a relatively slow or second mode of operation, any number of additional current mirrors may be coupled to the amplifier output in a similar manner (e.g., similar to current mirror arrangement 404) to provide one or more intermediate modes of operation having response times between the respective response times attributable to the fast and slow modes of operation. The current limiter response times between any two current mirror arrangements may be considered different if, for example, the response times differ by at least 10%, at least 15%, at least 20%, or at least 25%. Other examples may have current limiter response times that are closer together but still considered meaningfully different (e.g., at least 5% different) for a given application and process. More generally, any number of current limiter response times that are purposefully configured to differ from one another may be used.

[0040] According to some embodiments, the first current mirror arrangement 402 includes mirror FETs M7 and M8, and the second current mirror arrangement 404 includes mirror FETs M9 and M10. As further shown, the first current mirror arrangement 402 includes select FETs M11 and M12, and the second current mirror arrangement 404 includes select FETs M13 and M14. In some embodiments, activation FET M6 provides an activation path for the gates of mirror FETs M7 and M8, and activation FET M15 provides an activation path for the gates of mirror FETs M9 and M10. The first terminal of mirror FET M7 can be considered to be coupled to the amplifier output via select FET M11, and the first terminal of mirror FET M9 can be considered to be coupled to the amplifier output via select FET M13. Furthermore, the first terminal of mirror FET M8 can be considered to be coupled to the output of gain adjustment circuit 208 via select FET M12, and the first terminal of mirror FET M10 can be considered to be coupled to the output of gain adjustment circuit 208 via select FET M14.

[0041] According to some embodiments, the switch inputs (A and B) are used to determine which current mirror arrangement is active at a given time. The number of switch inputs may be equal to the number of current mirror arrangements so that each of the current mirror arrangements is addressed individually. According to some embodiments, the switch inputs are used to activate one or more select FETs of a given current mirror arrangement. In the illustrated example, switch input A is used to activate the gates of select FETs M11 and M12 of the first current mirror arrangement 402, and switch input B is used to activate the gates of select FETs M13 and M14 of the second current mirror arrangement 404.

[0042] Focusing on the first current mirror arrangement 402, the switch input A can be asserted to activate the select FETs M11 and M12, thereby allowing the current received from the amplifier output to flow through the current mirror FET M7. The first current mirror arrangement 402 causes a proportional current to flow through the current mirror FET M8 based on the size ratio between the FETs M7 and M8. The current flowing through the FET M8 acts as a pull-down current to reduce the rail current via the acceleration circuit 210. In some embodiments, the pull-down current through the FET M8 also passes through the FET M16, which acts as a buffer between the various current mirror arrangements and the acceleration circuit 210. When the first current mirror arrangement 402 is active, the second current mirror arrangement 404 is not active because the gates of the select FETs M13 and M14 are held low by the unasserted switch input B.

[0043] Focusing on the second current mirror arrangement 404, the switch input B can be asserted to activate the select FETs M13 and M14, thereby allowing the current received from the amplifier output to flow through the FET M9. In some embodiments, the switch input B also activates the gate of the activation FET M15 to provide an activation path to the gates of the FETs M9 and M10. The second current mirror arrangement 404 causes a proportional current to flow through the FET M10 based on the size ratio between the FETs M9 and M10. The current flowing through the FET M10 acts as a pull-down current to reduce the rail current via the acceleration circuit 210. In some embodiments, the pull-down current through the FET M10 also passes through the FET M16, which acts as a buffer between the various current mirror arrangements and the acceleration circuit 210. When the second current mirror arrangement 404 is active, the first current mirror arrangement 402 is not active because the gates of the select FETs M11 and M12 are held low by the unasserted switch input A.

[0044] According to some embodiments, the size ratio between FETs M7 and M8 is different from the size ratio between FETs M9 and M10 to provide two different speed operating modes. The size ratio between any two current mirror arrangements may be considered different if, for example, the size ratios differ by at least 10%, at least 15%, at least 20%, or at least 25%. Other examples may have current mirror size ratios that are closer together but still considered meaningfully different (e.g., at least 5% different) for a given application and process. More generally, any number of current mirror size ratios that are purposefully configured to be different from each other may be used. In an example, the size ratio between FETs M7 and M8 may be selected to provide a low pull-down current through M8, thereby producing a relatively slow operating mode (e.g., a slower pull-down on the rail current), while the size ratio between FETs M9 and M10 may be selected to provide a higher pull-down current through FET M10, thereby producing a relatively fast operating mode (e.g., a faster pull-down on the rail current). Any number of different speed modes may be selected by providing an equal number of different current mirror arrangements. A particular current mirror arrangement may then be selected from among the different current mirror arrangements via a switch input.

[0045] In some instances, the switch input may be manually provided or otherwise set by a user, while in other instances, the switch input may be provided or otherwise set by a processor that is programmed or otherwise configured to select a response time based on parameters of a given application and / or input from a user. In some cases, a 3 to 8 row decoder is used to provide the switch input. In one such example case, three input bits may be set to provide a 3-bit input control word at the input of the decoder, thereby providing up to eight different decoder outputs, each corresponding to a switch input (A, B, C, D, E, F, G, and H), each of which in turn corresponds to a selectable current mirror arrangement (and corresponding operating mode or response speed). The 3-bit input control word may be set by a user or a processor (based on user-provided and / or sensed inputs that indicate an appropriate response time and operating mode).

[0046] Figure 4B A block diagram illustrating a gain adjustment circuit 208 according to some embodiments, which is extrapolated to include one or more additional current mirror arrangements (e.g., up to N total current mirror arrangements) to select between N number of operating modes. A first current mirror arrangement 402 and a second current mirror arrangement 404 receive the amplifier output and have current outputs leading to the speed up circuit 210. Switch inputs A and B may be used to select the first current mirror arrangement 402 or the second current mirror arrangement 404, respectively. As discussed above, different current mirror arrangements have mirror FETs with different size ratios, so that selecting a particular current mirror changes the operating mode of the current limiter (e.g., the speed of the current limiter).

[0047] According to some embodiments, the third current mirror arrangement 406 may be implemented by receiving the same amplifier output and having a current output leading to the speed-up circuit 210. Another switch input (switch input C) may be used to activate the third current mirror arrangement 406 in the same manner as switch inputs A or B are used to activate the first current mirror arrangement 402 or the second current mirror arrangement 404. According to some embodiments, the third current mirror arrangement 406 includes Figure 4A The third current mirror arrangement 406 includes at least one set of select FETs in series with a set of mirror FETs, with the switch input C controlling the gates of the select FETs. As discussed above, any number of circuit mirror arrangements may be arranged in parallel with each other, up to the Nth current mirror arrangement 408, using a corresponding number of N switch inputs to activate a particular circuit mirror. Each of the N current mirror arrangements includes a plurality of select FETs in series with a set of mirror FETs, with the switch input C controlling the gates of the select FETs. Figure 4A A corresponding set of select FETs and mirror FETs are shown arranged as shown in the second current mirror arrangement 404 in FIG. 4 , which has an input coupled to the amplifier output and an output leading to the acceleration circuit 210 .

[0048] Figure 5 A graph showing the frequency response of both a slow and fast operating mode of a current limiter according to some embodiments. As observed via the crossover at 0 dB (unity gain), the faster operating mode has a higher gain bandwidth (GBW) than the slower operating mode, which translates into a faster response time of the current limiter. Although only two operating modes are illustrated here, any number of operating modes may be selected within a given current limiter based on a corresponding number of different current mirror arrangements.

[0049] Figure 6 A graph is shown providing a response time of a current limiter with respect to an over-current stimulus for different speed operation modes according to some embodiments. For example, a relatively slow operation mode (e.g., using a current mirror arrangement with a relatively small difference in the size ratio between FET M4 and FET M3) produces a relatively slow response time for a low over-current stimulus, while a relatively fast operation mode (e.g., using a current mirror arrangement with a relatively large difference in the size ratio between FET M4 and FET M3) produces a relatively fast response time even for a low over-current stimulus.

[0050] According to some embodiments, at a given overcurrent stimulus threshold identified as the acceleration point 602, the current becomes large enough (eg, I PD *R 312 =>V T_M5) to activate the speed up switch M5 of the speed up circuit 210, and the response time is dramatically reduced (e.g., a reduction of 80% or more) in all operating modes. For all higher over-current stimuli identified as region 604, very fast response times are observed regardless of the operating mode used. Region 606 is provided as a dashed line to illustrate what the response time of the slow operating mode would otherwise be without the speed up circuit 210. Thus, the implementation of the speed up circuit 210 allows the slower operating modes to withstand transient changes in rail current while still quickly clamping down on the rail current to achieve high over-current stimuli.

[0051] By way of example, Table 1 below provides actual response times in both fast and slow modes for various overcurrent amounts when using a current limiter with the aforementioned speed adjustment circuit implemented on a silicon chip. Figure 6 The simulation results presented in closely track .

[0052] Table 1: Circuit response time to different overcurrent stimuli

[0053] Overcurrent(A) Fast mode response time (μs) Slow mode response time (μs) 0.50 26.4 1090 1.00 3.43 422 2.00 2.29 19.6 5.00 2.27 2.69

[0054] As shown in Table 1, under low overcurrent stimulus (e.g., 2A or less), the current limiter operating in the fast mode exhibits a much faster response time than operating in the slow mode. However, after the overcurrent stimulus becomes higher (e.g., 5A or greater), the response time of both the fast and slow modes is approximately the same. In addition, the response time of the current limiter in the slow operating mode becomes much faster under high overcurrent stimulus compared to the response time under lower overcurrent stimulus.

[0055] Other Examples

[0056] Example 1 is a current limiter comprising: a gain stage; and a power switch having a control terminal and a current output and configured to control a current at the current output in response to a signal at the control terminal. The gain stage comprises: an amplifier having an amplifier output and a first amplifier input and a second amplifier input, wherein the first amplifier input is coupled to the current output and the second amplifier input is coupled to a reference terminal; a first current mirror; a first switch coupled between the first current mirror and the control terminal of the power switch; a second current mirror; and a second switch coupled between the second current mirror and the control terminal of the power switch. The first current mirror is configured to pull down a current from the control terminal of the power switch at a first rate in response to the first switch closing, and the second current mirror is configured to pull down a current from the control terminal of the power switch at a second rate in response to the second switch closing. The second rate is different from the first rate.

[0057] Example 2 includes the current limiter of Example 1, wherein the power switch includes a power field effect transistor (FET).

[0058] Example 3 includes the current limiter of example 1 or 2, wherein the amplifier comprises a transconductance amplifier configured to receive a first voltage at a first amplifier input and a second voltage at a second amplifier input. The first voltage represents the current output and the second voltage represents the voltage at the reference terminal.

[0059] Example 4 includes the current limiter of Example 3, wherein the reference terminal is a voltage terminal, and the second voltage is based on a magnitude of a voltage at the voltage terminal.

[0060] Example 5 includes the current limiter of any of Examples 1-4, wherein the gain stage has an output, and the current limiter further includes a speed adjustment circuit coupled to the output of the gain stage.

[0061] Example 6 includes the current limiter of Example 5, wherein the speed adjustment circuit includes: a resistor coupled between a control terminal of the power switch and an output of the gain stage; and a switch having a first terminal coupled to the control terminal of the power switch and a second terminal coupled to the current output.

[0062] Example 7 includes the current limiter of Example 6, wherein the speed adjustment circuit further includes a diode coupled between a control terminal of the power switch and an output of the gain stage.

[0063] Example 8 includes the current limiter of Example 6 or 7, wherein the switch comprises a field effect transistor (FET) having a control terminal coupled to an output of the gain stage.

[0064] Example 9 includes the current limiter of any of Examples 1 to 8, wherein the gain stage further includes a third switch coupled to the amplifier output, and a third current mirror coupled to the third switch. The third current mirror is configured to pull down a current from a control terminal of the power switch at a third rate in response to the third switch closing. The third rate is different from the first rate and the second rate.

[0065] Example 10 includes the current limiter of any of Examples 1-9, wherein the power switch is a first power switch, and the current limiter further includes a second power switch that shares a terminal with the first power switch.

[0066] Example 11 is a printed circuit board (PCB) comprising: a current limiter coupled to a power terminal and having a power output; and a peripheral output port coupled to the power output. The current limiter comprises a gain stage and a power switch having a control terminal and a current output coupled to the power output, wherein the power switch is configured to control a current applied to the power output in response to a signal at the control terminal. The gain stage comprises: an amplifier having an amplifier output and a first amplifier input and a second amplifier input, wherein the first amplifier input is coupled to the current output and the second amplifier input is coupled to a reference terminal; a first current mirror; a first switch coupled between the first current mirror and the control terminal of the power switch; a second current mirror; and a second switch coupled between the second current mirror and the control terminal of the power switch. The first current mirror is configured to pull down a current from the control terminal of the power switch at a first rate in response to the first switch closing, and the second current mirror is configured to pull down a current from the control terminal of the power switch at a second rate in response to the second switch closing. The second rate is different from the first rate.

[0067] Example 12 includes the PCB of Example 11, wherein the power switch includes a power field effect transistor (FET).

[0068] Example 13 includes the PCB of Example 11 or 12, wherein the amplifier comprises a transconductance amplifier configured to receive a first voltage at a first amplifier input and a second voltage at a second amplifier input. The first voltage represents the current output and the second voltage represents the voltage at a reference terminal.

[0069] Example 14 includes the PCB of Example 13, wherein the reference terminal is a voltage terminal, and the second voltage is based on a magnitude of a voltage at the voltage terminal.

[0070] Example 15 includes the PCB of any of Examples 11-14, wherein the gain stage has an output, and the PCB further includes a speed adjustment circuit coupled to the output of the gain stage.

[0071] Example 16 includes the PCB of Example 15, wherein the speed adjustment circuit includes: a resistor coupled between a control terminal of the power switch and an output of the gain stage; and a switch having a first terminal coupled to the control terminal of the power switch and a second terminal coupled to the power output.

[0072] Example 17 includes the PCB of Example 16, wherein the speed adjustment circuit further includes a diode coupled between a control terminal of the power switch and an output of the gain stage.

[0073] Example 18 includes the PCB of Example 16 or 17, wherein the switch comprises a field effect transistor (FET) having a control terminal coupled to an output of the gain stage.

[0074] Example 19 includes the PCB of any of Examples 11 to 18, wherein the gain stage further includes a third switch coupled to the amplifier output and a third current mirror coupled to the third switch. The third current mirror is configured to pull down a current from a control terminal of the power switch at a third rate in response to the third switch closing. The third rate is different from the first rate and the second rate.

[0075] Example 20 includes the PCB of any of Examples 11-19, wherein the power switch is a first power switch, and the current limiter further includes a second power switch that shares a terminal with the first power switch.

[0076] Example 21 is a circuit comprising: a power switch having a first terminal, a second terminal, and a control terminal; an amplifier having an output and a first input and a second input, wherein the first input is coupled to the first terminal of the power switch and the second input is coupled to a reference voltage terminal; a first field effect transistor (FET) and a second field effect transistor (FET) having a first current mirror arrangement; and a third field effect transistor (FET) and a fourth field effect transistor (FET) having a second current mirror arrangement. The first terminal of the first FET is coupled to the output of the amplifier via a first switch, and the first terminal of the second FET is coupled to the current mirror output. The first terminal of the third FET is coupled to the output of the amplifier via a second switch, and the first terminal of the fourth FET is coupled to the current mirror output. A width / length (W / L) ratio between the first FET and the second FET is different from a W / L ratio between the third FET and the fourth FET.

[0077] Example 22 includes the circuit of Example 21, wherein the power switch comprises a power field effect transistor (FET).

[0078] Example 23 includes the circuit of Example 21 or 22, wherein the amplifier is a transconductance amplifier.

[0079] Example 24 includes the circuit of any of Examples 21-23, wherein a control terminal of the first FET is coupled to a control terminal of the second FET, and a second terminal of the first FET is coupled to a second terminal of the second FET.

[0080] Example 25 includes the circuit of any of Examples 21-24, wherein a control terminal of the third FET is coupled to a control terminal of the fourth FET, and a second terminal of the third FET is coupled to a second terminal of the fourth FET.

[0081] Example 26 includes the circuit of any of Examples 21-25, further comprising a diode coupled between a control terminal of the power switch and the current mirror output.

[0082] Example 27 includes the circuit of any of Examples 21-26, further comprising a resistor coupled between a control terminal of the power switch and the current mirror output.

[0083] Example 28 includes the circuit of Example 27, further comprising an additional field effect transistor (FET) having a first terminal coupled to the control terminal of the power switch, a second terminal coupled to the second terminal of the power switch, and a control terminal coupled to the current mirror output.

[0084] Example 29 includes the circuit of any one of Examples 21 to 28, further comprising a fifth field effect transistor (FET) and a sixth field effect transistor (FET) having a third current mirror arrangement, wherein a first terminal of the fifth FET is coupled to the output of the amplifier via a third switch, and a first terminal of the sixth FET is coupled to the current mirror output.

[0085] Example 30 includes the circuit of any of Examples 21-29, wherein the power switch is a first power switch, and the circuit further includes a second power switch that shares a terminal with the first power switch.

[0086] In this specification, the term "coupled" may encompass connections, communications, or signal paths that enable a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B through a direct connection; or (b) in a second instance, device A is coupled to device B through an intermediate component C, provided that the intermediate component C does not change the functional relationship between device A and device B, so that device B is controlled by device A via a control signal generated by device A.

[0087] A device "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function when manufactured by a manufacturer, and / or may be configured (or reconfigurable) by a user after manufacture to perform the function and / or other additional or alternative functions. Configuration may be performed through firmware and / or software programming of the device, through the construction and / or layout of the device's hardware components and interconnections, or a combination thereof.

[0088] As used herein, the terms "terminal", "node", "interconnect", "pin" and "lead" are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to refer to the interconnections between device elements, circuit elements, integrated circuits, devices or other electronic devices or semiconductor components or their ends.

[0089] A circuit or device described herein as including certain components may actually be adapted to be coupled to those components to form the described circuit system or device. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) may actually include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package), and may be adapted to be coupled to at least some of the passive elements and / or sources to form the described structure at the time of manufacture or after manufacture, for example, by an end user and / or a third party.

[0090] Although the use of specific transistors is described herein, other transistors (or equivalent devices) may be used alternatively. For example, a p-channel field effect transistor (PFET) may be used instead of an n-channel field effect transistor (NFET) with little or no change to the circuit. In addition, other types of transistors (e.g., bipolar junction transistors (BJTs)) may be used. In addition, the device may be implemented in / above a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN), or a gallium arsenide substrate (GaAs). In addition, references to transistor features such as a gate, source, or drain are not intended to exclude any suitable transistor technology. For example, features such as a source, drain, and gate are often used to refer to a FET, while an emitter, collector, and base are often used to refer to a BJT. Such features may be used interchangeably herein. For example, a reference to the gate of a transistor may refer to the gate of a FET or the base of a BJT, and vice versa. In some instances, a control terminal may refer to the gate of a FET or the base of a BJT. Any other suitable transistor technology may be used. Any such transistor may be used as a switch, with the gate or base or other comparable feature acting as a switch select input which may be driven to connect the source and drain (or emitter and collector as the case may be).

[0091] Reference herein to a field effect transistor (FET) being "on" (or the switch being closed) means that there is a conductive channel of the FET and drain current can flow through the FET. Reference herein to a FET being "off" (or the switch being open) means that there is no conductive channel and drain current does not flow through the FET. However, an off FET may have current flowing through the body diode of the transistor.

[0092] The circuits described herein may be reconfigured to include additional or different components to provide functionality at least partially similar to functionality available before component replacement. Unless otherwise stated, components shown as resistors generally represent any one or more elements coupled in series and / or in parallel to provide the amount of impedance represented by the resistor shown. For example, a resistor or capacitor shown and described herein as a single component may actually be a plurality of resistors or capacitors coupled in parallel between the same nodes, respectively. For example, a resistor or capacitor shown and described herein as a single component may actually be a plurality of resistors or capacitors coupled in series between the same two nodes as a single resistor or capacitor, respectively.

[0093] The use of the phrase "ground" in the foregoing description includes chassis ground, ground wire ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection that is applicable or suitable for the present specification. Unless otherwise stated, "about" before a parameter means within + / -10% of the parameter.

[0094] Modifications may be made in the described examples and other examples are possible within the scope of the claims.

Claims

1. A current limiter, comprising: a power switch having a control terminal and a current output, the power switch configured to control a current at the current output in response to a signal at the control terminal; and Gain stage, which includes: an amplifier having an amplifier output and a first amplifier input and a second amplifier input, the first amplifier input coupled to the current output and the second amplifier input coupled to a reference terminal; a first current mirror; a first switch coupled between the first current mirror and the control terminal of the power switch; a second current mirror; and a second switch coupled between the second current mirror and the control terminal of the power switch; wherein the first current mirror is configured to pull down current from the control terminal of the power switch at a first rate in response to the first switch closing, and the second current mirror is configured to pull down current from the control terminal of the power switch at a second rate in response to the second switch closing, the second rate being different from the first rate.

2. The current limiter according to claim 1, wherein: The amplifier comprises a transconductance amplifier configured to receive: a first voltage at the first amplifier input; and a second voltage at the second amplifier input; The first voltage represents the current output and the second voltage represents the voltage at the reference terminal. 3 . The current limiter of claim 2 , wherein the reference terminal is a voltage terminal, and the second voltage is based on a magnitude of a voltage at the voltage terminal.

4. The current limiter of claim 1, wherein the gain stage has an output, and the current limiter further comprises a speed adjustment circuit coupled to the output of the gain stage.

5. The current limiter of claim 4, wherein the speed adjustment circuit comprises: a resistor coupled between the control terminal of the power switch and the output of the gain stage; and A switch has a first terminal coupled to the control terminal of the power switch and a second terminal coupled to the current output. 6 . The current limiter of claim 5 , wherein the speed adjustment circuit further comprises a diode coupled between the control terminal of the power switch and the output of the gain stage.

7. The current limiter of claim 5, wherein the switch comprises a field effect transistor (FET) having a control terminal coupled to the output of the gain stage.

8. The current limiter of claim 1 , wherein the gain stage further comprises a third switch coupled to the amplifier output and a third current mirror coupled to the third switch, wherein the third current mirror is configured to pull down current from the control terminal of the power switch at a third rate in response to the third switch closing, the third rate being different from the first rate and the second rate.

9. A printed circuit board (PCB), comprising: a current limiter coupled to the power terminal and having a power output; and a peripheral output port coupled to the power output; The current limiter further comprises: a power switch having a control terminal and a current output coupled to the power output, the power switch configured to control a current applied to the power output in response to a signal at the control terminal; and Gain stage, which includes: an amplifier having an amplifier output and a first amplifier input and a second amplifier input, the first amplifier input coupled to the current output and the second amplifier input coupled to a reference terminal; a first current mirror; a first switch coupled between the first current mirror and the control terminal of the power switch; a second current mirror; and a second switch coupled between the second current mirror and the control terminal of the power switch; wherein the first current mirror is configured to pull down current from the control terminal of the power switch at a first rate in response to the first switch closing, and the second current mirror is configured to pull down current from the control terminal of the power switch at a second rate in response to the second switch closing, the second rate being different from the first rate.

10. The PCB according to claim 9, wherein: The amplifier comprises a transconductance amplifier configured to receive: a first voltage at the first amplifier input; and a second voltage at the second amplifier input; The first voltage represents the current output and the second voltage represents the voltage at the reference terminal. 11 . The PCB of claim 9 , wherein the reference terminal is a voltage terminal, and the second voltage is based on a magnitude of a voltage at the voltage terminal.

12. The PCB of claim 9, wherein the gain stage has an output, and the PCB further comprises a speed adjustment circuit coupled to the output of the gain stage.

13. The PCB according to claim 12, wherein the speed adjustment circuit comprises: a resistor coupled between the control terminal of the power switch and the output of the gain stage; and A switch has a first terminal coupled to the control terminal of the power switch and a second terminal coupled to the power output.

14. The PCB of claim 13, wherein the speed adjustment circuit further comprises a diode coupled between the control terminal of the power switch and the output of the gain stage.

15. The PCB of claim 13, wherein the switch comprises a field effect transistor (FET) having a control terminal coupled to the output of the gain stage.

16. The PCB of claim 9, wherein the gain stage further comprises a third switch coupled to the amplifier output and a third current mirror coupled to the third switch, wherein the third current mirror is configured to pull down a current from the control terminal of the power switch at a third rate in response to closing of the third switch, the third rate being different from the first rate and the second rate.

17. A circuit comprising: a power switch having a first terminal, a second terminal and a control terminal; an amplifier having an output and a first input and a second input, the first input coupled to the first terminal of the power switch and the second input coupled to a reference voltage terminal; a first field effect transistor (FET) and a second field effect transistor (FET) having a first current mirror arrangement, wherein a first terminal of the first FET is coupled to the output of the amplifier via a first switch and a first terminal of the second FET is coupled to a current mirror output; and a third field effect transistor (FET) and a fourth field effect transistor (FET) having a second current mirror arrangement, wherein a first terminal of the third FET is coupled to the output of the amplifier via a second switch and a first terminal of the fourth FET is coupled to the current mirror output, Wherein a width / length (W / L) ratio between the first FET and the second FET is different from a W / L ratio between the third FET and the fourth FET.

18. The circuit of claim 17, wherein the control terminal of the first FET is coupled to the control terminal of the second FET, the second terminal of the first FET is coupled to the second terminal of the second FET, the control terminal of the third FET is coupled to the control terminal of the fourth FET, and the second terminal of the third FET is coupled to the second terminal of the fourth FET.

19. The circuit of claim 17, further comprising: a diode coupled between the control terminal of the power switch and the current mirror output; a resistor coupled between the control terminal of the power switch and the current mirror output; and An additional field effect transistor (FET) has a first terminal coupled to the control terminal of the power switch, a second terminal coupled to the second terminal of the power switch, and a control terminal coupled to the current mirror output.

20. The circuit of claim 17, further comprising a fifth field effect transistor (FET) and a sixth field effect transistor (FET) having a third current mirror arrangement, wherein a first terminal of the fifth FET is coupled to the output of the amplifier via a third switch, and a first terminal of the sixth FET is coupled to the current mirror output.

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