Wiring board and mounting structure using same

Abstract

A wiring board according to the present disclosure has: an insulating substrate having a first surface and a second surface on the opposite side of the first surface; and a solder resist located on the first surface. The insulating substrate includes at least one recessed portion recessed from a peripheral edge of the insulating substrate toward a center direction in a plan view, and a plurality of electrodes located on the first surface along the recessed portion. The solder resist has an opening exposing the electrode. A peripheral edge of the solder resist includes a first peripheral edge along the recess and a second peripheral edge along a peripheral edge of the insulating substrate other than the recess. The first peripheral edge overlaps a peripheral edge of the recess, and the second peripheral edge includes a first region connected to the first peripheral edge. In a plan view, the first region is positioned closer to the center than the peripheral edge of the insulating substrate.

Description

Technical Field

[0001] The present disclosure relates to a wiring substrate and a mounting structure using the wiring substrate. Background Art

[0002] For example, there is a wiring substrate in which a processor bare chip is mounted on the upper surface and an optical module connected to an optical connector is mounted on the outer periphery (Patent Documents 1 and 2). The optical module includes a photonic chip.

[0003] After the optical module is mounted on the wiring substrate, the bottom filler (sealing resin) is filled between the photonic chip and the wiring substrate. Sometimes, part of the bottom filler (sealing resin) filled overflows to the outer peripheral side of the substrate, causing a connection obstacle with the optical connector. In particular, the bottom filler (sealing resin) is likely to overflow when the edge of the solder resist on the upper surface of the wiring substrate is missing. The outer periphery of the wiring substrate is easily impacted during transportation, and the edge of the relatively brittle solder resist is easily lost due to impact.

[0004] Prior Art Literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Publication No. 2005-286225

[0007] Patent Document 2: Japanese Patent Application No. 2009-536362 Summary of the invention

[0008] -Technical means to solve the problem-

[0009] The wiring substrate involved in the present disclosure includes: an insulating substrate having a first surface and a second surface located on the opposite side of the first surface; and a solder resist located on the first surface. The insulating substrate includes at least one recessed portion recessed from the periphery of the insulating substrate toward the central direction when viewed from above, and a plurality of electrodes located on the first surface along the recess. The solder resist has an opening exposing the electrodes. The periphery of the solder resist includes a first periphery along the recess and a second periphery along the periphery of the insulating substrate other than the recess. The first periphery overlaps with the periphery of the recess, and the second periphery includes a first area connected to the first periphery. When viewed from above, the first area is located closer to the central direction than the periphery of the insulating substrate.

[0010] Furthermore, the mounting structure involved in the present disclosure includes: the above-mentioned wiring substrate; an adapter located in the recess; and an electronic component connected to the adapter and multiple electrodes located on the first surface of the insulating substrate, and the sealing resin is located between the lower surface of the electronic component and the solder resist. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1It is an explanatory diagram showing a mounting structure including a wiring substrate according to an embodiment of the present disclosure.

[0012] Figure 2 It is an explanatory diagram showing a wiring board according to one embodiment of the present disclosure.

[0013] Figure 3 yes Figure 2 A top view of region X is shown.

[0014] Figure 4 It means in Figure 1 An enlarged explanatory diagram of the connection portion between the adapter and the optical connector in the mounting structure shown.

[0015] Figure 5 It means in Figure 1 An enlarged explanatory diagram of the state of the sealing resin in the connection portion between the adapter and the optical connector in the mounting structure shown. DETAILED DESCRIPTION

[0016] As described above, sometimes part of the filled sealing resin overflows to the outer peripheral side of the substrate, causing a connection obstacle with the optical connector. Therefore, a wiring substrate and a mounting structure using the wiring substrate are required that can prevent the overflow of the filled sealing resin to the outer peripheral side of the wiring substrate even if part of the filled sealing resin overflows.

[0017] The wiring board and the mounting structure according to the present disclosure have the structure described in the column of means for solving the above-mentioned problems, and thus can prevent the overflow to the outer peripheral side surface of the wiring board even if a part of the filled sealing resin overflows.

[0018] based on Figure 1 to Figure 5 A wiring board according to an embodiment of the present disclosure will be described. Figure 1 It is an explanatory diagram showing a mounting structure 10 including a wiring substrate 1 according to an embodiment of the present disclosure. Figure 2 1 is an explanatory diagram showing a wiring board 1 according to an embodiment of the present disclosure. The wiring board 1 according to the embodiment includes an insulating substrate 2 and a solder resist 3 .

[0019] The insulating substrate 2 has a first surface f1 and a second surface f2 located on the opposite side of the first surface f1. Examples of the insulating layer constituting the insulating substrate 2 include a core insulating layer and a build-up insulating layer.

[0020] The insulating layer for build-up is not particularly limited as long as it is made of insulating raw materials. Examples of insulating raw materials include epoxy resins, bismaleimide-triazine resins, polyimide resins, and polyphenylene ether resins. Two or more of these resins may be mixed and used.

[0021] The insulating layer for adding layers may include reinforcing materials. Examples of reinforcing materials include insulating fabrics such as glass fiber, glass nonwoven fabric, aramid nonwoven fabric, aramid fiber, and polyester fiber. Two or more reinforcing materials may be used in combination. Furthermore, inorganic insulating fillers such as silicon dioxide, barium sulfate, talc, clay, glass, calcium carbonate, and titanium oxide may be dispersed in the insulating layer for adding layers. Two or more inorganic insulating fillers may be used in combination.

[0022] exist Figure 2 In the embodiment, the build-up insulating layer is located on the upper surface side and the lower surface side of the core insulating layer. The thickness of the build-up insulating layer is not particularly limited, and is, for example, 10 μm or more and 50 μm or less.

[0023] In order to electrically connect the upper and lower surfaces of the build-up insulating layer, the through-hole conductor is located in the build-up insulating layer. The through-hole conductor is located in a through hole that penetrates the upper and lower surfaces of the build-up insulating layer. The through-hole conductor is formed of, for example, a metal such as copper, specifically, a metal plating such as a copper plating layer. The through-hole conductor may be filled in the through-hole, or may be formed only on the inner wall surface of the through-hole. The through-hole conductor is connected to the conductor layer located on the upper and lower surfaces of the build-up insulating layer.

[0024] The core insulating layer is not particularly limited as long as it is made of a raw material with insulating properties. As the raw material with insulating properties, similar to the build-up insulating layer, for example, resins such as epoxy resin, bismaleimide-triazine resin, polyimide resin, and polyphenylene ether resin can be cited. Furthermore, similar to the build-up insulating layer, a reinforcing material may be included, and an inorganic insulating filler may be dispersed.

[0025] The core insulating layer is located substantially in the center in the thickness direction of the wiring substrate 1 and is generally thicker than the build-up insulating layer. The thickness of the core insulating layer is not particularly limited, and is, for example, 100 μm to 1500 μm.

[0026] In order to electrically connect the upper and lower surfaces of the core insulating layer, the through-hole conductor is located in the core insulating layer. The through-hole conductor is located in a through hole that penetrates the upper and lower surfaces of the core insulating layer. The through-hole conductor is formed of a metal such as copper, specifically a metal plating such as a copper plating layer. The through-hole conductor may be formed only on the inner wall surface of the through-hole, or may be filled in the through-hole. The through-hole conductor is connected to the conductor layer located on the upper and lower surfaces of the core insulating layer.

[0027] The shape of the insulating substrate 2 is not limited. The insulating substrate 2 can be as follows when viewed from above: Figure 2 The insulating substrate 2 has a quadrilateral shape as shown, but may also have a polygonal shape, a circular shape, an elliptical shape, etc. The insulating substrate 2 has a concave portion 21 that is recessed from the periphery of the insulating substrate 2 toward the center when viewed from above. The insulating substrate 2 includes at least one concave portion 21. Figure 2 As shown, when the insulating substrate 2 has a quadrilateral shape, the recessed portion 21 is located at a position recessed from one side (first side) of the sides constituting the quadrilateral toward the center.

[0028] The size of the recess 21 is appropriately set according to the size of the adapter 4 located in the recess 21. The insulating substrate 2 only needs to include at least one recess 21, and when the insulating substrate 2 is a polygon such as a quadrilateral, a plurality of recesses 21 may be included on one side.

[0029] The plurality of electrodes 8 are located along the recess 21 on the first surface f1 of the insulating substrate 2. The first surface f1 of the insulating substrate 2 is the upper surface on the surface side in the thickness direction of the wiring substrate 1, and the second surface f2 is the lower surface on the side opposite to the first surface f1 in the thickness direction of the wiring substrate 1. The electrodes 8 are formed of a metal such as copper and are part of the conductor layer located on the first surface f1 of the insulating substrate 2. In the first surface f1 of the insulating substrate 2, the electrodes 8 are not only located along the recess 21, but also located at positions such as Figure 2 As shown, it is also located substantially in the center of the insulating substrate 2. The terminal of the processor bare chip is connected to the electrode 8 in the center via the solder 7 described later.

[0030] like Figure 2 As shown, the solder resist 3 is located on the first surface f1 of the insulating substrate 2. The solder resist 3 is made of resin, and examples of the resin include acrylic modified epoxy resins, etc. The solder resist 3 has a thickness of, for example, 10 μm or more and 50 μm or less.

[0031] The solder resist 3 has openings for exposing each electrode 8 individually. Figure 2 In the embodiment, solder 7 is attached to electrode 8 exposed in the opening.

[0032] In a plan view, the solder resist 3 is formed according to the shape of the insulating substrate 2. The periphery of the solder resist 3 includes a first periphery 31 along the recessed portion 21 of the insulating substrate 2 and a second periphery 32 along the periphery other than the recessed portion 21 of the insulating substrate 2. The first periphery 31 of the solder resist 3 overlaps with the periphery of the recessed portion 21 of the insulating substrate 2. That is, the side surface of the first periphery 31 and the side surface of the recessed portion 21 are arranged to be substantially coplanar.

[0033] The first periphery 31 of the solder resist 3 overlaps with the periphery of the recess 21 of the insulating substrate 2, so that the width of the solder resist 3 can be sufficiently ensured. As a result, for example, when the electronic component 5 described later is mounted, the thermal influence on the wiring substrate 1 is reduced. Furthermore, the gap between the lower surface of the electronic component 5 and the mounting area of ​​the wiring substrate 1 (solder resist 3) is fixed, and the filling property of the sealing resin 6 becomes uniform.

[0034] like Figure 3As shown, the second periphery 32 of the solder resist 3 includes a first region 321 connected to the first periphery 31. In a plan view, the first region 321 is located closer to the center than the periphery of the insulating substrate 2 other than the recess 21. Figure 3 yes Figure 2 A top view of the region X is shown. Figure 2 As shown, when the insulating substrate 2 has a quadrilateral shape, the first region 321 of the second peripheral edge 32 is located closer to the center than the first side of the insulating substrate 2. The first region 321 is located closer to the center than the peripheral edge of the insulating substrate 2, so that, for example, when the sealing resin 6 is filled between the wiring substrate 1 and the electronic component 5, the overflowing sealing resin 6 remains on the first surface f1 of the insulating substrate 2 exposed from the solder resist 3.

[0035] A height difference is formed between the periphery (second periphery 32) of the solder resist 3 and the periphery of the insulating substrate 2. By forming such a height difference, Figure 4 As shown in FIG. 1 , the sealing resin 6 is unlikely to overflow to the outer peripheral side of the wiring substrate 1. Even if the sealing resin 6 flows to the height difference portion, such as Figure 5 As shown in FIG. 1 , the sealing resin 6 also flows along the height difference and is unlikely to overflow to the outer peripheral side of the wiring substrate 1. As a result, Figure 4 as well as Figure 5 As shown, the optical connector 41 is well connected to the wiring substrate 1 via the adapter 4 . Figure 4 And 5 means Figure 1 The attached structure 10 is an enlarged explanatory diagram of the connection portion between the adapter 4 and the optical connector 41 .

[0036] Furthermore, since the solder resist 3 is relatively brittle, it is easy to have a defect or damage at the periphery. By locating the second periphery 32 in the central direction, the impact generated during transportation is difficult to be applied to the second periphery 32. As a result, it is not easy to have a defect or damage at the second periphery 32 of the solder resist 3. The defect generated at the periphery of the solder resist 3 becomes the starting point for the sealing resin 6 to flow out toward the outer peripheral side of the wiring substrate 1. Therefore, reducing the generation of defects is also beneficial in preventing the sealing resin 6 from flowing out.

[0037] As long as the first region 321 is located closer to the center than the periphery of the insulating substrate 2, the distance (third distance L3) between the first region 321 and the periphery of the insulating substrate 2 closest to the first region 321 is not limited. The third distance L3 may be, for example, 50 μm to 500 μm.

[0038] The electrode 8 located on the first surface f1 of the insulating substrate 2 includes a first electrode 81 located closest to the first periphery 31 and a second electrode 82 located closest to the first region 321 of the second periphery 32. In the wiring substrate 1 according to one embodiment, the distance between the first periphery 31 and the first electrode 81 (first distance L1) may be shorter than the distance between the first region 321 of the second periphery 32 and the second electrode 82 (second distance L2). Specifically, the first distance L1 may be greater than 100 μm and less than 400 μm, and the second distance L2 may be greater than 200 μm and less than 600 μm. If the first distance L1 is shorter than the second distance L2, the electrical insulation reliability of the plurality of electrodes 8 disposed along the recess 21 can be sufficiently maintained while the width of the recess 21 is sufficiently ensured. Furthermore, an area where the sealing resin 6 can be retained can be ensured in the peripheral side direction of the wiring substrate 1, and the risk of the sealing resin 6 flowing out to the peripheral side can be further reduced.

[0039] The difference between the first distance L1 and the second distance L2 may be, for example, 100 μm or more. If the difference between the first distance L1 and the second distance L2 is 100 μm or more, it is easier to fill the sealing resin 6 between the electronic component 5 and the wiring substrate 1 (solder resist 3). As a result, it is expected that the electrical insulation reliability of the plurality of electrodes 8 will be improved. Furthermore, the risk of the sealing resin 6 flowing out to the outer peripheral side of the wiring substrate 1 can be further reduced. The difference between the first distance L1 and the second distance L2 may be, for example, 200 μm or less.

[0040] The third distance L3 may be shorter than the first distance L1. By making the third distance L3 shorter than the first distance L1, it is easy to fully fill the sealing resin 6 between the plurality of electrodes 8 provided along the recess 21, and the electrical insulation reliability is improved. Furthermore, by making the third distance L3 shorter than the first distance L1, the exposed portion of the first surface f1 of the insulating substrate 2 is reduced, and the miniaturization of the wiring substrate 1 can be achieved.

[0041] The arithmetic mean roughness of each of the first surface f1 of the insulating substrate 2 and the surface of the solder resist 3 is not limited. For example, the arithmetic mean roughness of the first surface f1 of the insulating substrate 2 exposed along the second peripheral edge 32 may be greater than the arithmetic mean roughness of the surface of the solder resist 3. Specifically, the arithmetic mean roughness of the surface of the solder resist 3 may be greater than 200nm and less than 400nm. The arithmetic mean roughness of the first surface f1 of the insulating substrate 2 exposed along the second peripheral edge 32 may also be greater than 500nm and less than 800nm. The above-mentioned arithmetic mean roughness can be measured, for example, by a laser microscope.

[0042] When the arithmetic mean roughness of the first surface f1 of the insulating substrate 2 exposed along the second peripheral edge 32 is greater than the arithmetic mean roughness of the surface of the solder resist 3, the surface of the solder resist 3 is sufficiently wettable. As a result, it is easier to fill the sealing resin 6. Furthermore, the wettability of the first surface f1 of the insulating substrate 2 exposed along the second peripheral edge 32 becomes good. Therefore, for example, Figure 5 As shown, even if the sealing resin 6 flows to the exposed first surface f1 of the insulating substrate 2, the sealing resin 6 is easy to spread on the first surface f1 exposed along the corner of the end surface of the solder resist 3 and the exposed first surface f1. As a result, the sealing resin 6 is less likely to overflow to the outer peripheral side of the wiring substrate 1.

[0043] Next, the mounting structure involved in the present disclosure is described. Figure 1 As shown, a mounting structure 10 according to an embodiment of the present disclosure includes the wiring substrate 1 according to the above-mentioned embodiment, an adapter 4 , an electronic component 5 , an optical connector 41 , and a sealing resin 6 .

[0044] The adapter 4 is a member for connecting the optical connector 41 to the wiring substrate 1, and is located in the recess 21 of the insulating substrate 2. In the direction along the periphery of the insulating substrate 2, the width L4 of the first region 321 may be longer than the width L5 of the optical connector 41 in the direction along the first region 321. By setting such a structure, the portion of the optical connector 41 facing the outer peripheral side surface of the wiring substrate 1 is converged in the first region 321. Since the first region 321 is located closer to the center direction of the wiring substrate 1 than the periphery of the insulating substrate 2, it is possible to reduce the outflow of the sealing resin 6 to the outer peripheral side surface of the wiring substrate 1, and the connectivity between the optical connector 41 and the wiring substrate 1 can be improved.

[0045] The electronic component 5 is connected to the adapter 4 and the plurality of electrodes 8 located on the first surface f1 of the insulating substrate 2. As the electronic component 5, for example, a photoelectric element and an interface element can be cited. The sealing resin 6 is located between the lower surface of the electronic component 5 and the solder resist 3. The sealing resin 6 is used to fix the electronic component 5 to the wiring substrate 1. As the sealing resin 6, for example, epoxy resin, polyimide resin, and polyurethane resin can be cited.

[0046] The embodiments of the present disclosure have been described above. However, the invention according to the present disclosure is not limited to the above-described embodiments, and various changes and improvements can be made within the scope of the present disclosure as shown in the following (1) and (7).

[0047] (1) The wiring substrate involved in the present disclosure includes: an insulating substrate having a first surface and a second surface located on the opposite side of the first surface; and a solder resist located on the first surface. The insulating substrate includes at least one recessed portion that is recessed from the periphery of the insulating substrate toward the center when viewed from above, and a plurality of electrodes located on the first surface along the recess. The solder resist has an opening that exposes the electrodes. The periphery of the solder resist includes a first periphery along the recess and a second periphery along the periphery of the insulating substrate other than the recess. The first periphery overlaps with the periphery of the recess, and the second periphery includes a first region connected to the first periphery. When viewed from above, the first region is located closer to the center than the periphery of the insulating substrate.

[0048] Regarding the embodiments of the present disclosure, the following embodiments (2) to (6) and (8) are further disclosed.

[0049] (2) In the wiring substrate described in (1) above, when viewed from above, the insulating substrate has a quadrilateral shape including a first side, the recess is located at a position recessed from the first side toward the center, and when viewed from above, the first area of ​​the second peripheral edge is located closer to the center than the first side of the insulating substrate.

[0050] (3) In the wiring board described in (1) or (2) above, the arithmetic mean roughness of the first surface of the insulating substrate exposed along the second peripheral edge is larger than the arithmetic mean roughness of the surface of the solder resist.

[0051] (4) In the wiring substrate described in any one of (1) to (3) above, the plurality of electrodes include a first electrode located closest to the first periphery and a second electrode located in a first region closest to the second periphery, and a first distance between the first periphery and the first electrode is shorter than a second distance between the first region of the second periphery and the second electrode.

[0052] (5) In the wiring substrate described in (4) above, a difference between the first distance and the second distance is 100 μm or more.

[0053] (6) In the wiring substrate described in (4) or (5) above, a third distance between the first region and the periphery of the insulating substrate located closest to the first region is shorter than the first distance.

[0054] (7) The mounting structure involved in the present disclosure includes: the wiring substrate described in any one of (1) to (6) above; an adapter located in the recessed portion; an electronic component connected to the adapter and a plurality of electrodes located on the first surface of the insulating substrate, wherein the sealing resin is located between the lower surface of the electronic component and the solder resist.

[0055] (8) In the mounting structure described in (7), the adapter is connected to the optical connector on the side opposite to the recess, and the width of the first region in the direction along the periphery of the insulating substrate is greater than the width of a portion of the optical connector facing the first region.

[0056] -Explanation of symbols-

[0057] 1 Wiring board

[0058] 2 Insulation substrate

[0059] 21 recess

[0060] 3. Solder Resist

[0061] 31 First periphery

[0062] 32 Second perimeter

[0063] 321 First Area

[0064] 4 Adapter

[0065] 41 Optical connector

[0066] 5 Electronic components

[0067] 6 Sealing resin

[0068] 7. Solder

[0069] 8 Electrodes

[0070] 81 First electrode

[0071] 82 Second electrode

[0072] 10 Install the structure

[0073] f1 first side

[0074] f2 Second side.

Claims

1. A wiring substrate, comprising: An insulating substrate having a first surface and a second surface located on an opposite side of the first surface; as well as Solder resist, located on the first side, The insulating substrate includes at least one recessed portion recessed from the periphery of the insulating substrate toward the center in a plan view, and a plurality of electrodes located on the first surface along the recessed portion. The solder resist has an opening exposing the electrode, The periphery of the solder resist includes a first periphery along the recess and a second periphery along the periphery of the insulating substrate other than the recess. The first periphery overlaps with the periphery of the recess, The second periphery includes a first area connected to the first periphery, The first region is located closer to the center direction than the peripheral edge of the insulating substrate in a plan view.

2. The wiring substrate according to claim 1, wherein: In a plan view, the insulating substrate has a quadrilateral shape including a first side, and the recess is located at a position recessed from the first side toward the center. In a plan view, the first region of the second peripheral edge is located closer to the center direction than the first side of the insulating substrate.

3. The wiring substrate according to claim 1 or 2, wherein: The arithmetic mean roughness of the first surface of the insulating substrate exposed along the second peripheral edge is greater than the arithmetic mean roughness of the surface of the solder resist.

4. The wiring substrate according to any one of claims 1 to 3, wherein: The plurality of electrodes include a first electrode located closest to the first periphery and a second electrode located closest to the first region of the second periphery, A first distance between the first periphery and the first electrode is shorter than a second distance between the first region of the second periphery and the second electrode.

5. The wiring substrate according to claim 4, wherein: The difference between the first distance and the second distance is greater than or equal to 100 μm.

6. The wiring substrate according to claim 4 or 5, wherein: A third distance between the first region and a peripheral edge of the insulating substrate located closest to the first region is shorter than the first distance.

7. A mounting structure, comprising: The wiring substrate according to any one of claims 1 to 6; an adapter, located in the recess; as well as an electronic component connected to the adapter and the plurality of electrodes located on the first surface of the insulating substrate, The sealing resin is located between the lower surface of the electronic component and the solder resist.

8. The mounting structure according to claim 7, wherein: The adapter is connected to the optical connector on the side opposite to the recess, In a direction along the peripheral edge of the insulating substrate, the width of the first region is greater than the width of a portion of the optical connector that faces the first region.

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