Semiconductor device

Abstract

A semiconductor device includes: a gate electrode layer embedded in a gate trench; a contact trench including a first crossing region crossing the gate trench; and an emitter contact electrode layer embedded in the contact trench. A gate electrode recess is formed in a first intersection region and a peripheral portion of the first intersection region in the gate trench, a gate cover insulating layer is embedded in the gate electrode recess, and an emitter region is formed deeper than an upper surface of the gate electrode layer at the peripheral portion of the first intersection region.

Description

[0001] Related Application

[0002] This application corresponds to Japanese Patent Application No. 2022-143916 filed with the Japan Patent Office on September 9, 2022, and all the disclosure of the application is incorporated into this application by reference. Technical Field

[0003] The present disclosure relates to a semiconductor device. Background Art

[0004] Patent document 1 discloses a semiconductor device, comprising: a semiconductor layer having a main surface formed with a groove; a main body region of a first conductivity type, which is formed on a surface portion of the main surface of the semiconductor layer along the side wall of the groove; an impurity region of a second conductivity type, which is formed on a surface portion of the main body region along the side wall of the groove; a gate insulating layer, which is formed on an inner wall of the groove; a gate electrode, which is buried in the groove and is opposite to the main body region and the impurity region via the gate insulating layer; a contact electrode, which penetrates the side wall of the groove from the inside of the groove and is led out to the surface portion of the main surface of the semiconductor layer and is electrically connected to the main body region and the impurity region; and a buried insulating layer, which is between the gate electrode and the contact electrode in the groove and insulates the gate electrode and the contact electrode.

[0005] Prior art literature

[0006] Patent Literature

[0007] Patent Document 1: International Publication No. 2019 / 103135 Summary of the invention

[0008] Problems to be solved by the invention

[0009] One embodiment of the present disclosure provides a semiconductor device capable of improving the degree of freedom in designing the size of a first impurity region such as an emitter region and a source region, thereby improving breakdown resistance.

[0010] One embodiment of the present disclosure provides a semiconductor device that can suppress reduction in channel width and reduce on-resistance in a structure including a contact trench intersecting a gate trench.

[0011] Solutions to Solve Problems

[0012] A semiconductor device according to an embodiment of the present disclosure includes: a chip having a first main surface on which a gate trench is formed, the gate trench having a bottom wall and side walls and extending in a first direction; a main body region of a first conductivity type formed along the side walls of the gate trench on a surface portion of the first main surface; a first impurity region of a second conductivity type formed along the side walls of the gate trench on a surface portion of the main body region; a gate insulating layer formed on the bottom wall and the side walls of the gate trench; a gate electrode buried in the gate trench and opposed to the main body region and the first impurity region via the gate insulating layer; a contact trench including an intersection region intersecting the gate trench, and is led out from the intersection region to the outside of the gate groove along a second direction intersecting the first direction; and a contact electrode, which is buried in the contact groove and is electrically connected to the main region and the first impurity region inside the contact groove, and a space region is formed on the gate electrode at least in the intersection region and the peripheral portion of the intersection region in the gate trench, and a covering insulating layer is buried in the space region, the covering insulating layer covers the upper surface of the gate electrode in the intersection region and the peripheral portion of the intersection region, and insulates the gate electrode from the contact electrode, and the first impurity region is formed deeper than the upper surface of the gate electrode at the peripheral portion of the intersection region.

[0013] Effects of the Invention

[0014] According to one embodiment of the present disclosure, the first impurity region is formed deeper than the upper surface of the gate electrode in the periphery of the intersection region. Thus, a channel can be formed in the periphery of the intersection region, thereby suppressing reduction of the channel width and reducing on-resistance.

[0015] According to one embodiment of the present disclosure, the first impurity region is formed deeper than the upper surface of the gate electrode. Thus, a channel can also be formed in the lower region of the peripheral portion of the intersection region. Therefore, there is no need to consider the patterning margin during etching and contact pattern formation, and the design freedom of the size of the first impurity region can be increased, thereby improving the breakdown tolerance. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is a schematic cross-sectional perspective view showing a partial region of the semiconductor device according to the first embodiment of the present disclosure.

[0017] Figure 2 is from Figure 1 The structure on the first main surface of the chip is removed from the figure.

[0018] Figure 3 is from Figure 2 Image with emitter contact electrode layer removed.

[0019] Figure 4 is observed from the first main surface of the chip Figure 3 Schematic top view of .

[0020] Figure 5 It is along Figure 4 A cross-sectional view taken along line VV is shown.

[0021] Figure 6 It is along Figure 4 A cross-sectional view taken along line VI-VI is shown.

[0022] Figure 7 It is along Figure 4 A cross-sectional view taken along line VII-VII is shown.

[0023] Fig. 8A It is a diagram showing an example of a method for manufacturing the semiconductor device.

[0024] Figure 8B Yes means Fig. 8A A diagram of the subsequent process.

[0025] Figure 8C Yes means Figure 8B A diagram of the subsequent process.

[0026] Fig.8D Yes means Figure 8C A diagram of the subsequent process.

[0027] Fig. 8E Yes means Fig.8D A diagram of the subsequent process.

[0028] Figure 8F Yes means Fig. 8E A diagram of the subsequent process.

[0029] Figure 8G Yes means Figure 8F A diagram of the subsequent process.

[0030] Figure 8H Yes means Figure 8G A diagram of the subsequent process.

[0031] Figure 8I Yes means Figure 8H A diagram of the subsequent process.

[0032] Figure 8J Yes means Figure 8I A diagram of the subsequent process.

[0033] Figure 8K Yes means Figure 8J A diagram of the subsequent process.

[0034] Figure 8L Yes means Figure 8K A diagram of the subsequent process.

[0035] Figure 8M Yes means Figure 8L A diagram of the subsequent process.

[0036] Figure 8N Yes means Figure 8M A diagram of the subsequent process.

[0037] Fig. 9A This is a diagram for explaining channel formation in a semiconductor device under condition 1.

[0038] Fig. 9B This is a diagram for explaining the arrangement pattern of the emitter region and the contact region of the semiconductor device under condition 1.

[0039] Fig. 10A This is a diagram for explaining channel formation in a semiconductor device under condition 2.

[0040] Fig. 10B This is a diagram for explaining the arrangement pattern of the emitter region and the contact region of the semiconductor device under condition 2.

[0041] Fig.11 This is a graph of short-circuit waveforms of semiconductor devices under conditions 1 and 2 obtained by simulation.

[0042] Fig.12 This is a graph showing the current-voltage characteristics of the semiconductor device under conditions 1 and 2 obtained by simulation.

[0043] Fig.13 Yes Fig.12 A portion of the graph is enlarged.

[0044] Fig.14 This is a graph showing the current-voltage characteristics of the semiconductor device under conditions 1 and 2 obtained by simulation.

[0045] Fig.15 1 is a schematic cross-sectional perspective view showing a partial region of a semiconductor device according to a second embodiment of the present disclosure.

[0046] Fig.16 Yes means Fig.15 Schematic cross-sectional view of a portion of a semiconductor device.

[0047] Fig.17 Yes means Fig.15 Schematic cross-sectional view of a portion of a semiconductor device.

[0048] Fig.18 1 is a schematic cross-sectional perspective view showing a partial region of a semiconductor device according to a third embodiment of the present disclosure. DETAILED DESCRIPTION

[0049] <Description of the Structure of Semiconductor Device 1 (First Embodiment)>

[0050] Figure 1 1 is a schematic cross-sectional perspective view showing a partial region of the semiconductor device 1 according to the first embodiment of the present disclosure. Figure 2 is from Figure 1 The structure on the first main surface 3 of the chip 2 is removed from the figure. Figure 3 is from Figure 2 The emitter contact electrode layer 51 is removed from the figure.

[0051] Figure 4 is viewed from the first main surface 3 of the chip 2 Figure 3 Schematic top view of . Figure 5 It is along Figure 4 A cross-sectional view taken along line VV is shown. Figure 6 It is along Figure 4 A cross-sectional view taken along line VI-VI is shown. Figure 7 It is along Figure 4 A cross-sectional view taken along line VII-VII is shown. Figures 5 to 7 Also shown are structures on the first main face 3 of the chip 2 .

[0052] In this embodiment, the semiconductor device 1 has a basic form of an IGBT (Insulated Gate Bipolar Transistor) having a trench gate. Figure 1 to Figure 7 , the semiconductor device 1 includes n - In this embodiment, the chip 2 is composed of n - The single crystal silicon substrate is made of n-type single crystal silicon substrate. - The chip 2 may be referred to as a semiconductor chip or a semiconductor layer.

[0053] The chip 2 has a first main surface 3 on one side and a second main surface 4 on the other side. The thickness of the chip 2 can be greater than 50 μm and less than 300 μm. The thickness of the chip 2 can be greater than 50 μm and less than 100 μm, greater than 100 μm and less than 150 μm, greater than 150 μm and less than 200 μm, greater than 200 μm and less than 250 μm, or greater than 250 μm and less than 300 μm.

[0054] A p-type collector region 5 is formed on the surface of the second main surface 4. An n-type charge storage region 6 is formed on the surface of the first main surface 3. The charge storage region 6 is formed at a distance from the collector region 5 on the first main surface 3 side.

[0055] In the chip 2, n is formed in the region between the collector region 5 and the charge storage region 6. - The drift region 7 is formed by a region located between the collector region 5 and the charge storage region 6 in the chip 2. A p-type body region 8 is formed on the surface of the charge storage region 6. A plurality of trench gate electrode structures 10 and a plurality of trench emitter electrode structures 11 are formed at intervals on the surface of the first main surface 3.

[0056] exist Figure 1 to Figure 7 , only one trench gate electrode structure 10 and one trench emitter electrode structure 11 adjacent to each other are shown. Hereinafter, the structure of the semiconductor device 1 will be described with attention paid to the structures of the one trench gate electrode structure 10 and the one trench emitter electrode structure 11 .

[0057] The trench gate electrode structure 10 and the trench emitter electrode structure 11 extend in a strip shape along an arbitrary first direction X in a plan view. The trench gate electrode structure 10 and the trench emitter electrode structure 11 are formed along a second direction Y intersecting the first direction X at intervals.

[0058] More specifically, the top view refers to a top view observed from the normal direction Z (hereinafter referred to as “normal direction Z”) of the first main surface 3. More specifically, the second direction Y is a direction orthogonal to the first direction X. The first direction X and the second direction Y are also tangent directions of the first main surface 3.

[0059] The trench pitch P0 between the trench gate electrode structure 10 and the trench emitter electrode structure 11 may be 0.1 μm or more and less than 0.6 μm. The trench pitch P0 may be 0.1 μm or more and less than 0.2 μm, 0.2 μm or more and less than 0.3 μm, 0.3 μm or more and less than 0.4 μm, 0.4 μm or more and less than 0.5 μm, or 0.5 μm or more and less than 0.6 μm. The trench pitch P0 is preferably 0.2 μm or more and less than 0.4 μm (e.g., about 0.25 μm).

[0060] The trench gate electrode structure 10 includes a gate trench 12, a gate insulating layer 13, a gate electrode layer 14, a plurality of gate electrode recesses 15 (space regions), and a plurality of gate cap insulating layers 16. The gate trench 12 penetrates the body region 8 and the charge storage region 6 from the first main surface 3 to reach the drift region 7.

[0061] The depth of the gate trench 12 may be greater than or equal to 2.0 μm and less than or equal to 4.0 μm. The depth of the gate trench 12 may be greater than or equal to 2.0 μm and less than or equal to 2.5 μm, greater than or equal to 2.5 μm and less than or equal to 3.0 μm, greater than or equal to 3.0 μm and less than or equal to 3.5 μm, or greater than or equal to 3.5 μm and less than or equal to 4.0 μm. The depth of the gate trench 12 is preferably greater than or equal to 2.5 μm and less than or equal to 3.5 μm (e.g., about 3.0 μm).

[0062] The second direction width of the gate trench 12 may also be 0.5 μm to 1.5 μm. The second direction width of the gate trench 12 may be 0.5 μm to 0.75 μm, 0.75 μm to 1.0 μm, 1.0 μm to 1.25 μm, or 1.25 μm to 1.5 μm. The second direction width of the gate trench 12 is preferably 0.5 μm to 1.0 μm (e.g., about 0.75 μm).

[0063] The gate insulating layer 13 may also be formed of silicon oxide. The gate insulating layer 13 is formed in a film shape along the inner wall of the gate trench 12. The gate insulating layer 13 defines a concave space in the gate trench 12.

[0064] The gate electrode layer 14 may also be formed of conductive polysilicon. The gate electrode layer 14 is controlled by a gate voltage. The gate electrode layer 14 is embedded in the gate trench 12 via the gate insulating layer 13. More specifically, the gate electrode layer 14 is embedded in a concave space defined by the gate insulating layer 13 in the gate trench 12. The upper end of the gate electrode layer 14 is located on the first main surface 3 side relative to the bottom of the main region 8.

[0065] In this embodiment, a plurality of gate electrode recesses 15 are formed on the main surface of the gate electrode layer 14 at intervals along the first direction X. Thus, the upper end portion of the gate electrode layer 14 has a concavo-convex structure including the plurality of gate electrode recesses 15 .

[0066] The interval between the plurality of adjacent gate electrode recesses 15 may be greater than 0 μm and less than 10 μm. The interval between the plurality of adjacent gate electrode recesses 15 is also the width of the first direction X of the portion sandwiched by two adjacent gate electrode recesses 15 in the gate electrode layer 14. The interval between the plurality of adjacent gate electrode recesses 15 may be greater than 0 μm and less than 2 μm, greater than 2 μm and less than 4 μm, greater than 4 μm and less than 6 μm, greater than 6 μm and less than 8 μm, or greater than 8 μm and less than 10 μm.

[0067] In this embodiment, the side walls of each gate electrode recess 15 are formed by the gate insulating layer 13 and the gate electrode layer 14. The bottom wall 22 of each gate electrode recess 15 is formed by the gate electrode layer 14. Figure 6as well as Figure 7 The bottom wall 22 of each gate electrode recess 15 is located in the region between the first main surface 3 and the bottom 50 of the emitter region 25 (described later) in the normal direction Z.

[0068] Reference Figure 6 Each gate electrode recess 15 is formed into a cone shape with a bottom area smaller than an opening area. An angle θ formed by the main surface of the gate electrode layer 14 and the sidewall of the gate electrode recess 15 in the gate electrode layer 14 may be greater than 90° and less than 105° (for example, about 102°).

[0069] A plurality of gate cover insulating layers 16 are buried in the gate trench 12 up to the upper end of the gate electrode layer 14 . More specifically, the gate cover insulating layer 16 is buried independently for each gate electrode recess 15 . Each gate cover insulating layer 16 is exposed from the opening of the gate trench 12 .

[0070] The trench emitter electrode structure 11 includes an emitter trench 17 , an emitter insulating layer 18 , an emitter electrode layer 19 , an emitter electrode recess 20 , and an emitter cap insulating layer 21 . The emitter trench 17 penetrates the body region 8 and the charge storage region 6 from the first main surface 3 to reach the drift region 7 .

[0071] The depth of the emitter trench 17 may be greater than or equal to 2.0 μm and less than or equal to 4.0 μm. The depth of the emitter trench 17 may be greater than or equal to 2.0 μm and less than or equal to 2.5 μm, greater than or equal to 2.5 μm and less than or equal to 3.0 μm, greater than or equal to 3.0 μm and less than or equal to 3.5 μm, or greater than or equal to 3.5 μm and less than or equal to 4.0 μm. The depth of the emitter trench 17 is preferably greater than or equal to 2.5 μm and less than or equal to 3.5 μm (e.g., about 3.0 μm). The depth of the emitter trench 17 is preferably substantially equal to the depth of the gate trench 12.

[0072] The second direction width of the emitter trench 17 may also be greater than 0.5 μm and less than 1.5 μm. The second direction width of the emitter trench 17 may be greater than 0.5 μm and less than 0.75 μm, greater than 0.75 μm and less than 1.0 μm, greater than 1.0 μm and less than 1.25 μm, or greater than 1.25 μm and less than 1.5 μm. The second direction width of the emitter trench 17 is preferably greater than 0.5 μm and less than 1.0 μm (e.g., about 0.75 μm). The second direction width of the emitter trench 17 is preferably substantially equal to the second direction width of the gate trench 12.

[0073] The emitter insulating layer 18 may also be formed of silicon oxide. The emitter insulating layer 18 is formed in a film shape along the inner wall surface of the emitter trench 17. The emitter insulating layer 18 defines a concave space in the emitter trench 17.

[0074] The emitter electrode layer 19 can be formed of conductive polysilicon. The emitter electrode layer 19 is controlled by an emitter voltage. The emitter voltage has a voltage value less than the gate voltage. The emitter voltage can also be a reference voltage (for example, a ground voltage). The emitter electrode layer 19 is buried in the emitter trench 17 through the emitter insulating layer 18. More specifically, the emitter electrode layer 19 is buried in a concave space defined by the emitter insulating layer 18 in the emitter trench 17.

[0075] In this embodiment, the emitter electrode recess 20 is formed by digging out substantially the entire main surface of the emitter electrode layer 19. In other words, the emitter electrode layer 19 is buried midway in the depth direction of the recessed space defined by the emitter insulating layer 18.

[0076] In this embodiment, the side walls of the emitter electrode recess 20 are formed by the emitter insulating layer 18. The bottom wall of the emitter electrode recess 20 is formed by the emitter electrode layer 19. The bottom wall of the emitter electrode recess 20 is located in the region between the first main surface 3 and the bottom 50 of the emitter region 25 (described later) in the normal direction Z. That is, the upper end of the emitter electrode layer 19 is located on the first main surface 3 side with respect to the bottom 50 of the emitter region 25. In the normal direction Z, the depth of the emitter electrode recess 20 may be substantially equal to the depth of the gate electrode recess 15.

[0077] The emitter cover insulating layer 21 is embedded in the upper surface of the emitter electrode layer 19 in the emitter trench 17. More specifically, the emitter cover insulating layer 21 is embedded in the emitter electrode recess 20. Thus, the emitter cover insulating layer 21 seals the emitter electrode layer 19. The emitter cover insulating layer 21 is exposed from the opening of the emitter trench 17.

[0078] In the surface portion of the body region 8, an n-type electrode is formed in a region along the side wall of the gate trench 12. + The emitter region 25 (first impurity region) of the type is formed. More specifically, a plurality of emitter regions 25 are formed along the sidewalls on one side and the other side of the gate trench 12 in the first direction X. The plurality of emitter regions 25 are respectively formed in a strip shape extending along the first direction X. The emitter region 25 is in contact with the sidewall of the gate trench 12. The emitter region 25 is also in contact with the sidewall of the emitter trench 17.

[0079] On the surface portion of the first main surface 3, in the region along the side wall of the gate trench 12, an emitter region 25, a body region 8, a charge storage region 6, and a drift region 7 are formed in order from the first main surface 3 toward the second main surface 4. In the body region 8, a channel CH of the IGBT is formed in a region facing the gate electrode layer 14 with the gate insulating layer 13 interposed therebetween.

[0080] Reference Figure 3 , Figure 4 , Figure 6 as well as Figure 7 A plurality of contact grooves 31 are formed on the surface portion of the first main surface 3. The plurality of contact grooves 31 are formed at intervals along the first direction X. The plurality of contact grooves 31 are respectively formed in a strip shape extending along the second direction Y. The first direction width of each contact groove 31 is smaller than the second direction width of the gate groove 12. The first direction width of each contact groove 31 may be, for example, not less than 0.3 μm and not more than 1.0 μm.

[0081] More specifically, each contact groove 31 penetrates the side wall of the gate groove 12 from the inner region of the corresponding gate cover insulating layer 16 and is led to the surface portion of the first main surface 3. In this embodiment, each contact groove 31 penetrates the side wall on one side and the side wall on the other side of the gate groove 12 from the inner region of the gate cover insulating layer 16 in the first direction X. The first direction width of each contact groove 31 is smaller than the first direction width of the corresponding gate cover insulating layer 16.

[0082] Each contact trench 31 includes a first intersection region 33 intersecting the gate electrode layer 14 in a plan view. In the first intersection region 33, the sidewall and the bottom wall of each contact trench 31 are formed by the gate cap insulating layer 16.

[0083] Each contact trench 31 includes a second intersection region 34 intersecting with the emitter electrode layer 19 in a plan view. In the second intersection region 34, the sidewall and the bottom wall of each contact trench 31 are formed by the emitter cover insulating layer 21.

[0084] Each contact trench 31 further includes a contact region 35 extending from the first intersection region 33 to the outside of the gate trench 12. The contact region 35 may also be referred to as a connection region that connects the first intersection region 33 and the second intersection region 34 in the region between the gate trench 12 and the emitter trench 17 when viewed from above. In the contact region 35, the bottom wall of each contact trench 31 is formed by the body region 8, and the side wall of each contact trench 31 is formed by the emitter region 25. That is, in the contact region 35, the emitter region 25 is exposed at the side wall of the contact trench 31.

[0085] Each contact trench 31 further includes a lead portion 32 extending outward from one side wall of the emitter trench 17. Each lead portion 32 penetrates one side wall of the emitter trench 17 from the surface of the first main surface 3 and reaches the emitter trench 17.

[0086] The sidewalls of each contact trench 31 are formed to have uniform surfaces in the first intersection region 33 , the second intersection region 34 , and the contact region 35 . The bottom walls of each contact trench 31 are formed to have uniform surfaces in the first intersection region 33 , the second intersection region 34 , and the contact region 35 .

[0087] In the first intersection region 33, the upper end of the gate electrode layer 14 is located on the first main surface 3 side with respect to the bottom 50 of the emitter region 25. Figure 6 as well as Figure 7 The emitter region 25 has an opposing portion 40 that is opposed to the gate electrode layer 14 via the gate insulating layer 13 below the peripheral portions 9 on both sides of the first intersection region 33 in the first direction X.

[0088] The gate electrode layer 14 has an electrode concavo-convex structure formed by a first intersection region 33 formed in each contact groove 31 along the first direction X and a gate electrode concave portion 15 in the peripheral portion 9. A portion of the upper surface of the gate electrode layer 14 (the upper surface 23 of the convex portion of the electrode concavo-convex structure) is exposed between adjacent contact grooves 31.

[0089] The gate electrode recess 15 is formed across the peripheral portion 9 on one side and the peripheral portion 9 on the other side of the first intersection region 33 in the first direction X. Figure 6 as well as Figure 7 The gate cover insulating layer 16 includes a first portion 47 disposed in the first intersection region 33 and a second portion 48 disposed in the peripheral portion 9 on one side of the first direction X and the peripheral portion 9 on the other side of the first portion 47 .

[0090] The peripheral portion 9 of the first intersection region 33 may be, for example, a region from the side wall of the contact trench 31 to the side wall of the gate electrode recess 15. The peripheral portion 9 may be, for example, a region in a range of 0.05 μm or more and 0.5 μm or less from the side wall of the first intersection region 33. That is, in this embodiment, the side wall of the gate electrode recess 15 is formed at a distance of 0.05 μm or more and 0.5 μm or less on both sides of the contact trench 31 in the first direction X.

[0091] The arrangement of the plurality of contact grooves 31 is arbitrary. The plurality of contact grooves 31 may be formed at equal intervals along the first direction X. The plurality of contact grooves 31 may be formed at unequal intervals along the first direction X.

[0092] In the body region 8, a p-type contact groove 31 is formed in a region along the bottom wall of each contact trench 31. + The contact region 36 may also be formed in the main body region 8 in the region along the bottom wall and the side wall of each contact groove 31.

[0093] The contact region 36 has an exposed surface exposed from the bottom wall of the contact groove 31. The exposed surface of the contact region 36 is formed in the region between the first main surface 3 and the bottom of the main body region 8. More specifically, the exposed surface of the contact region 36 is formed in the region between the first main surface 3 and the bottom 50 of the emitter region 25. In this embodiment, the main body region 8 has a main body region protrusion 49 that selectively protrudes toward the first main surface 3 side along the contact groove 31. The contact region 36 is formed at the front end of the main body region protrusion 49. The main body region protrusion 49 is sandwiched by the emitter region 25 in the first direction X.

[0094] exist Figure 1 to Figure 3 , an example is shown in which the contact region 36 is shallowly formed on the bottom surface of the contact groove 31 by a single ion implantation. However, the contact region 36 may be formed deeper by adjusting the number of ion implantations and the energy of the ion implantations. For example, the contact region 36 may be formed deeper than the bottom 50 of the emitter region 25.

[0095] An interlayer insulating layer 41 is formed on the first main surface 3 . The interlayer insulating layer 41 covers the trench gate electrode structure 10 and the trench emitter electrode structure 11 . The interlayer insulating layer 41 covers the gate cover insulating layer 16 exposed from the gate trench 12 and the emitter cover insulating layer 21 exposed from the emitter trench 17 .

[0096] The interlayer insulating layer 41 may also be formed of silicon oxide or silicon nitride. The interlayer insulating layer 41 may also have a stacked structure including an oxide film (SiO2 film) and a nitride film (SiN film). The oxide film (SiO2 film) may include an NSG (Nondoped Silicon Glass) film containing no impurities and / or a PSG (Phosphorus Silicon Glass) film containing phosphorus.

[0097] The interlayer insulating layer 41 may also have a stacked structure including an NSG film and a PSG film stacked in sequence from the first main surface 3. The thickness of the NSG film may be Above and The following (for example The thickness of the PSG film can be Above and The following (for example about).

[0098] A plurality of contact holes 42 are formed in the interlayer insulating layer 41. The plurality of contact holes 42 are connected to the corresponding contact trenches 31. That is, the plurality of contact holes 42 are formed at intervals along the first direction X and are formed in a strip shape extending along the second direction Y.

[0099] The plurality of contact holes 42 penetrate the interlayer insulating layer 41 and are respectively connected to the corresponding contact trenches 31 . Thus, the plurality of contact holes 42 form one emitter contact trench 31 , 42 between the plurality of contact holes 42 and the corresponding contact trenches 31 .

[0100] The first direction width of each contact hole 42 may also be greater than the first direction width of each contact groove 31. That is, the first direction width of each contact hole 42 may be equal to the first direction width of each contact groove 31, or may exceed the first direction width of each contact groove 31. In the case where the first direction width of each contact hole 42 exceeds the first direction width of each contact groove 31, the inner wall of each contact hole 42 may also surround the inner wall of the corresponding contact groove 31.

[0101] The arrangement of the plurality of contact holes 42 is arbitrary and is adjusted according to the arrangement of the contact trench 31. The plurality of contact holes 42 may be formed at equal intervals along the first direction X. The plurality of contact holes 42 may be formed at unequal intervals along the first direction X.

[0102] An emitter main surface electrode layer 43 is formed on the interlayer insulating layer 41. The emitter main surface electrode layer 43 enters the contact hole 42 and the contact groove 31 (i.e., the emitter contact grooves 31, 42) from the interlayer insulating layer 41. The emitter main surface electrode layer 43 may also include a stacked structure of a barrier layer such as titanium and an electrode layer such as tungsten. In this embodiment, a plurality of emitter contact electrode layers 51 are formed by the portion of the emitter main surface electrode layer 43 located in the plurality of contact grooves 31. Thus, a structure in which the plurality of emitter contact electrode layers 51 are buried in the surface portion of the chip 2 is formed.

[0103] The emitter contact electrode layers 51 have an arrangement and shape corresponding to the arrangement and shape of the contact trenches 31. That is, the emitter contact electrode layers 51 are formed at intervals along the first direction X and are formed in stripes extending along the second direction Y.

[0104] In the first intersection region 33 where each emitter contact electrode layer 51 intersects with the gate electrode layer 14 in a plan view, the emitter contact electrode layer 51 is opposed to the gate electrode layer 14 via the gate cover insulating layer 16 in the normal direction Z and the first direction X. Each emitter contact electrode layer 51 is insulated from the gate electrode layer 14 by the gate cover insulating layer 16. The first direction width of each emitter contact electrode layer 51 is smaller than the first direction width of the gate trench 12.

[0105] Each emitter contact electrode layer 51 penetrates the side wall of the gate trench 12 from the inner region of the corresponding gate cover insulating layer 16 and is led out to the surface portion of the first main surface 3. In this embodiment, each emitter contact electrode layer 51 penetrates the side wall on one side and the side wall on the other side of the gate trench 12 from the inner region of the gate cover insulating layer 16 in the second direction Y. The first direction width of each emitter contact electrode layer 51 is smaller than the first direction width of the corresponding gate cover insulating layer 16.

[0106] In the second intersection region 34 where each emitter contact electrode layer 51 intersects with the emitter electrode layer 19 in a plan view, the emitter contact electrode layer 51 is opposed to the emitter electrode layer 19 via the emitter cover insulating layer 21 in the normal direction Z and the first direction X. Each emitter contact electrode layer 51 is insulated from the emitter electrode layer 19 by the emitter cover insulating layer 21. The first direction width of each emitter contact electrode layer 51 is smaller than the first direction width of the emitter trench 17.

[0107] Each emitter contact electrode layer 51 is connected to the body region 8 (contact region 36 ) exposed from the bottom wall of the contact trench 31 in the contact region 35 , and is connected to the emitter region 25 exposed from the side wall of the contact trench 31 .

[0108] A collector electrode layer 61 is formed on the second main surface 4 of the chip 2. The collector electrode layer 61 is connected to the collector region 5. Although not shown in the figure, a gate main surface electrode layer having the same structure as the emitter main surface electrode layer 43 may be formed on the interlayer insulating layer 41. The gate main surface electrode layer may also be electrically connected to the gate electrode layer 14 via a gate contact hole formed in the interlayer insulating layer 41.

[0109] <Description of the method for manufacturing semiconductor device 1>

[0110] Figure 8A to Figure 8N It is a diagram showing an example of a method for manufacturing the semiconductor device 1 . Figure 8A to Figure 8N is with Figure 1 A cross-sectional perspective view of the corresponding parts.

[0111] Reference Fig. 8A , first, prepare n - Then, a p-type collector region 5 and an n-type charge storage region 6 are formed in the chip 2. The collector region 5 is formed by introducing p-type impurities into the second main surface 4 of the chip 2. The collector region 5 can also be formed on the surface portion of the second main surface 4 of the chip 2 by ion implantation through an ion implantation mask (not shown).

[0112] The charge storage region 6 is formed by introducing n-type impurities into the first main surface 3. The charge storage region 6 may be formed on the surface portion of the first main surface 3 by ion implantation through an ion implantation mask (not shown).

[0113] Next, refer to Figure 8B A mask 71 having a predetermined pattern is formed on the first main surface 3. The mask 71 has a plurality of openings 72 that expose regions where the gate trenches 12 and the emitter trenches 17 are to be formed.

[0114] Next, refer to Figure 8C , and the unnecessary part of the chip 2 is removed from the first main surface 3. The unnecessary part of the chip 2 can also be removed by etching (for example, wet etching) through the mask 71. Thus, the gate trench 12 and the emitter trench 17 are formed. Thereafter, the mask 71 is removed.

[0115] Next, refer to Fig.8D The base insulating layer 73 serving as the base of the gate insulating layer 13 and the emitter insulating layer 18 is formed so as to cover the first main surface 3. The base insulating layer 73 may also be formed by subjecting the first main surface 3 to oxidation treatment.

[0116] The oxidation treatment method may be a thermal oxidation treatment method or a wet oxidation treatment method. The base insulating layer 73 may also include silicon oxide. The base insulating layer 73 may also be formed by a CVD (chemical vapor deposition) method instead of the oxidation treatment method.

[0117] Next, refer to Fig. 8E A first base conductor layer 74 serving as a base for the gate electrode layer 14 and the emitter electrode layer 19 is formed on the first main surface 3. The first base conductor layer 74 may also be a conductive polysilicon layer. The first base conductor layer 74 may also be formed by a CVD method. The CVD method may also be a LP-CVD (Low Pressure-CVD) method.

[0118] Next, unnecessary portions of the first base conductor layer 74 are removed. The unnecessary portions of the first base conductor layer 74 are removed until at least the base insulating layer 73 is exposed. The unnecessary portions of the first base conductor layer 74 may also be removed by etching (for example, wet etching).

[0119] Unnecessary portions of the first base conductor layer 74 may be removed by etching (for example, wet etching) after the main surface of the first base conductor layer 74 is planarized by CMP (Chemical Mechanical Polishing).

[0120] Next, refer to Figure 8FA mask 75 having a predetermined pattern is formed on the first main surface 3. The mask 75 has a plurality of openings 76 that expose regions where the gate electrode recesses 15 and the emitter electrode recesses 20 are to be formed.

[0121] Next, unnecessary portions of the gate electrode layer 14 and the emitter electrode layer 19 are removed. The unnecessary portions of the gate electrode layer 14 and the emitter electrode layer 19 can also be removed by etching (for example, wet etching) through the mask 75. Thus, the gate electrode recess 15 and the emitter electrode recess 20 are formed.

[0122] Afterwards, refer to Figure 8G , and remove the mask 75. The gate electrode recess 15 and the emitter electrode recess 20 may be formed separately through different masks (not shown). That is, the gate electrode recess 15 and the emitter electrode recess 20 may be formed to have different depths.

[0123] Next, refer to Figure 8H A base insulating layer 77 serving as a base for the gate cover insulating layer 16 and the emitter cover insulating layer 21 is formed on the first main surface 3. The base insulating layer 77 may include silicon oxide. The base insulating layer 77 may also be formed by a CVD method. The CVD method may also be an LP-CVD method.

[0124] Next, refer to Figure 8I , removing unnecessary portions of the base insulating layer 77. The unnecessary portions of the base insulating layer 73 may also be removed by etching (eg, wet etching). Thus, the gate cover insulating layer 16 and the emitter cover insulating layer 21 are formed.

[0125] In this step, the portion of the base insulating layer 73 covering the first main surface 3 is also removed. Thus, the gate insulating layer 13 and the emitter insulating layer 18 are formed. Thus, the trench gate electrode structure 10 and the trench emitter electrode structure 11 are formed.

[0126] Next, refer to Figure 8J , forming a p-type main region 8 and an n-type main region 8 in the chip 2 + The body region 8 is formed by introducing p-type impurities into the first main surface 3. The body region 8 may also be formed on the surface of the first main surface 3 by ion implantation through an ion implantation mask (not shown).

[0127] The emitter region 25 is formed by introducing n-type impurities into the first main surface 3. The emitter region 25 may be formed on the surface of the first main surface 3 by ion implantation through an ion implantation mask (not shown).

[0128] Next, refer to Figure 8K, forming an interlayer insulating layer 41 on the first main surface 3. The interlayer insulating layer 41 is formed on the first main surface 3 to cover the trench gate electrode structure 10 and the trench emitter electrode structure 11. This process may include sequentially forming an NSG film (e.g. ) and PSG membranes (e.g. ) process.

[0129] Next, refer to Figure 8L A mask 78 having a predetermined pattern is formed on the interlayer insulating layer 41. The mask 78 has a plurality of openings 79 that expose regions where the contact trenches 31 and the contact holes 42 are to be formed.

[0130] Next, refer to Figure 8M , removing unnecessary portions of the interlayer insulating layer 41, unnecessary portions of the gate cover insulating layer 16, and unnecessary portions of the emitter cover insulating layer 21. The unnecessary portions such as the interlayer insulating layer 41 may also be removed by etching through the mask 78 (eg, dry etching).

[0131] Furthermore, in this process, after removing unnecessary portions such as the interlayer insulating layer 41, unnecessary portions of the chip 2 are removed. The unnecessary portions of the chip 2 may also be removed by etching through the mask 78 (eg, dry etching).

[0132] Thus, the contact trench 31 is formed in the first main surface 3, and the contact hole 42 communicating with the contact trench 31 is formed in the interlayer insulating layer 41. Thereafter, the mask 78 is removed.

[0133] Next, the contact region 36 is formed on the surface of the first main surface 3. More specifically, the contact region 36 is formed in the region along the bottom wall of the contact groove 31 on the surface of the body region 8. The contact region 36 may also be formed in the region along the sidewall and bottom wall of the contact groove 31.

[0134] The contact region 36 is formed by introducing p-type impurities into the contact trench 31. The contact region 36 may also be introduced into the contact trench 31 by ion implantation through an ion implantation mask (not shown). Thus, the contact region 36 is formed along the bottom wall of the contact trench 31.

[0135] The contact area 36 can also be formed by Figure 8J In the process of introducing p-type impurities into the first main surface 3, the contact region 36 is formed. In this case, the contact region 36 can also be formed on the surface portion of the first main surface 3 by ion implantation through an ion implantation mask (not shown). Through this process, the contact region 36 along the bottom wall of the contact trench 31 is also formed.

[0136] Next, refer to Figure 8N, an emitter main surface electrode layer 43 is formed on the interlayer insulating layer 41. Furthermore, an emitter contact electrode layer 51 is formed through a portion of the emitter main surface electrode layer 43 that enters the contact groove 31. In addition, a collector electrode layer 61 is formed on the second main surface 4 of the chip 2. Through the above steps, the semiconductor device 1 is formed.

[0137] <<Relationship between the Depth of the Emitter Region 25 and the Areas of the Channel Formation Regions 102 and 202>>

[0138] Fig. 9A This is a diagram for explaining the channel formation of the semiconductor device 101 under condition 1. Fig. 9B It is a diagram for explaining the arrangement pattern of the emitter region 25 and the contact region 36 of the semiconductor device 101 under condition 1. Fig. 10A This is a diagram for explaining the channel formation of the semiconductor device 201 under condition 2. Fig. 10B It is a diagram for explaining the arrangement pattern of the emitter region 25 and the contact region 36 of the semiconductor device 201 under condition 2. In the semiconductor devices 101 and 201 , the same reference numerals are used to indicate the structures corresponding to those of the semiconductor device 1 , and the description thereof will be omitted.

[0139] Reference Fig. 9A The semiconductor device 101 has the same structure as the semiconductor device 1. The emitter region 25 is formed deeper than the upper surface of the gate electrode layer 14 in the gate electrode recess 15 (the bottom wall 22 of the gate electrode recess 15). That is, the bottom 50 of the emitter region 25 is located on the second main surface 4 side (the opposite side of the first main surface 3) relative to the upper surface of the gate electrode layer 14 (the bottom wall 22 of the gate electrode recess 15) at the peripheral portions 9 on both sides of the first intersection region 33 in the first direction X. The depth D1 of the emitter region 25 from the first main surface 3 is greater than the depth D2 of the gate electrode recess 15 from the first main surface 3 (D1>D2). Therefore, the emitter region 25 has an opposing portion 40 that is opposed to the gate electrode layer 14 via the gate insulating layer 13 below the peripheral portions 9 on both sides of the first intersection region 33 in the first direction X.

[0140] Reference Fig. 9B The width W1 of the emitter region 25 in the first direction X is, for example, 1.0 μm or less, preferably 0.5 μm or more and 1.0 μm or less. The width W2 of the contact region 36 in the first direction X may be equal to or slightly wider than the first direction width of the contact groove 31 described above.

[0141] Reference Fig. 10AIn the semiconductor device 201, the emitter region 25 is formed shallower than the upper surface of the gate electrode layer 14 in the gate electrode recess 15 (the bottom wall 22 of the gate electrode recess 15). That is, the bottom 50 of the emitter region 25 is located on the first main surface 3 side relative to the upper surface of the gate electrode layer 14 (the bottom wall 22 of the gate electrode recess 15) at the peripheral portion 9 on both sides of the first intersection region 33 in the first direction X. The depth D1 of the emitter region 25 from the first main surface 3 is less than the depth D2 of the gate electrode recess 15 from the first main surface 3 (D1<D2). Therefore, in the semiconductor device 201, there is no Fig. 9A In the facing portion 40 shown, the emitter region 25 does not face the gate electrode layer 14 below the peripheral portions 9 on both sides of the first intersection region 33 in the first direction X.

[0142] Reference Fig. 10B The width W3 of the emitter region 25 in the first direction X exceeds 1.0 μm, for example. The width W4 of the contact region 36 in the first direction X may be equal to or slightly wider than the first direction width of the contact trench 31 .

[0143] Reference Fig. 9A as well as Fig. 10A The first direction width W5 of the gate electrode recess 15 is set wider than the first direction width W6 of the contact groove 31. This is to take into account the patterning of the mask 78 for forming the contact groove 31 (see Figure 8L as well as Figure 8M ) to ensure a margin. By ensuring this margin, the emitter contact electrode layer 51 is contained within the range of the gate cover insulating layer 16, and the emitter contact electrode layer 51 is reliably insulated from the gate electrode layer 14 by the gate cover insulating layer 16. Thus, a short circuit between the emitter and the gate is avoided. That is, it is necessary to make the digging width of the gate electrode layer 14 (the width W5 of the gate electrode recess 15) wider than the contact dimension of the emitter contact electrode layer 51 (the width W6 of the contact groove 31).

[0144] Therefore, if Fig. 10A As in the semiconductor device 201, if the depth D1 of the emitter region 25 is less than the depth D2 of the gate electrode recess 15 (D1<D2), the area below the peripheral portion 9 becomes an area where the emitter region 25 does not exist, and the channel CH can be formed in this area, but the main current path cannot be formed. Therefore, in the semiconductor device 201, the area in the main region 8 other than the area below the gate electrode recess 15 is an area in which the main current path can be formed in the channel formation region 202 where the channel CH can be formed, and the area below the gate electrode recess 15 becomes an area where it is difficult to form the main current path. As a result, there is a tendency for the channel width to decrease and the on-resistance to increase. Fig. 10A In FIG. 1 , the channel formation region 202 is indicated by hatching including solid lines and dotted lines.

[0145] In addition, if Fig. 10B As shown, there is a constraint that the width W3 of the emitter region 25 must be designed to be relatively wide in consideration of the etching margin. This is because if the width W3 of the emitter region 25 is too narrow, the portion of the emitter region 25 facing the gate electrode layer 14 will be greatly reduced after the gate electrode recess 15 is formed.

[0146] In contrast, Fig. 9A As in the semiconductor device 101, if the depth D1 of the emitter region 25 is greater than the depth D2 of the gate electrode recess 15 (D1>D2), the emitter region 25 also exists in the lower region of the peripheral portion 9, and the main current path can be formed in this region. Therefore, in the semiconductor device 101, the entire region in the first direction X of the main region 8 including the lower region of the gate electrode recess 15 is the channel formation region 102 that can form the main current path. As a result, compared with the semiconductor device 201, the channel width can be increased and the on-resistance can be reduced. Fig. 9A In FIG. 1 , the channel formation region 102 is indicated by hatching including solid lines and dotted lines.

[0147] In addition, when designing the width W1 of the emitter region 25, it is not necessary to consider the etching margin and the pattern of the gate electrode recess 15. This is because even after the gate electrode recess 15 is formed, the opposing portion 40 of the emitter region 24 can be ensured below the peripheral portion 9, thereby ensuring the channel formation region 102 having a sufficient channel width. Therefore, the width W1 of the emitter region 25 can be narrowed compared to the width W3 of the emitter region 25 of the semiconductor device 201.

[0148] <Relationship between the Depth of the Emitter Region 25 and the Characteristics of the Semiconductor Devices 101 and 201>

[0149] Next, refer to Figure 11 to Figure 14 , the relationship between the depth of the emitter region 25 and the characteristics of the semiconductor devices 101 and 201 will be described.

[0150] Fig.11 This is a graph of short-circuit waveforms of the semiconductor device 101 under condition 1 and the semiconductor device 201 under condition 2 obtained by simulation. Fig.11 In the graph, the left vertical axis is the collector current IC [A], the right vertical axis is the collector-emitter voltage VCE [V], and the horizontal axis is time [s]. Fig.11, the gate voltages under conditions 1 and 2 are represented by dashed curves, the collector voltages under conditions 1 and 2 are represented by solid curves, and the collector currents under conditions 1 and 2 are represented by dashed-dotted curves.

[0151] Referring to the gate voltage, collector voltage, and collector current of condition 1, it was confirmed that the semiconductor device 101 did not exceed the stable value after the rise of the short-circuit wave, and that latch-up behavior did not occur even with the passage of time. On the other hand, referring to the gate voltage, collector voltage, and collector current of condition 2, it was confirmed that the collector current overshoots and greatly exceeds the stable value shown in condition 1, resulting in latch-up behavior.

[0152] As can be seen from the above, according to the semiconductor device 101 , the breakdown resistance can be improved by including the emitter region 25 having the width W1 which is narrower than the width W3 of the emitter region 25 of the semiconductor device 201 .

[0153] Fig.12 This is a graph showing the current-voltage characteristics of the semiconductor device 101 under condition 1 and the semiconductor device 201 under condition 2 obtained by simulation. Fig.13 It is a magnified representation Fig.12 A portion of a graph of . Fig.12 as well as Fig.13 In the figure, the vertical axis is the collector current IC[A], and the horizontal axis is the collector-emitter voltage VCE[V]. Fig.13 Shown in Fig.12 A graph showing a collector-emitter voltage VCE in the range of 0 to 2V.

[0154] exist Fig.12 In FIG. 1 , the solid line curve represents the characteristics of the semiconductor device 101 under condition 1, and the dotted line curve represents the characteristics of the semiconductor device 201 under condition 2. Conditions 1 and 2 both represent current-voltage characteristics when the collector-emitter voltage VCE is changed from 0V to 10V.

[0155] Referring to the characteristics of condition 1, in the semiconductor device 101, the collector-emitter voltage VCE when the collector current IC is 20A, 40A, 60A, 80A, and 100A is 1.26V, 1.60V, 1.91V, 2.25V, and 2.66V, respectively. On the other hand, referring to the characteristics of condition 2, in the semiconductor device 201, the collector-emitter voltage VCE when the collector current IC is 20A, 40A, 60A, 80A, and 100A is 1.28V, 1.65V, 2.01V, 2.42V, and 3.20V, respectively.

[0156] As can be seen from the above, according to the semiconductor device 101 , the collector-emitter voltage VCE required for rising can be lowered compared to the semiconductor device 201 , and thus the conduction loss can be reduced.

[0157] Fig.14 The graph is a graph of the current-voltage characteristics of the semiconductor device 101 under condition 1 and the semiconductor device 201 under condition 2 obtained by simulation. Fig.14 In the figure, the vertical axis is the collector current IC[A] and the horizontal axis is the gate-emitter voltage VGE[V]. Fig.14 In FIG. 1 , the solid line curve represents the characteristics of the semiconductor device 101 under condition 1, and the dotted line curve represents the characteristics of the semiconductor device 201 under condition 2. Conditions 1 and 2 both represent current-voltage characteristics when the gate-emitter voltage VGE is changed from 0V to 15V.

[0158] <Description of the Structure of Semiconductor Device 81 (Second Embodiment)>

[0159] Fig.15 1 is a schematic cross-sectional perspective view showing a partial region of a semiconductor device 81 according to a second embodiment of the present disclosure. Fig.16 Yes means Fig.15 Schematic cross-sectional view of a portion of a semiconductor device 81. Fig.17 Yes means Fig.15 Schematic cross-sectional view of a portion of a semiconductor device 81. Hereinafter, structures corresponding to those described in relation to the semiconductor device 1 are denoted by the same reference numerals and description thereof will be omitted.

[0160] In the semiconductor device 1 described above, an example is described in which the gate electrode layer 14 has a concave-convex structure including a plurality of gate electrode recesses 15. In contrast, in the semiconductor device 81, the gate electrode layer 14 has a flat structure in which the depth position of the upper surface 82 is constant as a whole. More specifically, referring to Fig.16 as well as Fig.17 The upper surface 82 of the gate electrode layer 14 is located in the region between the first main surface 3 and the bottom 50 of the emitter region 25 in the normal direction Z. Thus, similar to the semiconductor device 1, the emitter region 25 has an opposing portion 40 that is opposed to the gate electrode layer 14 via the gate insulating layer 13 near the first intersection region 33 in the first direction X.

[0161] Reference Fig.16, the gate covering insulating layer 16 has an integral structure extending along the first direction X across multiple contact grooves 31. The gate covering insulating layer 16 has an insulating layer concave-convex structure formed by insulating layer recesses 83 formed in the first intersection area 33 of each contact groove 31. The emitter contact electrode layer 51 is buried in the insulating layer recess 83. More specifically, the gate covering insulating layer 16 may also include a base 85 having a flat lower surface 84 connected to the upper surface 82 of the gate electrode layer 14 along the first direction X, and a convex portion 86 protruding from the base 85 between adjacent insulating layer recesses 83. The concave-convex structure of the gate covering insulating layer 16 is formed by alternately arranging the convex portions 86 and the insulating layer recesses 83 along the first direction X.

[0162] As described above, the semiconductor device 81 can also achieve the same effects as those described for the semiconductor device 1. That is, the entire region of the body region 8 in the first direction X can be used as the channel formation region 102 where the channel CH can be formed. The semiconductor device 81 can be formed by etching the first base conductor layer 74 in the method for manufacturing the semiconductor device 1 (see Figure 8F ), the first base conductor layer 74 is not patterned, but substantially the entire main surface of the first base conductor layer 74 is dug out to manufacture.

[0163] <Description of the Structure of Semiconductor Device 91 (Second Embodiment)>

[0164] Fig.18 1 is a schematic cross-sectional perspective view showing a partial region of a semiconductor device 91 according to a third embodiment of the present disclosure. Hereinafter, structures corresponding to those described for the semiconductor device 1 are denoted by the same reference numerals and description thereof will be omitted.

[0165] In the aforementioned semiconductor device 1, an example in which a p-type collector region 5 is formed on the surface portion of the second main surface 4 is described. In contrast, in the semiconductor device 91, an n-type drain region 92 is formed on the surface portion of the second main surface 4 instead of the p-type collector region 5. Thus, the semiconductor device 91 has a basic form of a MISFET (Metal Insulator Semiconductor Field Effect Transistor) having a trench gate. The description of the aforementioned semiconductor device 1 replaces "emitter" with "source" and "collector" with "drain", and is applicable to the description of the semiconductor device 91.

[0166] As described above, semiconductor device 91 can also achieve the same effects as those described for semiconductor device 1. Semiconductor device 91 can be manufactured by forming n-type drain region 92 instead of p-type collector region 5 in the manufacturing method of semiconductor device 1 and by simply changing the layout of each mask.

[0167] Although the embodiments of the present disclosure have been described, the present disclosure can also be implemented in other forms.

[0168] For example, in each of the above-mentioned embodiments, a structure in which the conductivity type of each semiconductor portion is reversed may be adopted. That is, a p-type portion may be changed to an n-type portion, and an n-type portion may be changed to a p-type portion.

[0169] In the above-mentioned embodiments, an example in which the chip 2 is made of single crystal silicon is described. However, the chip 2 may include SiC. In addition, the chip 2 may also be made of SiC single crystal.

[0170] The embodiments of the present disclosure described above are illustrative in all aspects and should not be interpreted restrictively, but are intended to include modifications in all aspects.

[0171] The following features of the supplementary notes can be extracted from the description of this specification and the drawings.

[0172] [Additional Note 1-1]

[0173] A semiconductor device 1, 81, 91, 101, comprising:

[0174] A chip 2 having a first main surface 3 formed with a gate trench 12 having a bottom wall and side walls and extending in a first direction X;

[0175] A body region 8 of a first conductivity type, formed on a surface portion of the first main surface 3 along the sidewall of the gate trench 12;

[0176] A first impurity region 25 of a second conductivity type, formed on a surface portion of the body region 8 along the sidewall of the gate trench 12;

[0177] a gate insulating layer 13 formed on the bottom wall and the side wall of the gate trench 12;

[0178] a gate electrode 14 embedded in the gate trench 12 and facing the body region 8 and the first impurity region 25 via the gate insulating layer 13;

[0179] a contact trench 31 , comprising an intersection region 33 intersecting the gate trench 12 , and extending from the intersection region 33 to an outer side of the gate trench 12 along a second direction Y intersecting the first direction X; and

[0180] a contact electrode 51 embedded in the contact trench 31 and electrically connected to the main region 8 and the first impurity region 25 in the contact trench 31;

[0181] In at least the intersection region 33 and the peripheral portion 9 of the intersection region 33 in the gate trench 12 , a space region 15 is formed on the gate electrode 14 .

[0182] A cover insulating layer 16 is embedded in the space region 15 , and the cover insulating layer covers the upper surface 22 of the gate electrode 14 in the intersection region 33 and the peripheral portion 9 of the intersection region 33 , and insulates the gate electrode 14 from the contact electrode 51 .

[0183] The first impurity region 25 is formed deeper than the upper surface 22 of the gate electrode 14 in the peripheral portion 9 of the intersection region 33 .

[0184] [Additional Notes 1-2]

[0185] The semiconductor device 1, 81, 91, 101 according to Supplement 1-1, wherein:

[0186] The first impurity region 25 includes an opposing portion 40 that opposes the gate electrode 14 below the peripheral portion 9 of the intersection region 33 .

[0187] [Notes 1-3]

[0188] The semiconductor device 1, 81, 91, 101 according to Supplement 1-1 or Supplement 1-2, wherein:

[0189] The contact electrode 51 is connected to the body region 8 at the bottom wall of the contact trench 31 , and is connected to the first impurity region 25 at the side wall of the contact trench 31 .

[0190] [Notes 1-4]

[0191] The semiconductor device 1, 81, 91, 101 according to any one of Supplementary Notes 1-1 to 1-3, wherein:

[0192] The width W1 of the first impurity region 25 in the first direction X is less than or equal to 1.0 μm.

[0193] [Notes 1-5]

[0194] The semiconductor device 1, 81, 91, 101 according to Supplement 1 to 4, wherein:

[0195] The width W1 of the first impurity region 25 is greater than or equal to 0.5 μm and less than or equal to 1.0 μm.

[0196] [Appendix 1-6]

[0197] The semiconductor device 1, 81, 91, 101 according to any one of Supplementary Notes 1-1 to 1-5, wherein:

[0198] The peripheral portion 9 of the intersection region 33 includes a region ranging from 0.05 μm to 0.5 μm inclusive from the intersection region 33 .

[0199] [Appendix 1-7]

[0200] The semiconductor device 1, 91, 101 according to any one of Supplementary Notes 1-1 to 1-6, wherein:

[0201] The plurality of contact grooves 31 are formed at intervals along the first direction X.

[0202] The gate electrode 14 has an electrode concavo-convex structure formed by a gate electrode concave portion 15 formed along the first direction X at the intersection region 33 of each contact groove 31 and the peripheral portion 9 of the intersection region 33.

[0203] The cover insulating layer 16 is embedded in the gate electrode recess 15 .

[0204] [Appendix 1-8]

[0205] The semiconductor device 1, 91, 101 according to Supplement 1-7, wherein:

[0206] The cover insulating layer 16 is independently buried in each of the gate electrode recesses 15.

[0207] Between adjacent contact trenches 31 , a portion of the upper surface 23 of the gate electrode 14 is exposed.

[0208] [Appendix 1-9]

[0209] The semiconductor device 1, 91, 101 according to Supplement 1-7 or Supplement 1-8, wherein:

[0210] The gate electrode recess 15 is formed across the peripheral portion 9 on one side and the peripheral portion 9 on the other side of the intersection region 33 in the first direction X.

[0211] The insulating cover layer 16 includes a first portion 47 disposed in the intersection region 33 and a second portion 48 disposed in the peripheral portion 9 on one side and the peripheral portion 9 on the other side in the first direction X with respect to the first portion 47 .

[0212] [Notes 1-10]

[0213] The semiconductor device 1, 91, 101 according to any one of Supplementary Notes 1-7 to 1-9, wherein:

[0214] The width W6 of the contact groove 31 in the first direction X is greater than or equal to 0.3 μm and less than or equal to 1.0 μm.

[0215] The side walls of the gate electrode recess 15 are formed at both sides of the contact trench 31 in the first direction X with a spacing of 0.05 μm or more and 0.5 μm or less.

[0216] [Appendix 1-11]

[0217] The semiconductor device 81 according to any one of Supplementary Notes 1-1 to 1-6, wherein:

[0218] The plurality of contact grooves 31 are formed at intervals along the first direction X.

[0219] The gate electrode 14 has a flat structure in which the depth position of the upper surface 82 is generally constant.

[0220] [Appendix 1-12]

[0221] The semiconductor device 81 according to any one of Supplementary Notes 1 to 11, wherein:

[0222] The cover insulating layer 16 has an integral structure extending along the first direction X across the plurality of contact grooves 31 and has an insulating layer concave-convex structure formed by insulating layer concave portions 83 formed in the intersection regions 33 of the contact grooves 31.

[0223] The contact electrode 51 is embedded in the insulating layer recess 83 .

[0224] [Appendix 1-13]

[0225] The semiconductor device 81 according to Supplement 1-12, wherein:

[0226] The cover insulating layer 16 includes: a base portion 85 having a flat lower surface 84 that contacts the upper surface 82 of the gate electrode 14 along the first direction X; and a convex portion 86 that protrudes from the base portion 85 between adjacent insulating layer concave portions 83.

[0227] The convex portions 86 and the concave portions 83 of the insulating layer are alternately arranged along the first direction X to form the concave-convex structure of the insulating layer.

[0228] [Appendix 1-14]

[0229] The semiconductor device 1 according to any one of Supplementary Notes 1-1 to 1-13, wherein:

[0230] The first impurity region 25 includes an emitter region 25,

[0231] The contact electrode 51 includes an emitter contact electrode 51 .

[0232] [Note 1-15]

[0233] The semiconductor device 91 according to any one of Supplementary Notes 1-1 to 1-13, wherein:

[0234] The first impurity region 25 includes a source region 25,

[0235] The contact electrode 51 includes a source contact electrode 51 .

[0236] Explanation of symbols

[0237] 1—semiconductor device; 2—chip; 3—first main surface; 4—second main surface; 5—collector region; 6—charge storage region; 7—drift region; 8—main region; 9—peripheral portion; 10—trench gate electrode structure; 11—trench emitter electrode structure; 12—gate trench; 13—gate insulating layer; 14—gate electrode layer; 15—gate electrode recess; 16—gate cover insulating layer; 17—emitter trench; 18—emitter insulating layer ; 19—emitter electrode layer; 20—emitter electrode recess; 21—emitter cover insulating layer; 22—bottom wall; 23—upper surface; 24—emitter region; 25—emitter region; 31—contact groove; 32—lead-out portion; 33—first intersection region; 34—second intersection region; 35—contact region; 36—contact region; 40—opposite portion; 41—interlayer insulating layer; 42—contact hole; 43—emitter main surface electrode layer; 47— first part; 48—second part; 49—main region protrusion; 50—bottom; 51—emitter contact electrode layer; 61—collector electrode layer; 71—mask; 72—opening; 73—base insulating layer; 74—first base conductor layer; 75—mask; 76—opening; 77—base insulating layer; 78—mask; 79—opening; 81—semiconductor device; 82—upper surface; 83—insulating layer recess; 84—lower surface; 85—base portion; 86—convex portion; 91—semiconductor device; 92—drain region; 101—semiconductor device; 102—channel formation region; 201—semiconductor device; 202—channel formation region; CH—channel; D1—depth; D2—depth; P0—trench pitch; W1—width; W2—width; W3—width; W4—width; W5—width; W6—width; X—first direction; Y—second direction; Z—normal direction; θ—angle.

Claims

1. A semiconductor device, characterized in that: include: A chip having a first main surface formed with a gate trench, wherein the gate trench has a bottom wall and side walls and extends in a first direction; A body region of a first conductivity type, formed along the sidewall of the gate trench on a surface portion of the first main surface; A first impurity region of a second conductivity type is formed on a surface portion of the body region along the sidewall of the gate trench; a gate insulating layer formed on the bottom wall and the side wall of the gate trench; a gate electrode buried in the gate trench and facing the body region and the first impurity region via the gate insulating layer; a contact trench including an intersection region intersecting the gate trench and extending from the intersection region to an outer side of the gate trench along a second direction intersecting the first direction; as well as a contact electrode embedded in the contact trench and electrically connected to the main region and the first impurity region in the contact trench, A space region is formed on the gate electrode in at least the intersection region and the periphery of the intersection region in the gate trench. A cover insulating layer is embedded in the space region, the cover insulating layer covers the upper surface of the gate electrode in the intersection region and the periphery of the intersection region and insulates the gate electrode from the contact electrode. The first impurity region is formed deeper than an upper surface of the gate electrode in a peripheral portion of the intersection region.

2. The semiconductor device according to claim 1, wherein: The first impurity region includes an opposing portion that opposes the gate electrode below a peripheral portion of the intersection region.

3. The semiconductor device according to claim 1 or 2, characterized in that: The contact electrode is connected to the body region at a bottom wall of the contact trench, and is connected to the first impurity region at a side wall of the contact trench.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that The width of the first impurity region in the first direction is 1.0 μm or less.

5. The semiconductor device according to claim 4, wherein: The width of the first impurity region is greater than or equal to 0.5 μm and less than or equal to 1.0 μm.

6. The semiconductor device according to any one of claims 1 to 5, wherein: The peripheral portion of the intersection region includes a region in a range of 0.05 μm to 0.5 μm inclusive from the intersection region.

7. The semiconductor device according to any one of claims 1 to 6, characterized in that comprising a plurality of the contact grooves, the plurality of the contact grooves being formed at intervals along the first direction, The gate electrode has an electrode concave-convex structure formed by a gate electrode concave portion, wherein the gate electrode concave portion is formed along the first direction at the intersection region of each of the contact grooves and at the periphery of the intersection region. The cover insulating layer is buried in the gate electrode recess.

8. The semiconductor device according to claim 7, wherein: The cover insulating layer is independently buried in each of the gate electrode recesses, Between adjacent contact trenches, a portion of the upper surface of the gate electrode is exposed.

9. The semiconductor device according to claim 7 or 8, characterized in that: The gate electrode recess is formed across a peripheral portion on one side and a peripheral portion on the other side of the intersection region in the first direction. The cover insulating layer includes a first portion disposed in the intersection region and a second portion disposed at a peripheral portion on one side and a peripheral portion on the other side of the first portion in the first direction.

10. The semiconductor device according to any one of claims 7 to 9, wherein: The width of the contact groove in the first direction is greater than or equal to 0.3 μm and less than or equal to 1.0 μm, The side walls of the gate electrode recess are formed at intervals of 0.05 μm or more and 0.5 μm or less on both sides of the contact trench in the first direction.

11. The semiconductor device according to any one of claims 1 to 6, wherein: comprising a plurality of the contact grooves, the plurality of the contact grooves being formed at intervals along the first direction, The gate electrode has a flat structure in which a depth position of the upper surface is constant as a whole.

12. The semiconductor device according to claim 11, wherein: The cover insulating layer has an integral structure extending along the first direction across the plurality of contact grooves, and has an insulating layer concave-convex structure formed by insulating layer concave portions, the insulating layer concave portions being formed in the intersection regions of the contact grooves. The contact electrode is buried in the recessed portion of the insulating layer.

13. The semiconductor device according to claim 12, wherein: The cover insulating layer includes: a base portion having a flat lower surface in contact with the upper surface of the gate electrode along the first direction; and a convex portion protruding from the base portion between adjacent concave portions of the insulating layer, The insulating layer concavo-convex structure is formed by alternately arranging the convex portions and the insulating layer concave portions along the first direction.

14. The semiconductor device according to any one of claims 1 to 13, wherein: The first impurity region includes an emitter region, The contact electrode includes an emitter contact electrode.

15. The semiconductor device according to any one of claims 1 to 13, characterized in that The first impurity region includes a source region, The contact electrode includes a source contact electrode.

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