Semiconductor device and method for manufacturing semiconductor device

Abstract

A semiconductor device includes: a gate electrode embedded in a gate trench; a surface insulating layer formed on the first main surface and having a contact hole; a cover insulating layer covering the gate electrode in the gate trench and insulating between the gate electrode and the contact electrode; and an embedded body embedded in a region on the cover insulating layer in the gate trench, the embedded body having an etching selection ratio with respect to the surface insulating layer.

Description

[0001] This application corresponds to Tokugan 2022-143915 filed with the Japan Patent Office on September 9, 2022, and all disclosed contents of this application are incorporated by reference. Technical Field

[0002] The present disclosure relates to a semiconductor device and a method for manufacturing the same. Background Art

[0003] Patent document 1 discloses a semiconductor device, comprising: a semiconductor layer having a main surface formed with a groove; a main body region of a first conductivity type, which is formed along the side wall of the groove in the surface portion of the main surface of the semiconductor layer; an impurity region of a second conductivity type, which is formed along the side wall of the groove in the surface portion of the main body region; a gate insulating layer formed on the inner wall of the groove; a gate electrode buried in the groove and opposite to the main body region and the impurity region via the gate insulating layer; a contact electrode, which passes through the side wall of the groove from the inside of the groove and is led out to the surface portion of the main surface of the semiconductor layer, and is electrically connected to the main body region and the impurity region; and a buried insulating layer, which is interposed between the gate electrode and the contact electrode in the groove to insulate the gate electrode from the contact electrode.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: International Publication No. 2019 / 103135 Summary of the invention

[0007] Problems to be solved by the invention

[0008] One embodiment of the present disclosure provides a semiconductor device and a method for manufacturing the same that can improve controllability of capacitance between a gate electrode and a contact electrode.

[0009] One embodiment of the present disclosure provides a semiconductor device and a method for manufacturing the same, which can suppress reduction in channel width and reduce on-resistance in a structure including a contact trench intersecting a gate trench.

[0010] Solutions to Solve Problems

[0011] A semiconductor device according to an embodiment of the present disclosure includes: a chip having a first main surface on which a gate trench extending in a first direction is formed; a main body region of a first conductivity type formed along a side wall of the gate trench in a surface portion of the first main surface; a first impurity region of a second conductivity type formed along a side wall of the gate trench in a surface portion of the main body region; a gate insulating layer formed on an inner wall of the gate trench; a gate electrode embedded in the gate trench and opposed to the main body region and the first impurity region via the gate insulating layer; and the surface insulating layer formed on the upper surface of the gate electrode in a manner covering the gate electrode. The present invention relates to a first main surface, and has a contact hole extending from an area on the gate trench to the outside of the gate trench along a second direction intersecting the first direction; a contact electrode, which is electrically connected to the main body region and the first impurity region through the contact hole, and is extended from the inside of the gate trench through the sidewall of the gate trench to the surface portion of the first main surface; a covering insulating layer, which covers the gate electrode in the gate trench to insulate the gate electrode from the contact electrode; and an embedded body, which is embedded in the area on the covering insulating layer in the gate trench and has an etching selectivity ratio relative to the surface insulating layer.

[0012] A method for manufacturing a semiconductor device according to an embodiment of the present disclosure includes the following steps: a step of forming a gate insulating layer on an inner wall of the gate trench of a semiconductor wafer, the semiconductor wafer having a first main surface on which the gate trench is formed; a step of burying a gate electrode in the gate trench after the gate insulating layer is formed; a step of forming a recess in the gate trench by selectively removing the gate electrode from the upper surface side; a step of forming a covering insulating layer in the recess in a manner covering the upper surface of the gate electrode; a step of burying an embedded body in a region on the covering insulating layer in the recess; a step of forming a main body region along the sidewall of the gate trench by selectively injecting impurities of a first conductivity type into the surface portion of the first main surface; a step of selectively injecting impurities of a first conductivity type into the main body region a process of injecting second conductive type impurities into the surface portion of the first main surface to form a first impurity region along the side wall of the gate trench; a process of forming a surface insulating layer on the first main surface in a manner covering the gate electrode and the buried body; a process of forming a contact hole intersecting the gate trench in a manner of selectively etching the surface insulating layer so that the buried body and the first main surface are selectively exposed; a process of forming a contact trench on the surface portion of the first main surface in a manner of exposing the main body region and the first impurity region by etching through the contact hole; and a process of forming a contact electrode connected to the main body region and the first impurity in a manner of being buried in the contact trench, the buried body being formed of a material having an etching selectivity ratio relative to the surface insulating layer.

[0013] Effects of the Invention

[0014] According to one embodiment of the present disclosure, the buried body is formed of a material having an etching selectivity ratio relative to the surface insulating layer. Thus, when a contact hole is formed in the surface insulating layer, the buried body can be used as an etching limit layer, thereby preventing the etching of the covering insulating layer. Therefore, the thickness of the covering insulating layer can be simply controlled as a design value when the covering insulating layer is formed. Thus, the short circuit between the gate electrode and the contact electrode and the decrease of TZDB (Time Zero Dielectric Breakdown) can be prevented, and the controllability of the capacitance between the gate electrode and the contact electrode can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 This is a schematic cross-sectional perspective view showing a partial region of the semiconductor device according to the first embodiment of the present disclosure.

[0016] Figure 2 is from Figure 1 Figure 1 shows a diagram of a chip with structures on the first main surface removed.

[0017] Figure 3 is from Figure 2 Image with emitter contact electrode layer removed.

[0018] Figure 4 The chip is viewed from the first main surface Figure 3 Schematic top view of .

[0019] Figure 5 is along Figure 4 A cross-sectional view taken along line V-V is shown.

[0020] Figure 6 is along Figure 4 A cross-sectional view taken along line VI-VI is shown.

[0021] Figure 7 is along Figure 3 The sectional stereogram along line VII-VII is shown.

[0022] Figure 8 is along Figure 4 A cross-sectional view taken along line VIII-VIII is shown.

[0023] Fig. 9 Is Figure 6 An enlarged view of the portion enclosed by the double-dashed line IX.

[0024] Fig. 10A as well as Fig. 10B A diagram showing a part of the manufacturing process of the semiconductor device.

[0025] Fig.11A as well as Fig. 11B It means respectively Fig. 10A as well as Fig. 10B A diagram of the subsequent process.

[0026] Fig. 12A as well as Fig. 12B It means respectively Fig.11A as well as Fig. 11B A diagram of the subsequent process.

[0027] Fig.13A as well as Fig. 13B It means respectively Fig. 12A as well as Fig. 12B A diagram of the subsequent process.

[0028] Fig.14A as well as Fig. 14B It means respectively Fig.13A as well as Fig. 13B A diagram of the subsequent process.

[0029] Fig.15A as well as Fig. 15B It means respectively Fig.14A as well as Fig. 14B A diagram of the subsequent process.

[0030] Fig.16A as well as Fig. 16B It means respectively Fig.15A as well as Fig. 15B A diagram of the subsequent process.

[0031] Fig.17A as well as Fig. 17B It means respectively Fig.16A as well as Fig. 16B A diagram of the subsequent process.

[0032] Fig.18 It is a schematic cross-sectional view showing a partial region of a semiconductor device according to a second embodiment of the present disclosure.

[0033] Fig.19 It is a schematic cross-sectional view showing a partial region of a semiconductor device according to a second embodiment of the present disclosure.

[0034] Fig. 20 It is a schematic cross-sectional view showing a partial region of a semiconductor device according to a second embodiment of the present disclosure.

[0035] Fig.21 It is a schematic cross-sectional perspective view showing a partial region of a semiconductor device according to a third embodiment of the present disclosure.

[0036] Fig. 22It is a schematic cross-sectional perspective view showing a partial region of a semiconductor device according to a fourth embodiment of the present disclosure.

[0037] Fig.23 It means Fig. 22 A diagram showing processes related to formation of a structure. DETAILED DESCRIPTION

[0038] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0039] Figure 1 It is a schematic cross-sectional perspective view showing a partial region of the semiconductor device 1 according to the first embodiment of the present disclosure. Figure 2 is from Figure 1 Figure 1 shows a diagram of a structure on the first main surface 3 of the chip 2 without removal. Figure 3 is from Figure 2 A diagram showing the emitter contact electrode layer 51 being removed.

[0040] Figure 4 is viewed from the first main surface 3 of the chip 2 Figure 3 Schematic top view of . Figure 5 is along Figure 4 A cross-sectional view taken along line V-V is shown. Figure 6 is along Figure 4 A cross-sectional view taken along line VI-VI is shown. Figure 7 is along Figure 3 The sectional stereogram along line VII-VII is shown. Figure 8 is along Figure 4 A cross-sectional view taken along line VIII-VIII is shown. Fig. 9 Is Figure 6 This is an enlarged view of the portion surrounded by the double-dashed line IX. Figure 5 , Figure 6 as well as Figure 8 FIG. 4 also shows the structure on the first main surface 3 of the chip 2 .

[0041] In this embodiment, the semiconductor device 1 has a basic form of an IGBT (Insulated Gate Bipolar Transistor) having a trench gate. Figure 1 to Figure 3 , the semiconductor device 1 includes n － In this embodiment, the chip 2 is composed of n － The silicon single crystal substrate is made of n type silicon single crystal substrate manufactured by FZ (Floating Zone) method. － The chip 2 may be referred to as a semiconductor chip or a semiconductor layer.

[0042] The chip 2 has a first main surface 3 on one side and a second main surface 4 on the other side. The thickness of the chip 2 may be greater than 50 μm and less than 300 μm. The thickness of the chip 2 may be greater than 50 μm and less than 100 μm, greater than 100 μm and less than 150 μm, greater than 150 μm and less than 200 μm, greater than 200 μm and less than 250 μm, or greater than 250 μm and less than 300 μm.

[0043] Reference Figure 1 to Figure 3 A p-type collector region 5 is formed on the surface of the second main surface 4. An n-type charge storage region 6 is formed on the surface of the first main surface 3. The charge storage region 6 is formed at a distance from the collector region 5 toward the first main surface 3.

[0044] Reference Figure 1 to Figure 3 In the chip 2, n is formed in the region between the collector region 5 and the charge storage region 6. － The drift region 7 is formed by a region located between the collector region 5 and the charge storage region 6 in the chip 2. A p-type body region 8 is formed on the surface of the charge storage region 6. A plurality of trench gate electrode structures 10 and a plurality of trench emitter electrode structures 11 are formed at intervals on the surface of the first main surface 3.

[0045] exist Figure 1 to Figure 7 , only one trench gate electrode structure 10 and one trench emitter electrode structure 11 adjacent to each other are shown. Hereinafter, the structure of the semiconductor device 1 will be described with attention paid to the structures of the one trench gate electrode structure 10 and the one trench emitter electrode structure 11.

[0046] The trench gate electrode structure 10 and the trench emitter electrode structure 11 extend in a stripe shape in a plan view along an arbitrary first direction X. The trench gate electrode structure 10 and the trench emitter electrode structure 11 are formed along a second direction Y intersecting the first direction X with a gap therebetween.

[0047] More specifically, the top view refers to the top view observed from the normal direction Z of the first main surface 3 (hereinafter referred to as “normal direction Z”). More specifically, the second direction Y is a direction orthogonal to the first direction X. The first direction X and the second direction Y are also tangent directions of the first main surface 3.

[0048] The trench pitch P0 between the trench gate electrode structure 10 and the trench emitter electrode structure 11 may also be 0.1 μm or more and less than 0.6 μm. The trench pitch P0 may also be 0.1 μm or more and less than 0.2 μm, 0.2 μm or more and less than 0.3 μm, 0.3 μm or more and less than 0.4 μm, 0.4 μm or more and less than 0.5 μm, or 0.5 μm or more and less than 0.6 μm. The trench pitch P0 is preferably 0.2 μm or more and less than 0.4 μm (e.g., about 0.25 μm).

[0049] The trench gate electrode structure 10 includes a gate trench 12, a gate insulating layer 13, a gate electrode layer 14, a plurality of gate electrode recesses 15, a plurality of gate cap insulating layers 16, a plurality of gate buried bodies 9, and a plurality of gate intermediate insulating layers 22. The gate trench 12 penetrates the body region 8 and the charge storage region 6 from the first main surface 3 to reach the drift region 7.

[0050] The depth of the gate trench 12 may be greater than or equal to 2.0 μm and less than or equal to 4.0 μm. The depth of the gate trench 12 may be greater than or equal to 2.0 μm and less than or equal to 2.5 μm, greater than or equal to 2.5 μm and less than or equal to 3.0 μm, greater than or equal to 3.0 μm and less than or equal to 3.5 μm, or greater than or equal to 3.5 μm and less than or equal to 4.0 μm. The depth of the gate trench 12 is preferably greater than or equal to 2.5 μm and less than or equal to 3.5 μm (e.g., about 3.0 μm).

[0051] The second direction width of the gate trench 12 may also be 0.5 μm to 1.5 μm. The second direction width of the gate trench 12 may also be 0.5 μm to 0.75 μm, 0.75 μm to 1.0 μm, 1.0 μm to 1.25 μm, or 1.25 μm to 1.5 μm. The second direction width of the gate trench 12 is preferably 0.5 μm to 1.0 μm (e.g., about 0.75 μm).

[0052] The gate insulating layer 13 may also be formed of silicon oxide. The gate insulating layer 13 is formed in a film shape along the inner wall of the gate trench 12. The gate insulating layer 13 defines a concave space in the gate trench 12.

[0053] The gate electrode layer 14 may also be formed of conductive polysilicon. The gate electrode layer 14 is controlled by a gate voltage. The gate electrode layer 14 is embedded in the gate trench 12 via the gate insulating layer 13. More specifically, the gate electrode layer 14 is embedded in a concave space defined by the gate insulating layer 13 in the gate trench 12.

[0054] In this embodiment, a plurality of gate electrode recesses 15 are formed on the upper surface of the gate electrode layer 14 at intervals along the first direction X. Thus, the upper end portion of the gate electrode layer 14 has a concavo-convex structure including the plurality of gate electrode recesses 15 .

[0055] The interval between the plurality of adjacent gate electrode recesses 15 may be greater than 0 μm and less than 10 μm. The interval between the plurality of adjacent gate electrode recesses 15 may be the width of the portion of the gate electrode layer 14 sandwiched by two adjacent gate electrode recesses 15 in the first direction X. The interval between the plurality of adjacent gate electrode recesses 15 may be greater than 0 μm and less than 2 μm, greater than 2 μm and less than 4 μm, greater than 4 μm and less than 6 μm, greater than 6 μm and less than 8 μm, or greater than 8 μm and less than 10 μm.

[0056] In this embodiment, the side walls of each gate electrode recess 15 are formed by the gate insulating layer 13 and the gate electrode layer 14. A pair of side walls facing each other in the first direction X are formed by the gate electrode layer 14, and a pair of side walls facing each other in the second direction Y are formed by the gate insulating layer 13. The bottom wall of each gate electrode recess 15 is formed by the gate electrode layer 14. Figure 8 The bottom wall of each gate electrode recess 15 may be located in the region between the first main surface 3 and the bottom of the emitter region 25 (described later) in the normal direction Z, or may be located deeper than the bottom of the emitter region 25 .

[0057] Reference Figure 8 Each gate electrode recess 15 is formed into a conical shape with a bottom area smaller than the opening area. The angle θ formed by the upper surface of the gate electrode layer 14 and the sidewall of the gate electrode recess 15 in the gate electrode layer 14 can also be greater than 90° and less than 120° (for example, about 102°).

[0058] A plurality of gate cover insulating layers 16 are formed on the upper surface of the gate electrode layer 14 and the sidewalls of the gate electrode recess 15 in the gate trench 12. More specifically, a plurality of gate cover insulating layers 16 are independently formed in the plurality of gate electrode recesses 15. Each gate cover insulating layer 16 covers the gate electrode layer 14 in the gate trench 12, and is formed along the sidewalls of the gate electrode recess 15, and is exposed from the opening of the gate trench 12. Each gate cover insulating layer 16 defines a concave space in each gate electrode recess 15. The concave space in the gate electrode recess 15 is surrounded by the gate cover insulating layer 16 from below and from the side.

[0059] Reference Fig. 9The gate covering insulating layer 16 includes a bottom 23 covering the upper surface of the gate electrode layer 14, and a side 24 extending upward from the bottom 23 along the side wall of the gate trench 12. The bottom 23 of the gate covering insulating layer 16 has a thickness of more than 150nm and less than 300nm. On the other hand, the side 24 of the gate covering insulating layer 16 has a first thickness T1 at the lower end 47 in the depth direction of the gate trench 12, and has a second thickness T2 thinner than the first thickness T1 at the upper end 48 in the depth direction of the gate trench 12. The first thickness T1 is, for example, less than 300nm, and the second thickness T2 is, for example, less than 50nm. In addition, the width W1 of the upper end of the gate buried body 9 may be narrower than the width W2 of the upper end of the gate electrode layer 14.

[0060] The side portion 24 of the gate cover insulating layer 16 has a tapered shape inclined in a cross-sectional view in such a manner that an outer side surface 29 on a side close to the side wall of the gate trench 12 and an inner side surface 30 on the opposite side of the outer side surface 29 approach each other from a lower end portion 47 toward an upper end portion 48 of the gate cover insulating layer 16. A step S may be formed between the upper end of the side portion 24 of the gate cover insulating layer 16 and the first main surface 3. In other words, the upper end of the side portion 24 of the gate cover insulating layer 16 may be arranged at a lower height position relative to the first main surface 3 in the depth direction of the gate trench 12.

[0061] In this embodiment, the plurality of gate buried bodies 9 may also be formed of the same material as the gate electrode layer 14. That is, the plurality of gate buried bodies 9 may also be formed of conductive polysilicon. The gate buried body 9 has conductivity, but may also be electrically floating in this embodiment. The gate buried body 9 is buried in the gate electrode recess 15 via the gate cover insulating layer 16. More specifically, the gate buried body 9 is buried in the concave space defined by the gate cover insulating layer 16 in the gate electrode recess 15.

[0062] The plurality of gate intermediate insulating layers 22 may also be formed of silicon oxide. Each gate intermediate insulating layer 22 is interposed between the gate electrode layer 14 and the gate cover insulating layer 16 in each gate electrode recess 15. Fig. 9 In this embodiment, the gate intermediate insulating layer 22 is formed between the upper surface of the gate electrode layer 14 and the bottom 23 of the gate cover insulating layer 16. The thickness (third thickness T3) of the gate intermediate insulating layer 22 may be, for example, greater than 20 nm and less than 150 nm. The gate intermediate insulating layer 22 is clearly distinguished from the gate cover insulating layer 16 (bottom 23) in the figure. Depending on the conditions of the manufacturing process, it may also be indistinguishable from the gate cover insulating layer 16 and may be integrated with the gate cover insulating layer 16 in appearance.

[0063] The trench emitter electrode structure 11 includes an emitter trench 17, an emitter insulating layer 18, an emitter electrode layer 19, an emitter electrode recess 20, an emitter cap insulating layer 21, an emitter buried body 27, and an emitter intermediate insulating layer 28. The emitter trench 17 penetrates the body region 8 and the charge storage region 6 from the first main surface 3 to reach the drift region 7.

[0064] The depth of the emitter trench 17 may also be greater than 2.0 μm and less than 4.0 μm. The depth of the emitter trench 17 may also be greater than 2.0 μm and less than 2.5 μm, greater than 2.5 μm and less than 3.0 μm, greater than 3.0 μm and less than 3.5 μm, or greater than 3.5 μm and less than 4.0 μm. The depth of the emitter trench 17 is preferably greater than 2.5 μm and less than 3.5 μm (e.g., about 3.0 μm). The depth of the emitter trench 17 is preferably substantially equal to the depth of the gate trench 12.

[0065] The width of the emitter trench 17 in the second direction may also be greater than 0.5 μm and less than 1.5 μm. The width of the emitter trench 17 in the second direction may also be greater than 0.5 μm and less than 0.75 μm, greater than 0.75 μm and less than 1.0 μm, greater than 1.0 μm and less than 1.25 μm, or greater than 1.25 μm and less than 1.5 μm. The width of the emitter trench 17 in the second direction is preferably greater than 0.5 μm and less than 1.0 μm (e.g., about 0.75 μm). The width of the emitter trench 17 in the second direction is preferably substantially equal to the width of the gate trench 12 in the second direction.

[0066] The emitter insulating layer 18 may also be formed of silicon oxide. The emitter insulating layer 18 is formed in a film shape along the inner wall of the emitter trench 17. The emitter insulating layer 18 defines a concave space in the emitter trench 17.

[0067] The emitter electrode layer 19 may also be formed of conductive polysilicon. The emitter electrode layer 19 is controlled by an emitter voltage. The emitter voltage has a voltage value lower than the gate voltage. The emitter voltage may also be a reference voltage (e.g., a ground voltage). The emitter electrode layer 19 is buried in the emitter trench 17 via the emitter insulating layer 18. More specifically, the emitter electrode layer 19 is buried in a concave space defined by the emitter insulating layer 18 in the emitter trench 17.

[0068] In this embodiment, the emitter electrode recess 20 is formed by digging out substantially the entire upper surface of the emitter electrode layer 19. In other words, the emitter electrode layer 19 is buried to the middle of the depth direction of the recessed space defined by the emitter insulating layer 18.

[0069] In this embodiment, the side walls of the emitter electrode recess 20 are formed by the emitter insulating layer 18. The bottom wall of the emitter electrode recess 20 is formed by the emitter electrode layer 19. Figure 5 as well as Figure 6 , the bottom wall of the emitter electrode recess 20 may be located in the region between the first main surface 3 and the bottom of the emitter region 25 (described later) or in a portion deeper than the bottom of the emitter region 25 in the normal direction Z. That is, the upper end of the emitter electrode layer 19 is located on the first main surface 3 side relative to the bottom of the emitter region 25 (described later). In the normal direction Z, the depth of the emitter electrode recess 20 may be substantially equal to the depth of the gate electrode recess 15.

[0070] The emitter cover insulating layer 21 is formed on the upper surface of the emitter electrode layer 19 and the side walls of the emitter electrode recess 20 in the emitter trench 17. That is, the emitter cover insulating layer 21 is formed along the inner wall of the emitter electrode recess 20. The emitter cover insulating layer 21 covers the emitter electrode layer 19 in the emitter trench 17, is formed along the side walls of the emitter electrode recess 20, and is exposed from the opening of the emitter trench 17. The emitter cover insulating layer 21 divides a concave space in the emitter electrode recess 20. The concave space in the emitter electrode recess 20 is surrounded by the emitter cover insulating layer 21 from below and from the side. Although the description is omitted, the emitter cover insulating layer 21 has the same Fig. 9 The gate cap insulating layer 16 shown has the same cross-sectional shape.

[0071] In this embodiment, the emitter buried body 27 may also be formed of the same material as the emitter electrode layer 19. That is, the emitter buried body 27 may also be formed of conductive polysilicon. The emitter buried body 27 has conductivity, but may also be electrically floating in this embodiment. The emitter buried body 27 is buried in the emitter electrode recess 20 via the emitter cover insulating layer 21. More specifically, the emitter buried body 27 is buried in the concave space defined by the emitter cover insulating layer 21 in the emitter electrode recess 20.

[0072] The emitter intermediate insulating layer 28 may also be formed of silicon oxide. The emitter intermediate insulating layer 28 is interposed between the emitter electrode layer 19 and the emitter cover insulating layer 21 in the emitter electrode recess 20 .

[0073] In the surface portion of the body region 8, an n-type layer is formed in a region along the side wall of the gate trench 12. +The emitter region 25 (impurity region) of the type is formed. More specifically, a plurality of emitter regions 25 are formed along the sidewall on one side and the sidewall on the other side of the gate trench 12 in the first direction X. The plurality of emitter regions 25 are respectively formed in a strip shape extending along the first direction X. The emitter region 25 is in contact with the sidewall of the gate trench 12. The emitter region 25 is also in contact with the sidewall of the emitter trench 17.

[0074] In the surface portion of the first main surface 3, in the region along the side wall of the gate trench 12, an emitter region 25, a body region 8, a charge storage region 6, and a drift region 7 are formed in order from the first main surface 3 toward the second main surface 4. In the body region 8, in the region facing the gate electrode layer 14 via the gate insulating layer 13, a channel CH of the IGBT is formed.

[0075] Reference Figure 3 to Figure 6 as well as Figure 7 A plurality of contact grooves 31 are formed on the surface of the first main surface 3. The plurality of contact grooves 31 are formed at intervals along the first direction X. The plurality of contact grooves 31 are respectively formed in a strip shape extending along the second direction Y. The first direction width of each contact groove 31 is smaller than the second direction width of the gate groove 12.

[0076] More specifically, each contact groove 31 penetrates the side wall of the gate groove 12 from the inner area of ​​the corresponding gate cover insulating layer 16 and leads to the surface portion of the first main surface 3. In this embodiment, each contact groove 31 penetrates the side wall on one side and the side wall on the other side of the gate groove 12 from the inner area of ​​the gate cover insulating layer 16 in the second direction Y.

[0077] Each contact trench 31 includes a first intersection region 33 intersecting the gate electrode layer 14 in a plan view. In the first intersection region 33, the bottom wall of each contact trench 31 is formed by the gate cap insulating layer 16, and the side wall of each contact trench 31 is formed by the gate buried body 9.

[0078] Each contact trench 31 includes a second intersection region 34 intersecting the emitter electrode layer 19 in a plan view. In the second intersection region 34 , the bottom wall of each contact trench 31 is formed by the emitter cover insulating layer 21 , and the side wall of each contact trench 31 is formed by the emitter buried body 27 .

[0079] Each contact trench 31 also includes a contact region 35 extending from the first intersection region 33 to the outside of the gate trench 12. The contact region 35 in the region between the gate trench 12 and the emitter trench 17 when viewed from above can also be referred to as a connection region connecting the first intersection region 33 and the second intersection region 34. In the contact region 35, the bottom wall of each contact trench 31 is formed by the main body region 8, and the side wall of each contact trench 31 is formed by the main body region 8 and the emitter region 25. That is, in the contact region 35, the stacked structure of the main body region 8 and the emitter region 25 is exposed on the side wall of the contact trench 31.

[0080] Each contact trench 31 further includes a lead portion 32 extending outward from one side wall of the emitter trench 17. Each lead portion 32 penetrates one side wall of the emitter trench 17 from the surface portion of the first main surface 3 and reaches the emitter trench 17.

[0081] Reference Figure 7 , the first depth D1 from the first main surface 3 to the upper surface of the gate electrode layer 14 in the first intersection region 33 is shallower than the second depth D2 of the contact groove 31 in the contact region 35. Therefore, the contact groove 31 has a concavo-convex structure in which the gate electrode layer 14 and the emitter electrode layer 19 selectively protrude in the second direction Y. For example, the first depth D1 is 1 μm or less, preferably 0.5 μm or more and 1 μm or less. The second depth D2 is 0.3 μm or more and 1.0 μm or less.

[0082] In the first intersection region 33, the upper end of the gate electrode layer 14 is located on the first main surface 3 side relative to the bottom of the emitter region 25. Thus, the gate electrode layer 14 has an opposing portion 40 that is opposed to the emitter region 25 via the gate insulating layer 13 near both sides of the first intersection region 33 in the first direction X. Figure 7 The opposing portion 40 is located below the pair of gate embedded bodies 9 in the normal direction Z.

[0083] The contact groove 31 includes a first bottom wall 37 in the first intersection region 33 and the second intersection region 34 and a second bottom wall 38 in the contact region 35 and the lead portion 32. A step 39 is formed between the first bottom wall 37 and the second bottom wall 38 due to the difference between the first depth D1 and the second depth D2.

[0084] The arrangement of the plurality of contact grooves 31 is arbitrary. The plurality of contact grooves 31 may be formed at equal intervals along the first direction X. The plurality of contact grooves 31 may be formed at unequal intervals along the first direction X.

[0085] In the body region 8, a p-type conductive layer is formed along the bottom wall of each contact trench 31. +The contact region 36 may be formed in the body region 8 in a region along the bottom wall and sidewall of each contact trench 31. The contact region 36 is formed in a region deeper than the emitter region 25 in the body region 8 in the normal direction Z.

[0086] The contact region 36 has an exposed surface exposed from the bottom wall of the contact groove 31. The exposed surface of the contact region 36 is formed in the region between the first main surface 3 and the bottom of the body region 8. More specifically, the exposed surface of the contact region 36 is formed in the region between the bottom of the body region 8 and the bottom of the emitter region 25. More specifically, the exposed surface of the contact region 36 is formed below the upper surface of the gate electrode layer 14 and the upper surface of the emitter electrode layer 19.

[0087] An interlayer insulating layer 41 is formed on the first main surface 3. The interlayer insulating layer 41 covers the trench gate electrode structure 10 and the trench emitter electrode structure 11. The interlayer insulating layer 41 covers the gate cover insulating layer 16 and the gate buried body 9 exposed from the gate trench 12, and the emitter cover insulating layer 21 and the emitter buried body 27 exposed from the emitter trench 17.

[0088] The interlayer insulating layer 41 may also be formed of silicon oxide or silicon nitride. The interlayer insulating layer 41 may also have a stacked structure including an oxide film (SiO2 film) and a nitride film (SiN film). The oxide film (SiO2 film) may also include an NSG (Nondoped Silicon Glass) film containing no impurities and / or a PSG (Phosphorus Silicon Glass) film containing phosphorus.

[0089] The interlayer insulating layer 41 may have a stacked structure including an NSG film and a PSG film stacked in order from the first main surface 3. The thickness of the NSG film may be Above and The following (for example The thickness of the PSG film can also be Above and The following (for example about).

[0090] A plurality of contact holes 42 are formed in the interlayer insulating layer 41. The plurality of contact holes 42 are connected to the corresponding contact trenches 31. That is, the plurality of contact holes 42 are formed at intervals along the first direction X and are formed in stripes extending along the second direction Y.

[0091] The plurality of contact holes 42 penetrate the interlayer insulating layer 41 and are respectively connected to the corresponding contact trenches 31 . Thus, the plurality of contact holes 42 form one emitter contact trench 31 , 42 between the plurality of contact holes 42 and the corresponding contact trenches 31 .

[0092] The first direction width of each contact hole 42 may also be greater than the first direction width of each contact groove 31. That is, the first direction width of each contact hole 42 may be equal to or greater than the first direction width of each contact groove 31. When the first direction width of each contact hole 42 exceeds the first direction width of each contact groove 31, the inner wall of each contact hole 42 may also surround the inner wall of the corresponding contact groove 31.

[0093] The arrangement of the plurality of contact holes 42 is arbitrary and is adjusted according to the arrangement of the contact trench 31. The plurality of contact holes 42 may be formed at equal intervals along the first direction X. The plurality of contact holes 42 may be formed at unequal intervals along the first direction X.

[0094] An emitter main surface electrode layer 43 is formed on the interlayer insulating layer 41. The emitter main surface electrode layer 43 enters the contact hole 42 and the contact groove 31 (that is, the emitter contact grooves 31, 42) from above the interlayer insulating layer 41. The emitter main surface electrode layer 43 may also include a stacked structure of a barrier layer such as titanium and an electrode layer such as tungsten. In this embodiment, a plurality of emitter contact electrode layers 51 are formed in the emitter main surface electrode layer 43 by the portion located in the plurality of contact grooves 31. Thus, the plurality of emitter contact electrode layers 51 form a structure buried in the surface portion of the chip 2.

[0095] The emitter contact electrode layers 51 have an arrangement and shape corresponding to the arrangement and shape of the contact trenches 31. That is, the emitter contact electrode layers 51 are formed at intervals along the first direction X and are formed in stripes extending along the second direction Y.

[0096] In a plan view, each emitter contact electrode layer 51 faces the gate electrode layer 14 via the gate cover insulating layer 16 in the normal direction Z and the first direction X in the first intersection region 33 intersecting the gate electrode layer 14 . Each emitter contact electrode layer 51 is insulated from the gate electrode layer 14 by the gate cover insulating layer 16 .

[0097] In the first intersection region 33, the gate buried body 9 is interposed between the emitter contact electrode layer 51 and the gate cover insulating layer 16. In this embodiment, in the first intersection region 33, the gate buried body 9 includes a pair of gate buried bodies 9, which are respectively arranged on both sides of the first direction X relative to the first intersection region 33, and sandwich the emitter contact electrode layer 51 from the sides of both sides of the first direction X. Therefore, in the first intersection region 33, the emitter contact electrode layer 51 is directly connected to the gate cover insulating layer 16 in the normal direction Z, and is connected to the gate buried body 9 in the first direction X. The emitter contact electrode layer 51 is surrounded from three directions by the gate cover insulating layer 16 below and the gate buried bodies 9 on both sides.

[0098] In a plan view, each emitter contact electrode layer 51 faces the emitter electrode layer 19 via the emitter cover insulating layer 21 in the normal direction Z and the first direction X in the second intersection region 34 intersecting with the emitter electrode layer 19 . Each emitter contact electrode layer 51 is insulated from the emitter electrode layer 19 by the emitter cover insulating layer 21 .

[0099] In the second intersection region 34, the emitter buried body 27 is interposed between the emitter contact electrode layer 51 and the emitter cover insulating layer 21. In this embodiment, in the second intersection region 34, the emitter buried body 27 includes a pair of emitter buried bodies 27, which are respectively arranged on both sides of the first direction X relative to the second intersection region 34, and sandwich the emitter contact electrode layer 51 from the sides of both sides of the first direction X. Therefore, in the second intersection region 34, the emitter contact electrode layer 51 is directly connected to the emitter cover insulating layer 21 in the normal direction Z, and is connected to the emitter buried body 27 in the first direction X. The emitter contact electrode layer 51 is surrounded from three directions by the emitter cover insulating layer 21 below and the emitter buried bodies 27 on both sides.

[0100] A collector electrode layer 61 is formed on the second main surface 4 of the chip 2. The collector electrode layer 61 is connected to the collector region 5. Although not shown in the figure, a gate main surface electrode layer having the same structure as the emitter main surface electrode layer 43 may be formed on the interlayer insulating layer 41. The gate main surface electrode layer may also be electrically connected to the gate electrode layer 14 via a gate contact hole formed in the interlayer insulating layer 41.

[0101] Fig. 10A , 10B ~ Fig.17A , 17B FIG. 1 is a diagram showing a part of the manufacturing process of the semiconductor device 1 in order of process. Fig. 10A , 10B ~ Fig.17A , 17BIn the figure, the figure with the figure number "A" is recorded at the same time Figure 5 The cross-section of the figure is corresponding to that of the figure with the drawing number "B" Figure 8 The cross section corresponds to .

[0102] Reference Fig. 10A , 10B First, prepare n － A semiconductor wafer 26 of type is provided. The semiconductor wafer 26 has the first main surface 3 and the second main surface 4 (not shown) of the above-mentioned chip 2. Next, a p-type collector region 5 (not shown) and an n-type charge storage region 6 are formed in the semiconductor wafer 26. The collector region 5 is formed by the introduction of p-type impurities relative to the second main surface 4 of the semiconductor wafer 26. The collector region 5 can also be formed on the surface portion of the second main surface 4 of the semiconductor wafer 26 by an ion implantation method through an ion implantation mask (not shown). The charge storage region 6 is formed by the introduction of n-type impurities relative to the first main surface 3. The charge storage region 6 can also be formed on the surface portion of the first main surface 3 by an ion implantation method through an ion implantation mask (not shown).

[0103] Next, unnecessary portions of the semiconductor wafer 26 are selectively removed from the first main surface 3 via a mask having a predetermined pattern. The unnecessary portions of the semiconductor wafer 26 may also be removed by an etching method (e.g., a wet etching method). Thus, a gate trench 12 and an emitter trench 17 are formed. Then, the mask is removed. Next, a gate insulating layer 13 and an emitter insulating layer 18 are formed on the inner wall of the gate trench 12 and the inner wall of the emitter trench 17, respectively, by, for example, a thermal oxidation treatment method or a wet oxidation treatment method. Next, a gate electrode layer 14 and an emitter electrode layer 19 are buried in the gate trench 12 and the emitter trench 17, respectively, by, for example, a CVD method. Thus, a trench gate electrode structure 10 and a trench emitter electrode structure 11 are formed.

[0104] Next, refer to Fig.11A , 11B , the gate electrode layer 14 and the emitter electrode layer 19 are selectively removed from the first main surface 3 via a mask having a predetermined pattern. Thus, the gate electrode recess 15 and the emitter electrode recess 20 are formed. The unnecessary portion of the gate electrode layer 14 and the unnecessary portion of the emitter electrode layer 19 can also be removed by etching (for example, wet etching).

[0105] Next, refer to Fig. 12A , 12B, a first base insulating layer 44 serving as a base of the gate intermediate insulating layer 22 and the emitter intermediate insulating layer 28, and a second base insulating layer 45 serving as a base of the gate cover insulating layer 16 and the emitter cover insulating layer 21 are formed. The first base insulating layer 44 may be formed, for example, by thermal oxidation treatment of the surfaces of the gate electrode layer 14 and the emitter electrode layer 19, and the surface of the semiconductor wafer 26. On the other hand, the second base insulating layer 45 may be formed, for example, by CVD method, by depositing an insulating material on the first base insulating layer 44. The first base insulating layer 44 and the second base insulating layer 45 are formed in the gate trench 12 and the emitter trench 17, and are formed in a manner covering the first main surface 3 of the semiconductor wafer 26.

[0106] Next, refer to Fig.13A , 13B For example, by CVD, a polysilicon layer that will become the base of the gate buried body 9 and the emitter buried body 27 is deposited on the entire surface of the first main surface 3. Then, the polysilicon layer is flattened by etching back to obtain the gate buried body 9 and the emitter buried body 27 buried in the gate electrode recess 15 and the emitter electrode recess 20, respectively.

[0107] Next, a p-type body region 8 and an n-type body region 8 are formed in the semiconductor wafer 26. + The emitter region 25 is formed by introducing p-type impurities into the first main surface 3. The body region 8 may be formed on the surface of the first main surface 3 by ion implantation through an ion implantation mask (not shown). The emitter region 25 is formed by introducing n-type impurities into the first main surface 3. The emitter region 25 may be formed on the surface of the first main surface 3 by ion implantation through an ion implantation mask (not shown).

[0108] Next, refer to Fig.14A , 14B , an interlayer insulating layer 41 is formed on the first main surface 3. The interlayer insulating layer 41 is formed on the first main surface 3 in a manner covering the trench gate electrode structure 10 and the trench emitter electrode structure 11. This step may also include sequentially forming an NSG film (e.g. ) and PSG membranes (e.g. ) process.

[0109] Next, refer to Fig.15A , 15B, through a mask having a predetermined pattern, the unnecessary portion of the interlayer insulating layer 41, the unnecessary portion of the gate cover insulating layer 16, and the unnecessary portion of the emitter cover insulating layer 21 are selectively removed. The unnecessary portion of the interlayer insulating layer 41 and the like can also be removed by etching (for example, dry etching). Thus, the contact hole 42 is formed.

[0110] Next, refer to Fig.16A , 16B , the unnecessary part of the semiconductor wafer 26 is removed through the mask used when forming the contact hole 42. The unnecessary part of the semiconductor wafer 26 can also be removed by, for example, etching (for example, dry etching). Thus, the contact groove 31 is formed on the first main surface 3. Fig.16A In FIG. 1 , the structure that can be seen on the inner side of the contact groove 31 is shown by the dotted hatching.

[0111] In this embodiment, the semiconductor wafer 26 is a silicon single crystal substrate, and the gate embedded body 9 is polycrystalline silicon, so the gate embedded body 9 is etched simultaneously when the contact groove 31 is formed. In addition, the second depth D2 of the contact groove 31 is greater than the thickness T4 of the gate embedded body 9 (refer to Fig.15A , 15B Therefore, in the first intersection region 33 , the gate buried body 9 is etched so as to penetrate from the first main surface 3 to the bottom wall of the gate electrode recess 15 .

[0112] Next, a contact region 36 is formed on the surface portion of the first main surface 3. More specifically, the contact region 36 is formed in a region along the bottom wall of the contact groove 31 in the surface layer portion of the main body region 8. The contact region 36 may also be formed in a region along the sidewall and bottom wall of the contact groove 31. The contact region 36 is formed by introducing p-type impurities into the contact groove 31. The contact region 36 may also be introduced into the contact groove 31 by an ion implantation method through an ion implantation mask (not shown). Thus, the contact region 36 along the bottom wall of the contact groove 31 is formed.

[0113] Next, refer to Fig.17A , 17B , an emitter main surface electrode layer 43 is formed on the interlayer insulating layer 41. The emitter main surface electrode layer 43 can also be formed by a sputtering method or a CVD method. In addition, an emitter contact electrode layer 51 is formed in the emitter main surface electrode layer 43 at a portion that enters the contact groove 31. In addition, a collector electrode layer 61 is formed on the second main surface 4 of the semiconductor wafer 26. After the steps including the above description, the semiconductor device 1 is obtained.

[0114] In summary, according to the semiconductor device 1, the gate embedded body 9 is formed of polysilicon and has an etching selectivity ratio with respect to the interlayer insulating layer 41 composed of silicon oxide or silicon nitride. The gate embedded body 9 has an etching selectivity ratio with respect to the interlayer insulating layer 41, and for example, the etching selectivity ratio (a / b) represented by the ratio of the etching amount (a) of the interlayer insulating layer 41 to the etching amount (b) of the gate embedded body 9 is, for example, 1.5 or more, preferably 5 or more, and more preferably 10 or more.

[0115] Thus, when the contact hole 42 is formed in the interlayer insulating layer 41 (see Fig.15A , 15B ), the gate embedded body 9 can be used as an etching limiter. The gate intermediate insulating layer 22 can be prevented from being exposed to the etching gas when the contact hole 42 is formed. Therefore, the thickness of the gate intermediate insulating layer 22 can be simply controlled to a designed value according to the formation conditions of the gate intermediate insulating layer 22 (for example, thermal oxidation conditions, CVD conditions, etc.). Therefore, the short circuit between the gate electrode layer 14 and the emitter contact electrode layer 51 and the decrease of TZDB (Time Zero Dielectric Breakdown) can be prevented, and the controllability of the capacitance between the gate electrode layer 14 and the emitter contact electrode layer 51 can be improved.

[0116] In addition, the gate intermediate insulating layer 22 is not etched when the contact hole 42 is formed. Therefore, it is not necessary to form the gate intermediate insulating layer 22 too thick for the purpose of preventing a short circuit between the gate and the emitter due to over-etching of the gate intermediate insulating layer 22. In addition, it is not necessary to form the gate electrode recess 15 deeper in order to form a thicker gate intermediate insulating layer 22. Thus, the gate electrode recess 15 can be formed relatively shallow, so that the opposing portion 40 of the gate electrode layer 14 that is opposite to the emitter region 25 via the gate insulating layer 13 can be ensured near both sides of the first intersection region 33. As a result, the vicinity of the first intersection region 33 can be used as the channel formation region 46 (see Figure 3 ) is utilized, so that the reduction of the channel width can be suppressed. Therefore, a semiconductor device 1 capable of reducing on-resistance can be provided.

[0117] Fig.18 It is a schematic cross-sectional view showing a partial region of a semiconductor device 71 according to the second embodiment of the present disclosure. Fig.19 It is a schematic cross-sectional view showing a partial region of a semiconductor device 71 according to the second embodiment of the present disclosure. Fig. 20 It is a schematic cross-sectional view showing a partial region of a semiconductor device 71 according to the second embodiment of the present disclosure. Fig.18 and Figure 5 The cross section corresponds to Fig.19 and Figure 6 The cross section corresponds to Fig. 20 and Figure 8 Hereinafter, structures corresponding to the structures described for the semiconductor device 1 according to the first embodiment are denoted by the same reference numerals and description thereof will be omitted.

[0118] Reference Figures 18 to 20 In the second embodiment, the first depth D1 from the first main surface 3 to the upper surface of the gate electrode layer 14 in the first intersection region 33 is deeper than the second depth D2 of the contact groove 31 in the contact region 35. In addition, in the first intersection region 33, a stacked structure of the gate cover insulating layer 16 and the gate buried body 9 is formed on the bottom wall of the contact groove 31. Fig. 20 As shown, the gate buried body 9 is formed to extend from one side of the first intersection region 33 in the first direction X to the other side, and surrounds the emitter contact electrode layer 51 from three directions: laterally on both sides of the first direction X and from below.

[0119] In the first intersection region 33, the upper end of the gate electrode layer 14 is located on the second main surface 4 side (the opposite side of the first main surface 3) relative to the bottom of the emitter region 25. Therefore, in the semiconductor device 71 of the second embodiment, there is no Figure 7 In the facing portion 40 shown, the gate electrode layer 14 faces the emitter region 25 near both sides of the first intersection region 33 in the first direction X without the gate insulating layer 13 interposed therebetween.

[0120] As described above, the semiconductor device 71 of the second embodiment can also achieve the same effects as those described for the semiconductor device 1. The semiconductor device 71 can be manufactured by simply changing the depths of the gate electrode recess 15 and the emitter electrode recess 20 in the manufacturing method of the semiconductor device 1.

[0121] Fig.21 1 is a schematic cross-sectional perspective view showing a partial region of a semiconductor device 81 according to a third embodiment of the present disclosure. Hereinafter, structures corresponding to those described in relation to the semiconductor device 1 are denoted by the same reference numerals and description thereof will be omitted.

[0122] In the above-mentioned semiconductor device 1, an example in which a p-type collector region 5 is formed on the surface portion of the second main surface 4 is described. In contrast, in the semiconductor device 81, an n-type drain region 82 is formed on the surface portion of the second main surface 4 instead of the p-type collector region 5. Thus, the semiconductor device 81 has a basic form of a MISFET (Metal Insulator Semiconductor Field Effect Transistor) having a trench gate type. The description of the above-mentioned semiconductor device 1 replaces "emitter" with "source" and "collector" with "drain", and is used for the description of the semiconductor device 81.

[0123] As described above, the semiconductor device 81 can also achieve the same effects as those described for the semiconductor device 1. The semiconductor device 81 can be manufactured by simply forming an n-type drain region 82 instead of the p-type collector region 5 in the manufacturing method of the semiconductor device 1 and changing the layout of each mask.

[0124] Fig. 22 It is a schematic cross-sectional perspective view showing a partial region of a semiconductor device 91 according to a fourth embodiment of the present disclosure. Fig.23 It means Fig. 22 A diagram showing processes related to formation of a structure. Fig. 22 as well as Fig.23 The semiconductor device 1 described above Fig. 9 Hereinafter, structures corresponding to the structures described in relation to the semiconductor device 1 are denoted by the same reference numerals and their descriptions are omitted.

[0125] In the above-mentioned semiconductor device 1, an example is described in which the width W1 of the upper end of the gate buried body 9 is narrower than the width W2 of the upper end of the gate electrode layer 14. In contrast, in the semiconductor device 91, the width W1 of the upper end of the gate buried body 9 is wider than the width W2 of the upper end of the gate electrode layer 14. To explain in more detail, the gate trench 12 is formed into a tapered shape in which the bottom area is smaller than the opening area. The angle θ2 formed by the side wall of the gate trench 12 with respect to the surface 92 parallel to the first main surface 3 may, for example, be greater than 80° and less than 90°, and preferably greater than 85° and less than 90°. Therefore, in the depth direction of the gate trench 12, the width W1 of the gate buried body 9 formed at a position closer to the opening end of the gate trench 12 than the depth position of the gate electrode layer 14 is wider than the width W2 of the gate electrode layer 14.

[0126] In the above-described semiconductor device 1, an example is described in which the side portion 24 of the gate cover insulating layer 16 has a second thickness T2 at the upper end portion 48 that is thinner than the first thickness T1 at the lower end portion 47. In contrast, in the semiconductor device 91, the second thickness T2 may be 0 (zero) at the upper end portion 48 by contacting the outer side surface 29 with the inner side surface 30. The upper end portion 48 of the side portion 24 of the gate cover insulating layer 16 may also be a sharp tip portion that tapers upward.

[0127] In summary, according to the semiconductor device 91, the same effects as those described for the semiconductor device 1 can be achieved. The semiconductor device 91 can be manufactured by forming the gate trench 12 by etching under conditions that form a tapered shape in the manufacturing method of the semiconductor device 1, and forming the side portion 24 of the gate cover insulating layer 16 in a tapered shape. In addition, although omitted in the above description, the mesa structure 93 (a portion where the emitter region 25 and the like are formed) of the chip 2 formed on the side of the gate trench 12 can also be trapezoidal in cross-section and have an upper end portion 94 formed in a circular shape. With respect to such a mesa structure 93, by forming the gate cover insulating layer 16 under conditions that form a tapered shape, the width W1 of the gate buried body 9 can be made wider than the width W2 of the gate electrode layer 14.

[0128] Although the embodiments of the present disclosure have been described, the present disclosure can also be implemented in other forms.

[0129] For example, in each of the above-mentioned embodiments, a structure in which the conductivity type of each semiconductor portion is reversed may be adopted. That is, a p-type portion may be n-type, and an n-type portion may be p-type.

[0130] In the above-mentioned embodiments, an example in which the chip 2 is composed of a silicon single crystal is described. However, the chip 2 may include SiC. In addition, the chip 2 may also be composed of a SiC single crystal.

[0131] In summary, the embodiments of the present disclosure are illustrative in all aspects and should not be interpreted as limiting, and are intended to include changes in all aspects.

[0132] The following additional features can be extracted from the description of this specification and the drawings.

[0133] [Appendix 1-1]

[0134] A semiconductor device 1, 71, 81, comprising:

[0135] A chip 2 having a first main surface 3 formed with a gate trench 12 extending in a first direction X;

[0136] A first conductivity type body region 8 formed along the sidewall of the gate trench 12 in the surface portion of the first main surface 3;

[0137] A first impurity region 25 of a second conductivity type, which is formed in a surface portion of the body region 8 along a side wall of the gate trench 12;

[0138] A gate insulating layer 13 formed on the inner wall of the gate trench 12;

[0139] a gate electrode 14 embedded in the gate trench 12 and facing the body region 8 and the first impurity region 25 via the gate insulating layer 13;

[0140] The surface insulating layer 41 is formed on the first main surface 3 in a manner covering the gate electrode 14 and has a contact hole 42 extending from a region on the gate trench 12 to the outside of the gate trench 12 along a second direction Y intersecting the first direction X;

[0141] a contact electrode 51 which is electrically connected to the body region 8 and the first impurity region 25 via the contact hole 42 and is led out from the gate trench 12 through the sidewall of the gate trench 12 to the surface portion of the first main surface 3;

[0142] a covering insulating layer 16 covering the gate electrode 14 in the gate trench 12 to insulate the gate electrode 14 from the contact electrode 51 ; and

[0143] The buried body 9 , which is buried in a region on the cover insulating layer 16 in the gate trench 12 , has an etching selectivity with respect to the surface insulating layer 41 .

[0144] [Appendix 1-2]

[0145] According to the semiconductor device 1, 71, 81 described in Supplement 1-1,

[0146] The cover insulating layer 16 includes a bottom portion 23 covering the upper surface of the gate electrode 14 and a side portion 24 extending upward from the bottom portion 23 along the sidewall of the gate trench 12 .

[0147] [Appendix 1-3]

[0148] According to the semiconductor device 1, 71, 81 described in Supplementary Notes 1-2,

[0149] The bottom portion 23 of the cover insulating layer 16 has a thickness of not less than 150 nm and not more than 300 nm.

[0150] [Appendix 1-4]

[0151] The semiconductor device 1, 71, or 81 according to Supplement 1-2 or Supplement 1-3,

[0152] The side portion 24 of the cover insulating layer 16 has a first thickness T1 at a lower end portion 47 in the depth direction of the gate trench 12 , and has a second thickness T2 thinner than the first thickness T1 at an upper end portion 48 in the depth direction of the gate trench 12 .

[0153] [Appendix 1-5]

[0154] The semiconductor device 1, 71, or 81 according to any one of Supplementary Notes 1-2 to 1-4,

[0155] The side portion 24 of the cover insulating layer 16 has a tapered shape inclined in a cross-sectional view in the following manner: an outer side surface 29 on one side close to the side wall of the gate trench 12 and an inner side surface 30 on the opposite side of the outer side surface 29 approach each other from the lower end portion 47 toward the upper end portion 48 .

[0156] [Appendix 1-6]

[0157] The semiconductor device 1, 71, or 81 according to any one of Supplementary Notes 1-1 to 1-5,

[0158] The contact groove 31 is formed on the surface of the first main surface 3 in a manner extending along the contact hole 42 and has bottom walls 37 and 38 and side walls.

[0159] The main body region 8 is formed at least along the bottom walls 37 and 38 of the contact groove 31.

[0160] The first impurity region 25 is formed at least along the sidewall of the contact trench 31.

[0161] The contact electrode 51 is embedded in the contact trench 31 , and is connected to the body region 8 and the first impurity region 25 inside the contact trench 31 .

[0162] [Appendix 1-7]

[0163] According to the semiconductor device 1, 81 described in Supplementary Notes 1 to 6,

[0164] The contact trench 31 includes an intersection region 33 intersecting the gate trench 12, and a contact region 35 extending from the intersection region 33 to the outside of the gate trench 12 and exposing the body region 8 and the first impurity region 25.

[0165] A depth D1 from the first main surface 3 to the upper surface of the gate electrode 14 in the intersection region 33 is shallower than a depth D2 from the first main surface 3 to the bottom wall of the contact trench 31 in the contact region 35 .

[0166] [Appendix 1-8]

[0167] According to the semiconductor device 1, 81 described in Supplementary Notes 1 to 7,

[0168] In the intersection region 33 , the bottom 23 of the cover insulating layer 16 is exposed at the bottom wall 37 of the contact groove 31 .

[0169] The embedded bodies 9 include a pair of embedded bodies 9 , which are provided on both sides of the intersection region 33 in the first direction X and sandwich the contact electrode 51 from both sides in the first direction X.

[0170] [Appendix 1-9]

[0171] The semiconductor device 1 or 81 according to Supplement 1-7 or Supplement 1-8,

[0172] A depth D1 from the first main surface 3 to the upper surface of the gate electrode 14 in the intersection region 33 is 1 μm or less.

[0173] [Appendix 1-10]

[0174] According to the semiconductor device 71 described in Supplementary Notes 1 to 6,

[0175] The contact trench 31 includes an intersection region 33 intersecting the gate trench 12 and a contact region extending from the intersection region 33 to the outside of the gate trench 12 and where the body region 8 and the first impurity region 25 are exposed.

[0176] A depth D1 from the first main surface 3 to the upper surface of the gate electrode 14 in the intersection region 33 is deeper than a depth D2 from the first main surface 3 to the bottom wall of the contact trench 31 in the contact region.

[0177] [Supplement 1-11] According to the semiconductor device 71 described in Supplement 1-10,

[0178] In the intersection region 33 , a stacked structure of the bottom portion 23 of the cover insulating layer 16 and the embedded body 9 is formed on the bottom wall 37 of the contact groove 31 .

[0179] The embedded body 9 is formed to extend from one side to the other side of the intersection region 33 in the first direction X, and surrounds the contact electrode 51 from three directions: lateral sides of both sides in the first direction X and from below.

[0180] [Appendix 1-12]

[0181] The semiconductor device 1, 71, or 81 according to any one of Supplementary Notes 1-1 to 1-11,

[0182] The etching selectivity ratio of the embedded body 9 to the surface insulating layer 41 is 1.5 or more.

[0183] [Appendix 1-13]

[0184] The semiconductor device 1, 71, or 81 according to any one of Supplementary Notes 1-1 to 1-12,

[0185] The embedded body 9 is formed of the same material as that of the gate electrode 14 .

[0186] [Appendix 1-14]

[0187] The semiconductor device 1, 71, or 81 according to any one of Supplementary Notes 1-1 to 1-12,

[0188] The surface insulating layer 41 is formed of silicon oxide.

[0189] The gate electrode 14 and the buried body 9 are formed of polysilicon.

[0190] [Appendix 1-15]

[0191] A method for manufacturing a semiconductor device 1, 71, 81 comprises the following steps:

[0192] A step of forming a gate insulating layer 13 on an inner wall of the gate trench 12 of a semiconductor wafer 26 having a first main surface 3 in which the gate trench 12 is formed;

[0193] After the gate insulating layer 13 is formed, a gate electrode 14 is embedded in the gate trench 12;

[0194] A step of forming a recess 15 in the gate trench 12 by selectively removing the gate electrode 14 from the upper surface side;

[0195] a step of forming a cover insulating layer 16 in the recess 15 so as to cover the upper surface of the gate electrode 14;

[0196] A step of embedding the embedding body 9 in the region on the cover insulating layer 16 in the recess 15;

[0197] A step of selectively implanting first conductivity type impurities into a surface portion of the first main surface 3 to form a body region 8 along a side wall of the gate trench 12;

[0198] A step of selectively implanting second conductivity type impurities into the surface of the body region 8 to form a first impurity region 25 along the sidewall of the gate trench 12;

[0199] a step of forming a surface insulating layer 41 on the first main surface 3 so as to cover the gate electrode 14 and the embedded body 9;

[0200] A step of forming a contact hole 42 intersecting the gate trench 12 by selectively etching the surface insulating layer 41 so that the buried body 9 and the first main surface 3 are selectively exposed;

[0201] a step of forming a contact groove 31 on a surface portion of the first main surface 3 so that the body region 8 and the first impurity region 25 are exposed by etching through the contact hole 42 ; and

[0202] a step of forming a contact electrode 51 connected to the body region 8 and the first impurity so as to be buried in the contact trench 31;

[0203] The embedded body 9 is formed of a material having an etching selectivity ratio with respect to the surface insulating layer 41 .

[0204] Explanation of symbols

[0205] 1—semiconductor device, 2—chip, 3—first main surface, 4—second main surface, 5—collector region, 6—charge storage region, 7—drift region, 8—body region, 9—gate buried body, 10—trench gate electrode structure, 11—trench emitter electrode structure, 12—gate trench, 13—gate insulating layer, 14—gate electrode layer, 15—gate electrode recess, 16—gate cover insulating layer, 17—emitter trench, 18—emitter insulating layer, 19—emitter electrode layer, 20—emitter electrode recess, 21—emitter cover insulating layer, 22—gate intermediate insulating layer, 23—bottom, 24—side, 25—emitter region, 26—semiconductor wafer, 27—emitter buried body, 28—emitter intermediate insulating layer, 29—outer side surface, 30—inner side surface, 31—contact trench, 32—lead-out portion, 33—first intersection region, 34—second intersection Fork region, 35—contact region, 36—contact region, 37—first bottom wall, 38—second bottom wall, 39—step, 40—opposing portion, 41—interlayer insulating layer, 42—contact hole, 43—emitter main surface electrode layer, 44—first base insulating layer, 45—second base insulating layer, 46—channel formation region, 47—lower end, 48—upper end, 51—emitter contact electrode layer, 61—collector electrode layer, 71—semiconductor device, 81—semiconductor device, 82—drain region, 91—semiconductor device, 92—parallel plane, 3—terrace structure, 94—upper end, CH—channel, D1—first depth, D2—second depth, P0—trench pitch, S—step, T1—first thickness, T2—second thickness, T3—third thickness, T4—thickness, W1—width, W2—width, X—first direction, Y—second direction, Z—normal direction.

Claims

1. A semiconductor device, characterized in that: include: A chip having a first main surface formed with a gate trench extending in a first direction; A body region of the first conductivity type, formed along a side wall of the gate trench in a surface portion of the first main surface; A first impurity region of a second conductivity type is formed in a surface portion of the body region along a side wall of the gate trench; A gate insulating layer formed on the inner wall of the gate trench; a gate electrode embedded in the gate trench and facing the body region and the first impurity region via the gate insulating layer; The surface insulating layer is formed on the first main surface in a manner covering the gate electrode and has a contact hole extending from a region on the gate trench to an outer side of the gate trench along a second direction intersecting the first direction; a contact electrode electrically connected to the body region and the first impurity region via the contact hole and extending from the gate trench through the sidewall of the gate trench to the surface portion of the first main surface; a covering insulating layer covering the gate electrode in the gate trench to insulate the gate electrode from the contact electrode; and The buried body is buried in a region on the cover insulating layer in the gate trench and has an etching selectivity ratio with respect to the surface insulating layer.

2. The semiconductor device according to claim 1, wherein: The cap insulating layer includes a bottom portion covering an upper surface of the gate electrode and a side portion extending upward from the bottom portion along a side wall of the gate trench.

3. The semiconductor device according to claim 2, wherein: The bottom portion of the cover insulating layer has a thickness of not less than 150 nm and not more than 300 nm.

4. The semiconductor device according to claim 2 or 3, characterized in that The side portion of the cover insulating layer has a first thickness at a lower end portion in a depth direction of the gate trench, and has a second thickness thinner than the first thickness at an upper end portion in the depth direction of the gate trench.

5. The semiconductor device according to any one of claims 2 to 4, characterized in that The side portion of the cover insulating layer has a tapered shape inclined in a cross-sectional view such that an outer side surface close to a side wall of the gate trench and an inner side surface opposite to the outer side surface approach each other from the lower end portion toward the upper end portion.

6. The semiconductor device according to any one of claims 1 to 5, wherein: A contact groove is formed on the surface of the first main surface in a manner extending along the contact hole and has a bottom wall and a side wall. The main body region is formed at least along the bottom wall of the contact groove. The first impurity region is formed at least along the sidewall of the contact trench. The contact electrode is buried in the contact trench and connected to the body region and the first impurity region in the contact trench.

7. The semiconductor device according to claim 6, wherein: The contact trench includes: an intersection region intersecting with the gate trench; and a contact region extending from the intersection region to the outside of the gate trench and where the main region and the first impurity region are exposed. A depth from the first main surface to an upper surface of the gate electrode in the intersection region is shallower than a depth from the first main surface to a bottom wall of the contact trench in the contact region.

8. The semiconductor device according to claim 7, wherein: In the intersection region, the bottom of the cover insulating layer is exposed at the bottom wall of the contact trench. The embedded body includes a pair of embedded bodies, and the pair of embedded bodies are respectively provided on both sides of the intersection region in the first direction, and sandwich the contact electrode from the sides of both sides in the first direction.

9. The semiconductor device according to claim 7 or 8, characterized in that: A depth from the first main surface to the upper surface of the gate electrode in the intersection region is 1 μm or less.

10. The semiconductor device according to claim 6, wherein: The contact trench includes: an intersection region intersecting with the gate trench; and a contact region extending from the intersection region to the outside of the gate trench and where the main region and the first impurity region are exposed. A depth from the first main surface to an upper surface of the gate electrode in the intersection region is deeper than a depth from the first main surface to a bottom wall of the contact trench in the contact region.

11. The semiconductor device according to claim 10, wherein: In the intersection region, a stacked structure including the bottom of the cover insulating layer and the embedded body is formed on the bottom wall of the contact trench. The embedded body is formed so as to extend from one side to the other side of the intersection region in the first direction, and surrounds the contact electrode from three directions, lateral sides and bottom sides of both sides in the first direction.

12. The semiconductor device according to any one of claims 1 to 11, characterized in that The embedded body has an etching selectivity ratio of 1.5 or more with respect to the surface insulating layer.

13. The semiconductor device according to any one of claims 1 to 12, wherein: The buried body is formed of the same material as that of the gate electrode.

14. The semiconductor device according to any one of claims 1 to 12, wherein: The surface insulating layer is formed of silicon oxide. The gate electrode and the buried body are formed of polysilicon.

15. A method for manufacturing a semiconductor device, characterized in that: Including the following processes: A step of forming a gate insulating layer on an inner wall of a gate trench of a semiconductor wafer, the semiconductor wafer having a first main surface on which the gate trench is formed; After the gate insulating layer is formed, a step of embedding a gate electrode in the gate trench; A step of forming a recess in the gate trench by selectively removing the gate electrode from the upper surface side; forming a cover insulating layer in the recessed portion so as to cover the upper surface of the gate electrode; A step of embedding a buried body in a region on the cover insulating layer in the recess; A step of selectively implanting impurities of the first conductivity type into a surface portion of the first main surface to form a body region along a sidewall of the gate trench; A step of selectively implanting second conductivity type impurities into a surface portion of the body region to form a first impurity region along a sidewall of the gate trench; forming a surface insulating layer on the first main surface so as to cover the gate electrode and the embedded body; A step of forming a contact hole intersecting the gate trench by selectively etching the surface insulating layer so as to selectively expose the buried body and the first main surface; a step of forming a contact groove on a surface portion of the first main surface so as to expose the body region and the first impurity region by etching through the contact hole; and forming a contact electrode connected to the body region and the first impurity in a manner buried in the contact trench, The embedded body is formed of a material having an etching selectivity ratio with respect to the surface insulating layer.

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