Locally enlarged via-to-backside power rail

Abstract

A semiconductor structure with improved performance is provided that includes a locally enlarged via-to-backside power rail (VBPR) contact structure that connects a source / drain region of a field effect transistor (FET) to a backside power rail.

Description

Background Art

[0001] The present invention relates to semiconductor technology, and more particularly to a semiconductor structure including a locally enlarged via-to-backside power rail (VBPR) contact structure, which improves the performance of a circuit including the VBPR contact structure.

[0002] When forming a structure including multiple complementary metal oxide semiconductor (CMOS) devices, such as an integrated circuit, a standard cell can be used as a basic unit for designing and manufacturing the integrated circuit. The standard cell can be used to form one or more functional circuits, and each standard cell can have the same footprint (e.g., can have a standard footprint). Using standard cells when designing complex circuits and components reduces design and manufacturing costs.

[0003] In use, each standard cell of the semiconductor structure requires a power input (Vdd) and a ground (Vss) connection. In order to power its various components, each standard cell is typically coupled to a backside power rail that is electrically connected to the active layer of the standard cell to provide power (Vdd). In some examples, multiple backside power rails may be provided for each standard cell to provide power (Vdd) and ground (Vss), respectively.

[0004] The backside power rail is usually formed on the backside of the wafer. Such backside power rail is connected to the source / drain region of the field effect transistor (FET) using a VBPR contact structure. The size of the prior art VBPR contact structure is limited by the contact poly spacing between two adjacent gate structures. Summary of the invention

[0005] A semiconductor structure with improved performance is provided, which includes a locally enlarged VBPR contact structure connecting one of the source / drain regions of a field effect transistor (FET) to a backside power rail. In the present application, the term "via-to-backside power rail contact structure or VBPR contact structure" refers to a contact structure having a via portion connected to the backside power rail and a non-via portion connected to one of the source / drain regions of the FET.

[0006] In one aspect of the present application, a semiconductor structure is provided. In one embodiment of the present application, the semiconductor structure includes a first active device region and a second active device region, the first active device region includes a first FET having a first source / drain region and a second source / drain region, the second active device region is positioned adjacent to the first active device region and includes a second FET, wherein the end wall of the functional gate structure of the first FET faces the end wall of the functional gate structure of the second FET. The gate cut region is located between the first FET and the second FET, and the VBPR contact structure exists in the gate cut region between the first FET and the second FET. In the present application, the VBPR contact structure contacts the backside power rail and the first source / drain region of the first FET. Therefore, the VBPR contact structure routes the first FET to the backside power rail.

[0007] In some embodiments of the present application, the VBPR contact structure extends from the first source / drain region of the first FET through the gate cut region to the second source / drain region. This allows coupling between the first and second source / drain regions of the first FET using a single VBPR contact structure.

[0008] In some embodiments of the present application, the VBPR has a first width in a region between the first source / drain region of the first FET and the first source / drain region of the second FET and between the second source / drain region of the first FET and the second source / drain region of the second FET, and has a second width in a region between an end wall of a functional gate structure of the first FET and an end wall of a functional gate structure of the second FET, wherein the first width is greater than the second width. This provides an enlarged VPBR contact structure, which in turn improves the performance of the device.

[0009] In some embodiments of the present application, the gate cut region includes a double-layer dielectric filling structure, which includes an inner dielectric material layer and an outer dielectric material layer. In such an embodiment, the outer dielectric material layer is present around the end wall of the functional gate structure of both the first FET and the second FET. The double-layer dielectric filling structure provides electrical insulation between the VPBR contact structure and the first and second FETs.

[0010] In some embodiments of the present application, the structure further includes a front side source / drain contact structure in contact with each of the first source / drain region of the second FET and the second source / drain region of the second FET, wherein an external dielectric material layer is present between the front side source / drain contact structure and the VBPR contact structure. This provides wiring to the front side devices.

[0011] In some embodiments of the present application, the structure further comprises a front-side back-end-of-line (BEOL) structure contacting at least the VBPR contact structure. In such embodiments, a carrier wafer may be located on the front-side BEOL structure.

[0012] In some embodiments of the present application, the backside power rail is located in the backside interlayer dielectric (ILD) material layer. In some embodiments of the present application, the structure also includes a backside power distribution network that contacts both the backside ILD material layer and the backside power rail. This provides integration of the structure to the backside power distribution network.

[0013] In some embodiments of the present application, the structure includes a shallow trench isolation structure laterally surrounding a portion of the VBPR contact structure. In such embodiments, the shallow trench isolation structure contacts a surface of the backside power rail.

[0014] In some embodiments of the present application, the VBPR contact structure has a surface opposite to a surface contacting the backside power rail that is coplanar with surfaces of both the first FET and the second FET.

[0015] In some embodiments of the present application, each of the first FET and the second FET is a nanosheet-containing FET. In such embodiments, the nanosheet-containing FET includes a functional gate structure of the first FET and the second FET surrounding a plurality of vertically stacked semiconductor channel material nanosheets.

[0016] In some embodiments of the present application, the structure further comprises a gate spacer positioned laterally adjacent to the functional gate structures of the first FET and the second FET, wherein portions of the sidewalls of the functional gate structures of the first FET and the second FET near the gate cut region are free of the gate spacer. This allows for an expanded VBPR contact structure.

[0017] In some embodiments of the present application, the VBPR contact structure is completely separated from the second FET present in the second active device region by an outer dielectric material layer of the double-layer dielectric filling structure present in the gate cut region.

[0018] In some embodiments of the present application, a sidewall of a functional gate structure of the first FET is aligned with a sidewall of a functional gate structure of the second FET.

[0019] In some embodiments of the present application, the sidewall of the first source / drain region of the first FET is separated from the VBPR contact structure by an outer dielectric material layer of the double-layer dielectric filling structure present in the gate cut region.

[0020] In another aspect of the present application, a method for forming a semiconductor structure is provided. The method includes performing a gate cutting after forming a functional gate structure and a source / drain region (i.e., a FET). Next, a double-layer dielectric material filling structure is formed in the gate cutting region provided by the gate cutting process. The inner dielectric material layer of the double-layer dielectric material filling structure is selectively removed, and thereafter a VBPR contact structure is formed in the region previously including the inner dielectric material layer and on top of one of the source / drain regions. The VBPR contact structure is then connected to a backside power rail. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1A -1D are various views of an exemplary structure that can be used in the present application, the exemplary structure including a plurality of uncut functional gate structures oriented parallel to each other and perpendicular to two spaced-apart active device regions, within each active device region, the uncut functional gate structure surrounds a plurality of vertically stacked semiconductor channel material nanosheets, and within each active device region, there are source / drain regions on opposite sides of the uncut functional gate structure, the exemplary structure also including a semiconductor substrate and a front-side interlayer dielectric material (ILD) layer located between each uncut functional gate structure.

[0022] Figure 2A -2D are respectively after cutting each functional gate structure located between two active device regions to provide a gate cutting trench located between the two active device regions and providing a cut functional gate structure in each active device region Figure 1A - Various views of the exemplary structure shown in -1D, wherein the end walls of the cut functional gate structures in one of the active device regions face the end walls of the cut functional gate structures in the other active device region.

[0023] Figure 3A -3D are respectively after enlarging the width of the gate cutting trench between the source / drain regions of the cut functional gate structure and reducing the length of each gate spacer to physically expose the sidewall of each cut functional gate structure close to the gate cutting trench Figure 2A - Various views of an exemplary structure shown in 2D.

[0024] Figure 4A -4D after forming a double-layer dielectric material filling structure in the enlarged gate cut trench and on the physically exposed sidewalls of each cut functional gate structure Figure 3A - Various views of an exemplary structure shown in 3D.

[0025] Figure 5A -5D are respectively after forming a patterned mask layer having an opening that physically exposes the double-layer dielectric material filling structure Figure 4A- Various views of the exemplary structure shown in 4D.

[0026] Fig. 6A -6D are respectively after forming the VBPR trench in the gate cutting area Figure 5A - Various views of the exemplary structure shown in 5D.

[0027] Fig. 7A -7D are respectively after removing the patterned mask layer, forming source / drain contact openings, and filling the VBPR trench and each source / drain contact opening with at least a contact conductor material Fig. 6A - Various views of the exemplary structure shown in 6D.

[0028] Fig. 8A -8D is after forming the front-end back-end of line (BEOL) structure and carrier wafer, Fig. 7A - Various views of the exemplary structure shown in 7D.

[0029] Fig. 9A -9D are respectively after the wafer is flipped and the first semiconductor material layer of the semiconductor substrate is removed to physically expose the etching stop layer of the semiconductor substrate Fig. 8A - Various views of the exemplary structure shown in 8D.

[0030] Fig. 10A -10D are respectively after removing the etching stop layer to physically expose the second semiconductor material layer of the semiconductor substrate Fig. 9A - Various views of the exemplary structure shown in 9D.

[0031] Fig.11A -11D are respectively after the second semiconductor material layer of the semiconductor substrate is recessed Fig. 10A - Various views of the exemplary structure shown in 10D.

[0032] Fig. 12A -12D are respectively after forming the backside ILD material layer and forming the backside power rail in the backside ILD material layer Fig.11A - Various views of the exemplary structure shown in 11D.

[0033] Fig.13A -13D are after forming the backside power distribution network Fig. 12A - Various views of the exemplary structure shown in 12D. DETAILED DESCRIPTION

[0034] The present application will now be described in more detail by reference to the following discussion and the accompanying drawings of the present application. Note that the drawings of the present application are for illustrative purposes only and therefore the drawings are not drawn to scale. It should also be noted that identical and corresponding elements are represented by identical reference numerals.

[0035] In the following description, many specific details, such as specific structures, components, materials, dimensions, processing steps and techniques are set forth to provide an understanding of the various embodiments of the present application. However, it will be appreciated by those of ordinary skill in the art that the various embodiments of the present application can be practiced without these specific details. In other cases, in order to avoid obscuring the present application, well-known structures or processing steps are not described in detail.

[0036] It will be understood that when an element as a layer, region, or substrate is referred to as being "on" or "above" another element, it can be directly on the other element, or there can be intervening elements. Conversely, when an element is referred to as being "directly on" or "directly above" another element, there are no intervening elements. It will also be understood that when an element is referred to as being "below" or "under" another element, it can be directly below or under the other element, or there can be intervening elements. Conversely, when an element is referred to as being "directly below" or "directly under" another element, there are no intervening elements.

[0037] It should be understood that although the terms first, second, etc. can be used to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the scope of this concept, the first element discussed below can be referred to as the second element.

[0038] Before discussing the present application in detail, the present application provides various views showing exemplary structures through various processing steps of the present application. The various processing steps include performing a gate cut after forming a functional gate structure and a source / drain region (i.e., a FET), forming a double-layer dielectric material filling structure in the gate cut region provided by the gate cutting process, selectively removing the inner dielectric material layer of the double-layer dielectric material filling structure, and forming a VBPR contact structure in the region previously including the inner dielectric material layer and on top of one of the source / drain regions. The VBPR contact structure is then connected to the backside power rail.

[0039] It is worth noting that Figure 1A , 2A, 3A, 4A, 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A and 13A are top views of device layouts that show exemplary structures that can be used in the present application. In these top views, only the basic elements / components required for orientation purposes are shown; non-essential elements / components that are not required for orientation purposes are omitted from the top views. Each top view includes a tangent line XX, a tangent line Y1-Y2 and a tangent line Y2-Y2. The tangent line XX is an area between two active device regions (i.e., the first active device region 100 and the second active device region 102) in which gate cutting will occur; this area is referred to herein as a gate cutting area. The tangent line Y1-Y1 is in the area between two adjacent gate structures (i.e., the uncut functional gate structure 21 or the cut functional gate structure 22) located along the length of the gate structure. The tangent line Y2-Y2 passes through one of the gate structures (i.e., the uncut functional gate structure 21 or the cut functional gate structure 22). The Y1-Y1 and Y2-Y2 cuts extend through the first active device region 100, the gate cut region, and the second active device region 102. Figures 1B, 2B, 3B, 4B, 5B, 6B, 7B, 8B, 9B, 10B, 11B, 12B, and 13B are cross-sectional views along the cut line XX, Figures 1C, 2C, 3C, 4C, 5C, 6C, 7C, 8C, 9C, 10C, 11C, 12C, and 13C are cross-sectional views along the cut line Y1-Y1, and Figures 1D, 2D, 3D, 4D, 5D, 6D, 7D, 8D, 9D, 10D, 11D, 12D, and 13D are cross-sectional views along the cut line Y2-Y2. In the present application, the term "active device region" refers to a region where a functional device such as a FET is formed.

[0040] Note that although the present application describes and illustrates a FET containing nanosheets, i.e., a FET in which a functional gate structure surrounds a plurality of vertically stacked semiconductor channel material nanosheets, the present application also works for other types of FETs, such as a planar FET, a FinFET, a stacked FET, or a semiconductor nanowire FET. In the present application, the term "FET" is used to describe a device that includes a functional gate structure contacting a semiconductor channel material structure and having source / drain regions located on each side of the functional gate structure.

[0041] First reference Figure 1A-1D, an exemplary structure that can be used in the present application is shown through various views. The exemplary structure includes a plurality of uncut functional gate structures 21, which are oriented parallel to each other and perpendicular to two spaced apart active device regions (i.e., the first active device region 100 and the second active device region 102). The term "uncut" when used in conjunction with the term "functional gate structure" means that the functional gate structure extends continuously from the first active device region 100 to the second active device region 102 without forming any breaks or gaps therein. In each active device region (i.e., the first active device region 100 and the second active device region 102), each uncut functional gate structure 21 surrounds a plurality of vertically stacked semiconductor channel material nanosheets 21, and in each active device region (i.e., the first active device region 100 and the second active device region 102), there are source / drain regions 23 on opposite sides of the uncut functional gate structure 21. The exemplary structure also includes a semiconductor substrate 10 / 12 / 14, a shallow trench isolation structure 16, a gate dielectric spacer 20 located on the sidewalls of each uncut functional gate structure 21, and a front-side interlayer dielectric material (ILD) material layer 24 located between each uncut functional gate structure 21 and on top of the source / drain region 23. As shown, each source / drain region 23 contacts the surface of the semiconductor substrate.

[0042] The semiconductor substrate includes a first semiconductor material layer 10, an etch stop layer 12, and a second semiconductor material layer 14. The first semiconductor material layer 10 of the semiconductor substrate is composed of a first semiconductor material having semiconductor properties. Examples of the first semiconductor material that can be used to provide the first semiconductor material layer 10 include, but are not limited to, silicon (Si), silicon germanium (SiGe) alloys, silicon germanium carbide (SiGeC) alloys, germanium (Ge), III / V compound semiconductors, or II / VI compound semiconductors. The second semiconductor material layer 14 of the semiconductor substrate is composed of a second semiconductor material. The second semiconductor material providing the second semiconductor material layer 14 may be the same or different in composition from the first semiconductor material providing the first semiconductor material layer 10. In some embodiments of the present application, the etch stop layer 12 may be composed of a dielectric material, such as silicon dioxide and / or boron nitride. In other embodiments of the present invention, the etch stop layer 12 is composed of a semiconductor material that is different in composition from the semiconductor material providing the first semiconductor material layer 10 and the second semiconductor material layer 14. In one example, the first semiconductor material layer 10 is composed of silicon, the etch stop layer 12 is composed of silicon dioxide, and the second semiconductor material layer 14 is composed of silicon. Such a semiconductor substrate including silicon / silicon dioxide / silicon may be referred to as a silicon-on-insulator (SOI) substrate. In another example, the first semiconductor material layer 10 is composed of silicon, the etch stop layer 12 is composed of silicon germanium, and the second semiconductor material layer 14 is composed of silicon. Such a semiconductor substrate including silicon / silicon germanium / silicon may be referred to as a bulk semiconductor substrate.

[0043] The shallow trench isolation structure 16 is made of any trench dielectric material, such as silicon oxide. In some embodiments, the trench dielectric material, such as SiN, may exist along the sidewalls and bottom walls of the trench dielectric material. As shown in FIG. 1B , each uncut functional gate structure 21 and gate spacer 20 lands on the surface of the shallow trench isolation structure 16, and as shown in FIG. 1C , the shallow trench isolation structure 16 is laterally adjacent to the unetched portion of the second semiconductor material layer 14 of the semiconductor substrate.

[0044] Each semiconductor channel material nanosheet 18 is composed of one of the semiconductor materials of the first semiconductor material layer 10 for the semiconductor substrate described above. The semiconductor material providing each semiconductor material nanosheet 18 may be the same or different in composition from the second semiconductor material providing the second semiconductor layer 14 of the semiconductor substrate. In some embodiments, each semiconductor channel material nanosheet 18 is composed of a semiconductor material capable of providing a high channel mobility for an nFET device. In other embodiments, each semiconductor channel material nanosheet 18 is composed of a semiconductor material capable of providing a high channel mobility for a pFET device. In one example, each semiconductor material nanosheet 18 is composed of silicon. In the present application, there are multiple semiconductor material nanosheets 18.

[0045] Each uncut functional gate structure 21 includes at least a gate dielectric material layer and a gate electrode; the gate dielectric material layer and the gate electrode are not shown separately in the drawings of the present application. As is well known, the gate dielectric material layer of the uncut functional gate structure 21 is in direct contact with each semiconductor channel material nanosheet 18, and the gate electrode is located on the gate dielectric material layer. In some embodiments, the gate structure includes a work function metal (WFM) layer (not shown) located between the gate dielectric material layer and the gate electrode. In other embodiments, the WFM layer is used only as a gate electrode.

[0046] The gate dielectric material layer of each uncut functional gate structure 21 is composed of a gate dielectric material such as silicon oxide or a dielectric material having a dielectric constant greater than 4.0 (such a dielectric material may be referred to as a high-k gate dielectric material). Unless otherwise specified, all dielectric constants mentioned herein are measured in a vacuum. Illustrative examples of high-k gate dielectric materials include metal oxides, such as hafnium dioxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiO), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlO3), zirconium dioxide (ZrO2), zirconium silicon oxide (ZrSiO4), zirconium silicon oxynitride (ZrSiO x N y ), tantalum oxide (TaO x ), titanium oxide (TiO), barium strontium titanium oxide (BaO6SrTi2), barium titanium oxide (BaTiO3), strontium titanium oxide (SrTiO3), yttrium oxide (Yb2O3), aluminum oxide (Al2O3), lead scandium tantalum oxide (Pb(Sc,Ta)O3) and / or lead zinc niobium (Pb(Zn,Nb)O). The high-k gate dielectric material may also include dopants such as lanthanum (La), aluminum (Al) and / or magnesium (Mg).

[0047] The gate electrode of each uncut functional gate structure 21 may include a conductive metal-containing material, including but not limited to tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), zirconium (Zr), cobalt (Co), copper (Cu), aluminum (Al), lead (Pb), platinum (Pt), tin (Sn), silver (Ag) or gold (Au), tantalum nitride (TaN), titanium nitride (TiN), tantalum carbide (TaC X ), titanium carbide (TiC), titanium aluminum carbide, tungsten silicide (WSi2), tungsten nitride (WN), ruthenium oxide (RuO2), cobalt silicide or nickel silicide.

[0048] In some embodiments, the WFM layer can be used as a conductive metal-containing material to provide a gate electrode or as a separate layer located between a front layer of gate dielectric material and a gate electrode. The WFM layer can be used to set the threshold voltage of the FET to a desired value. In some embodiments, the WFM layer can be selected to achieve an n-type threshold voltage shift. As used herein, "n-type threshold voltage shift" means the shift of the effective work function of the work function metal-containing material toward the conduction band of silicon in the silicon-containing material. In one embodiment, the work function of the n-type work function metal is in the range of 4.1eV to 4.3eV. Examples of such materials that can achieve an n-type threshold voltage shift include, but are not limited to, titanium aluminum, titanium aluminum carbide, tantalum nitride, titanium nitride, hafnium nitride, hafnium silicon, or a combination thereof. In other embodiments, the WFM layer can be selected to achieve a p-type threshold voltage shift. In one embodiment, the work function of the p-type work function metal is in the range of 4.9eV to 5.2eV. As used herein, "threshold voltage" is the lowest achievable gate voltage that will turn on a semiconductor device (e.g., a transistor) by turning on the channel of the device. As used herein, the term "p-type threshold voltage shift" refers to a shift of the effective work function of a work function metal-containing material toward the valence band of silicon in a silicon-containing material. Examples of such materials that can achieve a p-type threshold voltage shift include, but are not limited to, titanium nitride, tantalum carbide, hafnium carbide, and combinations thereof.

[0049] The gate spacer 20 is composed of a gate spacer dielectric material. Examples of gate spacer dielectric materials that can be used to provide the gate spacer 20 include, but are not limited to, SiN, SiBCN, SiOCN, or SiOC. Although not shown in any of the illustrated views, the exemplary structure also includes an internal spacer that is present between the ends of each semiconductor channel material nanosheet 18 within each vertically stacked semiconductor channel material nanosheet 18 and below the end of the bottommost semiconductor channel nanosheet and the semiconductor substrate 10 / 12 / 14. Each internal spacer is composed of one of the gate spacer dielectric materials described above for the gate spacer 20, and the gate spacer dielectric material that provides the internal spacer can be the same or different in composition from the gate dielectric spacer material that provides the gate spacer 20.

[0050] Each source / drain region 23 is composed of a semiconductor material and a dopant. The "source / drain or S / D" region used herein can be a source region or a drain region, depending on the subsequent wiring and the voltage applied during the operation of the field effect transistor (FET). As is known, the source / drain region is located on each side of the gate structure. The semiconductor material providing the source / drain region 23 can include one of the semiconductor materials of the first semiconductor material layer 10 for the semiconductor substrate described above. The semiconductor material providing the source / drain region 23 can be the same or different in composition from each semiconductor channel material nanosheet 18. The dopant present in the source / drain region 23 can be a p-type dopant or an n-type dopant. The term "p-type" refers to the addition of impurities to an intrinsic semiconductor, which produces a lack of valence electrons. In silicon-containing semiconductor materials, examples of p-type dopants, i.e., impurities, include but are not limited to boron, aluminum, gallium, phosphorus, and indium. "N-type" refers to the addition of impurities that contribute free electrons to an intrinsic semiconductor. In silicon-containing semiconductor materials, examples of n-type dopants, i.e., impurities, include but are not limited to antimony, arsenic, and phosphorus. In one example, the source / drain region 23 may have a width from 4×10 20 Atom / cm 3 to 3×10 21 Atom / cm 3 of dopant concentration.

[0051] The front ILD material layer 24 may be made of a dielectric material, such as silicon oxide, silicon nitride, undoped silicate glass (USG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), a spin-on low-k dielectric layer, a chemical vapor deposition (CVD) low-k dielectric layer, or any combination thereof. The term "low-k" used throughout this application refers to a dielectric material having a dielectric constant of less than 4.0. In addition to being present between each uncut functional gate structure 21, the front ILD material layer 24 also embeds a source / drain region 23, as shown in FIG. 1C .

[0052] Figure 1A The exemplary structure shown in -1D can be formed using any known nanosheet-containing transistor formation process. In order not to obscure the method of the present application and the resulting structure formed by the method of the present application, the process of forming the nanosheet is not described herein. Figure 1A -1D shows the processing steps used in the exemplary structure.

[0053] Reference now Figure 2A-2D, respectively, show after cutting each uncut functional gate structure 21 between two active device regions (i.e., the first active device region 100 and the second active device region 102) to provide a gate cutting trench 28 between the two active device regions (i.e., the first active device region 100 and the second active device region 102) and providing a cut functional gate structure 22 in each active device region (i.e., the first active device region 100 and the second active device region 102), Figure 1A - The exemplary structure shown in 1D, where Figure 2A As shown, the end walls E1 of the cut functional gate structures 22 in each active device region face each other. The facing end walls E1 of the cut functional gate structures 22 are located near the gate cut trench 28. The gate cut trench 26 defines the gate cut region of the exemplary structure.

[0054] The gate cut mask 26 is formed by first forming a patterned gate cut mask 26 having an opening. Figure 2A -2D, the opening physically exposes the front side ILD material layer 24, a portion of the gate spacer 20 and a portion of the uncut functional gate structure 21 in the region between the first and second active device regions 100, 102 where the gate cut is desired, wherein the front side ILD material layer 24 is located between the source / drain regions 23 of the uncut functional gate structure 21. The patterned gate cut mask 26 can be composed of, for example, a mask material such as an organic planarization layer (OPL). The patterned gate cut mask 26 can be formed by depositing a mask material and then patterning the deposited mask material. Etching such as reactive ion etching (RIE), plasma etching or ion beam etching (IBE) can be used to remove the physically exposed material, thereby providing a gate cut trench 28. Note that after the gate cut process, the gate cut trench 28 physically exposes the shallow trench isolation layer 16, as shown in Figures 2B and 2C.

[0055] Reference now Figure 3A -3D, respectively, show after the width of the gate cut trench 28 is enlarged (providing an enlarged gate cut trench 28E) and the length of each gate spacer 20 is reduced to physically expose the sidewall of each cut functional gate structure 22 near the gate cut trench 28, Figure 2A -2D. Enlarging the width of the gate cut trench 28 includes a selective etching process that removes any front side ILD material layer 24 from the opposing sidewalls of the source / drain regions 23 present between the gate cut trenches 28. As shown in FIG. 3C, the selective etching provides an overhang region 30 below the patterned mask layer 26. Reducing the length of the gate spacer 20 includes a spacer etch that selectively removes a portion of the gate spacer 20 to provide a gate spacer 20S of reduced length. Figure 3AAs shown, the gate spacer 20S of reduced length does not exist on the entire sidewall of each cut functional gate structure 22. Therefore, the sidewall of the cut functional gate structure 22 adjacent to the gate cut trench 28 is now physically exposed. This enables the formation of an enlarged gate cut trench 28E.

[0056] Reference now Figure 4A -4D, respectively, show the double-layer dielectric material filling structure 32 / 34 after forming in the enlarged gate cut trench 28E and on the physically exposed sidewalls of each cut functional gate structure 22 Figure 3A - Exemplary structure shown in 3D. Before forming the dual-layer dielectric material filling structure 32 / 34, the patterned mask layer 26 may be removed from the exemplary structure using a material removal process that selectively removes the patterned mask layer 26. The dual-layer dielectric material filling structure 32 / 34 provides electrical insulation in the structure.

[0057] The double-layer dielectric material filling structure 32 / 34 includes an outer dielectric material layer 32 laterally adjacent to and surrounding an inner dielectric material layer 34. In the present application, the outer dielectric material layer 32 is composed of a first dielectric material that is different in composition from a second dielectric material that provides the inner dielectric material layer 34. The first and second dielectric materials that provide the outer dielectric material layer 32 and the inner dielectric material layer 34, respectively, may include a silicon nitride-based dielectric material, such as silicon nitride, silicon boron carbon nitride, or a dielectric including Si, O, C, and N atoms, a silicon carbon-based dielectric material, such as silicon carbide or a dielectric including Si, C, and O atoms, or any other dielectric material, such as silicon dioxide. In one example, the outer dielectric material layer 32 is composed of a dielectric including Si, C, and O atoms or silicon carbide, while the inner dielectric material layer 34 is composed of silicon dioxide. The first and second dielectric materials are different in composition from the front-side ILD material layer 24.

[0058] The double-layer dielectric material filling structure 32 / 34 can be formed by first depositing a blanket layer of a first dielectric material on the top surface of the enlarged gate cut trench 28E and the example structure, and then using directional etching to remove the blanket layer of the first dielectric material from all horizontal surfaces forming the outer dielectric material layer 32, as shown in the figure. Note that the outer dielectric material layer 32 is a liner present on the sidewalls of the enlarged gate cut trench 28E. Next, a blanket layer of a second dielectric material is deposited, and then a planarization process, such as chemical mechanical polishing (CMP), is performed to remove the second dielectric material formed outside the gate cut trench 28. The first deposition and the second deposition may include CVD, plasma enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD). The remaining first dielectric material in the enlarged gate cut trench 28E provides the outer dielectric material layer 32, and the remaining second dielectric material in the enlarged gate cut trench 28E forms the inner dielectric material layer 34. The double-layer dielectric material filling structure 32 / 34 including the outer dielectric material layer 32 and the inner dielectric material layer 34 has an uppermost surface coplanar with the uppermost surface of at least each cut functional gate structure 22 and the remaining front-side ILD material layer 24 .

[0059] Reference now Figure 5A -5D, respectively, show after forming a patterned mask layer 36 having openings 38 that physically expose the dual-layer dielectric material filling structure 32 / 34 Figure 4A -4D. The patterned mask layer 36 includes the mask material for the patterned gate cutting mask 26 described above, and the patterned mask layer 36 can be formed using the process steps for forming the patterned gate cutting mask 26 described above. In the Y1-Y1 cutting as shown in FIG. 5C, the opening 38 in the patterned mask layer 36 physically exposes the inner dielectric material layer 34 of the double-layer dielectric material filling structure 32 / 34; the inner dielectric material layer 34 in this area is completely protected or at least partially protected by the patterned mask layer 36. In the Y2-Y2 cutting as shown in FIG. 5D, the opening 38 in the patterned mask layer 36 physically exposes the inner dielectric material layer 34 and the outer dielectric material layer 32 of the double-layer dielectric material filling structure 32 / 34.

[0060] Reference now Fig. 6A -6D, respectively, show the gate cut region after the VBPR trench 39 is formed. Figure 5A-5D. The VBPR trench 39 is formed by first removing the inner dielectric material layer 34 using an etching process (e.g., reactive ion etching) that is selective in removing the inner dielectric material layer 34. The patterned mask layer 36 is used as an etching mask during this selective etching. Another etching or the same selective etching can be used to remove the shallow trench dielectric structure 16 present under the inner dielectric material layer 34 so as to physically expose the second semiconductor layer 14 of the semiconductor substrate. During the etching to remove the shallow trench isolation structure 16 present under the inner dielectric material layer 34, the patterned mask layer 36 is used as an etching mask.

[0061] Reference now Fig. 7A -7D, respectively, shows the VBPR trench 39 and each source / drain contact opening after removing the patterned mask layer 36, forming source / drain contact openings (not specifically shown), and filling the VBPR trench 39 and each source / drain contact opening with at least a contact conductor material. Fig. 6A -6D. Note that in the present application, source / drain contact openings are formed in communication with VBPR trench 39 to allow for the formation of a combined source / drain contact opening / VBPR trench that will subsequently be filled with at least a contact conductor material. According to the present application, at least the combined source / drain contact opening / VBPR trench filled with the contact conductor material provides a VBPR contact structure 40 that, at this point in the present application, has a surface that contacts one of the source / drain regions 23 of one of the FETs (e.g., see FIG. 7C). At least the contact material filled source / drain contact openings provide a front side source / drain contact structure 42, as shown in FIG. 7C.

[0062] As described above, the VBPR contact structure 40 and the front side source / drain contact structure 42 include at least a contact conductor material. Optional contact pads may be present on the sidewalls and bottom-most surfaces of the VBPR contact structure 40 and the front side source / drain contact structure 42. The contact conductor material may include, for example: a silicide liner, such as Ni, Pt, NiPt; an adhesion metal liner, such as TiN; and a conductive metal, such as W, Cu, Al, Co, Ru, Mo, Os, Ir, Rh, or alloys thereof. The contact conductor material may be formed by any suitable deposition method, such as ALD, CVD, physical vapor deposition (PVD), or plating. The VBPR contact structure 40 and the front side source / drain contact structure 42 may be formed by forming contact openings in the front side ILD material layer 34; these contact openings physically expose the source / drain regions 23. Each contact opening and combined source / drain contact openings / VBPR trenches is then filled with a contact conductor material and then planarized to remove any contact conductor material outside of the contact openings and combined source / drain contact openings / VBPR trenches.

[0063] The front side source / drain contact structures 42 and the VBPR contact structures 40 may include one or more contact pads (not shown) formed along the sidewalls of the contact openings and the combined contact openings / VBPR trenches before forming the front side source / drain contact structures 42 and the VBPR contact structures 40. In one or more embodiments, the contact pads (not shown) may include a diffusion barrier material. Exemplary diffusion barrier materials include, but are not limited to, Ti, Ta, Ni, Co, Pt, W, Ru, TiN, TaN, WN, WC, alloys thereof, or stacks thereof, such as Ti / TiN and Ti / WC. The contact pads may be formed using a conformal deposition process including CVD or ALD. The formed contact pads may have a thickness ranging from 1 nm to 5 nm, although lesser or greater thicknesses may also be used.

[0064] In one or more embodiments where a contact pad is present, the contact pad (not shown) may include a silicide liner, such as Ti, Ni, NiPt, etc., and a diffusion barrier material. Exemplary diffusion barrier materials include, but are not limited to, Ru, TiN, TaN, WN, WC, alloys thereof, or stacks thereof, such as Ti / TiN and Ti / WC. The contact pad may be formed using a conformal deposition process including PVD, CVD, or ALD. The formed contact pad may have a thickness ranging from 1 nm to 8 nm, although lesser or greater thicknesses may also be used.

[0065] like Fig. 7A As shown, the VBPR contact structure 40 has a first width W1 in the region between the first source / drain region 23 of the first FET and the first source / drain region 23 of the second FET and between the second source / drain region 23 of the first FET and the second source / drain region of the second FET, and has a second width W2 in the region between the end of the functional gate structure 22 of the first FET and the functional gate structure of the second FET, wherein the first width is greater than the second width. Such an enlarged VBPR contact structure 40 provides enhanced characteristics for the final structure.

[0066] Reference now Fig. 8A -8D, respectively, after forming the front side BEOL structure 44 and the carrier wafer 46 Fig. 7A -7D. The front side BEOL structure 44 includes one or more interconnect dielectric material layers, which include one or more wiring areas embedded thereon. The front side BEOL structure 44 can be formed using BEOL processing techniques known to those skilled in the art. As shown in Figures 8B-8D, the front side BEOL contact structure 44 contacts the VBPR contact structure 40. The carrier wafer 46 can include one of the semiconductor materials described above for the first semiconductor material layer 10. In the present application, the carrier wafer 46 is bonded to the front side BEOL structure 44.

[0067] Reference now Fig. 9A -9D, respectively, show the state after the wafer is flipped and the first semiconductor material layer 10 of the semiconductor substrate is removed so as to physically expose the etching stop layer 12 of the semiconductor substrate. Fig. 8A - The exemplary structure shown in 8D. Flipping will allow backside processing of the exemplary structure. In this application, the structure is flipped 180° (note that Fig. 8A as well as Fig. 9A , 10A , 11A, 12A and 13A are not flipped in order to continue to explain the device layout of the structure). The flipping of the structure can be performed by hand or by using a mechanical device such as a robot arm. The removal of the first semiconductor material layer 10 can be performed using a material removal process that is selective in removing the semiconductor material that provides the first semiconductor material layer 10.

[0068] Reference now Fig. 10A -10D, respectively, show the etching stop layer 12 after it is removed to physically expose the second semiconductor material layer 14 of the semiconductor substrate Fig. 9A - The exemplary structure shown in FIG9D. The removal of the etch stop layer 12 includes a material removal process that is selective in removing the etch stop layer 12.

[0069] Reference now Fig.11A -11D, respectively show the second semiconductor material layer 14 of the semiconductor substrate after being recessed Fig. 10A - Various views of the exemplary structure shown in FIG10D. The recessing of the second semiconductor material layer 14 includes a material removal process that is selective in removing the second semiconductor material layer 14. A portion of the second semiconductor material layer 14 remains in contact with the surface of the source / drain region 23 and in contact with the shallow trench isolation structure 16 along the sidewall, as shown in FIG11C.

[0070] Reference now Fig. 12A -12D, respectively, show the back side ILD material layer 48 after forming and the back side power supply track 50 in the back side ILD material layer 48 Fig.11A -11D. The backside ILD material layer 48 includes one of the dielectric materials mentioned above for the frontside ILD material layer 24. The backside ILD material layer 48 may be formed using a deposition process such as CVD, PECVD, ALD or spin coating.

[0071] The backside power rail 50 is composed of any conductive power rail material, including but not limited to tungsten (W), cobalt (Co), ruthenium (Ru), aluminum (Al), copper (Cu), platinum (Pt), rhodium (Rh) or palladium (Pd), wherein a thin metal adhesion layer (such as TiN, TaN) is usually formed before the conductive metal deposition; for clarity, the metal adhesion layer is not separately shown in the drawings of the present application. The backside power rail 50 can be formed by forming a backside power rail opening in the backside ILD material layer; the backside power rail opening physically exposes at least the surface of the VBPR contact structure 40. The backside power rail opening is then filled with at least one of the above-mentioned conductive power rail materials, and a planarization process is performed after filling the backside power rail opening. The filling may include CVD, PECVD, ALD, sputtering or electroplating.

[0072] Reference now Fig.13A -13D, respectively, show the back side power distribution network 52 after forming Fig. 12A -12D. A backside power distribution network 52 is formed on top of the backside ILD material layer 48 including the backside power rails 50 embedded therein. Thus, the backside power distribution network 52 contacts the backside power rails 50. The backside power distribution network 52 includes elements / components configured to distribute power to the FETs.

[0073] It is worth noting that Fig.13A -13D shows an exemplary structure of the present application. The exemplary structure includes a first active device region 100, which includes a first FET F1 having a first source / drain region 23 and a second source / drain region (not shown), and a second active device region 102, which is located near the first active device region 100 and includes a second FET F2. The end wall of the functional gate structure 22 of F1 faces the end wall of the functional gate structure of F2. The gate cut region is located between F1 and F2, and the VBPR contact structure 40 exists in the gate cut region. In the present application, the VBPR contact structure 40 contacts the backside power rail 50 and the first source / drain region 23 of F1. As shown in FIG. Fig.13A As shown, the VBPR contact structure 40 extends from the first source / drain region 23 through the gate cut region to the second source / drain region of F1. As described above, the gate cut region includes a double-layer dielectric filling structure 32 / 34, which includes an inner dielectric material layer 32 and an outer dielectric material layer 34. In the present application, as shown in FIG. Fig.13A As shown, an outer dielectric material layer 32 exists around the end walls of the functional gate structures 22 of F1 and F2 and along the side walls of the source and drain regions 23. This provides electrical insulation for the structure. Fig.13AAs shown in FIG. 13C , the front side source / drain contact structure 42 contacts each of the first source / drain region 23 of F2 and the second source / drain region 23 of F2, wherein an external dielectric material layer 32 is present between the front side source / drain contact structure 42 and the VBPR contact structure 40. As described above, the front side BEOL structure 44 contacts at least the VBPR contact structure 40, and the carrier wafer 46 contacts the front side BEOL structure 44. As also shown, there is a back side power distribution network 52 that contacts both the back side ILD material layer 48 and the back side power rail 50. In the present application, and as further shown, the shallow trench isolation structure 16 laterally surrounds a portion of the VBPR contact structure 40, and according to the present application, and as shown in the accompanying drawings, the VBPR contact structure is completely separated from F2 by the external dielectric material layer 32 of the double-layer dielectric fill structure 32 / 34 present in the gate cut region. In the present application, as Fig.13A As shown, the sidewalls of the functional gate structure 22 of F1 are aligned with the sidewalls of the functional gate structure 22 of F2, and as shown in FIG. 13C, the sidewalls of the first source / drain region 23 of F1 are separated from the VBPR contact structure 40 by the outer dielectric material layer 32 of the double-layer dielectric filling structure 32 / 34 present in the gate cut region.

[0074] Although the present application has been specifically shown and described with reference to the preferred embodiments of the present application, it should be understood by those skilled in the art that the foregoing and other changes may be made in form and detail without departing from the scope of the present application. Therefore, the present application is not intended to be limited to the exact form and details described and shown, but to fall within the scope of the appended claims.

Claims

1. A semiconductor structure comprising: a first active device region including a first field effect transistor (FET) having a first source / drain region and a second source / drain region; a second active device region located adjacent to the first active device region and comprising a second FET, wherein an end wall of a functional gate structure of the first FET faces an end wall of a functional gate structure of the second FET; a gate cut region between the first FET and the second FET; as well as A via-to-backside power rail (VBPR) contact structure is located in the gate cut region, the gate cut region is located between the first FET and the second FET, wherein the VBPR contact structure contacts the backside power rail and the first source / drain region of the first FET. 2 . The semiconductor structure of claim 1 , wherein the VBPR contact structure extends from the first source / drain region of the first FET to the second source / drain region through the gate cut region.

3. A semiconductor structure according to claim 2, wherein the VBPR contact structure has a first width in a region between the first source / drain region of the first FET and the first source / drain region of the second FET and between the second source / drain region of the first FET and the second source / drain region of the second FET, and has a second width in a region between the end wall of the functional gate structure of the first FET and the end wall of the functional gate structure of the second FET, wherein the first width is greater than the second width. 4 . The semiconductor structure according to claim 1 , wherein the gate cutting region comprises a double-layer dielectric filling structure, the double-layer dielectric filling structure comprising an inner dielectric material layer and an outer dielectric material layer.

5. The semiconductor structure of claim 4, wherein the outer dielectric material layer is present around the end walls of the functional gate structures of both the first FET and the second FET.

6. The semiconductor structure according to claim 4 further includes a front side source / drain contact structure contacting each of the first source / drain region of the second FET and the second source / drain region of the second FET, wherein the external dielectric material layer exists between the front side source / drain contact structure and the VBPR contact structure.

7. The semiconductor structure of claim 1, further comprising a front-side back-end-of-line (BEOL) structure contacting at least the VBPR contact structure.

8. The semiconductor structure of claim 7, further comprising a carrier wafer located on the front side BEOL structure.

9. The semiconductor structure of claim 1, wherein the backside power rail is located in a backside inter-layer dielectric (ILD) material layer.

10. The semiconductor structure of claim 9, further comprising a backside power distribution network contacting both the backside ILD material layer and the backside power rails.

11. The semiconductor structure of claim 1, further comprising a shallow trench isolation structure laterally surrounding a portion of the VBPR contact structure.

12. The semiconductor structure of claim 11, wherein the shallow trench isolation structure contacts a surface of the backside power rail.

13. The semiconductor structure of claim 1, wherein the VBPR contact structure has a surface opposite a surface contacting the backside power rail that is coplanar with surfaces of both the first FET and the second FET.

14. The semiconductor structure of claim 1, wherein each of the first FET and the second FET comprises a nanosheet-containing FET.

15. The semiconductor structure according to claim 14, wherein: The nanosheet-containing FET includes the functional gate structures of the first FET and the second FET surrounding a plurality of vertically stacked nanosheets of semiconductor channel material.

16. The semiconductor structure of claim 15, further comprising a gate spacer positioned laterally adjacent to the functional gate structures of the first FET and the second FET, wherein portions of sidewalls of the functional gate structures of the first FET and the second FET proximate to the gate cut region are devoid of the gate spacer.

17. The semiconductor structure according to claim 16, wherein: The plurality of vertically stacked semiconductor channel material nanosheets are spaced apart from the semiconductor material layer.

18. The semiconductor structure of claim 1, wherein the VBPR contact structure is completely separated from the second FET present in the second active device region by an outer dielectric material layer of a double-layer dielectric filling structure present in the gate cut region.

19. The semiconductor structure of claim 1, wherein a sidewall of the functional gate structure of the first FET is aligned with a sidewall of the functional gate structure of the second FET.

20. The semiconductor structure of claim 1, wherein sidewalls of the first source / drain region of the first FET are spaced apart from the VBPR contact structure by an outer dielectric material layer of a double-layer dielectric filling structure present in the gate cut region.

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