Semiconductor optical element array

Abstract

In the present disclosure, there is provided a semiconductor optical element array comprising: a semiconductor substrate; a mask layer disposed on the main surface of the semiconductor substrate and having an opening; a nanorod which extends in the thickness direction from the semiconductor substrate through the opening and is a columnar crystal of a group III nitride semiconductor; a light-emitting layer disposed at the tip of the nanopillar; and a cover semiconductor layer that covers the light-emitting layer and contains a semiconductor. The semiconductor optical element array has a pixel including a plurality of the nanopillars, and in the pixel, the size of the nanopillars increases in stages or continuously, or decreases in stages or continuously, from the center toward the outer periphery.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor optical element array. Background Art

[0002] In recent years, group III nitride semiconductors such as gallium nitride (GaN) have attracted attention as semiconductor materials useful for light-emitting diodes, laser diodes, and other light-emitting devices. Light-emitting devices are produced by forming a stacked structure of group III nitride semiconductors on a substrate using crystal growth techniques such as metal organic chemical vapor deposition (MOCVD) and molecular beam epitaxy (MBE).

[0003] For example, Patent Document 1 discloses a semiconductor optical element array including fine columnar crystals containing a group III nitride semiconductor grown from a semiconductor substrate through openings arranged in a mask pattern. One of the purposes of this technology is to control the position and shape of fine columnar crystals formed on a substrate with high precision.

[0004] [Prior art literature]

[0005] [Patent Document]

[0006] Patent Document 1: International Publication No. 2010 / 023921 Summary of the invention

[0007] [Problems to be solved by the invention]

[0008] Semiconductor optical element arrays are used, for example, in light-emitting elements. In order to improve the performance of light-emitting elements, it is desirable to improve the optical properties of semiconductor optical element arrays. The present disclosure is made in view of the above-mentioned actual situation, and its main purpose is to provide a semiconductor optical element array with good optical properties.

[0009] [Technical solutions for solving technical problems]

[0010] In the present disclosure, a semiconductor optical element array is provided, which includes: a semiconductor substrate; a mask layer, which is arranged on the main surface of the above-mentioned semiconductor substrate and has an opening portion; a nanocolumn, which extends from the above-mentioned semiconductor substrate through the above-mentioned opening portion along the thickness direction and is a columnar crystal of a group III nitride semiconductor; a light-emitting layer, which is arranged at the front end of the above-mentioned nanocolumn; and a covering semiconductor layer, which covers the above-mentioned light-emitting layer and contains a semiconductor; and the above-mentioned semiconductor optical element array has pixels including a plurality of the above-mentioned nanocolumns, and in the above-mentioned pixels, the size of the above-mentioned nanocolumns increases in a step-by-step or continuous manner, or decreases in a step-by-step or continuous manner from the center to the periphery.

[0011] Effects of the Invention

[0012] The semiconductor optical element array of the present disclosure exhibits an effect of having good optical characteristics. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 This is a schematic cross-sectional view illustrating a semiconductor optical element array according to the present disclosure.

[0014] Figure 2 1 is a schematic top view illustrating a mask layer and nanorods according to the present disclosure.

[0015] Figure 3 2 is a schematic top view illustrating a pixel of the present disclosure.

[0016] Figure 4 2 is a schematic top view illustrating a pixel of the present disclosure.

[0017] Figure 5 It is an explanatory diagram for explaining a pixel of the present disclosure.

[0018] Figure 6 It is an explanatory diagram for explaining a pixel of the present disclosure.

[0019] Figure 7 2 is a schematic cross-sectional view illustrating a nanocolumn of the present disclosure.

[0020] Figure 8 2 is a schematic top view illustrating a pixel of the present disclosure.

[0021] Fig. 9 This is a schematic perspective view illustrating a semiconductor optical element array according to the present disclosure.

[0022] Fig.10 This is a schematic perspective view illustrating a method for manufacturing a semiconductor optical element array according to the present disclosure.

[0023] Fig.11 This is an explanatory diagram for explaining pixels used in Comparative Example 1 and Examples 1 and 2.

[0024] Fig.12 These are the light emission spectra of the pixels obtained in Comparative Example 1 and Examples 1 and 2.

[0025] Fig.13 This is an explanatory diagram for explaining pixels used in Comparative Example 2 and Examples 3 and 4.

[0026] Fig.14 These are the light emission spectra of the pixels obtained in Comparative Example 2 and Examples 3 and 4. DETAILED DESCRIPTION

[0027] The semiconductor optical element array of the present disclosure is described in detail below. The sizes and shapes of the various parts are appropriately exaggerated in the following figures for ease of understanding. Furthermore, in the various figures, shadows or symbols are sometimes omitted for convenience. In addition, in the present disclosure, the so-called "other components are arranged on the surface (main surface) of a component" includes both the case where other components are arranged in contact with the surface (main surface) of a component, and the case where other components are arranged above the surface (main surface) of a component through other components.

[0028] Figure 1 This is a schematic cross-sectional view illustrating a semiconductor optical element array according to the present disclosure. Figure 1 The semiconductor optical element array 10 shown includes: a semiconductor substrate 1, a mask layer 2, nanorods 3, a light emitting layer 4, and a cover semiconductor layer 5. The semiconductor substrate 1 includes a base substrate 1a and a semiconductor layer 1b.

[0029] The mask layer 2 is disposed on the main surface m of the (semiconductor layer 1b) of the semiconductor substrate 1 and has an opening 2x. The nanocolumn 3 extends from the (semiconductor layer 1b) of the semiconductor substrate 1 through the opening 2x of the mask layer 2 in the thickness direction DT and is a columnar crystal of a group III nitride semiconductor. The light emitting layer 4 is disposed at the front end of the nanocolumn 3. The covering semiconductor layer 5 covers at least a portion of the light emitting layer 4 and contains a semiconductor.

[0030] Figure 2 is a schematic top view illustrating the mask layer and nanorods of the present disclosure. Figure 2 As shown in (a), the mask layer 2 has a patterned opening 2x. Through the opening 2x, a crystal of a group III nitride semiconductor is epitaxially grown. Figure 1 and Figure 2 The nanorod 3 shown in (b).

[0031] The semiconductor optical element array disclosed in the present invention has pixels including a plurality of nanocolumns. Specifically, the plurality of nanocolumns are arranged in a pattern to form a pixel. Each nanocolumn generally has the above-mentioned light-emitting layer and the covering semiconductor layer. Figure 3 and Figure 4 , respectively, are schematic top views illustrating pixels of the present disclosure. Figure 3 and Figure 4 As shown, the pixel P includes a plurality of nanorods 3. Figure 3 In the pixel P shown, the size of the nanorods 3 increases continuously from the center C to the periphery X. Figure 4 In the pixel P shown, the size of the nanorods 3 decreases continuously from the center C toward the periphery X.

[0032] According to the present disclosure, in a pixel including a plurality of nanocolumns, since the size of the nanocolumns increases in a stepwise or continuous manner, or decreases in a stepwise or continuous manner from the center to the periphery, a semiconductor optical element array having good optical characteristics is formed. Here, as described in Patent Document 1, the luminous characteristics of the light emitted from the light-emitting layer vary according to the size of the nanocolumns. Specifically, with respect to the peak wavelength of the light emitted from the light-emitting layer, the larger the size of the nanocolumns, the more it shifts toward the long wavelength side, and the smaller the size of the nanocolumns, the more it shifts toward the short wavelength side.

[0033] Therefore, it is assumed that a pixel including multiple nanocolumns of uneven sizes has poorer monochromaticity than a pixel including multiple nanocolumns of uniform size. However, when the size of the nanocolumns is changed from the center of the pixel to the periphery of the pixel, no reduction in monochromaticity is confirmed at least near the center of the pixel. Even more surprisingly, when the size of the nanocolumns is changed from the center of the pixel to the periphery of the pixel, an increase in luminous intensity is confirmed at least near the center of the pixel. Although the reason is not completely clear, it is speculated that the reason is that the nanocolumns arranged near the periphery of the pixel improve the light extraction efficiency near the center of the pixel by performing functions such as lenses or reflectors.

[0034] 1. Pixels

[0035] The pixel of the present disclosure includes a plurality of nanocolumns. Details of the nanocolumns will be described in "2. Nanocolumns" below. In addition, in the present disclosure, the size of the nanocolumns increases or decreases in a step-by-step or continuous manner from the center of the pixel to the periphery of the pixel.

[0036] In the present disclosure, the center of a pixel refers to the centroid of the top view of the pixel along the thickness direction. On the other hand, the periphery of a pixel refers to the periphery of the top view of the pixel along the thickness direction. In addition, the "size of a nanocolumn" refers to the columnar portion of the nanocolumn (described later). Figure 7 The size of the columnar portion 3a) is the length of a straight line that passes through the centroid (center) of the top view shape of the columnar portion along the thickness direction and has the longest distance between the intersection points of the straight lines that intersect the columnar portion at two points.

[0037] The size of the nanocolumn at the center of the pixel is, for example, greater than 10 nm and less than 1000 nm. The so-called "nanocolumn at the center of the pixel" means that when the pixel is viewed from above along the thickness direction, if there is a nanocolumn in the center of the pixel, it is the nanocolumn, and if there is no nanocolumn in the center of the pixel, it is the nanocolumn closest to the center of the pixel. The size of the nanocolumn can be, for example, less than 700 nm, less than 650 nm, or less than 600 nm. By setting the size of the nanocolumn to less than 700 nm, it is easy to suppress the occurrence of threading dislocations.

[0038] In the present disclosure, the size of the nanorods may increase in stages or continuously from the center of the pixel to the periphery of the pixel. Figure 5 To illustrate this situation. Figure 5 In the pixel P shown in (a), the size of the nanocolumns 3 increases continuously from the center C to the periphery X. Figure 5 In the pixel P shown in (a), the size of the nanocolumn 3 changes in a concentric circle from the center C to the periphery X. Figure 5 As shown in (b), the size of the nanocolumn may also increase linearly from the center C to the periphery X. On the other hand, although not shown in the figure, the size of the nanocolumn may increase curvilinearly (eg, nth-order function) from the center C to the periphery X.

[0039] Figure 5 (c) shows the nanocolumn 3 near the center of the pixel. Figure 5 (d) represents a nanocolumn 3 near the periphery of the pixel. The size of the nanocolumn at the center of the pixel is set to S1, and the size of the nanocolumn at the periphery of the pixel is set to S2. The "nanopillars at the center of the pixel" are as described above. On the other hand, the so-called "nanopillars at the periphery of the pixel" refers to the nanocolumns constituting the periphery of the pixel when the pixel is viewed from above along the thickness direction.

[0040] S1 is, for example, greater than 10 nm, or greater than 20 nm, or greater than 30 nm. On the other hand, S1 is, for example, less than 300 nm, or less than 200 nm, or less than 100 nm. In addition, S2 is not particularly limited, as long as it is greater than S1, and can be, for example, greater than 20 nm, or greater than 50 nm, or greater than 100 nm. On the other hand, S2 is, for example, less than 1000 nm, or less than 500 nm, or less than 300 nm. In addition, the ratio of the above-mentioned S2 to S1 (S2 / S1) is, for example, greater than 1.5 and less than 6.0, or greater than 2.0 and less than 4.0.

[0041] In addition, in the present disclosure, the size of the nanocolumn may increase in stages from the center of the pixel to the periphery of the pixel. In this case, the size of the nanocolumn may increase in 2 or more stages, 5 or more stages, or 10 or more stages from the center of the pixel to the periphery of the pixel.

[0042] On the other hand, in the present disclosure, the size of the nanorods may decrease in stages or continuously from the center of the pixel to the periphery of the pixel. Figure 6 To illustrate this situation. Figure 6 In the pixel P shown in (a), the size of the nanocolumn 3 decreases continuously from the center C to the periphery X. Figure 6In the pixel P shown in (a), the size of the nanocolumn 3 changes in a concentric circle from the center C to the periphery X. Figure 6 As shown in (b), the size of the nanocolumn may decrease linearly from the center C to the periphery X. On the other hand, although not shown in the figure, the size of the nanocolumn may decrease curvilinearly (for example, in the form of an nth-order function) from the center C to the periphery X.

[0043] Figure 6 (c) shows the nanocolumn 3 near the center of the pixel. Figure 6 (d) represents a nanocolumn 3 near the periphery of the pixel. The size of the nanocolumn at the center of the pixel is set to S3, and the size of the nanocolumn at the periphery of the pixel is set to S4. The “nanopillar at the center of the pixel” and the “nanopillar at the periphery of the pixel” are as described above.

[0044] S3 is, for example, more than 100nm, or more than 150nm, or more than 200nm. On the other hand, S3 is, for example, less than 1000nm, or less than 500nm, or less than 400nm. In addition, S4 is not particularly limited, as long as it is smaller than S3, and can be, for example, more than 10nm, or more than 100nm, or more than 150nm. On the other hand, S4 is, for example, less than 300nm, or less than 250nm. In addition, the ratio of the above-mentioned S4 to S3 (S4 / S3) is, for example, more than 0.4 and less than 0.8, or more than 0.45 and less than 0.6.

[0045] In addition, in the present disclosure, the size of the nanocolumn may decrease in stages from the center of the pixel to the periphery of the pixel. In this case, the size of the nanocolumn may decrease in 2 or more stages, 5 or more stages, or 10 or more stages from the center of the pixel to the periphery of the pixel.

[0046] In the direction from the center of the pixel to the periphery of the pixel, the difference in size between adjacent nanocolumns is, for example, less than 5 nm, less than 3 nm, or less than 1 nm. When the distance from the center of the pixel to the periphery of the pixel is set to L, in the area from the center of the pixel to 1 / 2L, the difference in size between adjacent nanocolumns can be within the above range. Similarly, in the area from the center of the pixel to 3 / 4L, the difference in size between adjacent nanocolumns can be within the above range. In addition, when the size of the nanocolumns changes continuously from the center of the pixel to the periphery of the pixel, the difference in size between adjacent nanocolumns is usually greater than 0.

[0047] The arrangement of the nanorods is not particularly limited, and they may be arranged in a triangular lattice or a square lattice, for example. Figure 2In the embodiment, the openings 2x of the mask layer 2 are arranged in a triangular lattice shape, and the nanorods 3 grown from the openings 2x are also arranged in a triangular lattice shape. Figure 5 As shown in (c), the distance between the centers of adjacent nanopillars is called a pitch. The pitch is, for example, greater than 200 nm, or greater than 300 nm. On the other hand, the pitch is, for example, less than 600 nm, or less than 500 nm. In addition, adjacent nanopillars are usually arranged in a non-contact manner.

[0048] The gap between adjacent nanocolumns is preferably greater than 1 nm, for example. The pitch of the nanocolumns in a pixel may be the same or different. The same pitch means that the difference between the maximum and minimum values ​​of the pitch of the nanocolumns in a pixel is less than 5 nm. On the other hand, different pitch means that the difference between the maximum and minimum values ​​of the pitch of the nanocolumns in a pixel is greater than 5 nm.

[0049] The top view shape of the pixel disclosed in the present invention is not particularly limited, and polygons such as triangular shapes, quadrilateral shapes (for example, square shapes, rectangular shapes, diamond shapes), and hexagonal shapes may be cited. The size of the pixel is, for example, greater than 10 μm, or greater than 50 μm. On the other hand, the size of the pixel is, for example, less than 500 μm, or less than 100 μm. In the present disclosure, the "size of the pixel" refers to the length of the straight line that is the longest distance between the centroid (center) of the top view shape of the pixel when viewed from above along the thickness direction, and the intersection of the straight lines that intersect the pixel at two points.

[0050] 2. Nanopillars

[0051] The nanocolumn disclosed in the present invention extends from the semiconductor substrate through the opening of the mask layer in the thickness direction and is a columnar crystal of a group III nitride semiconductor. The nanocolumn may be composed of a single crystal of a group III nitride semiconductor. Preferably, the nanocolumn has fewer crystal defects.

[0052] Group III nitride semiconductors contain group III elements and N elements. As a typical example of group III nitride semiconductors, gallium nitride (GaN) can be cited. In addition, as another example of group III nitride semiconductors, materials represented by the general formula: AlxGayIn1-x-yN (0≤x≤1, 0≤y≤1, 0≤x+y≤1) can be cited. x can be greater than 0. x can be less than 1. y can be greater than 0. y can be less than 1. x+y can be greater than 0 and less than 1. Regarding the group III nitride semiconductor represented by the above general formula, it is preferred that the band gap at room temperature is greater than 0.63 eV and less than 6.2 eV. In addition, as another example of group III nitride semiconductors, boron nitride can be cited. In addition, from the viewpoint of manufacturing stability, group III nitride semiconductors are preferably materials with a hexagonal crystal structure.

[0053] The nanocolumn may have a columnar portion and a small face structure portion located at the front end side of the columnar portion (the opposite side of the semiconductor substrate). The small face structure portion refers to a polyhedral structure with a small facet surface located obliquely relative to a direction perpendicular to the thickness direction as a side surface. The shape of the columnar portion is not particularly limited, and examples thereof include a cylindrical shape, a quadrangular prism shape, and a hexagonal prism shape.

[0054] For example, when a group III nitride semiconductor having a wurtzite crystal structure is grown along the c-plane (=(0001) plane, polar plane) to form a nanocolumn, the top view of the nanocolumn is as follows: Figure 2 As shown in (b), it becomes a hexagonal shape. Figure 7 (a) and (b) are schematic cross-sectional views showing the cross section when the nanocolumn is cut along the central axis. Figure 7 Each of the nanocolumns 3 shown in (a) and (b) has a columnar portion 3a and a facet structure portion 3b located on the front end side (opposite side to the semiconductor substrate) of the columnar portion 3a.

[0055] Figure 7 The small face structure part 3b shown in (a) has a small face surface 31 (a semipolar surface of a wurtzite crystal structure) in the shape of a hexagonal pyramid. Examples of the semipolar surface include the (10-1-1) surface, the (10-1-3) surface, the (11-22) surface, the (11-24) surface, and the (10-12) surface. On the other hand, Figure 7 The small plane structure portion 3b shown in (b) has a small plane surface 31 (a semipolar surface of a wurtzite crystal structure) and further has a flat surface 32 (a polar surface of a wurtzite crystal structure) parallel to a direction perpendicular to the thickness direction. Depending on the growth conditions of the crystal, for example, Figure 7 (a) or Figure 7 The small planar structure portion shown in (b).

[0056] When the size of the nanorods is small, it is easy to form Figure 7 The small planar structure portion having a hexagonal pyramid shape shown in (a) is easy to form as shown in FIG. Figure 7 The small plane structure shown in (b) of FIG. Depending on the growth conditions of the crystal, when the size of the nanocolumn is set to about 300nm or more, the following is likely to occur: Figure 7 The flat surface (polar surface) shown in (b) of FIG. 1 shows a flat surface (polar surface). In addition, when the size of the nanorod exceeds about 300 nm and becomes larger, the area of ​​the flat surface (polar surface) tends to increase.

[0057] The height of the nanocolumn is not particularly limited, and is, for example, 200 nm or more, or 500 nm or more. On the other hand, the height of the nanocolumn is, for example, 5 μm or less. The height of the nanocolumn refers to the distance from the surface of the mask layer 2 on the opposite side to the semiconductor substrate to the front end of the nanocolumn (the distance in the thickness direction).

[0058] 3. Luminous layer

[0059] The light-emitting layer of the present disclosure is disposed at the front end of the nanocolumn. That is, the light-emitting layer is disposed on the surface opposite to the semiconductor substrate. The light-emitting layer is preferably disposed in a manner covering the small planar structure of the nanocolumn.

[0060] The light-emitting layer preferably has a multiple quantum well (MQW) structure or a single quantum well (SQW) structure. A quantum well structure refers to a structure comprising a quantum well layer and a barrier layer sandwiching the quantum well layer. The band gap of the barrier layer is usually larger than the band gap of the quantum well layer. Examples of the light-emitting layer include InGaN, GaN, AlGaN, AlInGaN, InGaAsN, and InN. More specifically, examples of the light-emitting layer include InGaN / GaN (barrier layer: InGaN, well layer: GaN), InxGa1-xN / InyGa1-yN (0≤x≤1, 0≤y≤1), GaN / AlGaN (barrier layer: AlGaN, well layer: GaN), and AlxGa1-xN / AlyGa1-yN (0≤x≤1, 0≤y≤1).

[0061] The peak wavelength of light emitted from the light-emitting layer depends on the size of the nanocolumn before the light-emitting layer is formed. Specifically, the peak wavelength of light emitted from the light-emitting layer is shifted toward the long wavelength side as the size of the nanocolumn is larger, and is shifted toward the short wavelength side as the size of the nanocolumn is smaller. That is, the peak wavelength of light emitted from the light-emitting layer can be controlled based on the size of the nanocolumn. The size of the nanocolumn can be controlled based on the size of the opening of the mask layer.

[0062] The peak wavelength of light emitted from the light-emitting layer depends on the surface area of ​​the small facet structure of the nanocolumn. Specifically, regarding the peak wavelength of light emitted from the light-emitting layer, the larger the surface area of ​​the small facet structure, the more it shifts toward the long wavelength side, and the smaller the surface area of ​​the small facet structure, the more it shifts toward the short wavelength side. That is, the peak wavelength of light emitted from the light-emitting layer can be controlled based on the surface area of ​​the small facet structure of the nanocolumn.

[0063] 4. Covering semiconductor layer

[0064] The covering semiconductor layer disclosed in the present invention covers the light-emitting layer and is a layer containing a semiconductor. The covering semiconductor layer preferably contains a crystal of a semiconductor, and more preferably contains a crystal of a group III nitride semiconductor. The covering semiconductor layer can be composed of a single crystal of a group III nitride semiconductor. It is preferred that the covering semiconductor layer has fewer crystal defects. Regarding the group III nitride semiconductor, since the content is the same as that described in the above-mentioned "2. Nanopillars", the description here is omitted.

[0065] The covering semiconductor layer 5 only needs to cover at least a portion of the light emitting layer 4. The covering semiconductor layer 5 preferably covers the light emitting layer 4 in a manner that includes the entire circumference of the light emitting layer 4 when viewed from above along the thickness direction. This is because better optical properties can be obtained. Figure 1 As shown, the covering semiconductor layer 5 can completely cover the light emitting layer 4. That is, the covering semiconductor layer 5 can cover the light emitting layer 4 in a manner that the light emitting layer 4 has no exposed portion to the external space. By suppressing the formation of non-luminescent recombination energy levels caused by the exposed portion, a higher internal quantum efficiency is achieved.

[0066] In addition, the conductivity type of the nanopillar and the conductivity type of the covering semiconductor layer generally have an inverse relationship. When the conductivity type of the nanopillar is n-type, the conductivity type of the covering semiconductor layer is generally p-type. In this case, the light-emitting layer emits light because the electrons supplied from the nanopillars are combined with the holes supplied from the covering semiconductor layer. On the other hand, when the conductivity type of the nanopillar is p-type, the conductivity type of the covering semiconductor layer is generally n-type.

[0067] 5.Semiconductor substrate

[0068] The semiconductor substrate of the present disclosure supports the nanocolumns. In addition, the semiconductor substrate includes, for example, a base substrate and a semiconductor layer. Examples of the base substrate include a sapphire substrate, a silicon substrate, and a SiC substrate.

[0069] The semiconductor layer preferably contains a group III nitride semiconductor as a semiconductor. The semiconductor layer may be composed of a single crystal of a group III nitride semiconductor. It is preferred that the semiconductor layer has fewer crystal defects. The group III nitride semiconductor is the same as described in the above "2. Nanopillars". The composition of the group III nitride semiconductor in the semiconductor layer and the group III nitride semiconductor in the nanopillar may be the same.

[0070] like Figure 1 As shown, the semiconductor layer 1b may have a recess 1x at a position overlapping at least the opening 2x of the mask layer 2 in a plan view along the thickness direction DT. The depth of the recess 1x is not particularly limited, and is, for example, 1 nm to 250 nm.

[0071] A buffer layer may be disposed between the base substrate and the semiconductor layer. By providing the buffer layer, the crystal quality of the semiconductor layer (e.g., the flatness of the layer surface) is improved. As the buffer layer, for example, group III nitride semiconductors such as gallium nitride and aluminum nitride may be cited. In addition, the semiconductor substrate may not have a base substrate. That is, the semiconductor substrate may be an independent semiconductor layer (e.g., a GaN substrate).

[0072] 6. Mask layer

[0073] The mask layer disclosed in the present invention has an opening. As the top view shape of the opening, for example, a square shape, a circular shape, and a polygonal shape can be cited. The top view shape of the opening is preferably axisymmetric. By adjusting the pattern of the opening, the density of the nanocolumns can be controlled. Similarly, by adjusting the size of the opening, the size of the nanocolumns can be controlled. The pattern and size of the opening are adjusted in a manner to obtain the above-mentioned nanocolumns.

[0074] The mask layer is preferably a metal mask layer containing a metal. Examples of metal elements contained in the metal mask layer include titanium (Ti), tantalum (Ta), iron (Fe), nickel (Ni), platinum (Pt), gold (Au), cobalt (Co), tungsten (W) and molybdenum (Mo). The metal mask layer may contain only one metal element or more than two metal elements. The metal mask layer preferably contains at least Ti. The metal mask layer may be a layer having an oxide on the surface or a metal oxide layer. The thickness of the mask layer is not particularly limited, and may be, for example, greater than 2 nm and less than 100 nm.

[0075] 7. Semiconductor optical element array

[0076] In the semiconductor optical element array disclosed in the present invention, all pixels may be light-emitting areas, or only a part of the pixels may be light-emitting areas. Figure 8 A portion of the pixel P shown is a light emitting area α.

[0077] The light-emitting region α preferably includes the center C of the pixel P. In addition, as the top view shape of the light-emitting region, for example, a square shape, a circular shape, and a polygonal shape can be cited. The top view shape of the light-emitting region can be axisymmetric. In addition, the top view shape of the light-emitting region can be similar to the pixel or not.

[0078] The size of the light-emitting region is, for example, 5 μm or more, and may be, for example, 50 μm or more. On the other hand, the size of the light-emitting region is, for example, 300 μm or less, and may be, for example, 100 μm or less. In the present disclosure, the “size of the light-emitting region” refers to the length of the straight line that is the longest distance between the intersection points of the straight lines that intersect the light-emitting region at two points and pass through the centroid (center) of the top view shape of the light-emitting region along the thickness direction.

[0079] When a part of the pixel is a light-emitting region, the area ratio of the light-emitting region to the pixel is, for example, 5% or more, or 10% or more. On the other hand, the area ratio is, for example, 80% or less, or 60% or less. In addition, as a method for forming the light-emitting region, for example, a method of adjusting the shape of an electrode electrically connected to the covering semiconductor layer can be cited.

[0080] The luminous spectrum of the luminous region may have a peak wavelength at a position above 430nm and below 500nm, for example. In this case, blue luminescence is obtained. In addition, the so-called peak wavelength refers to the wavelength at which the highest luminous intensity is obtained in the luminous spectrum. In addition, the luminous spectrum of the luminous region may have a peak wavelength at a position above 500nm and below 580nm, for example. In this case, green luminescence is obtained. In addition, the luminous spectrum of the luminous region may have a peak wavelength at a position above 580nm and below 780nm, for example. In this case, red luminescence is obtained.

[0081] The number of peaks observed in the luminescence spectrum of the luminescent region in the visible light region of 380 nm to 780 nm is preferably 2 or less, and more preferably 1. In addition, when the number of peaks observed in the visible light region of 380 nm to 780 nm is 2 or more, the highest luminescence intensity is preferably 2 times or more, and more preferably 4 times or more, the second highest luminescence intensity.

[0082] In addition, a light-emitting region obtained by changing the size of all nanocolumns in the light-emitting region to the size of the nanocolumn at the center of the pixel is defined as a comparative light-emitting region. In this case, the light-emitting intensity of the peak wavelength of the light-emitting region is preferably greater than the light-emitting intensity of the peak wavelength of the comparative light-emitting region.

[0083] The semiconductor optical element array disclosed in the present invention preferably has a plurality of pixels. Fig. 9 As shown, the semiconductor optical element array preferably has a plurality of pixels (P1, P2, P3). The light-emitting characteristics of the nanocolumns disclosed herein vary according to their size. Therefore, for example, by adjusting the size of the nanocolumns, the pixels P1, P2, and P3 can be set to emit light of wavelengths of the three primary colors of R (red), G (green), and B (blue), respectively.

[0084] The application of the semiconductor optical element array of the present disclosure is not particularly limited. Examples of applications of the semiconductor optical element array include light emitting elements such as light emitting diodes and laser diodes.

[0085] The method for manufacturing the semiconductor optical element array disclosed in the present invention is not particularly limited. Fig.10 1 is a schematic perspective view illustrating a method for manufacturing a semiconductor optical element array according to the present disclosure. Fig.10In the method for manufacturing a semiconductor optical element array shown in the figure, first, a base substrate 1a ( Fig.10 Next, a buffer layer (not shown) containing a group III nitride semiconductor is formed on the base substrate 1a by MOCVD or MBE at low temperature, and crystals of the group III nitride semiconductor are grown on the buffer layer at high temperature to form a semiconductor layer 1b ( Fig.10 (b)). Thus, a semiconductor substrate 1 including a base substrate 1a and a semiconductor layer 1b is obtained.

[0086] Thereafter, a mask layer 2 containing titanium (Ti) is formed on the main surface of the semiconductor layer 1b by vacuum evaporation. Fig.10 Next, a resist layer 6 is formed on the mask layer 2, and electron beam drawing and development are performed to form an opening 6x ( Fig.10 (d)). At this time, the drawing pattern of the opening 6x is set in such a way as to obtain the above-mentioned pixel. Next, the mask layer 2 exposed from the opening 6x is removed by etching to form the opening 2x ( Fig.10 (e)). At this time, if not only the mask layer 2 but also the semiconductor layer 1b is etched, the following is formed: Figure 1 Recess 1x shown.

[0087] Then, a crystal of a group III nitride semiconductor is grown from the semiconductor layer 1b through the opening 2x by MOCVD or MBE. Fig.10 (f)). At this time, the light-emitting layer 4 and the covering semiconductor layer 5 can be continuously formed. For example, when the MBE method is used to form nanocolumns, a raw material gas containing active nitrogen generated by high-frequency plasma excitation and a group III metal is introduced onto the semiconductor layer to grow crystals of the group III nitride semiconductor. The crystal growth temperature is, for example, above 350°C and below 1200°C. For example, in the case of growing GaN crystals, the crystal growth temperature is preferably above 400°C and below 1000°C. In addition, when the crystals of the group III nitride semiconductor grow, there is a situation where they grow in the thickness direction and also in a direction orthogonal to the thickness direction (in-plane direction). In this case, as Figure 1 As shown in FIG. 1 , the size of the nanorod 3 is usually larger than the size of the opening 2x and the size of the recess 1x. Fig.10 As shown in (f), a semiconductor optical element array 10 is obtained. Fig.10 As shown in (g) , the electrodes 11 may be disposed on the cover semiconductor layer 5 and the mask layer 2 , respectively.

[0088] The present disclosure is not limited to the above-mentioned embodiments. The above-mentioned embodiments are merely examples, and any of the above-mentioned embodiments having substantially the same structure as the technical concept described in the scope of the present disclosure and having the same effects is included in the technical scope of the present disclosure.

[0089] [Example]

[0090] [Comparative Example 1]

[0091] GaN is grown on the (0001) surface of the sapphire substrate (base substrate) by MOCVD to form a GaN layer (semiconductor layer, thickness: about 3.5μm). Then, a titanium thin film (mask layer, thickness: about 5nm) is formed on the GaN layer by vacuum evaporation. Next, a resist layer is formed on the titanium thin film, and electron beam drawing and development are performed to form a resist pattern with an opening. Next, the mask layer exposed from the opening of the resist pattern is removed by etching, and a patterned opening is formed in the mask layer. Next, the resist pattern is peeled off.

[0092] Thereafter, GaN columnar crystals were grown from the semiconductor substrate through the openings of the mask layer by RF MBE at a temperature of 900° C., thereby forming nanocolumns (height: 2.5 μm). Fig.11 (a) and the pixels shown below.

[0093] Pixel top view shape: Hexagonal

[0094] Pixel size: 150μm

[0095] · The pitch between the centers of adjacent nanopillars: 350nm

[0096] The size of the nanopillar at the center of the pixel: 60nm

[0097] Size of nanopillars at the periphery of the pixel: 60nm

[0098] Then, a light-emitting layer having a multiple quantum well structure including an InGaN film (thickness: 1 nm) was formed at the tip of the nanorod. Then, GaN crystals were grown on the light-emitting layer to form a covering semiconductor layer (thickness: 10 nm). Thus, a semiconductor optical element array was obtained.

[0099] Furthermore, the same operation as above was performed, and at the stage of forming the nanocolumns, the nanocolumns were observed using a scanning electron microscope (SEM). Fig.11 (b) and Fig.11 (c) shows the result.

[0100] like Fig.11 (b) and Fig.11As shown in (c), the size of the nanocolumns at the center of the pixel is the same as the size of the nanocolumns at the periphery of the pixel.

[0101] [Example 1]

[0102] In addition to forming Fig.11 A semiconductor optical element array was obtained in the same manner as in Comparative Example 1 except for (d) and the pixels described below.

[0103] Pixel top view shape: Hexagonal

[0104] Pixel size (maximum length between opposite corners): 150 μm

[0105] · The pitch between the centers of adjacent nanopillars: 350nm

[0106] The size of the nanopillar at the center of the pixel: 60nm

[0107] Size of nanopillars at the periphery of the pixel: 100 nm

[0108] Fig.11 (e) and Fig.11 (f) shows the results of SEM observation of the nanorods. Fig.11 (e) and Fig.11 As shown in (f), in the pixel, the size of the nanocolumns increases continuously from the center to the periphery.

[0109] [Example 2]

[0110] In addition to forming Fig.11 A semiconductor optical element array was obtained in the same manner as in Comparative Example 1 except for the pixels (g) and those described below.

[0111] Pixel top view shape: Hexagonal

[0112] Pixel size (maximum length between opposite corners): 150 μm

[0113] · The pitch between the centers of adjacent nanopillars: 350nm

[0114] The size of the nanopillar at the center of the pixel: 60nm

[0115] Size of nanopillars at the periphery of the pixel: 350nm

[0116] Fig.11 (h) and Fig.11 (i) shows the results of SEM observation of the nanorods. Fig.11 (h) and Fig.11 As shown in (i), in a pixel, the size of the nanocolumns increases continuously from the center to the periphery.

[0117] [evaluate]

[0118] The same operation as in Comparative Example 1 and Examples 1 and 2 was performed. At the stage of forming the light-emitting layer, the light-emitting layer was irradiated with laser light and the light-emitting intensity was measured. Fig.11 (a) Fig.11 (d) Fig.11 The black circle in (g) is a region having a diameter of 30 μm including the center of the pixel. Fig.12 Indicates the result. Fig.12 As shown, in Examples 1 and 2, higher emission intensities were obtained compared to Comparative Example 1. More specifically, it was confirmed that by increasing the size of the nanocolumns around the measurement region, higher emission intensity can be obtained without increasing the size of the nanocolumns in the measurement region.

[0119] In Example 1, the size of the nanocolumn at the center of the measurement area is 50 nm, and the size of the nanocolumn at the periphery of the measurement area is 60 nm. Comparing the area occupied by the nanocolumns in the measurement area, Example 1 is 1.21 times that of Comparative Example 1. In Example 2, the size of the nanocolumn at the center of the measurement area is 50 nm, and the size of the nanocolumn at the periphery of the measurement area is 100 nm. Comparing the area occupied by the nanocolumns in Example 2 is 2.25 times that of Comparative Example 1. These increase rates are Fig.12 The increase in the emission intensity shown is smaller, so in Examples 1 and 2, it was confirmed that the emission intensity was improved due to factors other than the increase in area.

[0120] In addition, in determining Fig.12 The half-width of the peaks shown is 82 nm for Comparative Example 1, 47.6 nm for Example 1, and 55.4 nm for Example 2. In Examples 1 and 2, since the size of the nanocolumns was changed within the measurement region, an increase in the half-width (decrease in monochromaticity) was expected, but a decrease in the half-width (improvement in monochromaticity) was unexpectedly confirmed.

[0121] [Comparative Example 2]

[0122] In addition to forming Fig.13 A semiconductor optical element array was obtained in the same manner as in Comparative Example 1 except for the pixels (a) and those described below.

[0123] Pixel top view shape: Hexagonal

[0124] Pixel size (maximum length between opposite corners): 150 μm

[0125] · The pitch between the centers of adjacent nanopillars: 450nm

[0126] Size of the nanopillar at the center of the pixel: 200 nm

[0127] Size of nanopillars at the periphery of the pixel: 200 nm

[0128] Fig.13 (b) and Fig.13 (c) shows the results of SEM observation of the nanorods. Fig.13 (b) and Fig.13 As shown in (c), the size of the nanocolumns at the center of the pixel is the same as the size of the nanocolumns at the periphery of the pixel.

[0129] [Example 3]

[0130] In addition to forming Fig.13 A semiconductor optical element array was obtained in the same manner as in Comparative Example 1 except for the pixels (d) and those described below.

[0131] Pixel top view shape: Hexagonal

[0132] Pixel size (maximum length between opposite corners): 150 μm

[0133] · The pitch between the centers of adjacent nanopillars: 450nm

[0134] Size of the nanopillar at the center of the pixel: 200 nm

[0135] Size of nanopillars at the periphery of the pixel: 150nm

[0136] Fig.13 (e) and Fig.13 (f) shows the results of SEM observation of nanorods. Fig.13 (e) and Fig.13 As shown in (f), in the pixel, the size of the nanocolumns decreases continuously from the center to the periphery.

[0137] [Example 4]

[0138] In addition to forming Fig.13 A semiconductor optical element array was obtained in the same manner as in Comparative Example 1 except for (g) and the pixels described below.

[0139] Pixel top view shape: Hexagonal

[0140] Pixel size (maximum length between opposite corners): 150 μm

[0141] · The pitch between the centers of adjacent nanopillars: 450nm

[0142] Size of the nanopillar at the center of the pixel: 200 nm

[0143] Size of nanopillars at the periphery of the pixel: 100 nm

[0144] Fig.13 (h) and Fig.13 (i) shows the results of SEM observation of nanorods. Fig.13 (h) and Fig.13 As shown in (i), in a pixel, the size of the nanocolumns decreases continuously from the center to the periphery.

[0145] [evaluate]

[0146] The same operation as in Comparative Example 2 and Examples 3 and 4 was performed. At the stage of forming the light-emitting layer, the light-emitting layer was irradiated with laser light, and the light emission intensity was measured in the same manner as above. Fig.14 The results are displayed. Fig.14 As shown in FIG. 3 and FIG. 4, higher luminescence intensity is obtained in Examples 3 and 4 than in Comparative Example 2. Fig.14 The half-width of the peaks shown is 61.2 nm for Comparative Example 2, 57.5 nm for Example 3, and 53.9 nm for Example 4.

[0147] Thus, in the present disclosure, for example, the following inventions are provided. [1]

[0149] A semiconductor optical element array, comprising:

[0150] Semiconductor substrates;

[0151] a mask layer disposed on the main surface of the semiconductor substrate and having an opening;

[0152] A nanocolumn extending from the semiconductor substrate through the opening in the thickness direction and being a columnar crystal of a group III nitride semiconductor;

[0153] A light-emitting layer disposed at the front end of the nanorod; and

[0154] a covering semiconductor layer, which covers the light-emitting layer and contains a semiconductor; and

[0155] The semiconductor optical element array has pixels including a plurality of the nanorods.

[0156] In the above-mentioned pixel, the size of the above-mentioned nanocolumns increases stepwise or continuously, or decreases stepwise or continuously from the center to the periphery. [2]

[0158] The semiconductor optical element array as described in [1], wherein:

[0159] The size of the nanocolumn at the center of the pixel is greater than or equal to 10 nm and less than or equal to 1000 nm. [3]

[0161] The semiconductor optical element array as described in [1] or [2], wherein:

[0162] In the above-mentioned pixel, the size of the above-mentioned nanocolumns increases stepwise or continuously from the center to the periphery. [4]

[0164] The semiconductor optical element array as described in [3], wherein:

[0165] When the size of the nanocolumn at the center of the pixel is set to S1 [nm] and the size of the nanocolumn at the periphery of the pixel is set to S2 [nm], the ratio of S2 to S1 (S2 / S1) is greater than 1.5 and less than 6.0. [5]

[0167] The semiconductor optical element array as described in [1] or [2], wherein:

[0168] In the above-mentioned pixel, the size of the above-mentioned nanocolumns decreases stepwise or continuously from the center to the periphery. [6]

[0170] The semiconductor optical element array as described in [5], wherein:

[0171] When the size of the nanocolumn at the center of the pixel is set to S3 [nm] and the size of the nanocolumn at the periphery of the pixel is set to S4 [nm], the ratio of S4 to S3 (S4 / S3) is greater than 0.4 and less than 0.8. [7]

[0173] The semiconductor optical element array according to any one of [1] to [6], wherein:

[0174] In the direction from the center toward the periphery, a difference in size between adjacent nanocolumns is 5 nm or less. [8]

[0176] The semiconductor optical element array as described in any one of [1] to [7], wherein:

[0177] The nanocolumns are columnar crystals of GaN. [9]

[0179] The semiconductor optical element array as described in any one of [1] to [8], wherein:

[0180] The light emitting layer includes InGaN.

[10]

[0182] The semiconductor optical element array as described in any one of [1] to [9], wherein:

[0183] A portion of the pixel is a light-emitting region, and the light-emitting region includes the center.

[0184] [Explanation of Reference Numerals]

[0185] 1:Semiconductor substrate

[0186] 1a: Base substrate

[0187] 1b: Semiconductor layer

[0188] 2: Mask layer

[0189] 3: Nanopillars

[0190] 4: Luminous layer

[0191] 5: Covering semiconductor layer

[0192] 10: Semiconductor optical element array

Claims

1. A semiconductor optical element array, comprising: Semiconductor substrates; a mask layer disposed on the main surface of the semiconductor substrate and having an opening; A nanocolumn extending from the semiconductor substrate through the opening in the thickness direction and being a columnar crystal of a group III nitride semiconductor; A light-emitting layer, which is disposed at the front end of the aforementioned nanorod; and a covering semiconductor layer, which covers the light-emitting layer and contains a semiconductor; and The semiconductor optical element array has pixels including a plurality of the nanorods. In the aforementioned pixel, the size of the aforementioned nanocolumns increases in a stepwise or continuous manner, or decreases in a stepwise or continuous manner from the center to the periphery.

2. The semiconductor optical element array according to claim 1, wherein: The size of the nanocolumn at the center of the pixel is greater than or equal to 10 nm and less than or equal to 1000 nm.

3. The semiconductor optical element array according to claim 1 or 2, wherein: In the aforementioned pixel, the size of the aforementioned nanocolumns increases stepwise or continuously from the center toward the periphery.

4. The semiconductor optical element array according to claim 3, wherein: When the size of the nanocolumn at the center of the pixel is set to S1 [nm] and the size of the nanocolumn at the periphery of the pixel is set to S2 [nm], the ratio of S2 to S1 (S2 / S1) is greater than 1.5 and less than 6.

0.

5. The semiconductor optical element array according to claim 1 or 2, wherein: In the aforementioned pixel, the size of the aforementioned nanocolumns decreases stepwise or continuously from the center toward the periphery.

6. The semiconductor optical element array according to claim 5, wherein: When the size of the nanocolumn at the center of the pixel is set to S3 [nm] and the size of the nanocolumn at the periphery of the pixel is set to S4 [nm], the ratio of S4 to S3 (S4 / S3) is greater than 0.4 and less than 0.

8.

7. The semiconductor optical element array according to claim 1 or 2, wherein: In the direction from the center toward the periphery, the difference in size between adjacent nanocolumns is 5 nm or less.

8. The semiconductor optical element array according to claim 1 or 2, wherein: The aforementioned nanocolumns are columnar crystals of GaN.

9. The semiconductor optical element array according to claim 1 or 2, wherein: The light emitting layer includes InGaN.

10. The semiconductor optical element array according to claim 1 or 2, wherein: A portion of the pixel is a light-emitting region, and the light-emitting region includes the center.

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