MRAM with doped silicon germanium tin alloy electrode

Abstract

A semiconductor device and a method of forming the device are disclosed. The semiconductor device includes a bottom electrode, a magnetic tunnel junction (MTJ) stack on the bottom electrode, and a top electrode (136, 236) on the MTJ stack. At least one of the bottom and top electrodes (136, 236) includes doped SiGeSn.

Description

Background Art

[0001] The present disclosure relates to magnetic random access memory (MRAM) devices based on a perpendicular magnetic tunnel junction (MTJ) structure. Certain MRAM devices can be manufactured to include an MTJ stack including a bottom electrode, an MRAM stack, and a top electrode. In general, MRAM devices can be used in a variety of applications. One example application is embedded storage (e.g., an eFlash replacement). Another example is a cache (e.g., an embedded dynamic random access memory (eDRAM) or a static random access memory (SRAM)). Certain MTJ structures include a Co-based synthetic antiferromagnet (SAF), a CoFeB-based reference layer, a MgO-based tunnel barrier, a CoFeB-based free layer, and a cap layer including, for example, Ta and / or Ru. An embedded MTJ structure is typically formed by subtractively patterning a blanket MTJ stack into a column between two metal layers. The MTJ structure can benefit from an increased junction temperature due to Joule heating during a write operation, which can reduce the write current without affecting retention. Summary of the invention

[0002] Embodiments of the present disclosure relate to a semiconductor device. The semiconductor device includes a bottom electrode, a magnetic tunnel junction (MTJ) stack on the bottom electrode, and a top electrode on the MTJ stack. At least one of the bottom electrode and the top electrode includes doped SiGeSn.

[0003] Other embodiments relate to a method of manufacturing a semiconductor device. The method includes forming a bottom electrode, forming a magnetic tunnel junction (MTJ) stack on the bottom electrode, and forming a top electrode on the MTJ stack. At least one of the bottom electrode and the top electrode includes doped SiGeSn.

[0004] The above summary is not intended to describe each illustrated embodiment or every implementation of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The accompanying drawings included in this application are incorporated into the specification and form a part of the specification. They show embodiments of the present disclosure and together with the specification explain the principles of the present disclosure. The accompanying drawings only illustrate certain embodiments and do not limit the present disclosure.

[0006] Figure 1 is a cross-sectional view of a semiconductor device including an MRAM device including a double-layer dielectric surrounding a bottom electrode contact (BEC) according to an embodiment, the cross-sectional view being at an intermediate stage of a manufacturing process.

[0007] Figure 2 is according to an embodiment after additional production operations Figure 1A cross-sectional view of a semiconductor device.

[0008] Figure 3 is according to an embodiment after additional production operations Figure 2 A cross-sectional view of a semiconductor device.

[0009] Figure 4 is according to an embodiment after additional production operations Figure 3 A cross-sectional view of a semiconductor device.

[0010] Figure 5 is according to an embodiment after additional production operations Figure 4 A cross-sectional view of a semiconductor device.

[0011] Figure 6 is according to an embodiment after additional production operations Figure 5 A cross-sectional view of a semiconductor device.

[0012] Figure 7 is a cross-sectional view of a semiconductor device at an intermediate stage of a manufacturing process according to an embodiment.

[0013] Figure 8 is according to an embodiment after additional production operations Figure 7 A cross-sectional view of a semiconductor device.

[0014] Fig. 9 is according to an embodiment after additional production operations Figure 8 A cross-sectional view of a semiconductor device.

[0015] Fig.10 is according to an embodiment after additional production operations Fig. 9 A cross-sectional view of a semiconductor device.

[0016] Fig.11 is according to an embodiment after additional production operations Fig.10 A cross-sectional view of a semiconductor device.

[0017] Fig.12 is according to an embodiment after additional production operations Fig.11 A cross-sectional view of a semiconductor device. DETAILED DESCRIPTION

[0018] The present disclosure describes an MRAM device including a magnetic tunnel junction ("MTJ") stack and a method of manufacturing the same. Specifically, the present disclosure describes an MRAM device having a thermal isolation structure for an MTJ memory and a method of manufacturing the same.

[0019] Typically, for the electrodes of the MTJ stack, conductive metal materials such as Ta or TiN are used. However, in this embodiment, a semiconductor material (i.e., the opposite of the conductive material of the related device) is used as an electrode. For example, a doped silicon germanium tin (SiGeSn) alloy can be used as an electrode of the MRAM device in this embodiment. The conductivity of doped SiGeSn may not be as high as that of the related conductive metal (although its conductivity is still high enough for the device to operate normally). However, one benefit of using SiGeSn is that its thermal conductivity is generally lower than that of traditional metal conductors used for electrodes. Typically, the upper and lower electrodes of the MTJ stack are connected to the metal wires of the MRAM device (e.g., the front-end process (FEOL), the middle process (MOL), and the back-end process (BEOL)). If the electrode is composed of a metal conductor with high thermal conductivity, the heat generated in the MTJ stack is transferred to the metal wires (e.g., the metal wires of the BEOL layer) relatively quickly. In addition, the higher the temperature of the MTJ stack, the easier it is to switch the MTJ stack. Therefore, it is beneficial to maintain the heat in the MTJ stack to achieve better switching performance. Therefore, the doped semiconductor SiGeSn electrode in this embodiment has a lower heat transfer coefficient, which can reduce the heat transfer from the MTJ stack to the surrounding metal lines. This leads to a higher operating temperature of the MTJ stack and improved performance characteristics.

[0020] One effect of this embodiment is that the thermal isolation characteristics of the device can be improved without changing the structure of the MTJ stack. The embodiments of the present disclosure also provide a device with improved thermal isolation performance. In addition, no changes are required for packaging or other processes adjacent to the MTJ stack. In some embodiments, doped SiGeSn semiconductor contacts are used, which have good electrical conductivity but poor thermal conductivity while maintaining a deposition temperature compatible with BEOL. In some embodiments, there are a wide range of silicon, germanium and tin (Sn) compositions. For this ternary compound, compounds with low germanium content (SiSn in extreme cases) have lower thermal conductivity. However, in order to make the deposition temperature compatible with the BEOL process, germanium is added to the compound. In addition, tin helps to increase the conductivity of the material. In some instances, MOCVD, PECVD and other low-temperature compatible deposition methods can be used to grow the material. The bottom via can be formed on the metal via by a recess and fill / CMP or a blanket and subtractive via formation process. In certain embodiments, the pedestal, top electrode, and bottom electrode may be formed using a highly p-doped (p++) SiGeSn (eg, doped with boron, gallium, aluminum, etc.) fill / CMP process.

[0021] Various embodiments of the present disclosure are described herein with reference to the relevant drawings. Alternative embodiments may be designed without departing from the scope of the present disclosure. It should be noted that various connections and positional relationships (e.g., above, below, adjacent, etc.) are listed between the elements in the following description and drawings. Unless otherwise specified, these connections and / or positional relationships may be direct or indirect, and the present disclosure is not intended to be limited in this regard. Therefore, the coupling of entities may refer to direct coupling or indirect coupling, and the positional relationship between entities may be a direct or indirect positional relationship. As an example of an indirect positional relationship, references in this specification to forming layer "A" on layer "B" include such a situation: as long as there are related characteristics and functions of layer "A" and layer "B" that are not substantially changed by (multiple) intermediate layers, there are one or more intermediate layers (e.g., layer "C") between layer "A" and layer "B".

[0022] The following definitions and abbreviations are used to interpret the claims and specification. As used herein, the terms "comprises," "including," "having," "containing," or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a composition, mixture, process, method, article, or apparatus that includes a list of elements is not necessarily limited to only those elements but may include other elements not expressly listed or inherent to such composition, mixture, process, method, article, or apparatus.

[0023] For the purposes of the description below, the terms "upper", "lower", "right", "left", "vertical", "horizontal", "top", "bottom" and their derivatives shall refer to the described structures and methods as oriented in the accompanying drawings. The terms "overlying", "on top of", "on", or "positioned on top of" indicate that a first element (e.g., a first structure) is present on a second element (e.g., a second structure), wherein an intermediate element (e.g., an interface structure) may be present between the first element and the second element. The term "direct contact" refers to the connection of a first element (e.g., a first structure) and a second element (e.g., a second structure) at the interface of the two elements without any intermediate conductive, insulating, or semiconducting layer. It should be noted that the term "selective to" (e.g., "the first element is selective to the second element") means that the first element can be etched and the second element can act as an etch stop.

[0024] For the sake of brevity, conventional techniques related to the production of semiconductor devices and integrated circuits (ICs) may or may not be described in detail herein. In addition, the various tasks and process steps described herein may be incorporated into a more comprehensive procedure or process having additional steps or functionality not described in detail herein. In particular, the various steps in the manufacture of semiconductor devices and semiconductor-based ICs are well known, and therefore, for the sake of brevity, many conventional steps will only be briefly mentioned herein or will be omitted entirely without providing well-known process details.

[0025] Typically, the various processes used to form a microchip to be packaged into an IC fall into four general categories, namely, film deposition, removal / etching, semiconductor doping, and patterning / lithography.

[0026] Deposition is any process that grows, coats, or otherwise transfers a material onto a wafer. Available techniques include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently, atomic layer deposition (ALD), among others. Another deposition technique is plasma enhanced chemical vapor deposition (PECVD), a process that uses the energy within a plasma to initiate reactions on the wafer surface that would otherwise require the higher temperatures associated with conventional CVD. High-energy ion bombardment during PECVD deposition can also improve the electrical and mechanical properties of the film.

[0027] Removal / etching is any process that removes material from a wafer. Examples include etching processes (wet or dry), chemical mechanical planarization (CMP), etc. An example of a removal process is ion beam etching (IBE). Generally, IBE (or mill) refers to a dry plasma etching method that utilizes a remote broad beam ion / plasma source to remove substrate material by means of physically inert gases and / or chemically reactive gases. Similar to other dry plasma etching techniques, IBE has advantages such as etch rate, anisotropy, selectivity, uniformity, aspect ratio, and minimization of substrate damage. Another example of a dry removal process is reactive ion etching (RIE). Typically, RIE uses a chemically reactive plasma to remove material deposited on a wafer. With RIE, a plasma is generated at low pressure (vacuum) by an electromagnetic field. High energy ions from the RIE plasma attack the wafer surface and react with it to remove material.

[0028] Semiconductor lithography is the process of forming a three-dimensional relief image or pattern on a semiconductor substrate so that the pattern can be subsequently transferred to the substrate. In semiconductor lithography, the pattern is formed by a photosensitive polymer called a photoresist. In order to build the complex structure of transistors and the many wirings that connect the millions of transistors of the circuit, the lithography and etching pattern transfer steps are repeated many times. Each pattern printed on the wafer is aligned with the previously formed pattern, and conductors, insulators, and selectively doped areas are slowly built up to form the final device.

[0029] Turning now to an overview of technology more specifically related to aspects of the present disclosure, embedded DRAM (eDRAM) is dynamic random access memory (DRAM) integrated on the same die or multi-chip module (MCM) of an application specific integrated circuit (ASIC) or microprocessor. eDRAM has been implemented in silicon-on-insulator (SOI) technology, which involves the use of layered silicon-insulator-silicon substrates in place of traditional silicon substrates in semiconductor manufacturing. eDRAM technology has met with varying degrees of success, and demand for SOI technology as a server memory option has decreased in recent years. Magnetoresistive random access memory (MRAM) devices using magnetic tunnel junctions (MTJs) are one option to replace existing eDRAM technology. MRAM is a non-volatile memory, and this property is a driving factor that has accelerated the development of this memory technology.

[0030] Magnetic tunnel junction (MTJ) device, which is the main storage element in magnetic random access memory (MRAM), is a magnetic storage and switching device in which two ferromagnetic layers are separated by a thin insulating oxide layer (i.e., tunnel barrier layer) to form a stacked structure. The tunnel barrier layer may include, for example, magnesium oxide or aluminum oxide. One of the ferromagnetic layers has a fixed magnetization, so it is called a magnetic fixed layer (or pinned layer or reference layer). However, the other ferromagnetic layer has a magnetization that can be changed, so it is called a free layer (or magnetic free layer). When a bias is applied to the MTJ device, electrons spin-polarized by the ferromagnetic layer cross the insulating tunnel barrier layer through a process called quantum tunneling to generate a current whose magnitude depends on the magnetization orientation of the ferromagnetic layer. When the magnetic moment of the free layer is parallel to the magnetic moment of the fixed layer, the MTJ device will exhibit low resistance, and when the magnetic moment of the free layer is oriented antiparallel to the magnetic moment of the fixed layer, the MTJ device will exhibit high resistance.

[0031] The materials and geometry used to construct the stack of different layers that form the MTJ device are factors that affect the characteristics of the device in terms of speed (i.e., switching time) and power consumption (e.g., the voltage and / or current required to switch the device from one state to another). As briefly discussed above, some MTJ devices have a cylindrical column structure (i.e., a material stack) in which a current flows from the top layer to the bottom layer, or vice versa, in order to switch the magnetization of a ferromagnetic layer. These types of MTJ devices are generally referred to as spin transfer torque (STT) MTJ devices. Compared to static random access memory (SRAM) devices (i.e., random access memories that keep data bits in their memory as long as power is supplied), some STT MRAM devices may have limited switching speeds and durability. Other types of MTJ devices are referred to as spin-orbit torque (SOT) devices. In SOT-type devices, the stacked column structure is still cylindrical, but the stack is deposited on top of a heavy metal conductor. In a SOT-type MTJ device, the current flows horizontally in the conductor and switches the magnetization of the ferromagnetic layer at the interface.

[0032] In STT-type MRAM devices, the manufacture of the device is usually performed in conjunction with the formation of a middle process (MOL) or back-end process (BEOL) layer. This can be referred to as an embedded MRAM, in which the MRAM device is embedded in these layers, or formed in conjunction with these layers. In general, the front-end process (FEOL) refers to a group of process steps for forming transistors and other circuit elements (such as resistors and capacitors), which are later electrically connected to the middle process (MOL) layer and the back-end process (BEOL) layer. Typically, MOL refers to a collection of wafer processing steps for creating structures that provide local electrical connections between transistors (e.g., gate contact formation). MOL processing typically occurs after the FEOL process and before the BEOL process. Typically, BEOL is part of IC production where individual devices (transistors, capacitors, resistors, etc.) are interconnected with wiring on the wafer.

[0033] Referring now to the drawings, in which like numerals represent the same or similar elements, reference is first made to Figure 1, shows an exemplary method of manufacturing a semiconductor device 100 (i.e., an MRAM device) to which the present embodiment can be applied. In this embodiment, doped SiGeSn vias are formed by a subtractive operation. In some examples, several back-end-of-line (“BEOL”) layers and front-end-of-line (FEOL) layers may be formed. Generally speaking, the front-end-of-line (FEOL) is the first part of IC production, where individual devices (transistors, capacitors, resistors, etc.) are patterned in the semiconductor. The FEOL typically covers everything up to (but not including) the deposition of metal interconnect layers. Typically, the BEOL is the second part of IC production, where the individual devices (transistors, capacitors, resistors, etc.) are interconnected with wiring on the wafer. The BEOL metal layer (not shown) may include, for example, Cu, TaN, Ta, Ti, TiN, or a combination thereof. The BEOL dielectric layer (not shown) may be formed on the side of one or more of the BEOL metal layers. The BEOL dielectric layer may be composed of, for example, SiOx, SiNx, SiBCN, low-κ, NBLOK, or any other suitable dielectric material. The structure including the FEOL / BEOL layers may be a starting structure on which an MRAM device is formed.

[0034] like Figure 1 As shown in the semiconductor device 100, a first dielectric layer 102 (e.g., in BEOL) is provided as a base layer in which an interconnect structure of the semiconductor device 100 may be formed. The first dielectric layer 102 may include, for example, SiOx, SiNx, SiBCN, NBLOK, TEOS, low-κ or ultra-low-κ (ULK) materials, etc. In some embodiments, the interconnect structure (not shown) may be included in one of the BEOL layers. Figure 1 In the example of , the first dielectric layer 102 may be formed in the x-th BEOL layer. Figure 1 As shown, a first metal layer 104 (e.g., Mx layer metal) is formed. The first metal layer 104 may include, for example, Cu, TaN, Ta, Ti, TiN, or a combination thereof. In some embodiments, a metal etch stop layer 106 is formed on the first dielectric layer 102. The metal etch stop layer 106 may include, for example, Ru. However, it should be understood that other suitable metals or metal alloys may also be used for the metal etch stop layer 106. In some embodiments, a bottom via conductor layer 108 may be formed on the metal etch stop layer 104. The bottom via conductor layer 108 may include one or more suitable conductive materials. In other embodiments, the bottom via conductor layer 108 is not included. Figure 1As shown, a thin heavily doped SiGeSn layer 110 (doped with, for example, boron) is formed on the bottom via conductor layer 108. The SiGeSn layer 110 can be metallic or doped semiconductor material. The thermal conductivity of undoped SiGeSn can be as low as 1-10 W / mK. However, the thermal conductivity of any system is further reduced by increasing the doping, which in this embodiment allows for a conductive bottom electrode.

[0035] Reference now Figure 2 , which is a diagram of an embodiment after additional production operations Figure 1 A cross-sectional view of a semiconductor device. Figure 2 As shown, a hard mask 112 is formed on the SiGeSn layer 110. In some embodiments, the hard mask is first deposited and then patterned using, for example, a combination of photolithography and etching (eg, RIE). Figure 2 As shown in the example of FIG. 1 , the hard mask 112 is formed above the first metal layer 104 (i.e., approximately at a central position above the first metal layer 104). In this example, the hard mask 112 is initially formed as a continuous layer over the entire semiconductor device 100 and is then patterned. In some examples, the material of the hard mask 112 can be TEOS or any other suitable material. For example, the hard mask 112 can include one or more of the following materials: TEOS, SiN, SiC, SiON, SiCN, etc.

[0036] Reference now Figure 3 , which is a diagram of an embodiment after additional production operations Figure 2 A cross-sectional view of a semiconductor device. Figure 3 As shown, certain layers of the semiconductor device 100 are removed using an appropriate material removal process (e.g., RIE). In particular, the hard mask 112 is used as a mask to enable the removal of the underlying portions of the SiGeSn layer 110 and the bottom via conductor layer 108 while stopping on the metal etch stop layer 106. In subsequent production operations, the metal etch stop layer 106 (e.g., including Ru) can be removed using, for example, ion beam etching (IBE) or an Ar-based RIE operation. Therefore, at this stage of the manufacturing process, portions of the first dielectric layer 102 and the first metal layer 104 that are not covered by the hard mask 112 are exposed.

[0037] Reference now Figure 4 , which is a diagram of an embodiment after additional production operations Figure 3 A cross-sectional view of a semiconductor device. Figure 4As shown, the hard mask 112 is removed. Then, a via dielectric layer 116 is formed until the upper surface of the SiGeSn layer 110 or above. In some embodiments, the via dielectric layer 116 may include, for example, one or more of SiN, SiOx, SiBCN, SiCOH, etc. However, it should be understood that any other suitable dielectric material may be used to form the via dielectric layer 116 (or fill dielectric layer). Then, in some embodiments, a material removal process such as CMP may be used to planarize the upper surface of the via dielectric layer 116 and the SiGeSn layer 110. Therefore, a bottom electrode stack is formed by the metal etch stop layer 106, the bottom via conductor layer 108, and the SiGeSn layer 110.

[0038] Reference now Figure 5 , which is a diagram of an embodiment after additional production operations Figure 4 A cross-sectional view of a semiconductor device 100 is shown. Figure 5 As shown, a pedestal 130 is formed on the SiGeSn layer 110 and on the via dielectric layer 116. In some embodiments, the pedestal 130 is composed of the same heavily doped (i.e., p++) SiGeSn material as the SiGeSn layer 110. However, it should be understood that in other embodiments, the pedestal 130 may include other materials. In some examples, the pedestal 130 is wider than the SiGeSn layer 110.

[0039] Likewise Figure 5As shown in , the MTJ stack 132 is formed on the base 130. In general, the MTJ stack 132 may include a magnetic free layer, a tunnel barrier layer, and a reference layer (not shown). Typically, the magnetic free layer has a magnetic moment or magnetization that can be flipped. In some embodiments, the tunnel barrier layer is a barrier between two conductive materials, such as a thin insulating layer or an electric potential. Electrons (or quasiparticles) pass through the tunnel barrier through the process of quantum tunneling. In some embodiments, the tunnel barrier layer includes at least one sublayer composed of MgO. The reference layer (or fixed layer) may be annealed in a magnetic field (for example) to set the polarization state of the reference layer in the MTJ stack 132. In some embodiments, each layer of the MTJ stack 132 may have a thickness of less than one angstrom to several angstroms or nanometers. Examples of typical materials in the MTJ stack may include MgO for the tunnel barrier layer, CoFeB for the free layer, and multiple layers composed of different materials for the reference layer. It should be understood that the MRAM material stack (MTJ stack) is not limited to these materials or the layers described above. That is, the MRAM material stack can be composed of any known material stack used in MRAM devices. In addition, it should be understood that the MTJ stack 132 may include additional layers, omit certain layers, and each of the layers may include any number of sublayers. In some embodiments, the MTJ stack 132 may have a combination of iron and antiferromagnetic metals, such as Co / Fe / Ni, other metals such as Pt / Ir, and B. In some embodiments, the tunnel barrier layer may include materials such as MgO, MgAlOx, AlOx, etc.

[0040] Next, if Figure 5As shown in , an etch stop metal layer 134 is formed on the MTJ stack 132. The etch stop metal layer 134 may include, for example, Ru. Then, a top electrode 136 is formed on the etch stop metal layer 134. In some embodiments, the top electrode 136 is composed of the same heavily doped (i.e., p++) SiGeSn material as the SiGeSn layer 110. However, it should be understood that in other embodiments, the top electrode 136 may include other materials. In some embodiments, a hard mask (not shown) such as a dielectric hard mask is formed on the top electrode 136. In some embodiments, the hard mask is a multi-layer hard mask. At least initially, the hard mask is formed as a continuous layer on the entire semiconductor device 100. In some examples, the material of the hard mask may be TEOS or any other suitable (multiple) materials. For example, the hard mask may include one or more of the following materials: TEOS, SiN, SiC, SiON, SiCN, etc. Then, a photolithography mask (not shown) is formed, which can be used to pattern the MRAM stack. In one example, the photolithography mask is a three-layer mask including an organic planarization layer, a photolithography hard mask (e.g., SiCAR, SiN, SiON, etc.), and a photoresist. It should be understood that the photolithography hard mask may include multiple layers. The photoresist may be formed by patterning using any suitable photolithography process. Then, using appropriate material removal processes, the hard mask, top electrode 136, MTJ stack 132, and base 130 are patterned using photolithography, RIE, and / or IBE processes to create MTJ columns.

[0041] Reference now Figure 6 , which is a diagram of an embodiment after additional production operations Figure 5 A cross-sectional view of a semiconductor device 100 is shown. Figure 6 As shown, a dielectric packaging layer 138 is formed on the entire semiconductor device 100. The dielectric packaging layer 138 may include, for example, SiN, SiBCN, SiCN, SiOCN or SiON, or any other suitable dielectric material. One purpose of the dielectric packaging layer 138 is to isolate the tunnel barrier layer of the MTJ stack 132 from the external environment. Figure 6 As shown in , a dielectric filling layer 140 is formed in and around the MTJ pillar. In some embodiments, the dielectric filling layer 140 may be formed of an oxide-based dielectric material, which may be formed by an aggressive deposition process. Therefore, the dielectric encapsulation layer 140 may help protect the tunnel barrier layer from damage during such a process. A CMP process may be performed to planarize the upper surface of the semiconductor device 100. Then, as shown in FIG. Figure 6As shown, a second dielectric layer 142 is formed on the dielectric packaging layer 140, and a via is formed in the second dielectric layer 142 by any suitable combination of processes known to those skilled in the art. A top contact liner 144 may be first formed in the via. Then, a first top contact 146 (or a bit line metal layer) is formed in the remaining portion of the via in the memory region above the top contact liner 144.

[0042] Reference now Figure 7 , shows an exemplary method of manufacturing a semiconductor device 200 (ie, an MRAM device) to which the present embodiment can be applied. Figure 7-Figure 12 The illustrated embodiment is similar in some respects to Figure 1-Figure 10 The MRAM device shown, however, the manufacturing method includes forming a doped SiGeSn via by first recessing an existing via and then depositing SiGeSn in the via. In some examples, several back-end-of-line (“BEOL”) layers and front-end-of-line (FEOL) layers may be formed. Generally speaking, the front-end-of-line (FEOL) is the first part of IC production, where individual devices (transistors, capacitors, resistors, etc.) are patterned in the semiconductor. The FEOL typically covers everything up to (but not including) the deposition of metal interconnect layers. Typically, the BEOL is the second part of IC production, where the individual devices (transistors, capacitors, resistors, etc.) are interconnected with wiring on the wafer. The BEOL metal layer (not shown) may include, for example, Cu, TaN, Ta, Ti, TiN, or a combination thereof. The BEOL dielectric layer (not shown) may be formed on the side of one or more of the BEOL metal layers. The BEOL dielectric layer may be composed of, for example, SiOx, SiNx, SiBCN, low-κ, NBLOK, or any other suitable dielectric material. The structure including the FEOL / BEOL layers may be a starting structure on which an MRAM device is formed.

[0043] like Figure 7 As shown in the semiconductor device 200, a first dielectric layer 202 (e.g., in BEOL) is provided as a base layer in which an interconnect structure of the semiconductor device 200 can be formed. The first dielectric layer 202 may include, for example, SiOx, SiNx, SiBCN, NBLOK, TEOS, low-κ or ultra-low-κ (ULK) materials, etc. In some embodiments, the interconnect structure (not shown) may be included in one of the BEOL layers. Figure 7 In the example of , the first dielectric layer 202 may be formed in the x-th level BEOL layer. Figure 7 As shown, a first metal layer 204 (eg, Mx metal layer) is formed. The first metal layer 204 may include, for example, Cu, TaN, Ta, Ti, TiN, or a combination thereof. Figure 1-Figure 6The metal etch stop layer 106 described in the embodiment is not formed on the first dielectric layer 202. Then, a via dielectric layer 206 is formed on the first dielectric layer 202 and the first metal layer 204. In some embodiments, the via dielectric layer 206 may include, for example, one or more of SiN, SiOx, SiBCN, SiCOH, etc. However, it should be understood that any other suitable dielectric material can be used to form the via dielectric layer 206 (or filling dielectric layer). Then, a bottom via conductor layer 208 (or conductive via) is formed on the first metal layer 204. The bottom via conductor layer 208 may include one or more suitable conductive materials, such as Cu, Ta, TaN, W, etc., and is surrounded by the via dielectric layer 206.

[0044] Reference now Figure 8 , which is a diagram of an embodiment after additional production operations Figure 7 A cross-sectional view of a semiconductor device 200 is shown. Figure 8 As shown, a suitable material removal process (eg, wet etching, RIE, or a combination thereof) is performed to recess the upper surface of the bottom via conductor layer 208 .

[0045] Reference now Fig. 9 , which is a diagram of an embodiment after additional production operations Figure 8 A cross-sectional view of a semiconductor device 200 is shown. Fig. 9 As shown, a thin heavily doped SiGeSn layer 210 is formed on the bottom via conductor layer 208. The SiGeSn layer 210 can be a metal or a doped semiconductor material. Any excess material of the SiGeSn layer 210 can be removed by CMP to planarize the semiconductor device 200 and expose the upper surface of the via dielectric layer 206, such as Fig.10 shown. Fig.10 The semiconductor devices and Figure 4 One structural difference between the semiconductor devices 100 shown is the absence of the metal etch stop layer 106 .

[0046] Reference now Fig.11 , which is a diagram of an embodiment after additional production operations Fig.10 A cross-sectional view of a semiconductor device 200 is shown. Fig.11 As shown, a pedestal 230 is formed on the SiGeSn layer 210 and on the via dielectric layer 206. In some embodiments, the pedestal 230 is composed of the same heavily doped (i.e., p++) SiGeSn material as the SiGeSn layer 210. However, it should be understood that in other embodiments, the pedestal 230 may include other materials. In some examples, the pedestal 230 is wider than the SiGeSn layer 210.

[0047] Likewise Fig.11As shown in , the MTJ stack 232 is formed on the base 230. In general, the MTJ stack 232 may include a magnetic free layer, a tunnel barrier layer, and a reference layer (not shown). Typically, the magnetic free layer has a magnetic moment or magnetization that can be flipped. In some embodiments, the tunnel barrier layer is a barrier between two conductive materials, such as a thin insulating layer or an electric potential. Electrons (or quasiparticles) pass through the tunnel barrier through the process of quantum tunneling. In some embodiments, the tunnel barrier layer includes at least one sublayer composed of MgO. The reference layer (or fixed layer) may be annealed in a magnetic field (for example) to set the polarization state of the reference layer in the MTJ stack 232. In some embodiments, each layer of the MTJ stack 232 may have a thickness of less than one angstrom to several angstroms or nanometers. Examples of typical materials in the MTJ stack may include MgO for the tunnel barrier layer, CoFeB for the free layer, and multiple layers composed of different materials for the reference layer. It should be understood that the MRAM material stack (MTJ stack) is not limited to these materials or the layers described above. That is, the MRAM material stack can be composed of any known material stack used in MRAM devices. In addition, it should be understood that the MTJ stack 232 may include additional layers, omit certain layers, and each layer in the layer may include any number of sublayers. In some embodiments, the MTJ stack 232 may have a combination of iron and antiferromagnetic metals (e.g., Co / Fe / Ni), other metals (e.g., Pt / Ir), and B. In some embodiments, the tunnel barrier layer may include materials such as MgO, MgAlOx, AlOx, etc.

[0048] Next, if Fig.11As shown in , an etch stop metal layer 234 is formed on the MTJ stack 232. The etch stop metal layer 234 may include, for example, Ru. Then, a top electrode 236 is formed on the etch stop metal layer 234. In some embodiments, the top electrode 236 is composed of the same heavily doped (i.e., p++) SiGeSn material as the SiGeSn layer 210. However, it should be understood that in other embodiments, the top electrode 236 may include other materials. In some embodiments, a hard mask (not shown) such as a dielectric hard mask is formed on the top electrode 236. In some embodiments, the hard mask is a multi-layer hard mask. At least initially, the hard mask is formed as a continuous layer on the entire semiconductor device 200. In some examples, the material of the hard mask may be TEOS or any other suitable (multiple) materials. For example, the hard mask may include one or more of the following materials: TEOS, SiN, SiC, SiON, SiCN, etc. Then, a photolithography mask (not shown) is formed, which can be used to pattern the MRAM stack. In one example, the photolithography mask is a three-layer mask including an organic planarization layer, a photolithography hard mask (e.g., SiCAR, SiN, SiON, etc.), and a photoresist. It should be understood that the photolithography hard mask may include multiple layers. The photoresist may be formed by patterning using any suitable photolithography process. Then, using appropriate material removal processes, the hard mask, top electrode 236, MTJ stack 232, and base 230 are patterned using photolithography, RIE, and / or IBE processes to create MTJ columns.

[0049] Reference now Fig.12 , which is a diagram of an embodiment after additional production operations Fig.11 A cross-sectional view of a semiconductor device 200 is shown. Fig.12 As shown, a dielectric packaging layer 238 is formed on the entire semiconductor device 200. The dielectric packaging layer 238 may include, for example, SiN or SiCN(H), or any other suitable dielectric material. One purpose of the dielectric packaging layer 238 is to isolate the tunnel barrier layer of the MTJ stack 232 from the external environment. Fig.12 As shown in , a dielectric filling layer 240 is formed in and around the MTJ pillar. In some examples, the dielectric filling layer 240 may be formed of an oxide-based dielectric material that may be formed by an aggressive deposition process. Thus, the dielectric encapsulation layer 240 may help protect the tunnel barrier layer from damage during such a process. A CMP process may be performed to planarize the upper surface of the semiconductor device 200. Then, as shown in FIG. Fig.12As shown, a second dielectric layer 242 is formed on the dielectric packaging layer 240, and a via is formed in the second dielectric layer 242 by any appropriate combination of processes known to those skilled in the art. A top contact liner 244 may be first formed in the via. Then, a first top contact 246 (or a bit line metal layer) is formed in the remaining portion of the via in the memory region above the top contact liner 244.

[0050] In this embodiment, assuming that the power during switching of the MTJ is ~48μW, the temperature rise for a range of thermal conductivities of doped SiGeSn (K=3-10W / mK) is simulated and compared with the Cu micropillars for the bottom electrode of the 60nm high MTJ (which is 20nm smaller than the MTJ CD), resulting in a considerable temperature rise of the bottom electrode based on first-order calculations. The simulation shows that for heavily boron-doped SiGeSn, resistivities below 1000μOhm-cm can be achieved because this material provides higher mobility than Si at comparable solid solubility of boron. The simulation below shows the via resistance as a function of the via CD for the SiGeSn resistivity as a parameter. The simulation shows that the resistance penalty is not comparable to the MTJ resistance and is manageable for the circuit, making SiGeSn a viable option for the bottom electrode of STT MRAM, especially at aggressively scaled MTJ sizes. Moreover, in this embodiment, there is no need to change the process steps adjacent to the MTJ, so the MTJ is not disturbed during the manufacturing process. Moreover, the structure of the MTJ stack does not change. In addition, no additional structure needs to be formed to generate heat, resulting in a compact design of the MTJ device. Moreover, thermal isolation is provided by the doped semiconductor material of the SiGeSn layer. Therefore, the doped SiGeSn semiconductor contact has good electrical conductivity characteristics, but poor thermal conductivity characteristics, while maintaining a BEOL compatible deposition temperature.

[0051] The description of various embodiments is presented for the purpose of illustration and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the described embodiments. The terminology used herein is selected in order to best explain the principles of the embodiments, practical application or technical improvement of technologies found in the marketplace, or to enable those of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A semiconductor device, comprising: bottom electrode; A magnetic tunnel junction MTJ stack, wherein the MTJ stack is on the bottom electrode; as well as a top electrode, the top electrode being on the MTJ stack, At least one of the bottom electrode and the top electrode comprises doped SiGeSn.

2. The semiconductor device according to claim 1 , further comprising a pedestal between the bottom electrode and the MTJ stack, wherein The susceptor includes doped SiGeSn. The semiconductor device according to claim 2 , wherein the pedestal is wider than the bottom electrode. 4 . The semiconductor device of claim 2 , wherein the pedestal, the bottom electrode, and the top electrode all comprise doped SiGeSn. The semiconductor device according to claim 1 , wherein the doped SiGeSn is doped with boron. 6 . The semiconductor device according to claim 1 , further comprising a bottom via conductor layer below the bottom electrode. 7 . The semiconductor device of claim 1 , further comprising a metal etch stop layer below the bottom via conductor layer. The semiconductor device according to claim 7 , wherein the metal etch stop layer comprises Ru.

9. The semiconductor device of claim 1, wherein the bottom electrode comprises at least one conductive layer connected to a back end of line (BEOL) metal layer. 10 . The semiconductor device of claim 1 , further comprising a dielectric encapsulation layer formed around the MTJ stack.

11. A method for forming a semiconductor device, the method comprising: forming a bottom electrode; forming a magnetic tunnel junction MTJ stack on the bottom electrode; as well as forming a top electrode on the MTJ stack, At least one of the bottom electrode and the top electrode comprises doped SiGeSn. 12 . The method of claim 11 , further comprising forming a pedestal between the bottom electrode and the MTJ stack, wherein the pedestal comprises doped SiGeSn. The method of claim 12 , wherein the pedestal is wider than the bottom electrode.

14. The method of claim 12, wherein the pedestal, the bottom electrode, and the top electrode all comprise doped SiGeSn.

15. The method of claim 11, wherein the doped SiGeSn is doped with boron.

16. The method of claim 11, further comprising a bottom via conductor layer below the bottom electrode.

17. The method according to claim 11, further comprising: forming a bottom via conductor layer on the first metal layer; making the upper portion of the bottom via conductor layer concave; as well as The bottom electrode is formed in a recess formed in the upper portion of the bottom via conductor layer.

18. The method according to claim 11, further comprising: forming a metal etch stop layer on the first metal layer; forming a bottom via conductor on the metal etch stop layer; as well as The bottom electrode is formed on the bottom via conductor layer.

19. The method of claim 11, wherein the bottom electrode comprises at least one conductive layer connected to a back end of line (BEOL) metal layer.

20. The method of claim 11, further comprising forming a dielectric encapsulation layer formed around the MTJ stack.

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