Array substrate and display panel

Abstract

The application provides an array substrate and a display panel, and relates to the technical field of display. The array substrate comprises a substrate, an active layer, a gate driving layer and a source-drain electrode layer arranged on the substrate, an insulating layer formed on the source-drain electrode layer, wherein the insulating layer is provided with a touch signal line, a common electrode layer, a passivation layer and a pixel electrode layer arranged on the insulating layer, wherein the common electrode layer is electrically connected with the touch signal line through a first via, the pixel electrode layer is electrically connected with the drain electrode of the source-drain electrode layer through a second via, the pixel electrode layer in the second via is formed by a composite material layer, and the composite material layer comprises an organic conductive polymer material layer and a transparent metal oxide material layer arranged in a stack. The technical scheme provided by the application can reduce the disconnection rate of the array substrate and improve the reliability of the array substrate.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to an array substrate and a display panel. BACKGROUND

[0002] With the rapid development of liquid crystal display technology, touch display devices have been widely used in various fields due to their easy use, fast response and space saving.

[0003] According to the setting mode of the touch sensing layer, it can be divided into Add on Mode, In-cell and On-cell structures. Among them, the In-cell structure integrates the touch sensor into the embedded liquid crystal display layer, which can effectively reduce the thickness of the entire display panel and make the product more lightweight. In the related art, the electrode layer is usually prepared by Indium Tin Oxide (ITO), but ITO has high hardness and brittleness, which makes ITO easy to break when subjected to external force. In addition, during the production process of the array substrate, especially at the via hole of the touch electrode, ITO may have defects inside the touch electrode due to process problems, causing disconnection and reducing the reliability of the array substrate. SUMMARY

[0004] Therefore, the present application provides an array substrate and a display panel for improving the reliability of the array substrate.

[0005] In order to achieve the above purpose, in a first aspect, the embodiments of the present application provide an array substrate, which comprises:

[0006] a substrate substrate;

[0007] an active layer, a gate driving layer and a source-drain layer arranged on the substrate substrate;

[0008] an insulating layer formed on the source-drain layer, wherein the insulating layer is provided with a touch signal line;

[0009] a common electrode layer, a passivation layer and a pixel electrode layer arranged on the insulating layer;

[0010] The common electrode layer is electrically connected to the touch signal line through a first via hole, and the pixel electrode layer is electrically connected to the drain of the source-drain layer through a second via hole. The pixel electrode layer in the second via hole is formed by a composite material layer, and the composite material layer comprises an organic conductive polymer material layer and a transparent metal oxide material layer arranged in layers.

[0011] In a possible implementation of the first aspect, the insulating layer includes an organic insulating layer and an inorganic insulating layer arranged in a stack, and the touch signal line is located between the organic insulating layer and the inorganic insulating layer, and includes a first signal line and a second signal line connected to each other;

[0012] The first via exposes the first signal line through the inorganic insulating layer, and the second via exposes the drain through the passivation layer, the inorganic insulating layer, and the organic insulating layer;

[0013] The common electrode layer includes a first common electrode and a second common electrode arranged at intervals, the first common electrode is electrically connected to the first signal line through the first via, and part of the pixel electrode layer, part of the second common electrode, and part of the second signal line are located in the second via, in which the pixel electrode layer is electrically connected to the drain in sequence through the second common electrode and the second signal line.

[0014] In a possible implementation of the first aspect, the organic conductive polymer material layer includes a first organic conductive polymer material layer and a second organic conductive polymer material layer, and the first organic conductive polymer material layer, the transparent metal oxide material layer, and the second organic conductive polymer material layer are arranged in a stack.

[0015] In a possible implementation of the first aspect,

[0016] The pixel electrode layer includes a first pixel electrode and a second pixel electrode.

[0017] The insulating layer is an organic insulating layer, the source-drain electrode layer covers part of the gate drive layer, the organic insulating layer covers the source-drain electrode layer and another part of the gate drive layer, and the touch signal line is formed on the another part of the gate drive layer.

[0018] The first via includes a first sub-via and a second sub-via, the first pixel electrode is electrically connected to the common electrode layer through the first sub-via, and the first pixel electrode is electrically connected to the touch signal line through the second sub-via.

[0019] The second pixel electrode is electrically connected to the drain through a second via.

[0020] In a possible implementation of the first aspect, the common electrode layer includes a first common electrode and a second common electrode arranged at intervals, the first pixel electrode layer is electrically connected to the first common electrode through the first sub-via, and the second via is located between the first common electrode and the second common electrode.

[0021] In a possible implementation of the first aspect, the first pixel electrode in the first via and the second pixel electrode in the second via are both formed using the composite material layer.

[0022] In a possible implementation of the first aspect, the second via is formed using a one-time mask process after the organic insulating layer and the passivation layer are formed.

[0023] In a possible implementation of the first aspect, the gate driving layer includes a gate insulating layer, a gate layer, and an interlayer dielectric layer arranged in a stack, and the gate layer includes a gate line, at least part of the gate line being formed using a metal layer and an organic conductive polymer material layer arranged in a stack.

[0024] In a possible implementation of the first aspect, the organic conductive polymer is PEDOT, and the transparent metal oxide is ITO.

[0025] In a second aspect, an embodiment of the present application provides a display panel, which includes the array substrate of the first aspect or any one of the first aspect, an opposite substrate arranged opposite to the array substrate, and a display medium layer between the array substrate and the opposite substrate.

[0026] The array substrate provided by the embodiment of the present application includes a substrate, an active layer, a gate driving layer, a source-drain layer, an insulating layer formed on the source-drain layer, a touch signal line arranged in the insulating layer, a common electrode layer, a passivation layer, and a pixel electrode layer arranged on the insulating layer, wherein the common electrode layer is electrically connected to the touch signal line through a first via, the pixel electrode layer is electrically connected to a drain electrode of the source-drain layer through a second via, the pixel electrode layer in the second via is formed using a composite material layer, and the composite material layer includes an organic conductive polymer material layer and a transparent metal oxide material layer arranged in a stack. The technical solution provided by the present application can reduce the occurrence of disconnection in the array substrate and improve the reliability of the array substrate.

[0027] It can be understood that the beneficial effects of the second aspect described above can be referred to the related description of the first aspect, which will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 A structure diagram of a first array substrate provided by the embodiment of the present application is shown in FIG. 1.

[0029] Figure 2 A wire trace oblique view of a gate line of a non-curved display panel provided by the embodiment of the present application is shown in FIG. 2.

[0030] Figure 3 A wire trace oblique view of a gate line of a curved display panel provided by the embodiment of the present application is shown in FIG. 3.

[0031] Figure 4 A schematic diagram of a non-touch array substrate provided in an embodiment of this application;

[0032] Figure 5 This is a schematic diagram of the film structure of the organic conductive polymer material layer and the transparent metal oxide material layer provided in the embodiments of this application;

[0033] Figures 6A-6C This is a schematic flowchart of a method for preparing a pixel electrode layer provided in an embodiment of this application;

[0034] Figure 7 A schematic diagram of a second type of array substrate provided in an embodiment of this application;

[0035] Figure 8 This is a schematic diagram of the structure of the display panel provided in an embodiment of this application.

[0036] Explanation of reference numerals in the attached figures:

[0037] 10-Substrate; 11-Active layer; 12-Gate driving layer; 120-Gate insulating layer; 121-Gate layer; 122-Interlayer dielectric layer; 13-Source / drain layer; 130-Source; 131-Drain;

[0038] 14-Insulating layer; 140-Organic insulating layer; 141-Inorganic insulating layer; 15-Common electrode layer; 150-First common electrode; 151-Second common electrode; 16-Passivation layer;

[0039] 17 - Pixel electrode layer; 170 - Organic conductive polymer material layer; 171 - Transparent metal oxide material layer; 17a - First pixel electrode; 17b - Second pixel electrode; 18 - Touch signal line; 180 - First signal line; 181 - Second signal line;

[0040] 19-First contact hole; 20-Second contact hole; 21-Second via hole; 22-First via hole; 220-First sub-via hole; 221-Second sub-via hole; 23-Third contact hole;

[0041] 100 - Array substrate; 200 - Opposing substrate; 300 - Display medium layer. Detailed Implementation

[0042] The embodiments of this application are described below with reference to the accompanying drawings. The terminology used in the implementation section of this application is only for explaining specific embodiments and is not intended to limit the application. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0043] In embedded touch display panels, touch signal lines are provided in the array substrate to respond to touch operations after receiving user touch input. In existing display panels, ITO material is typically deposited using a deposition process when fabricating the electrode layer. However, when the taper angle of the process vias (or through-holes) in the array substrate is too large, or when the ITO is subjected to stress, poor hole overlap or even wire breakage may occur, leading to touch abnormalities. This reduces the reliability of the array substrate and consequently triggers customer complaints.

[0044] In view of this, this application provides an array substrate, which may include: a substrate, an active layer, a gate driving layer, and a source / drain layer disposed on the substrate, an insulating layer formed on the source / drain layer, and touch signal lines disposed in the insulating layer. A common electrode layer, a passivation layer, and a pixel electrode layer are disposed on the insulating layer. The common electrode layer is electrically connected to the touch signal lines through a first via, and the pixel electrode layer is electrically connected to the drain of the source / drain layer through a second via. The pixel electrode layer located in the second via may be formed using a composite material layer, which may include a stacked organic conductive polymer material layer and a transparent metal oxide material layer.

[0045] The array substrate described in this application is illustrated below with reference to the accompanying drawings and embodiments, using two specific examples.

[0046] Example 1

[0047] Figure 1 This is a schematic diagram of the array substrate provided in an embodiment of this application. Figure 1 As shown, the array substrate may include a substrate 10, an active layer 11, a gate driving layer 12, a source-drain layer 13, an insulating layer 14, a common electrode layer 15, a passivation layer 16, and a pixel electrode layer 17 stacked together. Touch signal lines 18 are also provided in the insulating layer 14.

[0048] The substrate 10 can be made of quartz, glass, organic polymer, silicon, metal and other semiconductor materials. In some embodiments, the substrate 10 can also be a flexible substrate made of polyimide.

[0049] It should be noted that when the substrate 10 is a transparent substrate, a light-shielding layer (not shown) can also be formed between the substrate 10 and the active layer 11 to shield the backlight and prevent the active layer 11 from generating photogenerated carriers under backlight illumination, which would lead to an increase in device leakage current. The material of the light-shielding layer can be amorphous silicon or metal and other light-absorbing and shielding materials, and this application does not impose any particular restrictions on this.

[0050] The active layer 11 can be fabricated on a portion of the substrate 10. During fabrication, a semiconductor material can be deposited using a chemical vapor deposition process, and the active layer is formed after a photomask process is performed on the semiconductor material. The photomask process mainly includes: coating photoresist, patterning and developing the photoresist, etching (dry etching or wet etching), and removing the photoresist.

[0051] The gate driving layer 12 may include a gate insulating layer 120, a gate layer 121, and an interlayer dielectric layer 122 stacked together. The gate insulating layer 120 may cover the active layer 11 and the substrate 10 to increase the gate electrode capacitance, thereby enhancing the gate's control over the channel. The material of the gate insulating layer 120 may be any one or more of oxides, nitrides, or oxynitrides, for example, silicon nitride. The material of the interlayer dielectric layer 122 may be one or more of silicon oxide, silicon nitride, and silicon oxide and silicon nitride.

[0052] The gate layer 121 may include multiple gate lines, which are typically made of one or more inorganic metals such as molybdenum, aluminum, aluminum-nickel alloy, molybdenum-tungsten alloy, chromium, or copper. Figure 2 This is a perspective view of the gate line routing of a non-curved display panel provided in an embodiment of this application. Figure 3 This is a perspective view of the gate line routing of the curved display panel provided in an embodiment of this application. Figures 1-3 The gate line 1210 is horizontally disposed in the gate layer 121 of the display panel and is used to provide scanning signals to the gate of the thin-film transistor. For curved display panels, the gate line 1210 is bent in the edge area of ​​the display panel. During the edge curvature process and product use, it is prone to brittleness or even breakage under the action of bending stress, causing touch abnormalities and local broken visual effects of the display screen.

[0053] In one possible implementation, the gate line 1210 can be fabricated using an organic conductive polymer material in the edge region. The organic conductive polymer material can be poly(3,4-ethylenedioxythiophene) (PEDOT). PEDOT possesses good flexibility and ductility, as well as excellent conductivity, thus effectively resisting bending stress and reducing the occurrence of wire breakage. Furthermore, since the PEDOT layer is a light-transmitting layer, it can reduce light shading, thereby improving light utilization. Of course, PEDOT can also be used to fabricate the gate line 1210 in flat regions, allowing for the use of the same material for the same trace, thus reducing fabrication difficulty.

[0054] Considering that PEDOT is a relatively soft material, in order to reduce scratches on the PEDOT layer during the manufacturing process, in some embodiments, a transparent metal oxide material layer or a metal layer can be prepared on one side of the PEDOT layer. This can not only improve the brittleness and breakage of the gate line 1210, but also reduce scratches on the PEDOT layer, extend the service life of the gate line 1210, and thus improve the reliability of the array substrate.

[0055] It is understandable that, taking the metal layer as an example, since the PEDOT layer is only set on one side of the metal layer, when the curvature of the edge area is large, cracks may be generated on the side of the metal layer away from the PEDOT layer, resulting in abnormal resistance and electrical properties. In some other embodiments, the PEDOT layer can also be set on the upper and lower sides of the metal layer.

[0056] It is understood that the above description is based on gate line 1210 as an example. In some embodiments, other metal traces on the array substrate, such as data lines, can also be prepared using organic conductive polymer materials or composite films of organic conductive polymer materials and metal layers.

[0057] The interlayer dielectric layer 122 can prevent interlayer short circuits and signal interference, improving the overall performance and energy efficiency of the array substrate. The material of the interlayer dielectric layer 122 can be one or more of silicon oxide, silicon nitride, and silicon oxide and silicon nitride. The interlayer dielectric layer 122 can be fabricated on the gate layer 121 using a chemical vapor deposition process.

[0058] After forming the interlayer dielectric layer 122, the interlayer dielectric layer 122 and the gate insulating layer 120 can be dry-etched using a photomask process to form a first contact hole 19 and a second contact hole 20. Both the first contact hole 19 and the second contact hole 20 penetrate the interlayer dielectric layer 122 and expose the active layer 11. Subsequently, a source / drain metal layer can be formed on top of the interlayer dielectric layer 122 using a physical vapor deposition or sputtering process, and a source / drain electrode layer 13 can be formed using a photomask process. The source / drain electrode layer 13 can include a source electrode 130 and a drain electrode 131. The source electrode 130 can be electrically connected to the active layer 11 through the first contact hole 19, and the drain electrode 131 can be electrically connected to the active layer 11 through the second contact hole 20. In some embodiments, the material of the source / drain electrode layer 13 can be the same as the material of the gate layer 121.

[0059] After forming the source-drain layer 13, an insulating layer 14 can be placed over the source-drain layer 13. In this embodiment, the insulating layer 14 may include an organic insulating layer 140 and an inorganic insulating layer 141 stacked together, see reference. Figure 1The touch signal line 18 can be located between the organic insulating layer 140 and the inorganic insulating layer 141. For example, the organic insulating layer 140 can be formed on the source-drain layer 13 first. The material of the organic insulating layer 140 can be indium gallium zinc oxide. Then, a second via 21 can be formed using a photomask process to expose the drain 131.

[0060] For example, a physical vapor deposition process can be used to deposit a metal material on the organic insulating layer 140 to form a touch metal layer. After applying a photomask process to the touch metal layer, interconnected first signal lines 180 and second signal lines 181 are formed. The material of the touch signal lines 180 can be the same as that of the gate layer 121 to reduce fabrication difficulty. The first signal line 180 can be located above the source 130 to reduce light shading; however, the first signal line 180 can also be located in other positions, such as on the side of the drain 131 away from the source 130. Part of the second signal line 181 can be located in the second via 21 and connected to the drain 131 through the second via 21.

[0061] An inorganic insulating material can be deposited above the touch signal line 18 and the organic insulating layer 140 using a chemical vapor deposition process to form an inorganic insulating layer 141. The material of the inorganic insulating layer 141 can be selected from inorganic insulating materials such as silicon nitride, silicon oxide, or ammonia silicon oxide. A first via 22 is formed above the first signal line 180 using a photomask process, exposing the first signal line 180, and the inorganic insulating material in the second via 21 is removed to expose the drain 142.

[0062] Subsequently, a common electrode layer 15 can be formed on the inorganic insulating layer 141. For example, a physical vapor deposition process can be used to deposit the common electrode material, and a photomask process can be used to form a first common electrode 150 and a second common electrode 151 spaced apart. By segmenting the common electrode layer 15, this embodiment of the application can more precisely control the electric field distribution, thereby optimizing the display effect, enhancing the reliability of the array substrate, and reducing the risk of the entire display panel failing due to a single electrode failure. The first common electrode 150 can be electrically connected to the first signal line 180 through the first via 22. A portion of the second common electrode 162 can be located in the second via 21 and electrically connected to the drain 131 through the second signal line 181.

[0063] By electrically connecting the first common electrode 150 to the first signal line 180 and the second common electrode 151 to the second signal line 181, the first common electrode 150 and the second common electrode 151 can be reused as touch electrodes. Firstly, this eliminates the need for separate film structures for the touch electrodes and the common electrode, simplifying the film structure of the display panel and reducing its thickness. Secondly, it reduces the process flow and manufacturing costs associated with additional touch electrode fabrication, helping to reduce the complexity of material and process preparation. Thirdly, since touch electrodes are typically made of metal, reusing the common electrode layer 15 reduces the weight of the display panel, facilitating its lightweight design. Fourthly, the reuse of the common electrode layer also improves the sensitivity and accuracy of touch sensing.

[0064] It is understood that in some embodiments, the common electrode layer 15 may also include a third common electrode, and there may be multiple third common electrodes, which are connected to the second common electrode 151 by bridging, thereby increasing the driving area of ​​the liquid crystal.

[0065] A passivation layer 16 can also be formed above the common electrode layer 15. For example, a passivation layer material can be deposited on the inorganic insulating layer 141 and the common electrode layer 15 using a chemical vapor deposition process, and a photomask process can be applied to the passivation layer material to remove at least a portion of the passivation layer material in the second via 21, forming the passivation layer 16. Pixel electrode material can be deposited on the passivation layer 16, and a pixel electrode layer 17 can be formed after patterning using a photomask process. A portion of the pixel electrode layer 17 is located in the second via 21 and is electrically connected to the second common electrode 162.

[0066] Figure 4 This is a schematic diagram of a non-touch array substrate provided in an embodiment of this application. (See attached diagram.) Figure 1 and Figure 4 Compared to non-touch array substrates, this solution adds an inorganic insulating layer 151 and touch signal lines 190. Taking the thickness of the inorganic insulating layer 141 as an example (0.25–1.5 μm), this increases the hole depth. When fabricating the second via 21, the different materials of the organic insulating layer 140 and the inorganic insulating layer 141 result in different etching rates. The inorganic insulating layer 140 has a larger taper angle, making it more prone to cracking or even line breakage when the pixel electrode layer 17 is climbing, thus causing display abnormalities in the display panel.

[0067] In one optional implementation, the pixel electrode layer 17 located in the second via 21 can be formed using a composite material layer, which includes a layer of organic conductive polymer material and a layer of transparent metal oxide material stacked together. The organic conductive polymer can be PEDOT, and the transparent metal oxide can be ITO. PEDOT has good ductility, excellent conductivity, high visible light transmittance, and low cost, which can effectively reduce the occurrence of cracks and line breaks in the pixel electrode layer 17. Of course, the pixel electrode layer 17 can also be fabricated using a composite material layer on its entire surface. In some embodiments, the composite material layer can also be prepared by forming a mixed solution of organic conductive polymer material and transparent metal oxide material.

[0068] In some embodiments, polystyrene sulfonic acid (PSS) can also be doped into PEDOT to further improve flexibility and stretchability, thereby enhancing the ability of the organic conductive polymer material layer to resist stress.

[0069] See Figure 1 The organic conductive polymer material layer 170 can be disposed below the transparent metal oxide material layer 171. It is understood that the transparent metal oxide material layer 171 can also be disposed below the organic conductive polymer material layer 170.

[0070] In some embodiments, see Figure 5 The organic conductive polymer material layer 170 may further include: a first organic conductive polymer material layer 1700 and a second organic conductive polymer material layer 1701. The first organic conductive polymer material layer 1700, the transparent metal oxide material layer 171 and the second organic conductive polymer material layer 1701 may be stacked from bottom to top, which can further reduce the breakage of the pixel electrode layer 17.

[0071] The following examples all use the case where a transparent metal oxide material layer 171 is disposed above an organic conductive polymer material layer 170. Figures 6A-6C This is a schematic flowchart of a method for preparing a pixel electrode layer according to an embodiment of this application. When preparing the pixel electrode layer 17, a solution of an organic conductive polymer material can first be applied to the passivation layer 16 using an imprint coating method to the target area (e.g., the area highlighted by the dotted line in the figure) where the organic conductive polymer material layer 170 needs to be formed. Then, the solution is heated to solidify it into a film, forming the organic conductive polymer material layer 170. (See also...) Figure 6A Next, a transparent metal oxide layer can be deposited over the organic conductive polymer material layer 170 using a sputtering process to form a transparent metal oxide material layer 171. A photoresist layer A is then coated onto the transparent metal oxide material layer 171. (See [reference]). Figure 6BA photoresist layer A is exposed and developed using a photomask (not shown) to expose the transparent metal oxide material layer 171 to be etched. Then, wet etching is used to remove the transparent metal oxide material layer 171 above the passivation layer 16, leaving only the transparent metal oxide layer 171 above the organic conductive polymer material layer 170. Finally, the remaining photoresist layer A is removed to form the pixel electrode layer 17, as shown below. Figure 6C As shown.

[0072] In some embodiments, an organic conductive polymer material layer 170 is disposed above a transparent metal oxide material layer 171. During fabrication, the transparent metal oxide material layer 171 can be first sputtered onto the passivation layer 16, and then wet etched onto the transparent metal oxide material layer 171 to retain only the transparent metal oxide material layer 171 in the target area. Afterward, the organic conductive polymer material layer 170 is formed on the transparent metal oxide material layer 171. This can also reduce the damage to the underlying organic conductive polymer material layer 170 when etching the transparent metal oxide material layer 171.

[0073] The thickness ratio of the organic conductive polymer material layer 170 to the transparent metal oxide material layer 171 can be 2:1 to ensure conductivity while reducing the occurrence of wire breaks. Of course, the specific thickness ratio can be determined according to actual needs.

[0074] Through the above implementation, during the display stage, after the gate line 1210 applies a scan signal to the thin-film transistor, the thin-film transistor is turned on, and the drain 131 can apply a driving voltage to the pixel electrode layer 17 through the second signal line 181 and the second common electrode 151, and sequentially apply a driving voltage to the first common electrode 150 through the second signal line 181 and the first signal line 180. The driving voltage applied to the first common electrode 150 has a voltage difference with the driving voltage applied to the pixel electrode layer 17 due to impedance and other reasons, which can drive the liquid crystal to deflect so that the display panel can display the image.

[0075] During the touch phase, if the user touches the area above the first common electrode 150 or the second common electrode 151, taking the user touching the first common electrode 150 as an example, the touch operation can cause a change in the capacitance value of the first common electrode 150. The change in capacitance value can be transmitted to the touch chip through the first signal line 180 to achieve touch sensing.

[0076] Second Embodiment

[0077] Compared with Example 1, the main difference in this example is the film structure above the interlayer dielectric layer.

[0078] Specifically, Figure 7This is a schematic diagram of a second type of array substrate provided in an embodiment of this application. (See attached diagram.) Figure 7 Above the interlayer dielectric layer 122, there may be a source / drain layer 13, an insulating layer, a common electrode layer 15, a passivation layer 16, and a pixel electrode layer 17 stacked together.

[0079] The source / drain layer 13 may partially cover the interlayer dielectric layer 122. The insulating layer may be an organic insulating layer 140, which can reduce stress differences between different materials and provide a flat surface to facilitate the fabrication of subsequent film layers. The organic insulating layer 140 may cover the source / drain layer 13 and another portion of the interlayer dielectric layer 122, and the touch signal line 18 may be formed on the other portion of the interlayer dielectric layer 122.

[0080] After forming the interlayer dielectric layer 122, during the photomask process, in addition to forming the first contact hole 19 and the second contact hole 20, a third contact hole 23 can also be formed to expose the gate layer 121. Then, a source / drain metal layer can be formed above the interlayer dielectric layer 122. A photomask process is performed on the source / drain metal layer so that the source electrode 130, the drain electrode 131, and the touch signal line 18 can be formed simultaneously. The touch signal line 18 is electrically connected to the gate layer 121, and the source electrode 130 and the drain electrode 131 are electrically connected to the active layer 11. By covering the touch signal line 18 and the source / drain electrode layer 13 with an organic insulating layer 140, it is not necessary to prepare an inorganic insulating layer, thereby reducing the film layer structure and thus reducing the thickness of the display panel.

[0081] The organic insulating layer 140 can be fabricated using a chemical vapor deposition (CVD) process. The first via 22 may include a first sub-via 220 and a second sub-via 221. For example, a photomask process can be used on the organic insulating layer 140 to form a first sub-via 220 exposing the touch signal line 18 and a second via 21 exposing the drain 131. A common electrode material can be deposited over the organic insulating layer 140 using a sputtering or physical vapor deposition (PVD) process to form a common electrode layer 15. A passivation layer 16 can be formed on the common electrode layer 15 using a CVD process. A photomask process is then used on the passivation layer 16 to remove the passivation layer material from the first sub-via 220 and the second via 21, and a second sub-via 221 is formed on the common electrode layer 15.

[0082] Considering that the second via 21 and the first sub-via 220 both have steps at the interlayer junction of the organic insulating layer 140 and the passivation layer 16, and the difference in taper angle is relatively obvious, burrs, breaks or missing parts are easily generated at the step transition, which causes changes in the resistance, electrical properties and surface roughness of the pixel electrode layer 17.

[0083] In some embodiments, an organic insulating layer 140, a common electrode layer 15, and a passivation layer 16 may be formed sequentially first. Then, a single photomask process is used to etch the passivation layer 16 and the organic insulating layer 140 sequentially to form a first sub-via 220 exposing the touch signal line 18 and a second via 21 exposing the drain 131. The passivation layer 16 is then etched to form a second sub-via 221 exposing the common electrode layer 15.

[0084] Since the second sub-via 221 exposes the common electrode layer 15, and the etching gas used in dry etching does not etch the common electrode layer 15, this embodiment achieves the following: on the one hand, the first sub-via 220, the second sub-via 221, and the second via 21 can be formed using only one mask, thereby reducing the use of masks and lowering fabrication costs; on the other hand, this also reduces the step size, making the taper angle at the interlayer junctions close to or even the same, thus reducing the occurrence of broken lines and improving the reliability of the array substrate.

[0085] Pixel electrode material can be deposited above the passivation layer 16. The pixel electrode material is patterned using a photomask process to form a first pixel electrode 17a and a second pixel electrode 17b. The first pixel electrode 17a can be electrically connected to the common electrode layer 15 through a first sub-via 220. The first pixel electrode 17a can also be electrically connected to the touch signal line 18 through a second sub-via 221. The second pixel electrode 17b can be electrically connected to the drain 131 through a second via 21.

[0086] The first pixel electrode 17a located in the first via 22 can be formed using a composite material layer. Alternatively, the entire pixel electrode layer 17 can be fabricated using a composite material layer to reduce fabrication difficulty. Figure 7 This description uses the first pixel electrode 17a as an example only. Compared to Embodiment 1, since the array substrate described in this embodiment does not include an inorganic insulating layer, the hole depth is shallower, and the thickness ratio of the organic conductive polymer material layer 170 to the transparent metal oxide material layer 171 can be 1:1, thereby reducing material costs. The preparation method and stacking method of the composite material layer can be referred to Embodiment 1, and will not be repeated here.

[0087] In some embodiments, the common electrode layer 15 may include a first common electrode 150 and a second common electrode 151 spaced apart. The first common electrode 150 may be electrically connected to the touch signal line 18 via a first pixel electrode 17a. A second via 21 may be located between the first common electrode 150 and the second common electrode 151. Specifically, the spacing between the first common electrode 150 and the second common electrode 151 may be greater than the aperture of the second via 21 to improve the connection reliability between the second pixel electrode 17b and the drain 131.

[0088] During the display stage, the thin-film transistor is turned on, and the drain 131 applies a driving voltage to the second pixel electrode 17b. The gate layer 121 can apply a driving voltage to the common electrode layer 15 through the touch signal line 18. Since there is a voltage difference between the driving voltage applied to the second pixel electrode 17b and the driving voltage applied to the first common electrode 150, the liquid crystal can be driven to deflect, so that the display panel can display the image.

[0089] During the touch phase, the first common electrode 150 can be reused as a touch electrode. If the user touches the area above the first common electrode 150, the touch operation can cause a change in the capacitance value of the first common electrode 150, which is transmitted to the touch chip through the touch signal line 18 to achieve touch sensing.

[0090] It should be noted that in the photomask process of this application embodiment, the photomasks used can be the same or different, and the thickness of each film layer structure can also be determined according to actual needs. This application embodiment does not impose any particular limitations on this. Furthermore, this application embodiment can be used not only for liquid crystal display devices but also for organic light-emitting diode display devices, etc. Obviously, those skilled in the art can make various modifications and variations to this invention without departing from the spirit and scope of this invention. Thus, if these modifications and variations of this invention fall within the scope of the claims of this invention and their equivalents, then this invention also intends to include these modifications and variations.

[0091] The array substrate provided in this application includes a substrate; an active layer, a gate driving layer, and a source / drain layer disposed on the substrate; an insulating layer formed on the source / drain layer, wherein touch signal lines are disposed in the insulating layer; a common electrode layer, a passivation layer, and a pixel electrode layer disposed on the insulating layer; wherein the common electrode layer is electrically connected to the touch signal lines through a first via, and the pixel electrode layer is electrically connected to the drain of the source / drain layer through a second via, and the pixel electrode layer located in the second via is formed of a composite material layer, the composite material layer including a stacked organic conductive polymer material layer and a transparent metal oxide material layer. The technical solution provided in this application can reduce the occurrence of broken lines in the array substrate and improve the reliability of the array substrate.

[0092] Based on the same inventive concept, embodiments of this application also provide a display panel. Figure 8 This is a schematic diagram of the structure of the display panel provided in the embodiments of this application, such as... Figure 8 As shown, the display panel may include the array substrate 100 described in any of the above embodiments, the opposing substrate 200 disposed opposite to the array substrate, and the display medium layer 300 located between the array substrate 100 and the opposing substrate 200.

[0093] The liquid crystal in the display medium layer 300 can be deflected under the drive of the array substrate 100, thereby transmitting light. After the light passes through the filtering effect of the opposing substrate 200, it is emitted out of the display panel, thereby displaying the image on the display panel.

[0094] Since the display panel in this embodiment includes the array substrate in the above embodiments, the display panel in this embodiment has all the technical features and effects of the above array substrate embodiments. For details, please refer to the above embodiments, and will not be repeated here.

[0095] It should be understood that in the description of this application and the appended claims, the terms "comprising," "including," "having," and any variations thereof are intended to cover non-exclusive inclusion and mean "including but not limited to," unless otherwise specifically emphasized.

[0096] In the description of this application, unless otherwise stated, " / " indicates that the objects before and after are in an "or" relationship. For example, A / B can mean A or B. "And / or" in this application is used to describe the relationship between the related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. A and B can be singular or plural.

[0097] Furthermore, in the description of this application, unless otherwise stated, "multiple" means two or more. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items.

[0098] Furthermore, it should be understood in the description of this application that the terms "longitudinal," "horizontal," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "vertical," "top," "bottom," "inner," "outer," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0099] In this application, unless otherwise expressly specified and limited, the terms "connection" and "linkage" should be interpreted broadly. For example, they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to the internal connection of two components or the interaction between two components. Unless otherwise expressly limited, those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0100] Furthermore, in the description of this application and the appended claims, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence, nor should they be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in a sequence other than that illustrated or described herein; features defined as "first" or "second" may explicitly or implicitly include at least one of those features.

[0101] In the embodiments of this application, the words "exemplarily" or "for example" are used to indicate examples, illustrations, or explanations. Any embodiment or design described as "exemplarily" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Specifically, the use of the words "exemplarily" or "for example" is intended to present the relevant concepts in a specific manner.

[0102] References to "one embodiment" or "some embodiments" in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized.

[0103] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. An array substrate, characterized in that, include: Substrate; An active layer, a gate driving layer, and a source / drain layer are disposed on the substrate. An insulating layer is formed on the source-drain layer, and a touch signal line is disposed in the insulating layer; A common electrode layer, a passivation layer, and a pixel electrode layer are disposed on the insulating layer; The common electrode layer is electrically connected to the touch signal line through a first via, and the pixel electrode layer is electrically connected to the drain of the source-drain layer through a second via. The pixel electrode layer located in the second via is formed of a composite material layer, which includes a stacked organic conductive polymer material layer and a transparent metal oxide material layer.

2. The array substrate according to claim 1, characterized in that, The organic conductive polymer material layer includes: a first organic conductive polymer material layer and a second organic conductive polymer material layer, wherein the first organic conductive polymer material layer, the transparent metal oxide material layer and the second organic conductive polymer material layer are stacked.

3. The array substrate according to claim 1, characterized in that, The pixel electrode layer includes a first pixel electrode and a second pixel electrode; The insulating layer is an organic insulating layer. The source-drain layer covers part of the gate driving layer. The organic insulating layer covers the source-drain layer and another part of the gate driving layer. The touch signal line is formed on the other part of the gate driving layer. The first via includes a first sub-via and a second sub-via. The first pixel electrode is electrically connected to the common electrode layer through the first sub-via, and the first pixel electrode is electrically connected to the touch signal line through the second sub-via. The second pixel electrode is electrically connected to the drain electrode through a second via.

4. The array substrate according to claim 3, characterized in that, The common electrode layer includes a first common electrode and a second common electrode spaced apart. The first pixel electrode layer is electrically connected to the first common electrode through the first sub-via, and the second via is located between the first common electrode and the second common electrode.

5. The array substrate according to claim 3, characterized in that, The first pixel electrode located in the first via and the second pixel electrode located in the second via are both formed using the composite material layer.

6. The array substrate according to claim 3, characterized in that, The second via is formed using a single photomask process after the organic insulating layer and the passivation layer are formed.

7. The array substrate according to claim 1, characterized in that, The gate driving layer includes a gate insulating layer, a gate layer, and an interlayer dielectric layer stacked together. The gate layer includes a gate line, at least a portion of which is formed by stacked metal layers and organic conductive polymer material layers.

8. The array substrate according to any one of claims 1-7, characterized in that, The organic conductive polymer is PEDOT, and the transparent metal oxide is ITO.

9. A display panel, characterized in that, include: The array substrate as described in any one of claims 1-8, the opposing substrate disposed opposite to the array substrate, and the display medium layer located between the array substrate and the opposing substrate.

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