Signal Control Method, Device, Electronic Device and Storage Medium

Abstract

An embodiment of the present invention provides a signal control method, apparatus, electronic device, and storage medium. The method includes: configuring each interface in a test program according to the configuration method of each interface in a design under test, and specifying the signals included in the interface; obtaining a first configuration parameter of a first signal in a first interface of the test program; determining a mapping strategy corresponding to the first signal according to the first configuration parameter; determining a second signal in the design under test that matches the first signal based on the mapping strategy; and mapping the first signal and the second signal according to the first configuration parameter and a second configuration parameter of the second signal. By means of dynamic mapping, the signal mapping efficiency is improved, and thus the signal control efficiency is enhanced.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular, to a signal control method, apparatus, electronic device, and storage medium. Background Art

[0002] In the functional verification of hardware, a set of pins of the design under test needs to be defined, that is, an interface needs to be defined. For example, AXI4 and Tilelink can both be defined as a set of interfaces. The interface can be used to decouple the verification code from the design under test. When writing the verification code, the user does not directly operate the signals in the design under test (DUT), but operates the signals in the interface definition.

[0003] After that, a mapping operation is required to connect the signals in the interface definition to the signals in the DUT one by one. After the connection, operating the signals in the interface by the verification code is equivalent to operating the signals in the DUT. In this way, through the mapping operation, this verification code can operate any DUT with the same interface, rather than only being able to operate this one DUT.

[0004] However, the existing solutions for defining interfaces, such as VirtualInterface in SystemVerilog, require statically defining each signal and manually connecting the signals in the interface to the signals in the DUT one by one, increasing the complexity of interface definition and interface mapping, and thus reducing the efficiency of signal control. Summary of the Invention

[0005] Embodiments of the present invention provide a signal control method, apparatus, electronic device, and storage medium, which can solve the problem that the high complexity of interface mapping in related technologies leads to a reduction in signal control efficiency.

[0006] On the one hand, embodiments of the present invention disclose a signal control method, the method including:

[0007] Configuring each interface in the test program according to the configuration method of each interface in the design under test, and specifying the signals included in the interface;

[0008] Obtaining a first configuration parameter of a first signal in a first interface of the test program;

[0009] Determining a mapping strategy corresponding to the first signal according to the first configuration parameter;

[0010] Determining a second signal in the design under test that matches the first signal based on the mapping strategy;

[0011] Map the first signal and the second signal according to the first configuration parameter and the second configuration parameter of the second signal.

[0012] Optionally, determining the mapping strategy corresponding to the first signal according to the first configuration parameter includes:

[0013] When the first configuration parameter includes common prefix information, determine that the mapping strategy corresponding to the first signal is prefix mapping;

[0014] Determining the second signal matching the first signal in the design under test based on the mapping strategy includes:

[0015] Based on the prefix mapping, determine, as the second signal matching the first signal, the signal in the design under test whose configuration parameter is the same as the other information in the first configuration parameter except the prefix information.

[0016] Optionally, determining the mapping strategy corresponding to the first signal according to the first configuration parameter includes:

[0017] Determine a parameter matching rule according to the first configuration parameter;

[0018] Determine the mapping strategy corresponding to the first signal according to the parameter matching rule.

[0019] Optionally, the mapping strategy includes dictionary mapping. Determining the second signal matching the first signal in the design under test based on the mapping strategy includes:

[0020] Search for a second signal having a mapping relationship with the first signal in the mapping dictionary according to the first configuration parameter; wherein, the mapping dictionary is used to indicate the one-to-one mapping relationship between the signals in the test program and the signals in the design under test.

[0021] Optionally, configuring each interface in the test program according to the configuration method of each interface in the design under test includes:

[0022] When the first interface in the design under test is a multi-level interface, configure the signals in the interface at the corresponding level in the test program according to the configuration method of each level in the first interface;

[0023] When the first interface in the design under test includes at least two signals, determine the number of signals included in the first interface and the signal identifiers corresponding to the at least two signals, and configure the corresponding interface in the test program according to the number of signals and the signal identifiers.

[0024] On the other hand, an embodiment of the present invention discloses a signal control device, and the device includes:

[0025] A configuration module, configured to configure each interface in a test program according to the configuration mode of each interface in a design under test, and specify signals included in the interface.

[0026] An acquisition module, configured to acquire a first configuration parameter of a first signal in a first interface of the test program.

[0027] A determination module, configured to determine a mapping strategy corresponding to the first signal according to the first configuration parameter; and determine a second signal in the design under test that matches the first signal based on the mapping strategy.

[0028] A mapping module, configured to map the first signal and the second signal according to the first configuration parameter and a second configuration parameter of the second signal.

[0029] Optionally, the determination module includes:

[0030] A first determination sub-module, configured to determine that the mapping strategy corresponding to the first signal is a prefix mapping when the first configuration parameter includes common prefix information; and based on the prefix mapping, determine a signal in the design under test whose configuration parameter is the same as other information in the first configuration parameter except the prefix information as the second signal that matches the first signal.

[0031] Optionally, the determination module further includes:

[0032] A second determination sub-module, configured to determine a parameter matching rule according to the first configuration parameter; and determine the mapping strategy corresponding to the first signal according to the parameter matching rule.

[0033] Optionally, the determination module further includes:

[0034] A search module, configured to search for a second signal having a mapping relationship with the first signal from a mapping dictionary according to the first configuration parameter; wherein the mapping dictionary is used to indicate a one-to-one mapping relationship between signals in the test program and signals in the design under test.

[0035] Optionally, the configuration module further includes:

[0036] A first configuration sub-module, configured to, when the first interface in the design under test is a multi-level interface, configure signals in interfaces at corresponding levels in the test program according to the configuration mode of each level in the first interface.

[0037] A third determination sub-module, configured to determine the number of signals included in the first interface in the design under test and the signal identifiers corresponding to the at least two signals when the first interface in the design under test includes at least two signals;

[0038] A second configuration sub-module, configured to configure the corresponding interface in the test program according to the number of signals and the signal identifiers.

[0039] In another aspect, an embodiment of the present invention further discloses an electronic device, including a processor, a memory, a communication interface, and a communication bus. The processor, the memory, and the communication interface complete communication with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions cause the processor to execute the foregoing signal control method.

[0040] An embodiment of the present invention further discloses a readable storage medium. When the instructions in the readable storage medium are executed by the processor of the electronic device, the electronic device can execute the foregoing signal control method.

[0041] The embodiments of the present invention include the following advantages:

[0042] An embodiment of the present invention provides a signal control method, which configures each interface in the test program according to the configuration method of each interface in the design under test, specifies the signals included in the interface; obtains the first configuration parameter of the first signal in the first interface of the test program; determines the mapping strategy corresponding to the first signal according to the first configuration parameter; determines the second signal in the design under test that matches the first signal based on the mapping strategy; maps the first signal and the second signal according to the first configuration parameter and the second configuration parameter of the second signal. The embodiment of the present invention can achieve dynamic mapping through the first configuration parameter and the second configuration parameter of the second signal, improve the signal mapping efficiency, and further improve the signal control efficiency. Description of the Drawings

[0043] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required to be used in the description of the embodiments of the present invention. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0044] Figure 1 is a flowchart of the steps of an embodiment of a signal control method of the present invention;

[0045] Figure 2 is a structural block diagram of an embodiment of a signal control device of the present invention;

[0046] Figure 3It is a block diagram of an electronic device provided by an example of the present invention. Detailed implementation manners

[0047] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0048] The terms "first", "second", etc. in the specification and claims of the present invention are used to distinguish similar objects, rather than to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are usually of the same category, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally represents an "or" relationship between the associated objects before and after. The term "plurality" in the embodiments of the present invention refers to two or more, and other quantifiers are similar.

[0049] Method embodiments

[0050] Refer to Figure 1 , which shows a step flowchart of an embodiment of a signal control method of the present invention. The method may specifically include the following steps:

[0051] Step 101: Configure each interface in the test program according to the configuration method of each interface in the design to be tested, and specify the signals included in the interface;

[0052] Step 102: Obtain the first configuration parameter of the first signal in the first interface of the test program;

[0053] Step 103: Determine the mapping strategy corresponding to the first signal according to the first configuration parameter;

[0054] Step 104: Determine the second signal in the design to be tested that matches the first signal based on the mapping strategy;

[0055] Step 105: Map the first signal and the second signal according to the first configuration parameter and the second configuration parameter of the second signal.

[0056] Configure each interface in the test program according to the configuration method of each interface in the design under test, and specify the signals included in the interface.

[0057] Among them, DUT refers to the circuit design or implementation to be tested in prototype verification. Exemplarily, the design under test can be a Register Transfer Level (RTL) circuit or other hardware design.

[0058] Exemplarily, in hardware design or system modeling, Adder (adder) is a common functional module. When using Python to define the structure of the Adder interface, the Adder module can be represented by a class (Class), and its inputs, outputs, and functions can be defined using attributes or methods. For example, in the case of using Python to define the structure of the Adder interface, the Adder interface usually includes input signals, output signals, and functions. Among them, the input signals are two operands (such as a and b); the output signal is the addition result (such as sum); the function is to implement the addition operation.

[0059] The design under test is driven by a clock signal. The operation of the design under test can be paused by controlling the clock signal. When the input of the clock signal in the design under test is stopped, the design under test will also stop running.

[0060] The configuration method of each interface in the design under test refers to setting parameters, protocols, timing, electrical characteristics, etc. for the interfaces in the design under test to ensure that the interfaces can work correctly and meet the design requirements. Interface configuration is an important part of hardware function verification and system integration, directly affecting the performance and compatibility of the design.

[0061] Exemplarily, interface configuration refers to setting relevant parameters and attributes for the interfaces in the design under test so that they can communicate correctly with other modules or external devices. To ensure that the interfaces meet the design specifications and protocol requirements; optimize the interface performance (such as speed, bandwidth, latency); improve the compatibility and reliability of the system.

[0062] Exemplarily, the content of interface configuration can include protocol configuration, timing configuration, function configuration, address configuration, etc.

[0063] Among them, protocol configuration refers to setting the communication protocol used by the interface. For example: through I 2Configure the clock frequency (e.g., 100 kHz, 400 kHz) and device address for the C; configure the clock polarity (CPOL), clock phase (CPHA), and data bit width through SPI. Configure the baud rate (e.g., 9600, 115200), data bits, stop bits, and parity bits through UART. Configure the link speed (e.g., Gen1, Gen2, Gen3) and number of channels (x1, x4, x16) through PCIe.

[0064] Timing configuration refers to setting the timing parameters of the interface to ensure that signals are sampled and transmitted at the correct time; for example: Timing configuration includes setting the clock frequency of the interface, setup time, and hold time to ensure that data is stable at the clock edge.

[0065] Functional configuration refers to setting the functional mode and working method of the interface. For example: Configure the GPIO pins as input, output, or interrupt mode. Exemplarily, the functional mode may include DMA configuration and interrupt configuration. Among them, the DMA configuration may include data transfer modes (such as single transfer, cyclic transfer); the interrupt configuration may include interrupt trigger conditions (such as rising edge, falling edge, high level). The working method may include whether to delay the transmission. For example, in the case of selecting delayed transmission, the delay time of signal transmission can be set.

[0066] Address configuration refers to setting the address space or register mapping of the interface. For example: Configure the base address and address range of the peripheral through memory-mapped I / O, or configure the address of the I 2 C or SPI device through the device address.

[0067] The ways of interface configuration can include hardware configuration, software configuration, firmware configuration, etc.

[0068] Among them, hardware configuration includes jumpers or DIP switches, resistor configuration, etc. Jumpers or DIP switches set interface parameters through physical jumpers or DIP switches, and resistor configuration sets the electrical characteristics of the interface (such as pull-up resistors, pull-down resistors) through external resistors.

[0069] Software configuration includes register configuration, configuration files, command-line parameters, etc. Register configuration sets interface parameters by writing to registers, configuration files set interface parameters by reading configuration files, and command-line parameters dynamically configure the interface through command-line parameters.

[0070] Firmware configuration includes Bootloader, FPGA configuration. For example: Bootloader configures interface parameters when the system starts; FPGA configuration sets interface parameters through the configuration file of the FPGA (such as bitstream).

[0071] The test program is used to test the performance or correctness of the design under test to verify whether the design under test meets the expected functional and performance requirements.

[0072] As an example, the user can pre-write a test program according to the test requirements, and divide the test program into at least one subroutine according to the dependencies and execution order of the test cases or execution flows in the test program. Each subroutine can be defined as a different interface.

[0073] Exemplarily, the signals included in the interface may include data signals, address signals, control signals, etc.

[0074] Exemplarily, the data signal is used to transmit the actual data content between the various parts connected by the interface. In different application scenarios, the manifestation forms and meanings of the data signals are different. For example, in the interface between the memory and the Central Processing Unit (CPU) of a computer, the data signal may be a group of binary bits representing the data of a byte or word being processed; in a network interface, the data signal is composed of a series of data packets encapsulated according to a specific protocol, containing information such as source address, destination address, payload, etc.

[0075] Exemplarily, the address signal is mainly used to specify the storage location of the data or the target device. In a system with storage functions, the address signal helps to determine the specific location where the data should be read or written. For example, in the memory interface of a computer, the address signal is used to select a specific storage unit in the memory; in the hard disk controller interface, the address signal can be used to locate a certain sector on the hard disk.

[0076] Exemplarily, the control signal is used to coordinate and control the operation process and timing relationship between the various parts of the interface. The control signal can indicate the data transfer direction (read or write), start or stop an operation, indicate whether the device is ready for data exchange, etc. For example, in a SPI (Serial Peripheral Interface) communication interface, there is a chip select signal (CS) used to select a specific slave device; read and write signals (such as MOSI and MISO respectively representing master out slave in and master in slave out, and the corresponding clock signal SCLK) are used to control the data flow direction and transfer rhythm.

[0077] The signal definitions and specifications in the interface are the key to ensuring correct and stable communication between different components. Whether it is the connection between various chips inside a computer or the docking between different electronic devices (such as a mobile phone and a charger, a computer and a printer), it is necessary to follow a unified signal standard and protocol to ensure the accurate transmission of information and the normal operation of the system.

[0078] Obtain the first configuration parameter of the first signal in the first interface of the test program.

[0079] Among them, the first interface can be any interface in each subroutine of the test program.

[0080] The first signal in the first interface can be: Data Signals, Clock Signal, Control Signals, Status Signals, SPI (Serial Peripheral Interface), I 2 C (Inter-Integrated Circuit), UART (Universal Asynchronous Receiver / Transmitter), USB (Universal Serial Bus), PCIe (Peripheral Component Interconnect Express), Ethernet, HDMI (High-Definition Multimedia Interface), GPIO (General Purpose Input / Output), etc.

[0081] Among them, the data signal is used to transmit actual data information. For example: Parallel interface: D0, D1, D2,..., Dn (data bus). Serial interface: TX (transmit data line), RX (receive data line).

[0082] The clock signal is used to provide a synchronous clock for synchronizing data transmission. For example: SPI: SCLK (serial clock); I2C: SCL (serial clock line); PCIe: REFCLK (reference clock).

[0083] The control signal is used to control the start, end, or direction of data transmission. For example: SPI: SS (chip select signal); I2C: START (start condition), STOP (stop condition); UART: RTS (request to send), CTS (clear to send).

[0084] The status signal is used to indicate the status of the interface or device. For example: GPIO: READY (ready signal); USB: VBUS (power status signal).

[0085] In the SPI interface, SCLK refers to the serial clock, MOSI refers to the master device output and slave device input, MISO refers to the master device input and slave device output, and SS refers to the chip select signal (active low).

[0086] I 2 In the I²C interface, SCL refers to the serial clock line; SDA refers to the serial data line.

[0087] In the UART interface, TX refers to the transmit data line; RX refers to the receive data line; RTS refers to Request to Send; CTS refers to Clear to Send.

[0088] In the USB interface, D+ refers to the positive data line, D- refers to the negative data line, VBUS refers to the power line, and GND refers to the ground line.

[0089] In the PCIe interface, REFCLK refers to the reference clock, TX+ / - refers to the transmit differential signal, RX+ / - refers to the receive differential signal, PERST# refers to the reset signal, and WAKE# refers to the wake-up signal.

[0090] In the Ethernet interface, TX+ / - refers to the transmit differential signal; RX+ / - refers to the receive differential signal; MDI / MDIX refers to the auto crossover detection signal.

[0091] In the HDMI interface, TMDS Data refers to the video and audio data signal, TMDS Clock refers to the clock signal; CEC refers to the Consumer Electronics Control signal; HPD refers to the Hot Plug Detection signal.

[0092] In the GPIO interface, GPIOx refers to the general-purpose input / output pin; DIR refers to the direction control signal (input / output); PULLUP / PULLDOWN refers to the pull-up / pull-down resistor control signal.

[0093] The types and quantities of signals included in the interface depend on the type and protocol of the interface. Common signals include data signals, clock signals, control signals, status signals, and power / ground signals, etc.

[0094] The first configuration parameter can be used to define and control the parameters of signal behavior. These parameters ensure that the signal can correctly transmit data and meet the design requirements.

[0095] Exemplarily, the configuration parameter can be a protocol-related parameter, and the protocol-related parameters include: communication protocol, data format, frame format, etc.

[0096] Among them, the communication protocol is used to define the protocol used by the interface (such as SPI, I²C, UART, PCIe).

[0097] The data format includes the data bit width (such as 8 bits, 16 bits) and the data encoding method (such as NRZ, Manchester).

[0098] The frame format includes a start bit, a stop bit, and a parity bit (such as odd parity, even parity).

[0099] Exemplarily, the configuration parameters of the SPI interface signals may include protocol-related parameters, timing-related parameters, etc.

[0100] Among them, the protocol-related parameters include clock polarity (CPOL, 0 or 1); clock phase (CPHA, 0 or 1); data bit width (8 bits), etc.

[0101] The timing-related parameters include clock frequency (1 MHz); setup time (10 ns), hold time (10 ns).

[0102] The configuration parameters of the signals in the interface include protocol-related parameters, timing-related parameters, electrical characteristic parameters, function-related parameters, address-related parameters, error detection and correction parameters, etc. By reasonably configuring these parameters, the correct transmission and function implementation of the interface signals can be ensured.

[0103] Determine the mapping strategy corresponding to the first signal according to the first configuration parameter.

[0104] Among them, the mapping strategy corresponding to the first signal refers to the rules and methods for corresponding and matching the first signal with the second signal in the design under test, so as to ensure that the signal can be correctly transmitted and processed; meet the design requirements and performance requirements; improve the compatibility and reliability of the system.

[0105] The mapping strategy of the signal may include signal name mapping, signal type mapping, signal timing mapping, signal function mapping, etc.

[0106] Signal name mapping refers to corresponding the name of the first signal in the first interface of the test program with the name in the design under test. For example: the first signal in the first interface of the test program: TX (transmission data line); the second signal in the design under test: DIN (data input line), and the mapping strategy can be TX → DIN.

[0107] Signal type mapping refers to corresponding the type of the first signal in the first interface of the test program with the type in the design under test. For example: the first signal in the first interface of the test program: CLK (clock signal), the second signal in the design under test: SCLK (serial clock signal), mapping strategy: CLK → SCLK.

[0108] Signal timing mapping refers to corresponding the timing of the first signal in the first interface of the test program with the timing of the second signal in the design under test. For example: the first signal in the first interface of the test program: clock frequency = 100 MHz, the second signal in the design under test: clock frequency = 50 MHz, mapping strategy: use a frequency divider to convert 100 MHz to 50 MHz.

[0109] Signal function mapping refers to corresponding the function of the first signal in the first interface of the test program with the function of the second signal in the design under test. For example: the first signal in the first interface of the test program: RST (reset signal), the second signal in the design under test: RESET (reset signal), mapping strategy: RST → RESET.

[0110] Determine the second signal in the design under test that matches the first signal based on the mapping strategy.

[0111] Among them, the second signal can include: the second signal with the same signal name as the first signal, or the second signal with the same signal type as the first signal, or the second signal with the same signal timing as the first signal, or the second signal with the same signal function as the first signal, etc.

[0112] Map the first signal and the second signal according to the first configuration parameter and the second configuration parameter of the second signal.

[0113] Among them, the second configuration parameter of the second signal can include protocol-related parameters, timing-related parameters, electrical characteristic parameters, function-related parameters, address-related parameters, error detection and correction parameters, etc.

[0114] Exemplarily, the signal values of each interface in the test program can be used to drive the design under test. Through the interface of the design under test, the signal value can be transmitted into the design under test, thereby controlling the operation of the design under test.

[0115] After obtaining the signal values of the first interface in each subroutine, the second interface in the design under test that matches the first interface can be determined.

[0116] Among them, different mapping methods can be used to map the first interface and the second interface, and then the second interface in the design under test that matches the first interface can be determined.

[0117] Exemplarily, in the embodiments of the present invention, two sets of interfaces in the design under test may be obtained separately, such as AXI4 and Tilelink. That is, the interfaces of the design under test are determined, and the AXI4 interface needs to be driven through the interfaces in each subroutine. At this time, a virtual AXI4 interface needs to be defined to enable the verification code (in each interface of each subroutine) to drive this virtual AXI4 interface.

[0118] Exemplarily, the process of matching the first interface with the second interface of the design under test may include: obtaining the name of the first interface in the first subroutine and capturing the name of the design under test at the same time. When the name of the design under test only has a common prefix more than the name of the first interface in the first subroutine, prefix mapping may be used to match the first interface with the second interface of the design under test.

[0119] In the embodiments of the present invention, according to the configuration methods of the interfaces in the design under test, the interfaces in the test program are configured to specify the signals included in the interfaces; obtain the first configuration parameter of the first signal in the first interface of the test program; determine the mapping strategy corresponding to the first signal according to the first configuration parameter; determine the second signal in the design under test that matches the first signal based on the mapping strategy; map the first signal and the second signal according to the first configuration parameter and the second configuration parameter of the second signal. In the embodiments of the present invention, dynamic mapping can be achieved through the first configuration parameter and the second configuration parameter of the second signal, improving the signal mapping efficiency and further enhancing the signal control efficiency.

[0120] In an alternative embodiment of the present invention, the step of determining the mapping strategy corresponding to the first signal according to the first configuration parameter may specifically include the following steps:

[0121] Step 1031: When the first configuration parameter contains common prefix information, determine that the mapping strategy corresponding to the first signal is prefix mapping.

[0122] Exemplarily, when at least one signal is io_a, io_b, io_cin, io_sum, io_cout, the common prefix information may be determined as io_, or when at least one signal is inout_a, inout_b, inout_cin, inout_sum, inout_cout, the common prefix information may be determined as inout_.

[0123] In the case where at least one of the signals is io_a, io_b, io_cin, io_sum, io_cout, by extracting io_a, io_b, io_cin, io_sum, io_cout, the common prefix information of the signals io_a, io_b, io_cin, io_sum, io_cout can be determined as io_. At this time, the prefix mapping can be used to map the first signal.

[0124] In an alternative embodiment of the present invention, the determining the second signal matching the first signal in the design under test based on the mapping strategy may specifically include the following steps:

[0125] Step 1041: Based on the prefix mapping, determine the signal in the design under test whose configuration parameters are the same as those of the first configuration parameter except for the prefix information as the second signal matching the first signal.

[0126] Exemplarily, use the prefix io_ as the mapping method to map to the DUT. When the DUT has one more common prefix than the name in the first interface of the test program, such as io_a, io_b, io_cin, io_sum, io_cout, in this case, the prefix io_ can be specified as the mapping method to map to the DUT, that is, when the common prefix can be extracted, directly use io_ as the mapping method, so that a is connected to io_a, b is connected to io_b, cin is connected to io_cin, sum is connected to io_sum, and cout is connected to io_cout. When the prefix of the new design under test is no longer io_, but inout_a, inout_b, inout_cin, inout_sum, inout_cout, in order to be able to connect, use inout_ for mapping. That is, by identifying this prefix and then mapping the subsequent identical ones.

[0127] In an alternative embodiment of the present invention, the determining the mapping strategy corresponding to the first signal according to the first configuration parameter may specifically include the following steps:

[0128] Step 1032: Determine the parameter matching rule according to the first configuration parameter;

[0129] Step 1033: Determine the mapping strategy corresponding to the first signal according to the parameter matching rule.

[0130] Determine the parameter matching rule according to the first configuration parameter.

[0131] Among them, the parameter matching rule can be a matching rule described by any expression, for example, a matching rule described by a regular expression, etc.

[0132] Exemplarily, the parameter matching rule refers to the specific rules and methods for corresponding and matching the source signal with the target signal, including signal name matching, signal type matching, signal electrical characteristic matching, signal timing matching, signal function matching, etc. Through reasonable signal matching rules, it can be ensured that the signal can be correctly transmitted and processed to meet the design requirements and performance requirements.

[0133] Determine the mapping strategy corresponding to the first signal according to the parameter matching rule.

[0134] Exemplarily, in the case where the name of the first signal in the first interface of the test program is described by a regular expression, the mapping strategy corresponding to the first signal can be determined as a regular expression mapping.

[0135] Exemplarily, the process of mapping the first interface to the second interface of the design under test may include: obtaining the name of the first interface in the first subroutine, and simultaneously capturing the name of the design under test. In the case where the name of the design under test can be represented by a regular expression, then regular expression mapping can be used to map the first interface to the second interface of the design under test.

[0136] Exemplarily, when the signal name in the DUT can be mapped by a regular expression and the captured name can match the name in the interface, regular expression mapping can be used. For example, in the above case, the regular expression r“io_(.*)” can be used for matching, and the characters captured by the parentheses just match the name in the interface. If there are multiple capture groups, then they are concatenated into a string in order and then matched. Among them, regular expression mapping means writing a matching rule and then mapping the first interface in the first subroutine to the second interface of the design under test. The “io_(.*)” matching mode is to capture the (signal) after io_.

[0137] In an alternative embodiment of the present invention, the mapping strategy includes dictionary mapping. Based on the mapping strategy, determine the second signal in the design under test that matches the first signal, which may specifically include the following steps:

[0138] Step 1042: Search for the second signal that has a mapping relationship with the first signal in the mapping dictionary according to the first configuration parameter; wherein, the mapping dictionary is used to indicate the one-to-one mapping relationship between the signals in the test program and the signals in the design under test.

[0139] In the case where the mapping strategy is dictionary mapping, the second signal having a mapping relationship with the first signal can be found from the mapping dictionary according to the first configuration parameter. For example: {"a": "io_a", "b": "io_b", "cin": "io_cin", "cout": "io_cout"}.

[0140] The process of mapping the first interface to the second interface of the design under test may include: obtaining the name of the first interface in the first subroutine, and at the same time capturing the name of the design under test, and establishing a one-to-one mapping relationship by passing in a dictionary, so as to match the first interface with the second interface of the design under test.

[0141] Exemplarily, a one-to-one mapping relationship is established by passing in a dictionary. This is consistent with the traditional connection method (however, mapping can be achieved through multi-level nesting, where the dictionary contains prefix mapping, and the prefix mapping includes regular expression mapping), and the mapping is completed through the dictionary in the first interface of the first subroutine.

[0142] After determining the second interface in the design under test that matches the first interface, the signal value can also be input to the second interface, and the design under test is driven to continue running to the next clock cycle edge.

[0143] Among them, through the ports, values can be assigned to the design under test, that is, each subroutine transfers the data required for the operation of the design under test to the design under test, and then the design under test can be controlled through each interface in each subroutine.

[0144] In an alternative embodiment of the present invention, configuring each interface in the test program according to the configuration method of each interface in the design under test may specifically include the following steps:

[0145] Step 1011, in the case where the first interface in the design under test is a multi-level interface, configure the signals in the interface at the corresponding level in the test program according to the configuration method of each level in the first interface;

[0146] Step 1012, in the case where the first interface in the design under test includes at least two signals, determine the number of signals included in the first interface and the signal identifiers corresponding to the at least two signals, and configure the corresponding interface in the test program according to the number of signals and the signal identifiers.

[0147] In the case where the first interface in the design under test is a multi-level interface, configure the signals in the interface at the corresponding level in the test program according to the configuration method of each level in the first interface.

[0148] Among them, the multi-level interface refers to an interface that defines an interface as a sub-interface in the current interface, forming a multi-level interface with interface nesting.

[0149] Exemplarily, a multi - level interface is a design method that divides an interface into multiple levels, with each level responsible for different functions or levels of abstraction.

[0150] The configuration method for each level can be software configuration, etc. Software configuration includes: register configuration, configuration file, command - line parameters, etc. Register configuration is to set interface parameters by writing to registers, the configuration file is to set interface parameters by reading the configuration file, and command - line parameters are to dynamically configure the interface through command - line parameters.

[0151] When the first interface in the design under test contains at least two signals, determine the number of signals contained in the first interface and the signal identifiers corresponding to at least two signals. According to the number of signals and signal identifiers, configure the corresponding interface in the test program.

[0152] Among them, the number of signals contained in the first interface can be any number. For example, it is defined that the first interface contains 5 signals, or 10 signals, etc.

[0153] The signal identifiers corresponding to at least two signals refer to the names, numbers, or symbols used to uniquely identify and distinguish different signals in hardware design, system integration, or communication protocols. Signal identifiers are an important basis for signal mapping, configuration, and management, ensuring that signals can be correctly identified and processed.

[0154] Exemplarily, SPI interface signal identifiers include: SCLK (Serial Clock), MOSI (Master Out Slave In), MISO (Master In Slave Out), SS (Slave Select).

[0155] Exemplarily, UART interface signal identifiers include: TX (Transmit Data Line), RX (Receive Data Line), RTS (Request to Send), CTS (Clear to Send).

[0156] In the functional verification of hardware, a set of pins of the design under test needs to be defined, hereinafter referred to as an interface. For example, AXI4 and Tilelink can both be defined as a set of interfaces. The interface can be used to decouple the verification code from the design under test. When the user writes the verification code, they do not directly operate the signals in the DUT, but operate the signals in the interface definition.

[0157] After that, a mapping operation is required to connect the signals in the interface definition to the signals in the DUT one - to - one. After the connection, when the verification code operates on the signals in the interface, it is equivalent to operating on the signals in the DUT. In this way, through the mapping operation, this verification code can operate on any DUT with the same interface, rather than only being able to operate on this one DUT.

[0158] However, existing solutions for defining interfaces, such as VirtualInterface in SystemVerilog, require statically defining each signal and manually connecting the signals in the interface to the signals in the DUT one by one. As a result, the definition and connection of relatively complex interfaces become rather complicated.

[0159] The present invention utilizes the feature in modern software programming languages that can dynamically resolve variable names, and designs a new interface definition method and a method for mapping to the DUT, making this process more flexible and efficient.

[0160] Use Bundle to complete the definition of a type of interface. For example, use Python to define the structure of the Adder interface, and only the specific signals included in the interface need to be specified during definition.

[0161] Exemplarily, it is defined through the following code:

[0162] class AdderBundle(Bundle):

[0163] a, b, cin, sum, cout = Signals(5)

[0164] In the embodiments of the present invention, in the case of mapping to the DUT, there are three mapping methods that can quickly implement the mapping process.

[0165] Prefix mapping means that when the DUT only has a common prefix more than the name in the definition, such as io_a, io_b, io_cin, io_sum, io_cout. In this case, the prefix io_ can be specified as the mapping method to map to the DUT, without the need for multiple manual mappings.

[0166] Regular expression mapping means that when the signal names in the DUT can be matched by a regular expression and the captured names can match the names in the interface, regular expression mapping can be used. For example: use the regular expression r"io_(.*)" for matching, and the characters captured by the parentheses just match the names in the interface. If there are multiple capture groups, they can be chained into a string in order and then matched.

[0167] Dictionary mapping means establishing a one-to-one mapping relationship by passing in a dictionary. This is consistent with the traditional connection method, but the mapping is completed through the dictionary in the software language. For example, {"a": "io_a", "b": "io_b", "cin": "io_cin", "cout": "io_cout"}.

[0168] Among them, the mapping method is specified when the Bundle is instantiated, and the mapping with the DUT is completed through the bind method in the Bundle.

[0169] The definition of a multi-level interface means that in addition to defining signals in a Bundle, another Bundle can be defined as a sub-Bundle in the current Bundle and given a name.

[0170] When the sub-Bundle is instantiated in the current Bundle, its mapping method also needs to be specified. After the effect of the current mapping is generated, the mapped name is passed to the sub-Bundle for matching.

[0171] Exemplarily, the definition of a multi-level interface is carried out through the following code:

[0172] class AXI4Bundle(Bundle):

[0173] aw = AXI4BundleAW.from_regex(r"aw_(?:(valid|ready)|bits_(.*))")

[0174] w = AXI4BundleW.from_regex(r"w_(?:(valid|ready)|bits_(.*))")

[0175] b = AXI4BundleB.from_regex(r"b_(?:(valid|ready)|bits_(.*))")

[0176] ar = AXI4BundleAR.from_regex(r"ar_(?:(valid|ready)|bits_(.*))")

[0177] r = RBundle.from_regex(r"r_(?:(valid|ready)|bits_(.*))")

[0178] Assume that the AXI4Bundle uses the prefix mapping method "io_", then the sub-Bundles in it will remove the io_ prefix and then use the regular expression method to map the sub-Bundles. That is to say, after the prefix mapping, the prefix will be removed, after the regular expression mapping, it will be converted to the captured name, and after the dictionary mapping, it will be converted to the name specified by the dictionary, and then the mapping of the sub-Bundle will be continued.

[0179] For some more complex interfaces, especially in the interface names generated by Chisel, there are often a group of signals or a group of interfaces differentiated by numbers, such as: signal_1, signal_2, ... signal_10. At this time, if 10 signals are defined, the definition will become complicated. Signal arrays are provided in Bundle to complete such definitions, and there are corresponding Bundle arrays.

[0180] These two arrays are defined by SignalList and BundleList respectively, and both need to be defined in a Bundle. When accessing, both of these structures can be accessed as arrays.

[0181] Exemplarily, the definition of the array structure is as follows through the following code:

[0182] class MyBundle(Bundle):

[0183] sl = SignalList("signal_ #", 10)

[0184] bl = BundleList(SubBundle, "subbundle_ #", 10)

[0185] In SignalList, a name containing a number needs to be specified, where the number is identified by "#", and the quantity n is specified. The Bundle will automatically generate the specified number of signals and replace the matching name with one in 0-(n-1). A custom conversion function from numbers to strings can also be passed in to define the conversion method from numbers to strings.

[0186] In BundleList, the definition of the sub-Bundle needs to be specified. This method will define a list of Bundles, and the mapping method of each Bundle is set to prefix matching, using the string after replacing the number as the prefix. Similarly, when defining, a prefix name containing a number and the quantity need to be specified.

[0187] Through the above definition method, the original method of statically defining all signals is overcome, and flexible hierarchical definition and array support are provided; the mapping method provides three dynamic mapping methods, overcoming the original one-to-one signal connection and improving the mapping efficiency.

[0188] Bundle generally refers to combining multiple signals or ports into a composite structure to facilitate modularization and reuse. For example, the Bundle class in Chisel allows users to define their own signal sets, and then pass and process these signals as a whole, improving the readability and maintainability of the code.

[0189] A Bundle refers to a structured definition of a set of signals.

[0190] In the fields of hardware design and programming (especially in the Chisel-based hardware construction language), a Bundle is a mechanism that combines multiple related signals (or ports) into a structured data type. It is similar to a struct in software programming, used to define a set of logically related signals, facilitating modular design and code reuse.

[0191] A Bundle can encapsulate multiple signals (such as data lines, control signals, status signals, etc.) into a whole.

[0192] Example: Define an interface that includes data, address, and valid flag.

[0193] Exemplarily, signals in the DUT can be passed in as a list, and different ones can be passed in each time. The test program can dynamically parse the passed-in signals, and determine a mapping strategy for mapping at least one signal in the interface of the design under test to the second interface of the test program according to the parsed signals.

[0194] In summary, the embodiments of the present invention provide a signal control method. According to the configuration methods of each interface in the design under test, each interface in the test program is configured to specify the signals included in the interface; obtain the first configuration parameter of the first signal in the first interface of the test program; determine the mapping strategy corresponding to the first signal according to the first configuration parameter; determine the second signal in the design under test that matches the first signal based on the mapping strategy; map the first signal and the second signal according to the first configuration parameter and the second configuration parameter of the second signal. The embodiments of the present invention can achieve dynamic mapping through the first configuration parameter and the second configuration parameter of the second signal, improve the signal mapping efficiency, and further improve the signal control efficiency.

[0195] It should be noted that for the method embodiments, for the sake of simple description, they are all expressed as a series of action combinations. However, those skilled in the art should know that the embodiments of the present invention are not limited by the described action sequence, because according to the embodiments of the present invention, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily essential for the embodiments of the present invention.

[0196] Device embodiments

[0197] Referring to Figure 2 , a structural block diagram of a signal control device of the present invention is shown. The device may specifically include:

[0198] A configuration module 401, configured to configure each interface in a test program according to the configuration method of each interface in a design under test, and specify the signals included in the interface.

[0199] An acquisition module 402, configured to acquire a first configuration parameter of a first signal in a first interface of the test program.

[0200] A determination module 403, configured to determine a mapping strategy corresponding to the first signal according to the first configuration parameter; and determine a second signal in the design under test that matches the first signal based on the mapping strategy.

[0201] A mapping module 404, configured to map the first signal and the second signal according to the first configuration parameter and a second configuration parameter of the second signal.

[0202] Optionally, the determination module includes:

[0203] A first determination sub-module, configured to determine that the mapping strategy corresponding to the first signal is a prefix mapping when the first configuration parameter includes common prefix information; and based on the prefix mapping, determine a signal in the design under test whose configuration parameter is the same as other information in the first configuration parameter except the prefix information as the second signal that matches the first signal.

[0204] Optionally, the determination module further includes:

[0205] A second determination sub-module, configured to determine a parameter matching rule according to the first configuration parameter; and determine the mapping strategy corresponding to the first signal according to the parameter matching rule.

[0206] Optionally, the determination module further includes:

[0207] A search module, configured to search for a second signal that has a mapping relationship with the first signal from a mapping dictionary according to the first configuration parameter; wherein the mapping dictionary is used to indicate a one-to-one mapping relationship between the signals in the test program and the signals in the design under test.

[0208] Optionally, the configuration module further includes:

[0209] A first configuration sub-module, configured to, when a first interface in the design under test is a multi-level interface, configure the signals in the interfaces at corresponding levels in the test program according to the configuration method of each level in the first interface.

[0210] A third determination sub-module, configured to determine the number of signals included in the first interface in the design under test and the signal identifiers corresponding to the at least two signals when the first interface in the design under test includes at least two signals;

[0211] A second configuration sub-module, configured to configure the corresponding interface in the test program according to the number of signals and the signal identifiers.

[0212] In summary, the embodiment of the present invention provides a signal control device. During the process of signal control, each interface in the test program is configured according to the configuration method of each interface in the design under test to specify the signals included in the interface; the first configuration parameter of the first signal in the first interface of the test program is obtained; the mapping strategy corresponding to the first signal is determined according to the first configuration parameter; the second signal matching the first signal in the design under test is determined based on the mapping strategy; the first signal is mapped to the second signal according to the first configuration parameter and the second configuration parameter of the second signal. The embodiment of the present invention can achieve dynamic mapping through the first configuration parameter and the second configuration parameter of the second signal, improve the signal mapping efficiency, and further improve the signal control efficiency.

[0213] For the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple. For the relevant parts, refer to the partial description of the method embodiment.

[0214] Each embodiment in this specification is described in a progressive manner. The key point of each embodiment is to illustrate the differences from other embodiments. The same or similar parts among the embodiments can be referred to each other.

[0215] Regarding the processor in the above embodiments, the specific manner in which each module performs operations has been described in detail in the embodiments related to the method, and will not be elaborated here.

[0216] Refer to Figure 3 , which is a structural block diagram of an electronic device for data transmission in a network on a chip provided by an embodiment of the present invention. As Figure 3 shown, the electronic device includes: a processor, a memory, a communication interface, and a communication bus. The processor, the memory, and the communication interface complete communication with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions cause the processor to execute the signal control method of the foregoing embodiment.

[0217] The processor may be a CPU, a general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable devices, transistor logic devices, hardware components, or any combination thereof. The processor may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0218] The communication bus may include a path for transmitting information between the memory and the communication interface. The communication bus may be a peripheral component interconnect (PCI) bus, an extended industry standard architecture (EISA) bus, or the like. The communication bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 3 only one line is shown in the figure, but it does not mean that there is only one bus or one type of bus.

[0219] The memory may be a read only memory (ROM) or other type of static storage device that can store static information and instructions, a random access memory (RAM), or other type of dynamic storage device that can store information and instructions. It may also be an electrically erasable programmable read only memory (EEPROM), a compact disc read only memory (CD-ROM), magnetic tape, floppy disk, and optical data storage device, etc.

[0220] The embodiments of the present invention also provide a non-transitory computer-readable storage medium. When the instructions in the storage medium are executed by the processor of an electronic device (server or terminal), the processor is enabled to execute Figure 1 the signal control method shown.

[0221] Each embodiment in this specification is described in a progressive manner. The key point of each embodiment is to illustrate the differences from other embodiments. The same or similar parts among the embodiments may be referred to each other.

[0222] Those skilled in the art should understand that the embodiments of the present invention can be provided as methods, devices, or computer program products. Therefore, the embodiments of the present invention can take the form of entirely hardware embodiments, entirely software embodiments, or embodiments combining software and hardware aspects. Moreover, the embodiments of the present invention can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0223] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each flow and / or block in the flowchart and / or block diagram can be implemented by computer program instructions, and the combination of the flows and / or blocks in the flowchart and / or block diagram can also be implemented. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal devices to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal devices generate a device for implementing the functions specified in one Figure 1 flow or multiple flows and / or blocks Figure 1 or multiple blocks.

[0224] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing terminal device to work in a predictive manner, so that the instructions stored in the computer-readable memory generate a manufactured article including an instruction device, and the instruction device implements the functions specified in one Figure 1 flow or multiple flows and / or blocks Figure 1 or multiple blocks.

[0225] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device, so that a series of operation steps are executed on the computer or other programmable terminal device to generate a computer-implemented process, and thus the instructions executed on the computer or other programmable terminal device provide steps for implementing the functions specified in one Figure 1 flow or multiple flows and / or blocks Figure 1 or multiple blocks.

[0226] Although the preferred embodiments of the embodiments of the present invention have been described, those skilled in the art can make additional changes and modifications to these embodiments once they know the basic creative concepts. Therefore, the appended claims are intended to be construed as including the preferred embodiments and all changes and modifications falling within the scope of the embodiments of the present invention.

[0227] Finally, it should also be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or terminal device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or elements inherent to such process, method, article or terminal device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or terminal device comprising said element.

[0228] The above has introduced in detail a signal control method, device, electronic device and storage medium provided by the present invention. Specific examples are used in this text to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. A signal control method, characterized in that, The method includes: Configuring each interface in the test program according to the configuration mode of each interface in the design under test, and specifying the signals included in the interface; Obtaining a first configuration parameter of a first signal in a first interface of the test program; Determining a mapping strategy corresponding to the first signal according to the first configuration parameter; Determining a second signal in the design under test that matches the first signal based on the mapping strategy; Mapping the first signal and the second signal according to the first configuration parameter and a second configuration parameter of the second signal; Among them, determining the mapping strategy corresponding to the first signal according to the first configuration parameter includes: When the first configuration parameter includes common prefix information, determining that the mapping strategy corresponding to the first signal is prefix mapping; The determining, based on the mapping strategy, a second signal in the design under test that matches the first signal includes: Based on the prefix mapping, determining, as the second signal that matches the first signal, a signal in the design under test whose configuration parameter is the same as other information in the first configuration parameter except the prefix information; Among them, determining the mapping strategy corresponding to the first signal according to the first configuration parameter includes: Determining a parameter matching rule according to the first configuration parameter; Determining the mapping strategy corresponding to the first signal according to the parameter matching rule.

2. The method according to claim 1, wherein The mapping strategy includes dictionary mapping. The determining, based on the mapping strategy, a second signal in the design under test that matches the first signal includes: Looking up, according to the first configuration parameter, a second signal that has a mapping relationship with the first signal in a mapping dictionary; wherein, the mapping dictionary is used to indicate a one-to-one mapping relationship between the signals in the test program and the signals in the design under test.

3. The method according to claim 1, wherein The configuring each interface in the test program according to the configuration mode of each interface in the design under test includes: When a first interface in the design under test is a multi-level interface, configuring the signals in the interface at the corresponding level in the test program according to the configuration mode of each level in the first interface; When the first interface in the design under test includes at least two signals, determining the number of signals included in the first interface and the signal identifiers corresponding to the at least two signals, and configuring the corresponding interface in the test program according to the number of signals and the signal identifiers.

4. A signal control device, characterized in that, The device includes: A configuration module, configured to configure each interface in the test program according to the configuration mode of each interface in the design under test, and specify the signals included in the interface; An obtaining module, configured to obtain a first configuration parameter of a first signal in a first interface of the test program; A determining module, configured to determine a mapping strategy corresponding to the first signal according to the first configuration parameter; and determine a second signal in the design under test that matches the first signal based on the mapping strategy; A mapping module, configured to map the first signal and the second signal according to the first configuration parameter and a second configuration parameter of the second signal; The first determination sub-module is configured to, when the common prefix information is included in the first configuration parameter, determine that the mapping strategy corresponding to the first signal is prefix mapping; based on the prefix mapping, determine the signal in the design under test whose configuration parameter is the same as the other information in the first configuration parameter except the prefix information as the second signal that matches the first signal. The second determination sub-module is configured to determine a parameter matching rule according to the first configuration parameter; and determine the mapping strategy corresponding to the first signal according to the parameter matching rule.

5. An electronic device, characterized in that, The electronic device includes a processor, a memory, a communication interface, and a communication bus. The processor, the memory, and the communication interface complete communication with each other through the communication bus. The memory is used to store executable instructions, and the executable instructions cause the processor to execute the signal control method according to any one of claims 1 to 3.

6. A readable storage medium, characterized in that, When the instructions in the readable storage medium are executed by the processor of the electronic device, the processor is enabled to execute the signal control method according to any one of claims 1 to 3.

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