Configurable MOCB hardware abstraction layer packaging design method

Abstract

The invention belongs to the technical field of software radio systems, and particularly relates to a configurable MOCB hardware abstraction layer packaging design method. The MOCB hardware comprises three types, namely a general purpose processor GPP, a digital signal processor DSP and a programmable logic gate array FPGA; each hardware can generate events to other hardware; each piece of hardware accesses the FPGA by generating an address access signal, wherein the address access signal is a signal which contains a specified memory address and an access mode and is used for describing operation on address pointing memory content; each hardware can access the shared memory of the DSP and the GPP; each piece of hardware is provided with an MOCB layer and a bus adaptation layer; the MOCB layer is used for logic mapping management and interaction time sequence control; and the bus adaptation layer is used for realizing a read-write interface of a memory and receiving and sending of events, and providing a local operable address for a bus with a local mapping requirement.

Description

Technical Field

[0001] The invention belongs to the technical field of software radio systems, and in particular relates to a configurable MOCB hardware abstraction layer encapsulation design method. Background Art

[0002] In the software radio system, the modem hardware abstraction layer (MHAL) and the MHAL on chip bus (MOCB) are used to provide the communication interface between heterogeneous computing units. MOCB is a hardware abstraction layer based on shared memory, mapping the target memory through logical ports. Users operate the target memory through logical ports. MOCB supports communication between general purpose processors (GPP), digital signal processors (DSP) and field programmable gate arrays (FPGA), providing a consistent interface for cross-platform waveforms.

[0003] The use of standard MOCB requires users to control timing and negotiate to achieve reliable communication. It is flexible but has higher requirements for users. The use of MOCB requires intrusive programming changes based on the bus, which puts a burden on MOCB designers to maintain program stability and maintenance. Summary of the invention

[0004] The purpose of the present invention is to provide a configurable MOCB hardware abstraction layer encapsulation design method to reduce the difficulty of users using MOCB and reduce the maintenance burden of MOCB designers.

[0005] The technical solution of the present invention:

[0006] A configurable MOCB hardware abstraction layer encapsulation design method, MOCB hardware includes three categories, namely: general purpose processor GPP, digital signal processor DSP and programmable logic gate array FPGA;

[0007] Each hardware can generate events to other hardware;

[0008] Each hardware accesses the FPGA by generating an address access signal. The address access signal refers to a signal containing a specified memory address and an access method used to describe the operation on the memory content pointed to by the address;

[0009] Each hardware can access the shared memory of DSP and GPP;

[0010] Each hardware has a MOCB layer and a bus adaptation layer;

[0011] The MOCB layer is used for logic mapping management and interactive timing control;

[0012] The bus adaptation layer is used to implement the memory read and write interface and the sending and receiving of events, and to provide local operable addresses for buses that require local mapping.

[0013] Furthermore, the bus adaptation layer includes the following operations:

[0014] Write memory: write data of specified length to the specified address of the specified bus node; MOCB obtains the address to be written to the bus node by calculating the base address and offset address, and writes through this interface;

[0015] Read memory: read data of specified length from the specified address of the specified bus node;

[0016] Event notification: Notify the specified bus node of the specified event number; through the event number notification, the MOCB of the target node knows the logical port where the data is written and obtains the data from the logical port;

[0017] Registered event reception callback: When this bus node receives an event, the registered callback should be called; used to notify the MOCB that the logical port is written to obtain data;

[0018] Mapping address acquisition: Map the address to a locally operable address.

[0019] Furthermore, logical mapping management includes:

[0020] i. Mapping of logical ports, querying physical ports, event numbers, offset addresses, block numbers and block sizes through logical ports;

[0021] ii. Mapping of physical ports, querying the bus number, bus node, base address and characteristics of the corresponding bus through the physical port;

[0022] iii. The bus number is associated with the bus adaptation layer, and the bus adaptation layer is obtained through the bus number to implement operations on a specific bus.

[0023] Further, the logical mapping management uses the following data format: the length is 16*N+20 bytes;

[0024] The first 15 bits of the first two bytes are the logical port, and the last bit is the flag bit to be released;

[0025] The 3rd and 4th bytes are the logical mapping table control type;

[0026] Bytes 5-8 are the length of the data packet;

[0027] Bytes 9-16 are reserved;

[0028] The 17th and 18th bytes are the mapping table update mode flags;

[0029] 19th and 20th are the number N of logical port mappings in the mapping table;

[0030] Each subsequent 16 bytes form a group, with a total of N groups, and each group represents a mapping relationship.

[0031] Furthermore, when registering the bus number, the event receiving callback operation should be registered through the bus adaptation layer. The registered event receiving callback searches for the associated semaphore according to the event number and triggers the semaphore.

[0032] Furthermore, the interactive timing control adopts the following data format: the length is 16 + payload length bytes;

[0033] The first 15 bits of the first two bytes are the logical port, and the last bit is the flag bit to be released;

[0034] The 3rd and 4th bytes are reserved;

[0035] Bytes 5-8 are the length of the data packet;

[0036] Bytes 9-16 are reserved;

[0037] The next part is the payload, which is the data that needs to be written or read.

[0038] Furthermore, in interactive timing control, data transmission includes the following processes:

[0039] Step a: Obtain the target base address, bus node, bus adaptation layer, offset address, event number, block number N and block size and characteristics according to the logical port;

[0040] Step b: If the feature is 0, it means that the logic port is located on the GPP / DSP, and the process goes to step c; if the feature is 1, it means that the logic port is located on the FPGA, and the process goes to step f;

[0041] Step c: If the hardware itself is GPP / DSP, go to step d, otherwise go to step e;

[0042] Step d: Calculate the address of the current target sending block number in combination with the target base address; write the payload to the target address + 16 of the bus node through the bus adaptation layer; write the data header to the target address + 0 of the bus node through the bus adaptation layer; send the target event number to the bus node through the bus adaptation layer; set the target sending block number to the next target sending block number, and if the number of blocks N is reached, return to the target sending block number 0;

[0043] Step e: Calculate the address of the current target sending block number in combination with the target base address; write the payload to the target address + 16 of the bus node through the bus adaptation layer. According to the characteristics of FPGA, the user writes the payload data to the MOCB layer in the form of streaming data, and the MOCB layer passes the data to the bus adaptation layer for writing; write the data header to the target address + 0 of the bus node through the bus adaptation layer; send the target event number to the bus node through the bus adaptation layer; the target sending block number is set to the next target sending block number. If the number of blocks N is reached, return to the target sending block number 0;

[0044] Step f: Calculate the address of the current target send block number in combination with the target base address; write the data header to the target address + 0 of the bus node through the bus adaptation layer; write the payload to the target address + 16 of the bus node through the bus adaptation layer; send the target event number to the bus node through the bus adaptation layer; set the target send block number to the next target send block number. If the number of blocks N is reached, return to the target send block number 0.

[0045] Furthermore, in interactive timing control, data reception includes the following processes:

[0046] If the hardware is FPGA, streaming data reception is adopted, and data is distributed according to the logical port of the data header and the input receiving logical port. If they are consistent, the data is passed to the matching module, otherwise the data is discarded. Data is read according to the following steps: Get the length of the data to be read according to the data header; Streaming data is received from the bus adaptation layer, and the length of the read data is calculated, and the data is passed to the specified module or discarded; When the length of the read data is greater than or equal to the length of the data to be read, it means that all the data has been read;

[0047] If the hardware is GPP / DSP, obtain the local operable address corresponding to the base address through the bus adaptation layer; calculate the address of the current target receiving block number; check the data block to be released field, if it is to be released, return the address and data length; otherwise, the target receiving block number + 1, if the number of blocks N is reached, return to the target receiving block number 0, if all target block numbers have not been checked, recalculate the address of the current target receiving block number and recheck the data block to be released field, if all target block numbers have been checked and none of them are to be released, then this reception is invalid.

[0048] Beneficial effects of the present invention:

[0049] 1) Encapsulate the mapping management of logical ports, physical ports and shared memory; determine the interaction sequence, encapsulate the communication process, implement a message-like interface, reduce user difficulty and improve user development efficiency;

[0050] 2) Design the MOCB bus adaptation layer to decouple the bus design from the MOCB design, forming a one-way dependency, reducing the maintenance burden, and improving the stability of the MOCB design. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 It is the system structure to which the present invention is directed, and describes the interaction capabilities between various components.

[0052] Figure 2 It is the overall design concept of the present invention, describing the functional position of each component of the present invention.

[0053] Figure 3 It is the overall design of logical mapping management and describes the content of logical mapping management.

[0054] Figure 4 It is a data block design that describes the format of the interactive data block.

[0055] Figure 5 It is the logical mapping table control format, which describes the control data format used to modify the logical mapping table.

[0056] Figure 6 It is the logical port query process, which describes how to query the required target information through the logical port. DETAILED DESCRIPTION

[0057] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0058] A configurable MOCB hardware abstraction layer encapsulation design method is used to reduce the difficulty of using MOCB for users and reduce the maintenance burden of MOCB designers.

[0059] The present invention mainly includes: interactive timing control, logic mapping management, bus adaptation layer design and the like.

[0060] 1. The typical system structure of this solution is as follows Figure 1 As shown:

[0061] 1.1GPP, DSP and FPGA can generate events to any device;

[0062] 1.2GPP, DSP and FPGA can access the shared memory of DSP and GPP;

[0063] 1.3 Access the FPGA by generating an address access signal. The address access signal refers to a signal containing a specified memory address, access mode (read, write), etc., which is used to describe the operation of the memory content pointed to by the address;

[0064] 1.4GPP, DSP and FPGA all have MOCB layer and bus adaptation layer;

[0065] 1.5MOCB layer is used for logic mapping management and interactive timing control.

[0066] 2. The overall design of this scheme is as follows Figure 2 As shown:

[0067] 2.1 During the sending process:

[0068] 2.1.1 Logical mapping management is responsible for converting the logical port input by the user into bus adaptation layer, bus node address, base address, ring buffer, event, offset address and other information;

[0069] 2.1.2 The bus adaptation layer is responsible for abstracting the bus write memory interface and event notification interface;

[0070] 2.1.3 Interactive Timing Control According to the determined process, the bus adaptation layer interface is called according to the information obtained by the logical mapping management, the data is written into the shared memory and event notification is performed.

[0071] 2.2 During the receiving process:

[0072] 2.2.1 Interactive timing control determines the design of reflecting data writing and writing location information through event numbers;

[0073] 2.2.2 The bus adaptation layer provides the ability to map addresses to locally operable addresses;

[0074] 2.2.3 Logical Mapping Management provides the ability to obtain information such as bus adaptation layer, base address, offset address, and ring buffer by event number.

[0075] 2.3 In addition, logical mapping management is also responsible for providing the ability to change mapping information.

[0076] 3. Logical mapping management

[0077] 3.1 The overall design of logical mapping management is shown in Figure 3 .

[0078] 3.2 Logical mapping consists of three parts

[0079] 3.3.1 Mapping of logical ports. Through logical ports, physical ports, event numbers, offset addresses, block numbers and block sizes can be queried.

[0080] 3.3.2 Mapping of physical ports: query the bus number, bus node, base address and characteristics of the corresponding bus through the physical port

[0081] 3.3.3 The bus number is associated with the bus adaptation layer, and the bus adaptation layer is obtained through the bus number to implement operations on a specific bus;

[0082] 3.3.4 All mappings are saved in the form of dynamic ordered arrays, and the mapping is completed through indexes and logical ports.

[0083] 3.2 Mapping Control

[0084] 3.2.1 Logical mapping control uses the same format as general data blocks, such as Figure 4 , where field 0 is reserved as the logical mapping table control type field;

[0085] 3.2.2 When the logical mapping table control type field is 0, it indicates the logical port mapping table control, which is the default control type. The remaining values ​​are extensible.

[0086] 3.2.3 The logical port mapping table control format is as follows Figure 5 When the feature field is 0, the logical port mapping table is completely replaced by the mapping table in the data; when it is 1, if the physical port value of the logical port mapping related to the mapping table in the data is 0, it means that the logical port mapping needs to be deleted;

[0087] 3.2.4 When applying MOCB to the actual system, plan and determine the logical port of each MOCB node for receiving logical mapping control.

[0088] 3.2.5 When the logical port mapping table is modified, a semaphore is created to associate with the event number.

[0089] 3.2.6 When the logical port mapping table modification is completed, the index mapping of all logical ports is updated.

[0090] 3.3: When registering a bus number, the event receiving callback operation should be registered through the bus adaptation layer. The registered callback looks up the associated semaphore according to the event number and triggers the semaphore.

[0091] 1) The MOCB management layer performs three-layer logical mapping, which distinguishes logical ports, physical ports, and bus numbers. The logical port expresses the data transmission needs of the port, and a physical port can be expressed as multiple logical ports through address division; the physical port expresses the bus information of the port, and a bus node can be expressed as multiple physical ports through base address division; the bus number expresses the bus driver used by the port to achieve multi-bus adaptation.

[0092] 2) Logical mapping table control: Through the logical mapping table control interface, MOCB can remotely configure the logical port mapping class table to meet the needs of system software node reconstruction.

[0093] 4. Bus Adaptation Layer Design

[0094] 4.1 The bus adaptation layer is required to implement the memory read and write interface and the event receiving and sending capabilities, and provide the ability to obtain local operable addresses for buses with local mapping requirements;

[0095] 4.2 Write memory: Write data of specified length to the specified address of the specified bus node. MOCB obtains the address to be written to the bus node by calculating the base address and offset address, and writes through this interface;

[0096] 4.3 Read memory: read data of specified length from the specified address of the specified bus node;

[0097] 4.4 Event notification: Notify the specified bus node of the specified event number; through the event number notification, the MOCB layer of the target node knows the logical port where the data is written, and obtains the data from the logical port;

[0098] 4.5 Registered event reception callback: When this bus node receives an event, the registered callback should be called; used to notify the MOCB that the logical port is written to obtain data;

[0099] 4.6 Mapping address acquisition: Map the address to a locally operable address.

[0100] 1) The bus adaptation layer provides memory interface and event interface to achieve the adaptation of multiple types of buses to MOCB.

[0101] 5. Interactive timing control

[0102] 5.1 Interaction Timing Encapsulation determines the data block format and interaction protocol.

[0103] 5.2 Data block format is as follows Figure 4 shown.

[0104] 5.3 Pass Figure 6 The target information corresponding to the logical port is queried in this way. At the same time, the target sending block number and receiving block number of the logical port are recorded.

[0105] 5.4 The data interaction sequence is described as follows:

[0106] 5.4.1 Obtain the target base address, bus node, bus adaptation layer, offset address, event number, block number N and block size and characteristics from the logical mapping management according to the logical port;

[0107] 5.4.2 If the feature is 0, it means that the logical port is located on the GPP / DSP, and the sending timing to the GPP / DSP is referred to; if the feature is 1, it means that the logical port is located on the FPGA, and the sending timing to the FPGA is referred to.

[0108] 5.4.3 GPP / DSP to GPP / DSP transmission timing

[0109] 5.4.3.1 Calculate the address of the current target sending block number in combination with the target base address;

[0110] 5.4.3.2 Write the payload to the target address + 16 of the bus node through the bus adaptation layer;

[0111] 5.4.3.3 Write the data header to the target address + 0 of the bus node through the bus adaptation layer;

[0112] 5.4.3.4 Send the target event number to the bus node through the bus adaptation layer;

[0113] 5.4.3.5 The target sending block number is set to the next target sending block number. If the number of blocks N is reached, it returns to the target sending block number 0.

[0114] 5.4.4 GPP / DSP to FPGA transmission timing

[0115] 5.4.4.1 Calculate the address of the current target sending block number in combination with the target base address;

[0116] 5.4.4.2 Write the data header to the target address + 0 of the bus node through the bus adaptation layer;

[0117] 5.4.4.3 Write the payload to the target address + 16 of the bus node through the bus adaptation layer;

[0118] 5.4.4.4 Send the target event number to the bus node through the bus adaptation layer;

[0119] 5.4.4.5 The target sending block number is set to the next target sending block number. If the number of blocks N is reached, it returns to the target sending block number 0.

[0120] 5.4.5GPP / DSP Receive Timing

[0121] 5.4.5.1 Wait for the semaphore associated with the logical port mapping event number;

[0122] 5.4.5.2 Obtain the local operable address corresponding to the base address through the bus adaptation layer;

[0123] 5.4.5.3 Calculate the address of the current target receiving block number;

[0124] 5.4.5.4 Check the data block to be released field. If it is to be released, return the address and data length; otherwise, return the target receiving block number + 1. If the number of blocks N is reached, return to the target sending block number 0. If not all target block numbers have been checked, return 3. If all target block numbers have been checked and none of them are to be released, this reception is invalid.

[0125] 5.4.6FPGA sends timing to GPP / DSP

[0126] 5.4.6.1 Calculate the address of the current target sending block number in combination with the target base address;

[0127] 5.4.6.2 Write the payload to the target address + 16 of the bus node through the bus adaptation layer. According to the characteristics of FPGA, the user writes the payload data to the MOCB layer in the form of streaming data, and the MOCB layer passes the data to the bus adaptation layer for writing;

[0128] 5.4.6.3 Write the data header to the target address + 0 of the bus node through the bus adaptation layer;

[0129] 5.4.6.4 Send the target event number to the bus node through the bus adaptation layer;

[0130] 5.4.6.5 The target sending block number is set to the next target sending block number. If the number of blocks N is reached, it returns to the target sending block number 0.

[0131] 5.4.7FPGA receiving timing, using streaming data reception

[0132] 5.4.7.2 The data is distributed according to the logical port of the data header and the input receiving logical port. If they are consistent, the data is passed to the matching module, otherwise the data is discarded. The data is read according to the following steps.

[0133] 5.4.7.3 Obtain the length of the data to be read based on the data header

[0134] 5.4.7.4 Streaming receives data from the bus adaptation layer, calculates the length of the data read, and passes the data to the specified module or discards it

[0135] 5.4.7.5 When the length of the data read is greater than or equal to the length of the data to be read, it means that all the data has been read.

[0136] 1) Data block protocol design: The data block contains the logical port and the control type used for mapping control, which is the basic protocol of this interactive timing design;

[0137] 2) Interaction timing design: By transmitting the payload and the data header separately, it is possible to avoid reading incorrect payload data based on the data header when the data is partially sent; by using streaming data on the FPGA, the processing efficiency of the FPGA for MOCB data is improved.

[0138] Example

[0139] The following example describes the implementation process on GPP / DSP:

[0140] A. System Initialization

[0141] A.1 Initialize the bus according to the system's bus usage, create a bus adaptation layer, and assign the bus adaptation layer a unique bus number;

[0142] A.2 Initialize the mapping control management resources, create an array structure for storing three-layer logical mapping: logical port mapping array, physical port mapping array, bus number registration array, create an event number array for storing the association between event numbers and semaphores, and determine the physical port of this hardware.

[0143] A.3 registers the bus number, sorts the "bus number, bus adaptation layer" from small to large according to the bus number and puts them into the bus number registration array, and calls the event receiving callback registration operation of the bus adaptation layer.

[0144] A.3.1 Event receiving callback: When the callback is called, it queries the event number array to obtain the semaphore according to the input event number, and triggers the semaphore;

[0145] A.4 Allocate physical ports according to system design, perform physical port mapping, and sort "physical port, bus number, bus target node, base address, and characteristics" from small to large according to the physical port and put them into the physical port mapping array;

[0146] A.5 performs the initialization of the logical port mapping, and puts the "logical port, physical port, offset address, event number, block number, and block size" into the logical port mapping array in ascending order according to the logical port; if the physical port is located in the hardware, a semaphore is created according to the event number, and the "event number and semaphore" are put into the event number array in ascending order according to the event number;

[0147] A.5 Create a mapping control task to receive and process the "logical mapping table control" message.

[0148] B. Data Operation

[0149] B.1 The user obtains the handle information for operating the logical port by inputting the logical port. The logical mapping management queries the logical port mapping array to obtain the index, event number and physical port of the logical port according to the logical port, queries the physical port mapping array to obtain the index and bus number of the physical port, queries the bus number registration array to obtain the index of the bus number, and queries the event number array to obtain the semaphore corresponding to the event number; the three indices, semaphores, target sending block number and target receiving block number obtained are returned as handle information, where the target sending block number and target receiving block number are initially identified as 0. The user performs read and write operations on the logical port with the handle information;

[0150] B.2 Data read operation: The user completes the data read operation through the handle information and obtains the local memory address and length of the data. After the user processes the data, the field to be released needs to be set to 0.

[0151] B.2.1 After the semaphore in the wait handle information is triggered, enter B.2.2;

[0152] B.2.2 Obtain the following mapping information "offset address, number of blocks, block size", "base address", "bus adaptation layer" and target receiving block number through the handle information;

[0153] B.2.3 The base address is converted into a local operable address through the mapping address acquisition operation of the bus adaptation layer;

[0154] B.2.4 The address is calculated as "local operable address + offset address + target receiving block number × block size" through the target receiving block number and block size. Figure 4 , query the field to be released, if it is 1, return the address and length of the load, and assign the result of adding one to the target receiving block number and taking the remainder of the block number to the target receiving block number, and this read operation ends. Otherwise, go to B.2.5;

[0155] B.2.5 adds one to the target receiving block number and then assigns the result modulo the number of blocks to the target receiving block number. If the number of entries in B.2.4 is not less than the number of blocks, the process ends; otherwise, the process proceeds to B.2.4.

[0156] B.3 Data write operation: The user completes the data write operation through the handle information and inputs the memory address and length of the data to be written;

[0157] B.3.1 Creation Figure 4 The data header and fill in the logical port and length;

[0158] B.3.2 Obtain the following mapping information through the handle information: "offset address, event number, number of blocks, block size", "bus target node, base address, characteristics", "bus adaptation layer" and target sending block number;

[0159] B.3.3 Calculate the data header write address as "base address + offset address + target send block number × block size", and calculate the payload write address as "base address + offset address + target send block number × block size + 16";

[0160] B.3.4 If the feature is 0, the data to be written by the user is written to the load write address of the bus target node through the bus adaptation layer, and then the data header is written to the data header write address; if the feature is 1, the data header is written to the data header write address of the bus target node through the bus adaptation layer, and then the data to be written by the user is written to the load write address;

[0161] B.3.5 Send event notification to the bus target node through the bus adaptation layer according to the event number;

[0162] B.3.6 Add one to the target sending block number and take the remainder of the block number as the value of the target sending block number.

[0163] C. Mapping control task, which starts a loop to read data and performs the following operations after reading the data:

[0164] C.1 parse the logical mapping table control type in the data header, if it is not 0, enter the next loop;

[0165] C.2 At this time, the load data is in the control format of the logical port mapping table. The characteristic value is parsed. If it is 0, it goes to C.3. If it is 1, it goes to C.5. Otherwise, it goes to the next cycle.

[0166] C.3 Clear the logical port mapping array, event number array, and destroy the semaphores therein;

[0167] C.4 Obtain all logical port mapping groups according to the number of logical port mappings N, and perform logical port mapping on each group according to the method of A.5; proceed to C.6;

[0168] C.5 Obtain all logical port mapping groups according to the number of logical port mappings N, check the logical port of each group, if it exists in the logical port mapping array, delete the event number corresponding to the item in the event number array, and destroy the corresponding semaphore, and then update the information of the item according to the "physical port, offset address, event number, block number, block size" of the obtained logical port mapping group. If the physical port is located in the current hardware, create a semaphore according to the event number, and insert the "event number, semaphore" into the event number array according to the size of the event number;

[0169] C.6 Check all logical ports in the logical port mapping array. If the user has obtained the handle information of the logical port, query the logical port mapping array to obtain the index, event number and physical port of the logical port, query the physical port mapping array to obtain the index and bus number of the physical port, query the bus number registration array to obtain the index of the bus number, query the event number array to obtain the semaphore corresponding to the event number, update the index and semaphore information in the handle information; enter the next loop.

[0170] D. Bus Adaptation Layer

[0171] Taking the Serial Rapid IO (SRIO) bus as an example, the bus node is designed as the node ID of SRIO, and the event number is designed as the Doorbell information;

[0172] D.1 Write memory: Use SRIO's NWrite transaction to write data to the bus node;

[0173] D.2 Read memory: Use SRIO's NRead transaction to read data from the bus node;

[0174] D.3 Event Notification: Use SRIO Doorbell transactions to send Doorbell information to bus nodes;

[0175] D.4 Register event reception callback: When receiving the Doorbell, trigger an interrupt and obtain the Doorbell information as the event number for processing;

[0176] 4.6 Mapping address acquisition: Convert the SRIO address to a local address.

[0177] The above is only a specific embodiment of the present invention, and the present invention is described in detail. The unexplained part is a conventional technology. However, the protection scope of the present invention is not limited to this. Any changes or substitutions that can be easily thought of by any technician familiar with the technical field within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. The protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. A configurable MOCB hardware abstraction layer encapsulation design method, characterized in that: MOCB hardware includes three categories: general purpose processor GPP, digital signal processor DSP and programmable logic gate array FPGA; Each hardware can generate events to other hardware; Each hardware accesses the FPGA by generating an address access signal. The address access signal refers to a signal containing a specified memory address and an access method used to describe the operation on the memory content pointed to by the address; Each hardware can access the shared memory of DSP and GPP; Each hardware has a MOCB layer and a bus adaptation layer; The MOCB layer is used for logic mapping management and interactive timing control; The bus adaptation layer is used to implement the memory read and write interface and the sending and receiving of events, and to provide local operable addresses for buses that require local mapping.

2. The method according to claim 1, characterized in that: The bus adaptation layer includes the following operations: Write memory: write data of specified length to the specified address of the specified bus node; MOCB obtains the address to be written to the bus node by calculating the base address and offset address, and writes through this interface; Read memory: read data of specified length from the specified address of the specified bus node; Event notification: Notify the specified bus node of the specified event number; through the event number notification, the MOCB of the target node knows the logical port where the data is written and obtains the data from the logical port; Registered event reception callback: When this bus node receives an event, the registered callback should be called; used to notify the MOCB that the logical port is written to obtain data; Mapping address acquisition: Map the address to a locally operable address.

3. The method according to claim 2, characterized in that: Logical mapping management includes: i. Mapping of logical ports, querying physical ports, event numbers, offset addresses, number of blocks and block sizes through logical ports; when the physical port is located on the hardware, creating a semaphore and associating the semaphore with the event number; ii. Mapping of physical ports, querying the bus number, bus node, base address and characteristics of the corresponding bus through the physical port; iii. The bus number is associated with the bus adaptation layer, and the bus adaptation layer is obtained through the bus number to implement operations on a specific bus.

4. The method according to claim 3, characterized in that: Logical mapping management uses the following data format: length is 16*N+20 bytes; The first 15 bits of the first two bytes are the logical port, and the last bit is the flag bit to be released; The 3rd and 4th bytes are the logical mapping table control type; Bytes 5-8 are the length of the data packet; Bytes 9-16 are reserved; The 17th and 18th bytes are the mapping table update mode flags; 19th and 20th are the number N of logical port mappings in the mapping table; Each subsequent 16 bytes form a group, with a total of N groups, and each group represents a mapping relationship.

5. The method according to claim 4, characterized in that: When registering a bus number, a registration event reception callback operation is performed through the bus adaptation layer; the registered event reception callback searches for the associated semaphore according to the event number and triggers the semaphore.

6. The method according to claim 5, characterized in that: The interactive timing control uses the following data format: the length is 16 + payload length bytes; The first 15 bits of the first two bytes are the logical port, and the last bit is the flag bit to be released; The 3rd and 4th bytes are reserved; Bytes 5-8 are the length of the data packet; Bytes 9-16 are reserved; The next part is the payload, which is the data that needs to be written or read.

7. The method according to claim 6, characterized in that: In interactive timing control, data transmission includes the following processes: Step a: Obtain the target base address, bus node, bus adaptation layer, offset address, event number, block number N and block size and characteristics according to the logical port; Step b: If the feature is 0, it means that the logical port is located on the GPP / DSP, and the process goes to step c; If the feature is 1, it means that the logic port is located on the FPGA, and the process goes to step f; Step c: If the hardware itself is GPP / DSP, go to step d, otherwise go to step e; Step d: Calculate the address of the current target sending block number in combination with the target base address; write the payload to the target address + 16 of the bus node through the bus adaptation layer; write the data header to the target address + 0 of the bus node through the bus adaptation layer; send the target event number to the bus node through the bus adaptation layer; set the target sending block number to the next target sending block number, and if the number of blocks N is reached, return to the target sending block number 0; Step e: Calculate the address of the current target sending block number in combination with the target base address; write the payload to the target address + 16 of the bus node through the bus adaptation layer. According to the characteristics of FPGA, the user writes the payload data to the MOCB layer in the form of streaming data, and the MOCB layer passes the data to the bus adaptation layer for writing; write the data header to the target address + 0 of the bus node through the bus adaptation layer; send the target event number to the bus node through the bus adaptation layer; the target sending block number is set to the next target sending block number. If the number of blocks N is reached, return to the target sending block number 0; Step f: Calculate the address of the current target send block number in combination with the target base address; write the data header to the target address + 0 of the bus node through the bus adaptation layer; write the payload to the target address + 16 of the bus node through the bus adaptation layer; send the target event number to the bus node through the bus adaptation layer; set the target send block number to the next target send block number. If the number of blocks N is reached, return to the target send block number 0.

8. The method according to claim 7, characterized in that: In interactive timing control, data reception includes the following processes: If the hardware is FPGA, streaming data reception is adopted, and data is distributed according to the logical port of the data header and the input receiving logical port. If they are consistent, the data is passed to the matching module, otherwise the data is discarded. Data is read according to the following steps: Get the length of the data to be read according to the data header; Streaming data is received from the bus adaptation layer, and the length of the read data is calculated, and the data is passed to the specified module or discarded; When the length of the read data is greater than or equal to the length of the data to be read, it means that all the data has been read; If the hardware is GPP / DSP, the local operable address corresponding to the base address is obtained through the bus adaptation layer; Calculate the address of the current target receiving block number; Check the data block to be released field, if it is to be released, return the address and data length; Otherwise, the target receiving block number + 1, if the number of blocks N is reached, then return to the target receiving block number 0, if not all target block numbers are checked, then recalculate the address of the current target receiving block number and recheck the data block to be released field, if all target block numbers have been checked and none of them are to be released, then this reception is invalid.

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