Write operation timing logic circuit and memory

Abstract

The application provides a write operation timing logic circuit, which identifies the last valid falling edge of a data sampling pulse according to a write operation instruction, a system clock and the data sampling pulse, and controls a circuit to be self-locked after the data is sampled at the falling edge, so as to latch the multi-bit parallel data from a parallel data generation module until the next write operation instruction is received, thereby completely avoiding the risk of data loss caused by too small duration of a write postamble (twpst).

Description

Technical Field

[0001] This invention relates to a write operation sequential logic circuit, and more particularly to a write operation sequential logic circuit for memory such as DDR3. Background Technology

[0002] Based on read / write capabilities, memory can be divided into Read-Only Memory (ROM) and Random Access Memory (RAM). ROM stores fixed information; it's a semiconductor memory that can only be read, not written to. RAM, on the other hand, allows both reading and writing. Furthermore, RAM can be further divided into SRAM (Static Random Access Memory) and DRAM (Dynamic Random Access Memory). SRAM includes SDR SRAM, DDR SRAM, QDR SRAM, ZBT SRAM, etc.; DRAM includes SDRAM, DDR DRAM, and RDRAM.

[0003] DRAM is a clock-synchronous memory that operates based on a clock signal issued by the processor. Command signals defining actions and address signals specifying memory cells are sent in parallel and synchronized with the rising edge of the clock. In DDR data transfer, the DQ Strobe (DQS) signal serves as the reference instead of the clock and transmits data via the DQ bus. Command and address signals are synchronized only to the rising edge of the clock, while data signals are synchronized to both the rising and falling edges of the DQS. The clock, command, and address signals are unidirectionally input to the DRAM from the processor, while DQS and DQS are bidirectional, input to the DRAM during writing and output from the DRAM during reading.

[0004] During a write operation, after the DQS (Data Sample Sampling Pulse) completes sampling of the last data, it needs to maintain a differential signal for a period of time before the write operation is allowed to completely end. This period is defined as twpst, which is the duration of the Write Postamble. The Write Postamble helps the receiver perform data verification and reconstruction. Its main function is to ensure the integrity and accuracy of data transmission and prevent transmission errors caused by various factors. Summary of the Invention

[0005] However, the minimum twpst defined by the DDR3 technical specification is only 0.3 clock cycles, or a minimum of 281.4ps. After this period, the data sampling pulse is no longer constrained. If the data sampling pulse deviates significantly from the middle level at this time, the data sampling pulse clock will resample the data (DQ), which will cause the latched valid data to be lost. Figure 5The calculation process of twpst is described. If this time has passed, DQS-DQSb will return to 0V and will no longer be strictly constrained. Figure 5 This is a schematic diagram showing the system clock, data sampling pulse, and duration (twpst) of the write postamble signal in the sequential logic circuit of the write operation.

[0006] In a complete write operation, after the data is latched by the data sampling pulse, it also needs to be synchronized to the CK (system clock) domain. Figure 3 This is a traditional circuit implementation method. Figure 4 It describes the timing relationship between data, data sampling pulses, clock, and write operation control instructions. Taking 4-bit data as an example, all data will be latched by the last falling edge of DQS when passing through the last latch, and wait for the CK field control signal for latch synchronization.

[0007] Figure 3 This is a circuit diagram illustrating the specific structure of a prior art write operation sequential logic circuit. Figure 4 This is a timing diagram illustrating the timing of various signals in a prior art write operation sequential logic circuit. Combined with... Figure 3 and Figure 4 It is known that if DQS-DQSb deviates significantly after returning to 0V, the data sampling pulse will be resampled. However, at this time, the fourth bit of data has ended, and the valid data will be incorrectly overwritten. The CK field needs to complete the data sampling or synchronization within the minimum twpst time, which is 281.4p. Considering the existence of tdqss (the time between the rising edge of DQS and the rising edge of CK), this is difficult to achieve.

[0008] The present invention was made in view of the above circumstances, and its purpose is to provide a write operation timing logic circuit that identifies the last valid falling edge of the data sampling pulse based on the write operation instruction, the system clock, and the data sampling pulse. After the data is sampled at the falling edge, the control circuit self-locks to latch the multi-bit parallel data from the parallel data generation module until the next write operation instruction arrives, thereby completely avoiding the risk of data loss caused by the short duration (twpst) of the write postamble signal.

[0009] Technical solutions to solve technical problems

[0010] To solve the above problems, the write operation sequential logic circuit according to the first aspect of the present invention includes:

[0011] A parallel data generation module that generates multi-bit parallel data based on the input serial data and data sampling pulses;

[0012] A data latch module, connected to the parallel data generation module, latches the multi-bit parallel data from the parallel data generation module according to the write operation instruction, the system clock, and the data sampling pulse, and generates a system clock domain synchronization signal; and

[0013] The system clock synchronization module is connected to the data latch module. Based on the latched multi-bit parallel data and the system clock domain synchronization signal, the system clock synchronization module synchronizes the latched multi-bit parallel data to the system clock domain.

[0014] Furthermore, the data latch module generates a data latch signal based on the write operation instruction, the system clock, and the data sampling pulse, and latches the multi-bit parallel data according to the data latch signal.

[0015] Furthermore, the pulse width of the data latch signal is less than a specified width.

[0016] Furthermore, the data latch module includes a first trigger unit, a first flip-flop, a multi-bit latch, a first inverter unit, a second inverter unit, a third inverter unit, an AND gate unit, and a first inverter.

[0017] The first trigger unit is connected to one end of the first inverting unit, one end of the second inverting unit, and one end of the third inverting unit, and inputs the write operation command and the system clock to the first trigger unit.

[0018] The data input terminal of the first flip-flop is connected to the other end of the first inverter unit, the reset terminal of the first flip-flop is connected to the AND gate unit, and the data output terminal of the first flip-flop is connected to one end of the first inverter. A data sampling pulse is input to the clock input terminal of the first flip-flop.

[0019] The clock input terminal of the multi-bit latch is connected to the other end of the first inverter and the AND gate unit, and the data output terminal of the multi-bit latch is connected to the data input terminal of the system clock synchronization module, so that the multi-bit parallel data is input to the data input terminal of the multi-bit latch.

[0020] The other end of the second inverting unit is connected to the AND gate unit.

[0021] The other end of the third inverting unit is connected to the clock input of the system clock synchronization module.

[0022] Furthermore, the first triggering unit generates a write operation control signal that delays the write operation instruction by a specified number of clock cycles based on the write operation instruction and the system clock, and outputs it to the first inverting unit.

[0023] The first trigger unit generates a control signal to turn on the first trigger before the last valid falling edge of the data sampling pulse arrives, based on the write operation instruction and the system clock, and outputs it to the second inverting unit.

[0024] The first triggering unit generates the system clock domain synchronization signal according to the write operation instruction and the system clock, and outputs it to the third inverting unit.

[0025] Furthermore, the first inverting unit comprises eight inverters connected in series.

[0026] The second inverting unit comprises nine inverters connected in series.

[0027] The third inverting unit comprises eight inverters connected in series.

[0028] Furthermore, the AND gate unit includes a first AND gate, a second AND gate, and a third AND gate.

[0029] The output of the first AND gate is connected to the first input of the second AND gate, the first input of the first AND gate is connected to the other end of the second inverting unit, and the second input of the first AND gate is connected to the first trigger unit.

[0030] The second input of the second AND gate is connected to the output of the third AND gate, and the output of the second AND gate is connected to the first input of the third AND gate and the reset terminal of the first flip-flop.

[0031] The second input terminal of the third AND gate is connected to the clock input terminal of the multi-bit latch.

[0032] Furthermore, the first triggering unit includes at least one trigger.

[0033] Furthermore, the system clock synchronization module is a multi-bit trigger.

[0034] The memory involved in the second aspect of the present invention includes the write operation timing logic circuit described above.

[0035] Invention Effects

[0036] According to the write operation timing logic circuit of the present invention, the last valid falling edge of the data sampling pulse is identified based on the write operation instruction, the system clock and the data sampling pulse. After the data is sampled at the falling edge, the control circuit self-locks to latch the multi-bit parallel data from the parallel data generation module until the next write operation instruction arrives. This completely avoids the risk of data loss caused by the short duration (twpst) of the write postamble signal. Attached Figure Description

[0037] Figure 1 This is a circuit diagram illustrating an example of the specific structure of the write operation sequential logic circuit according to an embodiment of the present invention.

[0038] Figure 2 This is a timing diagram illustrating an example of the timing of various signals in a write operation sequential logic circuit according to an embodiment of the present invention.

[0039] Figure 3 This is a circuit diagram illustrating the specific structure of a prior art write operation sequential logic circuit.

[0040] Figure 4 This is a timing diagram illustrating the timing of each signal in a prior art write operation sequential logic circuit.

[0041] Figure 5 This is a schematic diagram showing the system clock, data sampling pulse, and duration (twpst) of the write postamble signal in the sequential logic circuit of the write operation.

[0042] Label Explanation

[0043] 101 Parallel Data Generation Module

[0044] 102 Data Latch Module

[0045] 103 System Clock Synchronization Module

[0046] 1021 First Inverting Unit

[0047] 1022 Second Inverting Unit

[0048] 1023 Third Inverting Unit

[0049] 1024 AND gate unit Detailed Implementation

[0050] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments. These embodiments are implemented based on the technical solution of the present invention, providing detailed implementation methods and specific operating procedures. However, the scope of protection of the present invention is not limited to the following embodiments.

[0051] For ease of description, spatial relative terms such as “below,” “under,” “down,” “above,” “up,” etc., may be used herein to describe the relationship of one element or feature relative to another element or feature as shown in the figure. It should be understood that spatial relative terms are intended to include different orientations of the device used or operated in addition to those shown in the figure. For example, if the device in the figure were flipped, an element described as “below” or “under” other elements or features would be oriented as “above” other elements or features.

[0052] Unless otherwise specified, the terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Terms should be understood to have the meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formalized manner, unless explicitly stated otherwise herein.

[0053] <Structure of Sequential Logic Circuits for Writing Operations>

[0054] The specific structure of the write operation sequential logic circuit according to the embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0055] Figure 1 This is a circuit diagram illustrating an example of the specific structure of the write operation sequential logic circuit according to an embodiment of the present invention.

[0056] like Figure 1 As shown, as an example, the write operation sequential logic circuit 10 involved in the embodiment of the present invention includes a parallel data generation module 101, a data latch module 102, and a system clock synchronization module 103. Taking BL4 (4-bit data read / write) as an example, the system clock synchronization module 103 can be a multi-bit flip-flop DFF6<3:0>.

[0057] As an example, the parallel data generation module 101 generates multi-bit parallel data DQ0, DQ1, DQ2, and DQ3 based on the input serial data DQ and data sampling pulses DQS / DQSb. The data latch module 102, connected to the parallel data generation module 101, latches the multi-bit parallel data from the parallel data generation module 101 according to the write command, the system clock CK, and the data sampling pulses DQS / DQSb, and generates a system clock domain synchronization signal SCAS_WT. The system clock synchronization module 103, connected to the data latch module 102, synchronizes the latched multi-bit parallel data DQ_D0, DQ_D1, DQ_D2, and DQ_D3 to the system clock domain based on the system clock domain synchronization signal SCAS_WT.

[0058] Specifically, as an example, the data latch module 102 includes a first trigger unit DFF(n), a first flip-flop DFF5, a multi-bit latch LATCH2<3:0>, a first inverter unit 1021, a second inverter unit 1022, a third inverter unit 1023, an AND gate unit 1024, and a first inverter 1025. The first trigger unit DFF(n) may include at least one flip-flop, and the number of first trigger units DFF(n) can be changed according to the system latency setting to adjust the delay of write operation instructions.

[0059] The first trigger unit DFF(n) is connected to one end of the first inverting unit 1021, one end of the second inverting unit 1022, and one end of the third inverting unit 1023, and inputs the write operation instruction WriteCommand and the system clock CK to the first trigger unit DFF(n).

[0060] The data input terminal D of the first flip-flop DFF5 is connected to the other end of the first inverter unit 1021. The reset terminal Reset of the first flip-flop DFF5 is connected to the AND gate unit 1024. The data output terminal Q of the first flip-flop DFF5 is connected to one end of the first inverter 1025, and a data sampling pulse DQSb is input to the clock input terminal CK of the first flip-flop DFF5.

[0061] The clock input terminal CK of the multi-bit latch LATCH2<3:0> is connected to the other end of the first inverter 1025 and the AND gate unit 1024. The data output terminal Q of the multi-bit latch LATCH2<3:0> is connected to the data input terminal D of the system clock synchronization module 103, and multiple parallel data DQ0, DQ1, DQ2, and DQ3 are input to the data input terminal D of the multi-bit latch LATCH2<3:0>.

[0062] The other end of the second inverter unit 1022 is connected to the AND gate unit 1024, and the other end of the third inverter unit 1023 is connected to the clock input terminal CK of the system clock synchronization module 103.

[0063] also, Figure 1 As an example, the first inverter unit 101 includes eight inverters connected in series, the second inverter unit 102 includes nine inverters connected in series, and the third inverter unit 103 includes eight inverters connected in series, but the present invention is not limited thereto.

[0064] Furthermore, as an example, AND gate unit 1024 includes a first AND gate 1024a, a second AND gate 1024b, and a third AND gate 1024c. The output of the first AND gate 1024a is connected to the first input of the second AND gate 1024b, the first input of the first AND gate 1024a is connected to the other end of the second inverter unit 1022, and the second input of the first AND gate 1024a is connected to the first trigger unit DFF(n). The second input of the second AND gate 1024b is connected to the output of the third AND gate 1024c, and the output of the second AND gate 1024b is connected to the first input of the third AND gate 1024c and the reset terminal Reset of the first trigger DFF5. The second input of the third AND gate 1024c is connected to the other end of the first inverter 1025 and the clock input CK of the multi-bit latch LATCH2<3:0>.

[0065] In addition, such as Figure 1 As shown, taking BL4 (4-bit data read / write) as an example, the parallel data generation module 101 includes flip-flops DFF1, DFF2, DFF3, DFF4, and latch LATCH1.

[0066] The data input terminal D of flip-flop DFF1 is connected to the data input terminal D of flip-flop DFF3. The data output terminal Q of flip-flop DFF1 is connected to the data input terminal D of latch LATCH1. Serial data DQ is input to the data input terminal D of flip-flop DFF1, and a data sampling pulse DQS is input to the clock input terminal CK of flip-flop DFF1. The clock input terminal CK of latch LATCH1 is connected to the clock input terminals CK of flip-flops DFF2, DFF3, and DFF4. The data output terminal Q of latch LATCH1 is connected to the data input terminal D of flip-flop DFF2. The output signal from the data output terminal Q of flip-flop DFF1 is input to the data input terminal D of latch LATCH1, and a data sampling pulse DQSb is input to the clock input terminal CK of latch LATCH1. Data DQ2 is output from the data output terminal Q of latch LATCH1. Input the output data DQ2 from the latch LATCH1 to the data input terminal D of the flip-flop DFF2, input the data sampling pulse DQSb to the clock input terminal CK of the flip-flop DFF2, and output the data DQ0 from the data output terminal Q of the flip-flop DFF2.

[0067] The data output terminal Q of flip-flop DFF3 is connected to the data input terminal D of flip-flop DFF4. Serial data DQ is input to the data input terminal D of flip-flop DFF3, and a data sampling pulse DQSb is input to the clock input terminal CK of flip-flop DFF3. Data DQ3 is output from the data output terminal Q of flip-flop DFF3. The output data DQ3 from flip-flop DFF3 is input to the data input terminal D of flip-flop DFF4, and a data sampling pulse DQSb is input to the clock input terminal CK of flip-flop DFF4. Data DQ1 is output from the data output terminal Q of flip-flop DFF4.

[0068] In addition, the aforementioned multi-bit parallel data DQ0, DQ1, DQ2, and DQ3 are input to the data input terminal D of the multi-bit latch LATCH2<3:0> in the data latch module 102.

[0069] Figure 2 This is a timing diagram illustrating an example of the timing of various signals in a write operation sequential logic circuit according to an embodiment of the present invention. Figure 2 In this example, we will use BL4 (4-bit data read / write) as an example.

[0070] like Figure 1 and Figure 2As shown, the first trigger unit DFF(n) generates a write operation control signal SCAS_WT_PRE_1CLK that delays the write operation command by a specified number of clock cycles (WL+1)*tck according to the write operation command Write Command and the system clock CK, and outputs it to the first inverting unit 1021, and then further outputs it to the data input terminal D of the first flip-flop DFF5 via the first inverting unit 1021.

[0071] The write operation control signal SCAS_WT_PRE_1CLK includes the last valid falling edge of DQS. After the last valid falling edge of DQS is sampled by the first flip-flop DFF5, the output Q5 of the first flip-flop DFF5 is set to 0 after a short delay. The output DQ_LATCH of Q5 after passing through the first inverter 1025 becomes a low-level narrow pulse triggered by the last valid falling edge of DQS. Figure 2 As shown, the pulse width of this low-level narrow pulse is much smaller than twpst. Since the first flip-flop DFF5 has been set to 0, any change in DQS after twpst will not affect the low-level narrow pulse. The low-level narrow pulse will pass through the data DQ at a low level and latch 4 bits of DQ data on the rising edge.

[0072] Furthermore, the first trigger unit DFF(n) generates a control signal SCAS_WT_PRE_1d5CLK based on the Write Command and the system clock CK. This signal is used to enable the first flip-flop DFF5 before the last valid falling edge of the data sampling pulse DQS arrives. The signal is then output to the second inverting unit 1022, and further output to the reset terminal Reset of the first flip-flop DFF5 via the second inverting unit 1022 and the AND gate unit 1024. SCAS_WT_PRE_1d5CLK is a control signal that is half a clock cycle faster than SCAS_WT_PRE_1CLK, and it is used to enable the first flip-flop DFF5 before the last valid falling edge of the data sampling pulse DQS arrives.

[0073] Furthermore, the first trigger unit DFF(n) generates a system clock domain synchronization signal SCAS_WT based on the Write Command and the system clock CK, and outputs it to the third inverting unit 1023. Then, via the third inverting unit 1023, it is further output to the clock input CK of the system clock synchronization module 103. The system clock domain synchronization signal SCAS_WT is one clock cycle slower than SCAS_WT_PRE_1CLK. It is responsible for synchronizing the latched 4-bit data DQ_D0, DQ_D1, DQ_D2, and DQ_D3 to the system clock domain at the rising edge through the multi-bit flip-flop DFF6<3:0> (system clock synchronization module 103).

[0074] Furthermore, in BL4 (4-bit data read / write), the interval between two write operations is at least tccd (4 clock cycles), and the 4 bits of data will be latched for at least 4 clock cycles tck for the system clock domain synchronization signal SCAS_WT to perform latching synchronization. In BL8 (8-bit data read / write), the 8 bits of data are divided into two 4-bit data, which are written sequentially. The interval between the two SCAS_WT_PRE_1CLK signals is at least 2 clock cycles, and each 4-bit data will be latched for 2 clock cycles tck for the system clock domain synchronization signal SCAS_WT to perform latching synchronization. The time is very ample, thus avoiding the risk of data loss caused by the DQS not being constrained after the twpst time.

[0075] According to the write operation timing logic circuit of the present invention, the last valid falling edge of the data sampling pulse is identified based on the write operation instruction, the system clock and the data sampling pulse. After the data is sampled at the falling edge, the control circuit self-locks to latch the multi-bit parallel data from the parallel data generation module until the next write operation instruction arrives. This completely avoids the risk of data loss caused by the short duration (twpst) of the write postamble signal.

[0076] In addition, the present invention also provides a memory that includes the write operation timing logic circuit involved in the embodiments of the present invention.

[0077] It should be understood that the above description is illustrative and not restrictive. For example, the above embodiments (and / or aspects thereof) can be used in combination with each other. Furthermore, many modifications can be made to adapt particular conditions or materials to the teachings of the various embodiments of the invention without departing from the scope of the invention. While the dimensions and types of materials described herein are used to define parameters of the various embodiments of the invention, the embodiments are not intended to be restrictive but are exemplary. Many other embodiments will become apparent to those skilled in the art upon reading the above description. Therefore, the scope of the various embodiments of the invention should be determined by reference to the appended claims and the full scope of their equivalents.

[0078] Industrial practicality

[0079] The write operation timing logic circuit of this invention can be widely used in DDR3 and other memory.

Claims

1. A write operation timing logic circuit, characterized by, The write operation timing logic circuit comprises: a parallel data generation module configured to generate multi-bit parallel data according to input serial data and a data sampling pulse; a data latch module connected to the parallel data generation module, configured to latch the multi-bit parallel data from the parallel data generation module according to a write operation instruction, a system clock and the data sampling pulse, and generate a system clock domain synchronization signal; a system clock synchronization module connected to the data latch module, configured to synchronize the latched multi-bit parallel data to a system clock domain according to the latched multi-bit parallel data and the system clock domain synchronization signal. The data latch module comprises a first trigger unit, a first flip-flop, a multi-bit latch, a first inverting unit, a second inverting unit, a third inverting unit, an AND gate unit and a first inverter. The first trigger unit is connected to one end of the first inverting unit, one end of the second inverting unit and one end of the third inverting unit, and the write operation instruction and the system clock are input to the first trigger unit. The data input end of the first flip-flop is connected to the other end of the first inverting unit, the reset end of the first flip-flop is connected to the AND gate unit, the data output end of the first flip-flop is connected to one end of the first inverter, and the data sampling pulse is input to the clock input end of the first flip-flop. The clock input end of the multi-bit latch is connected to the other end of the first inverter and the AND gate unit, the data output end of the multi-bit latch is connected to the data input end of the system clock synchronization module, and the multi-bit parallel data is input to the data input end of the multi-bit latch. The other end of the second inverting unit is connected to the AND gate unit. The other end of the third inverting unit is connected to the clock input end of the system clock synchronization module.

2. The write operation timing logic circuit of claim 1, wherein the data latch module generates a data latch signal according to the write operation instruction, the system clock and the data sampling pulse, and latches the multi-bit parallel data according to the data latch signal.

3. The write operation timing logic circuit of claim 2, wherein the pulse width of the data latch signal is less than a specified width.

4. The write operation timing logic circuit of claim 1, wherein the first trigger unit generates a write operation control signal in which the write operation instruction is delayed by a specified number of clock cycles according to the write operation instruction and the system clock, and outputs the write operation control signal to the first inverting unit, the first trigger unit generates a control signal for turning on the first flip-flop before the last active falling edge of the data sampling pulse arrives according to the write operation instruction and the system clock, and outputs the control signal to the second inverting unit, the first trigger unit generates the system clock domain synchronization signal according to the write operation instruction and the system clock, and outputs the system clock domain synchronization signal to the third inverting unit.

5. The write operation timing logic circuit of claim 1, wherein ​ The first inverting unit includes 8 inverters connected in series with each other, The second inverting unit includes 9 inverters connected in series with each other, The third inverting unit includes 8 inverters connected in series with each other.

6. The write operation timing logic circuit of claim 1, wherein, The AND gate unit includes a first AND gate, a second AND gate, and a third AND gate, an output terminal of the first AND gate is connected with a first input terminal of the second AND gate, a first input terminal of the first AND gate is connected with the other end of the second inverting unit, and a second input terminal of the first AND gate is connected with the first flip-flop unit, a second input terminal of the second AND gate is connected with an output terminal of the third AND gate, and an output terminal of the second AND gate is connected with a first input terminal of the third AND gate and a reset terminal of the first flip-flop, a second input terminal of the third AND gate is connected with a clock input terminal of the multi-bit latch.

7. The write operation timing logic circuit of claim 1, wherein, The first flip-flop unit includes at least one flip-flop.

8. The write operation timing logic circuit of claim 1, wherein, The system clock synchronization module is a multi-bit flip-flop.

9. A memory, comprising: A system including the write operation timing logic circuit of any one of claims 1 to 8.

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