Storage device and memory control device

Abstract

The invention relates to a storage device and a memory control device. Embodiments of the present disclosure may provide a read retry table optimized for a corresponding memory based on a read voltage distribution of word lines included in the memory, and may provide an optimal read retry table even for a memory with insufficient sample data by changing a method of setting the read retry table according to a number of sample data.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0140166, filed on October 19, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of the present disclosure generally relate to a storage device and a memory control device. Background Art

[0004] The storage device may include a memory including a plurality of memory cells and storing data. The storage device may include a controller controlling the operation of the memory.

[0005] The controller may control an operation of writing data to the memory, reading data written to the memory, or erasing data written to the memory according to an external request or an internal operation.

[0006] When the controller performs an operation of reading data written to the memory, the read operation may be performed using a preset read voltage. In this case, due to the change in the characteristics of the memory, the read operation based on the preset read voltage may not be performed normally. Summary of the invention

[0007] Various embodiments of the present disclosure are directed to providing measures capable of improving the performance of an operation of reading data written to a memory and a read retry operation performed when the read operation fails.

[0008] In an embodiment of the present disclosure, a storage device may include: a memory, including a plurality of memory cells arranged between a plurality of word lines and a plurality of bit lines, and storing a read retry table; and a controller, configured to control a read retry operation for the plurality of memory cells using the read retry table, the read retry table being determined using internal data and external data, wherein the internal data is determined based on a read voltage of M word lines among the plurality of word lines, M being greater than or equal to 1, and wherein the external data is determined based on a read voltage of at least N word lines included in each of the plurality of external memories, N being greater than M.

[0009] In an embodiment of the present disclosure, a storage device may include: a first memory, including multiple first word lines and a block, in which the block stores a first read retry table determined based on the read voltages of M first word lines among the multiple first word lines, M is greater than or equal to 1; and a second memory, including multiple second word lines and a block, in which the block stores a second read retry table determined based on the read voltages of at least N second word lines among the multiple second word lines, N is greater than M.

[0010] In an embodiment, a memory control device may include: a sampling data receiving unit configured to receive sampling data of read voltages of K word lines from a memory or an outside, K being greater than or equal to 1; and an optimal read retry table generator configured to generate a read retry table of the memory including the K word lines based on the sampling data.

[0011] According to an embodiment of the present disclosure, it is possible to improve the performance of a read retry operation performed when a read operation of each memory included in a storage device fails.

[0012] These and other features and advantages of the present invention will become apparent from the detailed description of the embodiments of the present disclosure and the following drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a diagram showing a schematic configuration of a storage device according to an embodiment of the present disclosure.

[0014] Figure 2 It is shown Figure 1 A diagram showing a schematic configuration of a memory shown.

[0015] Figure 3 is a diagram illustrating a method of generating a read retry table of a storage device according to an embodiment of the present disclosure.

[0016] Figure 4A and Figure 4B yes Figure 3 Schematic diagram of other read retry tables that may be shown in .

[0017] Figures 5 to 9 is a diagram illustrating another method of generating a read retry table of a storage device based on an embodiment of the present disclosure.

[0018] Fig.10 is a diagram showing a configuration and an operation scheme of a memory control device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0019] In the following description of the embodiments of the present disclosure, reference will be made to the accompanying drawings, in which specific examples of embodiments that can be implemented are shown by way of illustration, and in the accompanying drawings, even if the same reference numerals and symbols are shown in different drawings from each other, they can also be used to represent the same or similar components. Further, in the following description of the examples or embodiments of the present disclosure, when it is determined that a detailed description of the well-known functions and components incorporated herein may obscure the subject matter in some embodiments of the present disclosure, the detailed description will be omitted. Unless terms such as "including", "having", "containing", "constituting", "comprising", "forming" used herein are used together with the term "only", these terms are generally intended to allow the addition of other components. As used herein, unless the context clearly indicates otherwise, the singular form is intended to include the plural form.

[0020] Terms such as "first", "second", "A", "B", "(A)" or "(B)" may be used herein to describe elements of the present disclosure. Each of these terms is not used to define the nature, sequence, order or quantity of the elements, etc., but is only used to distinguish the corresponding element from other elements.

[0021] When it is mentioned that a first element is "connected or coupled", "contacted or overlapped", etc. with a second element, it should be explained that not only the first element can be "directly connected or coupled", "directly contacted or overlapped" with the second element, but also a third element can be "interposed" between the first element and the second element, or the first element and the second element can be mutually "connected or coupled", "contacted or overlapped" etc. through a fourth element. Here, the second element can be included in at least one of the two or more elements that are "connected or coupled", "contacted or overlapped", etc. with each other.

[0022] When time relative terms such as "after", "subsequently", "next", "before" and the like are used to describe a process or operation of an element or configuration, or a flow or step in an operation, process, or manufacturing method, unless these terms are used with the terms "directly" or "immediately", these terms can also be used to describe non-continuous or non-sequential processes or operations.

[0023] In addition, when any dimension, relative dimension, etc. is mentioned, even if no relevant description is specified, it should be considered that the numerical value or corresponding information (e.g., level, range, etc.) of the element or feature includes a tolerance or error range that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.). Further, the term "may" fully encompasses all meanings of the term "can".

[0024] Hereinafter, various embodiments of the present disclosure will be described below with reference to the accompanying drawings.

[0025] Figure 1is a diagram showing a schematic configuration of a storage device 100 according to an embodiment of the present disclosure. Figure 2 It is shown Figure 1 A diagram showing a schematic configuration of the memory 110 is shown.

[0026] Reference Figure 1 , the storage device 100 may include a memory 110 that stores data and a controller 120 that controls the memory 110 .

[0027] The memory 110 may include a plurality of memory blocks, and may operate in response to the control of the controller 120. The operation of the memory 110 may include, for example, a read operation, a program operation (or a write operation), and an erase operation.

[0028] The memory 110 may include a memory cell array including a plurality of memory cells storing data. Such a memory cell array may exist in a memory block.

[0029] The memory 110 may be a volatile memory or a nonvolatile memory. The memory 110 may be implemented as a three-dimensional array structure. The embodiments of the present disclosure may be applied not only to a flash memory in which a charge storage layer is configured by a floating gate, but also to a charge capture flash memory in which a charge storage layer is configured by an insulating film.

[0030] The memory 110 may receive a command, an address, etc. from the controller 120, and may access a region selected by the address in the memory cell array. The memory 110 may perform an operation indicated by the command on the region selected by the address.

[0031] The memory 110 can perform a programming operation, a reading operation, and an erasing operation. When performing a programming operation, the memory 110 can program data into an area selected by an address. When performing a reading operation, the memory 110 can read data from an area selected by an address. In an erasing operation, the memory 110 can erase data stored in an area selected by an address.

[0032] The controller 120 may control a write operation (program operation), a read operation, an erase operation, and a background operation on the memory 110. The background operation may include, for example, at least one of garbage collection, wear leveling, read reclamation, and bad block management operations.

[0033] The controller 120 may control the operation of the memory 110 according to a request from a device (eg, a host) located outside the storage device 100. Also, the controller 120 may control the operation of the memory 110 regardless of the request of the host.

[0034] The host may include at least one operating system. The operating system may generally manage and control functions and operations of the host, and may provide interoperability between the host and the storage device 100. According to the mobility of the host, the operating system may be divided into a general operating system and a mobile operating system.

[0035] The controller 120 and the host may be separate devices from each other. In some embodiments, the controller 120 and the host may be implemented by being integrated into one device. Hereinafter, for convenience, the controller 120 and the host will be described as separate devices from each other.

[0036] The controller 120 may include a host interface 121 , a memory interface 122 , and a control circuit 123 .

[0037] The host interface 121 may provide an interface for communicating with the host. When receiving a command from the host, the control circuit 123 may receive the command through the host interface 121 and may perform an operation of processing the received command.

[0038] The memory interface 122 may be coupled with the memory 110 to provide an interface for communicating with the memory 110. The memory interface 122 may be configured to provide an interface between the memory 110 and the controller 120 in response to the control of the control circuit 123.

[0039] The control circuit 123 may perform general control operations of the controller 120 to control the operation of the memory 110. The control circuit 123 may include a processor 124 and a working memory 125, and may optionally include an error detection and correction circuit 126.

[0040] The processor 124 may control general operations of the controller 120 and may perform logic calculations. The processor 124 may communicate with the host through the host interface 121 and may communicate with the memory 110 through the memory interface 122.

[0041] The processor 124 may perform the function of the flash translation layer. The processor 124 may convert the logical block address provided by the host into a physical block address through the flash translation layer. The flash translation layer may receive the logical block address and convert the logical block address into a physical block address using a mapping table.

[0042] There are various address mapping methods for the flash translation layer according to different mapping units, and representative address mapping methods include page mapping method, block mapping method and hybrid mapping method.

[0043] The processor 124 may run firmware to control the operation of the controller 120. In order to control the general operation of the controller 120 and perform logic calculations, the processor 124 may run (drive) the firmware loaded into the working memory 125 at startup. Hereinafter, the operation of the storage device 100 described based on the embodiment may be implemented in a manner in which the processor 124 runs the firmware defining the corresponding operation.

[0044] The firmware may include various functional layers as a program to be executed in the storage device 100 to drive the storage device 100. For example, the firmware may include binary data defining codes for executing the various functional layers.

[0045] The firmware may include at least one of a flash translation layer, a host interface layer, and a flash interface layer. The flash translation layer performs a conversion function between a logical address requested by the host to the storage device 100 and a physical address of the memory 110. The host interface layer is used to analyze a command requested by the host to the storage device 100 and transmit the command to the flash translation layer. The flash interface layer transmits the command indicated by the flash translation layer to the memory 110.

[0046] The firmware may be loaded into the working memory 125 from, for example, the memory 110 or a separate nonvolatile memory (eg, ROM or NOR flash memory) located outside the memory 110. When the processor 124 performs a startup operation after power-on, it may first load all or part of the firmware in the working memory 125.

[0047] The processor 124 may execute the logic operations defined in the firmware loaded into the working memory 125 to control the general operation of the controller 120. The processor 124 may store the result of executing the logic operations defined in the firmware in the working memory 125. The processor 124 may control the controller 120 to generate commands or signals according to the result of executing the logic operations defined in the firmware. When a portion of the firmware defining the logic operations to be executed is not loaded into the working memory 125, the processor 124 may generate an event (e.g., an interrupt) for loading the corresponding portion of the firmware into the working memory 125.

[0048] The processor 124 may load metadata required for driving firmware from the memory 110. The metadata, which is data for managing the memory 110, may include management information on user data stored in the memory 110.

[0049] The working memory 125 may store firmware, program codes, commands, and data necessary for driving the controller 120. The working memory 125, which is, for example, a volatile memory, may include at least one of an SRAM, a DRAM, and an SDRAM.

[0050] The error detection and correction circuit 126 can detect an error bit of the target data by using an error correction code and correct the detected error bit. The target data can be, for example, data stored in the working memory 125 or data read from the memory 110.

[0051] The error detection and correction circuit 126 may be implemented to decode data using an error correction code. The error detection and correction circuit 126 may be implemented by various code decoders. For example, a decoder that performs non-systematic code decoding or a decoder that performs systematic code decoding may be used.

[0052] The bus 127 may be configured to provide a channel between the components 121, 122, 124, 125, and 126 of the controller 120. The bus 127 may include, for example, a control bus for transmitting various control signals, commands, etc., a data bus for transmitting various data, etc.

[0053] Some of the above components 121, 122, 124, 125 and 126 of the controller 120 may be omitted or integrated into one component. In some embodiments, in addition to the above components 121, 122, 124, 125 and 126 of the controller 120, one or more other components may be added.

[0054] In the following, reference will be made to Figure 2 The memory 110 is described in more detail.

[0055] Reference Figure 2 , the memory 110 may include a memory cell array 210 , an address decoder 220 , a read and write circuit 230 , a control logic 240 , and a voltage generation circuit 250 .

[0056] The memory cell array 210 may include a plurality of memory blocks BLK1 to BLKz, where z is a natural number of 2 or more.

[0057] A plurality of memory blocks BLK1 to BLKz may be disposed between a plurality of word lines WL and a plurality of bit lines BL, and each memory block may include a plurality of memory cells arranged therein.

[0058] The plurality of memory blocks BLK1 to BLKz may be coupled to the address decoder 220 through a plurality of word lines WL. The plurality of memory blocks BLK1 to BLKz may be coupled to the read and write circuit 230 through a plurality of bit lines BL.

[0059] Each of the plurality of memory blocks BLK1 to BLKz may include a plurality of memory cells. The plurality of memory cells may be nonvolatile memory cells, and may be configured of nonvolatile memory cells having a vertical channel structure.

[0060] The memory cell array 210 may be configured by a memory cell array of a two-dimensional structure, or may be configured by a memory cell array of a three-dimensional structure.

[0061] Each of the plurality of memory cells included in the memory cell array 210 may store at least one bit of data. For example, each of the plurality of memory cells included in the memory cell array 210 may be a single-layer cell (SLC) storing 1 bit of data. For another example, each of the plurality of memory cells included in the memory cell array 210 may be a multi-layer cell (MLC) storing 2 bits of data. For another example, each of the plurality of memory cells included in the memory cell array 210 may be a triple-layer cell (TLC) storing 3 bits of data. For another example, each of the plurality of memory cells included in the memory cell array 210 may be a quad-layer cell (QLC) storing 4 bits of data. For another example, the memory cell array 210 may include a plurality of memory cells, each of which stores 5 or more bits of data.

[0062] The number of bits of data stored in each of the plurality of memory cells can be dynamically determined. For example, a single-layer cell storing 1 bit of data can be changed to a triple-layer cell storing 3 bits of data.

[0063] The address decoder 220 , the read and write circuit 230 , the control logic 240 , and the voltage generating circuit 250 may operate as peripheral circuits driving the memory cell array 210 .

[0064] The address decoder 220 may be coupled to the memory cell array 210 through a plurality of word lines WL. The address decoder 220 may be configured to operate in response to the control of the control logic 240.

[0065] The address decoder 220 may receive an address through an input / output buffer in the memory 110. The address decoder 220 may be configured to decode a block address in the received address. The address decoder 220 may select at least one memory block of the memory cell array 210 according to the decoded block address.

[0066] The address decoder 220 may receive a read voltage Vread and a pass voltage Vpass from the voltage generating circuit 250 .

[0067] In a read voltage applying operation during a read operation, the address decoder 220 may apply a read voltage Vread to a selected word line WL in a selected memory block, and may apply a pass voltage Vpass to remaining unselected word lines WL.

[0068] In a program verification operation, the address decoder 220 may apply a verification voltage generated by the voltage generation circuit 250 to a selected word line WL in a selected memory block, and may apply a pass voltage Vpass to remaining unselected word lines WL in the selected memory block.

[0069] The address decoder 220 may be configured to decode the column address in the received address. The address decoder 220 may send the decoded column address to the read and write circuit 230.

[0070] The read operation and the program operation of the memory 110 may be performed in units of pages. An address received along with a request for a read operation or a program operation may include at least one of a block address, a row address, and a column address.

[0071] The address decoder 220 may select a memory block and a word line WL according to the block address and the row address. The column address may be decoded by the address decoder 220 and provided to the read and write circuit 230.

[0072] The address decoder 220 may include at least one of a block decoder, a row decoder, a column decoder, and an address buffer.

[0073] The read and write circuit 230 may include a plurality of page buffers PB. The read and write circuit 230 may operate as a read circuit in a read operation of the memory cell array 210 and may operate as a write circuit in a write operation of the memory cell array 210.

[0074] The read and write circuit 230 may also be referred to as a page buffer circuit or a data register circuit including a plurality of page buffers PB. The read and write circuit 230 may include a data buffer responsible for a data processing function, and in some embodiments, may further include a cache buffer responsible for a cache function.

[0075] The plurality of page buffers PB may be coupled to the memory cell array 210 through the plurality of bit lines BL. In a read operation and a program verification operation, the plurality of page buffers PB may continuously supply a sensing current to the bit lines BL coupled to the memory cells to sense a threshold voltage (Vth) of the memory cells, and may latch sensing data by sensing a current amount that changes according to a programming state of a corresponding memory cell through a sensing node.

[0076] The read and write circuit 230 may operate in response to a page buffer control signal output from the control logic 240 .

[0077] In a read operation, the read and write circuit 230 temporarily stores the read data by sensing the data of the memory cell and then outputs the read data to the input / output buffer of the memory 110. In an embodiment, the read and write circuit 230 may further include a column selection circuit, etc. in addition to the page buffer PB or the page register.

[0078] The control logic 240 may be coupled to the address decoder 220, the read and write circuit 230, and the voltage generating circuit 250. The control logic 240 may receive a command CMD and a control signal CTRL through an input / output buffer of the memory 110.

[0079] The control logic 240 may be configured to control a general operation of the memory 110 in response to the control signal CTRL. The control logic 240 may output a control signal for adjusting a precharge potential level of a sensing node of a plurality of page buffers PB.

[0080] The control logic 240 may control the read and write circuit 230 to perform a read operation of the memory cell array 210. The voltage generation circuit 250 may generate a read voltage Vread and a pass voltage Vpass used in a read operation in response to a voltage generation circuit control signal output from the control logic 240.

[0081] Each memory block of the above-described memory 110 may be configured by a plurality of pages corresponding to a plurality of word lines WL and a plurality of strings corresponding to a plurality of bit lines BL.

[0082] In the memory block BLK, a plurality of word lines WL and a plurality of bit lines BL may be arranged to cross each other. A memory cell connected to one of the plurality of word lines WL and one of the plurality of bit lines BL may be defined. A transistor may be arranged in each memory cell.

[0083] The transistor provided in the memory cell may include a drain, a source, and a gate. The drain (or source) of the transistor may be directly or via another transistor TR coupled to a corresponding bit line BL. The source (or drain) of the transistor may be directly or via another transistor coupled to a source line (which may be grounded). The gate of the transistor may include a floating gate surrounded by a dielectric and a control gate to which a gate voltage is applied from a word line WL.

[0084] Each memory block may include a first selection line (also referred to as a source selection line or a drain selection line) and a second selection line (also referred to as a drain selection line or a source selection line). The first selection line may be additionally disposed outside a first outermost word line WL of the two outermost word lines WL that is closer to the read and write circuit 230. The second selection line may be additionally disposed outside a second outermost word line WL of the two outermost word lines WL.

[0085] In some embodiments, at least one dummy word line may be additionally disposed between the first outermost word line and the first selection line. At least one dummy word line may be additionally disposed between the second outermost word line and the second selection line.

[0086] The read operation and the program operation (write operation) of the above-mentioned memory block may be performed in units of pages, and the erase operation may be performed in units of memory blocks.

[0087] When performing a read operation on the memory 110, due to changes in the characteristics of the memory cell, the read operation performed by the preset read voltage Vread may not be performed normally. In this case, the read operation may be performed by changing the read voltage Vread.

[0088] Embodiments of the present disclosure may provide a scheme in which a read retry value for performing a read retry operation is set to an optimal value for the memory 110 , thereby providing a measure capable of improving the performance of a read operation of the memory 110 .

[0089] Figure 3 is a diagram illustrating a method of generating a read retry table of the storage device 100 according to an embodiment of the present disclosure. Figure 4A and Figure 4B yes Figure 3 Schematic diagram of other read retry tables that may be shown in .

[0090] Reference Figure 3 , multiple memories 111, 112, 113, and 114 (collectively referred to as 110) can be obtained from the same wafer 300. As an example, Figure 3 Four memories 111 , 112 , 113 , and 114 are shown, each memory comprising one memory die (DIE).

[0091] The characteristics of the plurality of memories 110 obtained from the same wafer 300 may be different from each other. When the same read retry table is applied to the plurality of memories 110, the efficiency of the read retry operation in each memory 110 may be different. An embodiment of the present disclosure may provide a method for setting a read retry table in consideration of the characteristics of the read voltage of each of the plurality of memories 110. The read retry table set according to the method may be referred to as an optimal read retry table.

[0092] For example, the read retry value may be set based on a read voltage of a plurality of word lines WL included in each of the plurality of memories 110 . Figure 3 1 shows a read voltage distribution when each memory cell included in the memory 110 stores 3-bit data. As an example, Figure 3A case of checking distributions of a third read voltage RV3 and a seventh read voltage RV7 used when reading data of a least significant bit (LSB) page among 3-bit data of each memory cell is shown.

[0093] As an example, the second memory 112 is described, and the second memory 112 may include N word lines WL or more than N word lines WL. There may be differences between the word lines WL included in the second memory 112. The third read voltage RV3 and the seventh read voltage RV7 of each word line WL may be checked.

[0094] The read voltages of the first to Nth word lines WL1 to WLn may be checked. According to the distribution of the read voltages, the read voltage at the center of the region with the largest number of read voltage distributions may be set to a first read retry value RR1. The read voltage at the center of the region with the second largest number of read voltage distributions may be set to a second read retry value RR2.

[0095] The read retry value may be set based on the read voltage distribution of the N word lines WL included in the second memory 112. Since the read retry value is set based on the read voltage distribution of the word lines WL included in each memory 110, the efficiency of the read retry operation performed using the read retry table in which the corresponding read retry value is set for each memory 110 may be improved.

[0096] For example, an optimal read retry value that can cover all word lines WL of the corresponding memory 110 or as many word lines WL as possible can be obtained through a machine learning algorithm such as K-means clustering or neural network-based clustering. Figure 3 As shown, when clustering is performed, the center of each cluster can be obtained as a read retry value. The number of read retry values ​​can be determined according to the number of clusters.

[0097] Similar to the case of the second memory 112, a read retry value reflecting the characteristics of each memory 110 can be obtained based on the read voltage distribution of the word line WL included in each of the first memory 111, the third memory 113, and the fourth memory 114. A read retry table including the obtained read retry value can be generated. The generated read retry table can be stored in a block included in each memory 110.

[0098] For each memory 110 having different characteristics, a read retry table reflecting the characteristics of the corresponding memory 110 may be set. By using the read retry table, the efficiency of the read retry operation of each memory 110 may be improved.

[0099] The read retry values ​​included in the read retry table can be set for a plurality of conditions.

[0100] For example, a read retry value may be set for each of the plurality of first conditions. In addition, a read retry value may be set for each of the plurality of second conditions. The plurality of first conditions and the plurality of second conditions may correspond one to one. Optionally, each of the plurality of first conditions may correspond to at least two second conditions.

[0101] The read retry value may be set for each of the plurality of first conditions and each of the plurality of second conditions set for each of the plurality of first conditions.

[0102] For example, the plurality of first conditions may be a number of cycles. Here, a cycle represents a cycle of a write operation. The number of cycles represents the number of write operations performed on a memory cell. For example, the plurality of second conditions may be a retention period.

[0103] At least two retention periods may correspond to each of the plurality of cycle times.

[0104] A read retry table may be generated that sets optimal read retry values ​​for the number of cycles and the retention period.

[0105] The read retry table may be stored in a block included in each memory 110. The controller 120 may perform a read retry operation on the corresponding memory 110 by using the read retry table stored in the block of the memory 110.

[0106] Since the read retry operation is performed for each memory 110 by using the read retry table in which the optimum read retry value is set, it is possible to prevent the performance of the read retry operation from being degraded due to the difference between the memories 110 .

[0107] The read retry value of the read retry table may be set for each of at least two conditions, or the read retry value of the read retry table may be set for each of at least three conditions.

[0108] exist Figure 4A In the read retry table, the read retry value may include a read retry value set for each of the plurality of first conditions, each of the plurality of second conditions corresponding to each of the plurality of first conditions, and each of the plurality of third conditions corresponding to each of the plurality of second conditions.

[0109] For example, each first condition may be a cycle number. For example, each second condition may be a retention period. For example, each third condition may be a read disturbance number.

[0110] Each of the read retry values ​​may be set for the number of cycles, the retention period, and the number of read disturbances.

[0111] In other embodiments, at least one condition may be further added, such as the amount of change of the threshold voltage with temperature, to provide a read retry table for setting read retry values ​​for multiple conditions.

[0112] Since the optimal read retry value obtained for each memory (eg, die) is set and provided for each condition, a read retry operation based on a read retry table stored in each memory 110 may be performed to improve performance of the read retry operation.

[0113] Furthermore, even in the memory 110 , a read retry table can be generated by obtaining the optimum read retry value for groups having similar characteristic distributions.

[0114] exist Figure 4B In the embodiment, at least two retention periods may correspond to each cycle. At least two word line groups may correspond to the retention period. Figure 4B As shown, three retention periods correspond to each cycle, and three word line groups correspond to the retention periods.

[0115] In an embodiment, the word line group may include at least two word lines WL having similar characteristic distribution among the plurality of word lines WL. The at least two word lines WL having similar characteristic distribution may be adjacent to each other or separated from each other. Optionally, the word line group may include at least two adjacent word lines WL.

[0116] When the optimum read retry value is obtained and set for each cycle, each retention period, and each word line group, a read retry table may be generated.

[0117] Since the read retry value set for each word line group having a similar characteristic distribution is applied, even in the memory 110 , a read retry operation performance degradation due to a characteristic difference between the word lines WL is reduced.

[0118] The word line group is an example, and the group for setting the read retry value in the memory 110 may be set in various ways. For example, the read retry value may be set for each memory block group having at least two memory blocks included in the memory 110. Alternatively, the read retry value may be set for each page group including at least two pages.

[0119] In the process of obtaining the best read retry value for each memory such as a memory die, a read retry value may be obtained for each group having similar characteristics in the memory 110, such as a word line group or a memory block group. A read retry operation may be performed based on the read retry value, which reflects not only the characteristic difference between the dies but also the characteristic difference within the memory 110.

[0120] Even when the read retry value is set for each word line group or each memory block group, a read retry table that sets the read retry value for each of at least three conditions may be provided.

[0121] Furthermore, in some embodiments, read retry values ​​for condition combinations not included in the read retry table may be obtained to be applied to the read retry operation.

[0122] For example, a read retry value for a cycle number between cycle numbers 100 and 200 may be calculated to be applied to the read retry operation based on the read retry values ​​set for cycle numbers 100 and 200. Alternatively, a read retry value for a retention period not set for cycle number 1 may be obtained based on the read retry value set for a combination of the cycle number and the retention period and applied.

[0123] Since the read retry operation based on the read retry table that sets the optimum read retry value for each memory 110 is performed, it is possible to prevent the performance of the read retry operation from being degraded due to the die characteristic difference.

[0124] In addition, the read retry value for the unset condition combination can be calculated by learning the change of the set read retry value to be applied to the read retry operation.

[0125] In this way, the method of setting the optimal read retry table based on the read voltage distribution of the word line WL included in each memory 110 can be called a learning method. When the sampled data according to the read voltage distribution of the word line WL included in the memory 110 is sufficient, the optimal read retry table of the corresponding memory 110 can be obtained by the learning method.

[0126] When sample data according to the read voltage distribution of the word lines WL included in the memory 110 is insufficient, it may not be easy to obtain an optimal read retry table through a learning method.

[0127] Embodiments of the present disclosure may provide a method of setting an optimal read retry table suitable for characteristics of a corresponding memory 110 even when sampling data according to a read voltage distribution of a word line WL included in the memory 110 is insufficient.

[0128] A method of setting an optimal read retry table when sample data according to a read voltage distribution of word lines WL included in the memory 110 is insufficient may be referred to as a test method.

[0129] Figures 5 to 9 is a diagram illustrating another method of generating a read retry table of the storage device 100 based on an embodiment of the present disclosure.

[0130] Reference Figure 5, four memories 111, 112, 113 and 400 (collectively referred to as 110) obtained from the same wafer 300 are taken as an example for description. Figure 5 As shown, each memory may include one memory die. Embodiments of the present disclosure may be applied between memories 110 obtained from the same wafer 300 or different wafers.

[0131] Figure 5 This diagram shows a case where sufficient sample data of the read voltage of the word line WL of some memories 110 among the memories 110 obtained from the wafer 300 is ensured, while sufficient sample data of the read voltage of the word line WL of other memories 110 is not obtained.

[0132] exist Figure 5 In the embodiment, it is possible to sufficiently ensure the sampling data of the read voltage of the word line WL included in each of the first memory 111, the second memory 112, and the third memory 113. Since the sampling data of the read voltage of at least N word lines WL included in each of the first memory 111, the second memory 112, and the third memory 113 is ensured, a read retry table can be generated based on the corresponding sampling data.

[0133] An optimal read retry table may be generated based on the read voltage distribution of the word line WL in each of the first memory 111, the second memory 112, and the third memory 113. The read retry table may be one of the examples of the above-described read retry table.

[0134] Different from the first memory 111, the second memory 112, and the third memory 113, there may be a memory 110 for which the sampled data of the read voltage of the word line WL is not sufficiently ensured. The insufficiently ensured memory 110 may be referred to as a test memory 400, for example Figure 5 Memory die X.

[0135] The number of sample data of the read voltage of the word line WL included in the test memory 400 may be less than the number of sample data secured for the first memory 111. The accuracy of a read retry table that may be generated based on the sample data secured for the test memory 400 may not be high.

[0136] The embodiments of the present disclosure can generate an optimal read retry table for the test memory 400 using the distribution characteristics of the read voltage of the word line WL included in the test memory 400 and the read retry table of other memories 110 based on sufficient sampling data to generate the read retry table. Alternatively, the optimal read retry table for the test memory 400 can be generated using the sampling data of the memory 110, wherein the sampling data of the read voltage of the word line WL of the memory 110 is sufficiently ensured so that the read retry table can be generated.

[0137] Even when sample data of the read voltage of the word line WL included in each memory 110 is insufficient, a read retry table optimized for the corresponding memory 110 may be provided.

[0138] There are many ways to generate the optimal read retry table for testing the memory 400, such as Figures 6 to 9 shown.

[0139] exist Figure 6 In the embodiment, the optimal read retry table for the test memory 400 may be generated using the sampled data of the read voltage distribution of the word lines WL of the test memory 400 and the sampled data of the read voltage distribution of the word lines WL of the other memories 111 to 113 .

[0140] The first memory 111, the second memory 112, and the third memory 113 represent a case where the sampled data of the read voltage of the word line WL included in the corresponding memory 110 is sufficient. For example, the sampled data of the read voltage of at least N word lines WL included in each of the first memory 111, the second memory 112, and the third memory 113 may be provided. The sampled data of the read voltage may be represented by an offset value relative to a basic value.

[0141] Sample data of read voltages of word lines WL included in the test memory 400 may be provided. Sample data of read voltages of M word lines WL included in the test memory 400 may be provided. In one embodiment, M may be a value less than N.

[0142] An offset value according to a read voltage of a first word line WL1, an offset value according to a read voltage of a second word line WL2, ..., and an offset value according to a read voltage of an M-th word line WLm included in the test memory 400 may be provided. Some of the first word line WL1, the second word line WL2, and the M-th word line WLm may be continuous or discontinuous.

[0143] The offset value of the read voltage of the word line WL included in the test memory 400 may be compared with the offset value of the read voltage of the word line WL included in each of the first memory 111, the second memory 112, and the third memory 113. Although the description is made by taking the case where three memories 110 are compared with the test memory 400 as targets, the number of memories 110 as comparison targets is not limited.

[0144] Based on a difference between an offset value of a read voltage of a word line WL included in the test memory 400 and an offset value of a read voltage of a word line WL included in the first memory 111 , a read retry table of the test memory 400 may be set.

[0145] For example, the read retry table of the test memory 400 may be set based on an average or maximum value of Euclidean distances between offset values ​​of read voltages of word lines WL included in the test memory 400 and the first memory 111 .

[0146] The read retry table of the memory 110 having the smallest average or maximum value of the Euclidean distances between the test memory 400 and the remaining memories such as the first memory 111 , the second memory 112 , and the third memory 113 may be set as the optimal read retry table for the test memory 400 .

[0147] For example, when the average value of the Euclidean distance between the test memory 400 and the first memory 111 is the smallest, the read retry table set for the first memory 111 may be set as the read retry table of the test memory 400 .

[0148] The read retry table of the test memory 400 may be the same as the read retry table of the first memory 111 , and may be different from the read retry table of the second memory 112 and the read retry table of the third memory 113 .

[0149] The read voltage distribution of the memory 110 having the smallest Euclidean distance between the read voltage offset values ​​of the word lines WL of the memory 110 can be regarded as similar. When the sampling data of the read voltage of the word lines WL in the test memory 400 is insufficient, the read retry table generated for the memory 110 having the most similar read voltage distribution of the word lines WL and set based on the sufficient sampling data can be set as the read retry table of the test memory 400. The performance of the read retry operation based on the read retry table of the test memory 400 can be improved.

[0150] When comparing the read voltage distribution of the word line WL of the test memory 400 and the read voltage distribution of the word line WL of the first memory 111 , the word lines WL located in the same layer may be compared.

[0151] For example, an offset value of a p-th word line WLp among offset values ​​of read voltages of the M word lines WL included in the test memory 400 may be compared with an offset value of a q-th word line WLq among offset values ​​of read voltages of the N word lines WL included in the first memory 111. A layer where the p-th word line WLp in the test memory 400 is located may be the same as a layer where the q-th word line WLq in the first memory 111 is located. For example, an offset value of a read voltage of a first word line WL1 of the test memory 400 may be compared with an offset value of a read voltage of a first word line WL1 of each of the first memory 111, the second memory 112, and the third memory 113.

[0152] The read voltage of the word line WL of the test memory 400 may be compared with the read voltage of the word line WL located at the same layer as the layer where the corresponding word line WL of the test memory 400 is located in each of the first memory 111, the second memory 112, and the third memory 113. Since the offset values ​​of the read voltages of the word lines WL located at the same layer of the wafer 300 and thus having similar characteristics are compared, the memory 110 having a characteristic distribution similar to that of the test memory 400 may be easily selected.

[0153] In this way, based on the comparison result of the offset value of the read voltage of the M word lines WL of the test memory 400 and the offset value of each of the first memory 111, the second memory 112 and the third memory 113 that respectively ensures the offset value of the read voltage of at least N word lines WL, one of the read retry tables set for the first memory 111, the second memory 112 and the third memory 113 can be set as the read retry table of the test memory 400.

[0154] Alternatively, by comparing the read retry tables between the test memory 440 and the first memory 111 , an optimal read retry table for the test memory 400 may be set.

[0155] exist Figure 7 In the embodiment, an optimal read retry table of the first memory 111 may be set based on the sampled data of the read voltages of at least N word lines WL included in the first memory 111. The optimal read retry table of the first memory 111 may be referred to as a first external read retry table. Similarly, a second external read retry table and a third external read retry table may be set for the second memory 112 and the third memory 113, respectively, to ensure sufficient sampled data.

[0156] It is possible to ensure sample data of read voltages of the M word lines WL included in the test memory 400. A pre-read retry table may be set based on the sample data of the read voltages of the M word lines WL.

[0157] The pre-read retry table of the test memory 400 may be a read retry table set based on M sampling data.

[0158] The method for setting the pre-read retry table may be similar to the method for setting the read retry table described above. Clustering may be performed on the read voltages of the M word lines WL. According to the distribution of the read voltages, the read voltage at the center of the region with the largest number of read voltage distributions may be determined as the read retry value, and the pre-read retry table may be set.

[0159] Since the pre-read retry table is set based on the read voltage distribution of the insufficient M word lines WL, the accuracy of the read retry operation may not be high.

[0160] The pre-read retry table may be used to set an optimal read retry table for the test memory 400. The pre-read retry table may be compared with an external read retry table set for the first memory 111.

[0161] For example, an average value or a maximum value of Euclidean distances between the read retry values ​​included in the pre-read retry table and the read retry values ​​included in the external read retry table set for the first memory 111 may be calculated.

[0162] The Euclidean distance between the read retry values ​​corresponding to the same condition in the pre-read retry table of the test memory 400 and the external read retry table of the other memory 110 may be calculated.

[0163] For example, the first read retry value RR1 and the second read retry value RR2 set for the cycle number of 1 and the first retention period in the pre-read retry table can be compared with the first read retry value RR1 and the second read retry value RR2 set for the cycle number of 1 and the first retention period in the first external read retry table of the first memory 111.

[0164] The average or maximum value of the Euclidean distance between the read retry value of the pre-read retry table and the read retry value of the external read retry table under the same conditions can be calculated. The external read retry table with the smallest average or maximum value of the Euclidean distance can be set as the optimal read retry table for the test memory 400.

[0165] The pre-read retry table of the test memory 400 can be used to select the memory 110 having a distribution characteristic similar to the read voltage distribution of the word line WL of the test memory 400, and the optimal read retry table of the test memory 400 can be set by comparing the pre-read retry table with the external read retry table.

[0166] One of the external read retry tables of the first memory 1110 , the second memory 112 , and the third memory 113 may be set as an optimal read retry table for the test memory 400 .

[0167] Alternatively, without generating a pre-read retry table for the test memory 400 , an optimal read retry table for the test memory 400 may be set by comparing the read voltage distribution of the word lines WL of the test memory 400 with an external read retry table of each of the other memories 110 .

[0168] exist Figure 8 In the embodiment, the external read retry table may be set based on the read voltage distribution of the word lines WL included in the first memory 111 , the second memory 112 , and the third memory 113 .

[0169] Each of the first memory 111 , the second memory 112 , and the third memory 113 may store an external read retry table based on a read voltage distribution of sufficient word lines WL, such as at least N word lines WL.

[0170] The test memory 400 can ensure the sample data of the read voltage distribution of the M word lines WL, M is less than N. By comparing the offset value of the read voltage of the M word lines WL of the test memory 400 with the read retry value set in the external read retry table included in the first memory 111, an optimal read retry table can be set for the test memory 400.

[0171] For example, the average or maximum value of the Euclidean distances between the offset value of the read voltage of the word line WL of the test memory 400 and the read retry values ​​of the external read retry table of the first memory 111 , the second memory 112 , and the third memory 113 may be calculated respectively.

[0172] The Euclidean distance between the offset value of the read voltage of the word line WL of the test memory 400 and the read retry value set for the same condition in each external read retry table can be calculated. For example, the Euclidean distance between the M offset values ​​of the test memory 400 and the read retry value set for the first retention period with a cycle number of 1 in each external read retry table can be calculated.

[0173] Since the offset value of the read voltage of the word line WL of the test memory 400 is used, it may not be necessary to generate a pre-read retry table for the test memory 400 .

[0174] Since the offset value of the read voltage of the word line WL of the test memory 400 is compared with the read retry value of the external read retry table of the first memory 111, an external read retry table having a distribution characteristic similar to that of the read voltage of the word line WL of the test memory 400 can be selected.

[0175] By comparing the offset value of the read voltage of the word line WL of the test memory 400 with the external read retry table set for the other memories 110 , an optimal read retry table for the test memory 400 may be set.

[0176] Alternatively, in an embodiment of the present disclosure, an optimal read retry table for the test memory 400 may be set according to the read voltage distribution of the word lines WL of the test memory 400 without using sampled data or a pre-read retry table.

[0177] exist Fig. 9 In the example embodiment, an optimal read retry table for the memory 110 other than the test memory 400 may be set.

[0178] A first external read retry table may be provided for the first memory 111. A second external read retry table and a third external read retry table may be provided for the second memory 112 and the third memory 113, respectively.

[0179] The external read retry table set for each memory 110 may be stored in a block included in each memory 110 .

[0180] By applying the external read retry table set for the other memory 110 to the test memory 400 , a test for a read operation can be performed.

[0181] Since the read operation is performed by applying the external read retry table, when the read operation fails, a read retry operation based on the external read retry table can be performed. The read retry operation based on the external read retry table is performed, and the failure bit when each external read retry table is applied can be counted.

[0182] An external read retry table having the lowest fail bit count (FBC) among the respective external read retry tables may be set as an optimal read retry table for testing the memory 400 .

[0183] Since the read retry table of the test memory 400 is set by the fail bit count, the read retry table of the test memory 400 can be set without generating sample data of the read voltage distribution of the word lines WL included in the test memory 400 or a pre-read retry table based on the sample data.

[0184] In this way, in an embodiment of the present disclosure, by using internal data based on the read voltage of the word line WL of the test memory 400 (e.g., an offset value, a pre-read retry table, etc.) and external data based on the read voltage of the word lines of multiple external memories such as the first memory 111, the second memory 112, and the third memory 113 (e.g., an external read retry table, etc.), an optimal read retry table for the test memory 400 for which the sampling data according to the read voltage distribution of the word line WL is not sufficiently ensured can be set.

[0185] The optimal read retry table of the test memory 400 may be set as an external read retry table set for any one of the external memories such as the first memory 111. Alternatively, the optimal read retry table of the test memory 400 may be set as a combination of external read retry tables set for at least two external memories.

[0186] In an embodiment of the present disclosure, an optimal read retry table for the test memory 400 can be set by comparing the distribution characteristics of the read voltage of the word line WL of the test memory 400 with each word line group or each page included in the external memory, rather than with the external memory unit.

[0187] For example, when using a pre-read retry table of the test memory 400, the read retry values ​​corresponding to each word line group in the pre-read retry table can be compared with the read retry values ​​corresponding to each word line group included in the first memory 111, the second memory 112 and the third memory 113.

[0188] Since the read retry values ​​of the other memory 110 are combined according to the similarity between the read retry values, an optimal read retry table for the test memory 400 can be set.

[0189] For example, the read retry value of the first word line group of the test memory 400 may be set to the read retry value set for the first word line group in the first external read retry table of the first memory 111. The read retry value of the second word line group of the test memory 400 may be set to the read retry value set for the second word line group in the external read retry table of the second memory 112 or the third memory 113.

[0190] In addition, when each memory cell operates as a three-level cell, the read retry values ​​of the LSB / CSB / MSB pages can be set independently for each word line, so the read retry values ​​of different external memories can be set to the optimal read retry values.

[0191] In this way, according to an embodiment of the present disclosure, even when sampling data of the read voltage of the word line WL of the test memory 400 is insufficient, an optimal read retry table of the test memory 400 can be provided based on the external read retry table of other external memories.

[0192] Furthermore, since the read retry values ​​of the read retry table included in another external memory are partially combined in units of word line groups, in units of pages, or in units of word lines, an optimal read retry table for the test memory 400 can be provided, thereby improving the accuracy of setting the read retry table for the test memory 400. The efficiency of the read retry operation based on the corresponding read retry table can be improved.

[0193] The setting of the read retry table of the test memory 400 according to the embodiment of the present disclosure may be performed by the device of the test memory 110. The device of the test memory 110 may be configured by a system such as a computer, or may be provided in the form of a circuit such as a system on chip.

[0194] Fig.10 is a diagram showing a configuration and an operation scheme of a memory control device 1000 according to an embodiment of the present disclosure. Fig.10 An apparatus for providing an optimal read retry table for the memory 110 is shown implemented in circuit form.

[0195] Reference Fig.10 , the memory control device 1000 may perform an operation of generating an optimal read retry table of the memory 110 and storing the optimal read retry table in a block included in the memory 110. The memory control device 1000 may include a memory control circuit 2000. In some embodiments, the memory control circuit 2000 may be implemented by configuring the controller 120 of the memory device 100.

[0196] For example, when describing a structure in which the memory control circuit 2000 is implemented by being included in a separate memory control device 1000, the memory 110 may be connected to the memory control device 1000 including the memory control circuit 2000. Under the control of the memory control circuit 2000, an optimal read retry table for the memory 110 may be generated and stored in a block included in the memory 110.

[0197] In describing the basic functions of the components included in the memory control circuit 2000, the input / output control 2020 may receive data about a die, a cycle number, a memory block, and a word line WL from the outside. The data received by the input / output control 2020 may be stored in a die address register 2031, a block address register 2032, a word line address register 2033, and a cycle number address register 2034.

[0198] The data stored in the loop number address register 2034 may be transferred to the condition generation logic 2090. The condition generation logic 2090 may generate and output conditions such as the loop number, the retention period, or the read disturbance number. When the condition output by the condition generation logic 2090 passes through the reliability register 2080, the domain loop array 2071 and the domain retention array 2072 may be selected.

[0199] Based on the data stored in the die address register 2031, the domain die generation circuit 2051 may select the domain die array 2061. Based on the data stored in the block address register 2032, the domain block generation circuit 2052 may select the domain block array 2062. Based on the data stored in the word line address register 2033, the domain word line generation circuit 2053 may select the domain word line array 2063.

[0200] The optimal read retry table (RRT) generator 2040 may generate a read retry table setting an optimal read retry value for each condition based on the selected domain die array 2061 , domain block array 2062 , domain word line array 2063 , domain cycle array 2071 , and domain reserve array 2072 .

[0201] The command control logic 2010 may store the read retry table generated by the optimal read retry table generator 2040 in the memory 110 .

[0202] A read retry table that sets an optimal read retry value for each die, each block, or each word line for each condition provided by the condition generation logic 2090 may be stored in the memory 110 and thereafter may be used for a read retry operation of the corresponding memory 110 .

[0203] Furthermore, in the case where the memory control circuit 2000 is implemented as a partial configuration of the controller 120 of the memory device 100 , the memory control circuit 2000 may update the read retry table stored in the memory 110 .

[0204] In this way, the optimal read retry table of the memory 110 may be generated and provided by the optimal read retry table generator 2040 included in the memory control circuit 2000 .

[0205] The optimal read retry table generator 2040 may generate a read retry table using sufficient or insufficient sampled data of the read voltage of the word line WL of the memory 110. In addition, the optimal read retry table generator 2040 may obtain sampled data of the read voltage from the memory 110 or from the outside. In this case, the optimal read retry table generator 2040 may include a sampled data receiving unit that obtains sampled data of the read voltage from the memory 110 or from the outside. Alternatively, the sampled data receiving unit may be located outside the optimal read retry table generator 2040 and may be included in the memory control circuit 2000.

[0206] For example, as shown in case A, the optimal read retry table generator 2040 may obtain sample data of the read voltage of the word line WL from the memory 110 .

[0207] The optimal read retry table generator 2040 may obtain sufficient sample data from the memory 110 and may generate a read retry table based on the sufficient sample data. The generated read retry table may be stored in a block included in the memory 110 and may provide an optimal read retry table of the corresponding memory 110.

[0208] For another example, as shown in case B, the optimal read retry table generator 2040 may receive sample data of a read voltage of a word line WL included in the memory 110 from the outside.

[0209] When the sample data received from the outside is sufficient, the optimal read retry table generator 2040 may generate an optimal read retry table for the memory 110 based on the corresponding sample data.

[0210] When the sampling data received from the outside is insufficient, the optimal read retry table generator 2040 can generate an optimal read retry table for the corresponding memory 110 by comparing with the read voltage distribution of the word line WL included in another memory 110 that ensures sufficient sampling data or the read retry table of the other memory 110.

[0211] For example, the optimal read retry table generator 2040 may compare the number of received sample data of the word line WL with a preset value θ ( S1001 ).

[0212] When it is determined that the number of received sampled data of the word line WL is greater than or equal to the preset value θ, the optimal read retry table generator 2040 may generate an optimal read retry table for the memory 110 through a learning method, ie, a training phase, based on the sampled data.

[0213] When it is determined that the number of received sampled data of the word line WL is less than the preset value θ, the optimal read retry table generator 2040 can generate an optimal read retry table for the memory 110 through a test method, i.e., a test phase, by using the received sampled data and external data based on a read voltage of the word line WL of another external memory (S1003).

[0214] In both cases where the sampled data of the read voltage of the word line WL included in the memory 110 is sufficient or insufficient, the optimal read retry table generator 2040 included in the memory control circuit 2000 of the memory control device 1000 can provide an optimal read retry table reflecting the characteristics of the corresponding memory 110.

[0215] Since a read retry table reflecting the characteristics of each memory 110 can be provided by storing it in a block of the memory 110, the efficiency of the read retry operation using the read retry table can be improved, thereby improving the performance of the read operation of the storage device 100 including the corresponding memory 110.

[0216] Although various embodiments of the present disclosure have been described with specific details and varying details for the purpose of illustration, it will be understood by those skilled in the art that various modifications, additions and substitutions may be made based on the contents disclosed or described in the present disclosure without departing from the spirit and scope of the disclosed technology as defined in the appended claims. Therefore, the scope of the present disclosure should not be limited to the above-described embodiments, but should include equivalents thereof.

[0217] In the above-described embodiments, all operations may be selectively performed or some operations may be omitted. In each embodiment, the operations are not necessarily performed in the order described and may be rearranged. The embodiments disclosed in this specification and the accompanying drawings are only examples for facilitating understanding of the present disclosure, and the present disclosure is not limited thereto. In other words, it should be understood by those skilled in the art that various modifications may be made based on the technical scope of the present disclosure.

[0218] Embodiments of the present disclosure have been described in the drawings and the specification. Although specific terms are used herein, those terms are only used to describe embodiments of the present disclosure. Therefore, the present disclosure is not limited to the above-described embodiments, and many changes can be made within the scope of the present disclosure. It should be understood by those skilled in the art that, in addition to the embodiments disclosed herein, various modifications can also be made based on the technical scope of the present disclosure. In addition, the embodiments can be combined to form additional embodiments.

Claims

1. A storage device, comprising: a memory including a plurality of memory cells arranged between a plurality of word lines and a plurality of bit lines and storing a read retry table; as well as a controller that controls a read retry operation for the plurality of memory cells using the read retry table, the read retry table being determined using internal data and external data, wherein the internal data is determined based on a read voltage of M word lines among the plurality of word lines, M being greater than or equal to 1, and The external data is determined based on read voltages of at least N word lines included in each of the plurality of external memories, N being greater than M.

2. The storage device according to claim 1, wherein: The read retry table is determined based on a comparison result of a read voltage of a p-th word line among the M word lines and a read voltage of a q-th word line among the at least N word lines, and The layer where the p-th word line in the memory is located is the same as the layer where the q-th word line in each of the plurality of external memories is located.

3. The storage device according to claim 1, wherein: The read retry table is set based on a comparison result between the read voltages of the M word lines and a plurality of external read retry tables that are set based on the read voltages of the at least N word lines.

4. The storage device according to claim 1, wherein: The read retry table is set based on a comparison result of the pre-read retry table and a plurality of external read retry tables, The pre-read retry table is determined based on the read voltages of the M word lines, and The plurality of external read retry tables are determined based on read voltages of the at least N word lines.

5. The storage device according to claim 1, wherein: The read retry table is determined based on a failed bit count of the memory according to a read retry operation performed using a plurality of external read retry tables set based on read voltages of the at least N word lines.

6. The storage device according to claim 1, wherein: The read retry table is identical to one of the external read retry tables respectively stored in the plurality of external memories.

7. The storage device according to claim 1, wherein: The read retry table is the same as a first external read retry table stored in a first external memory among the plurality of external memories, and is different from a second external read retry table stored in a second external memory among the plurality of external memories.

8. The storage device according to claim 7, wherein: A read voltage distribution of a plurality of word lines included in the memory is different from a read voltage distribution of a plurality of word lines included in the first external memory.

9. The storage device according to claim 1, wherein: The first portion of the read retry table is identical to a portion of a first external read retry table stored in a first external memory among the multiple external memories, and the second portion of the read retry table is identical to a portion of a second external read retry table stored in a second external memory among the multiple external memories.

10. The storage device according to claim 1, wherein: Each of the plurality of external memories includes a block in which an external read retry table determined based on sampled data according to a read voltage distribution of the at least N word lines is stored.

11. The storage device according to claim 1, wherein: The read retry table includes at least one read retry value determined for each of a plurality of first conditions and each of a plurality of second conditions corresponding to each of the plurality of first conditions.

12. The storage device according to claim 11, wherein: The at least one read retry value is determined for a word line group including at least two word lines among the plurality of word lines.

13. A storage device, comprising: A first memory including a plurality of first word lines and a block, wherein the block stores a first read retry table determined based on read voltages of M first word lines among the plurality of first word lines, where M is greater than or equal to 1; as well as The second memory includes a plurality of second word lines and a block, wherein a second read retry table determined based on read voltages of at least N second word lines among the plurality of second word lines is stored in the block, where N is greater than M.

14. The storage device according to claim 13, wherein: The first read retry table is determined using internal data and external data, The internal data is determined based on the read voltages of the M first word lines, and The external data is determined based on read voltages of at least N word lines included in each of the plurality of external memories.

15. The memory device according to claim 13, further comprising a controller, the controller controlling the first memory and the second memory, controlling a read retry operation on the first memory using the first read retry table, and controlling a read retry operation on the second memory using the second read retry table.

16. A memory control device, comprising: A sampling data receiving unit receives sampling data of read voltages of K word lines from a memory or an external device, where K is greater than or equal to 1; as well as An optimal read retry table generator generates a read retry table of a memory including the K word lines based on the sampled data.

17. The memory control device according to claim 16, wherein: When K is greater than or equal to a preset number, the optimal read retry table generator generates a read retry table for the memory based on sampled data of the read voltages of the K word lines.

18. The memory control device according to claim 17, wherein: When K is less than the preset number, the optimal read retry table generator generates the read retry table by comparing the sampled data of the read voltages of the K word lines with the read voltages of word lines whose number is greater than or equal to the preset number, or comparing the sampled data of the read voltages of the K word lines with a read retry table generated based on the read voltages of word lines whose number is greater than or equal to the preset number.

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