Current balancing circuit and technique

Abstract

The invention relates to current balancing circuits and techniques. Current balancing techniques are disclosed. In an example, a circuit (100) includes a synchronization terminal (106), an error amplifier (114), and a clock generator (118). The error amplifier (114) is configured to generate a first control voltage signal (VC) based on a reference voltage (VREF) and a power converter output voltage (FB). The clock generator (118) is configured to generate an outgoing clock signal having an outgoing clock frequency. The circuit (100) further includes an encoder (116), a frequency detector (122), and a decoder (120). The encoder (116) is coupled to the clock generator (118) and a synchronization terminal (106) and is configured to encode the outgoing clock signal based on the first control voltage signal (VC) to provide an outgoing encoded clock signal at the synchronization terminal.

Description

Technical Field

[0001] The present description relates to power converters, and more particularly, to current balancing techniques for multi-phase power converters. Background Art

[0002] Many electronic applications utilize power management techniques to ensure that the power delivered to the application circuit system meets specific specifications. For example, the power management chip of a high-performance microprocessor requires efficient current driving capability with low output voltage ripple. A multiphase DC-DC converter has multiple parallel channels that distribute current equally, and can reduce output voltage ripple compared to a single-channel DC-DC converter. However, mismatches between components in multiple channels (e.g., power transistors, inductors, and controllers) can cause current imbalance and reduce efficiency. Therefore, current balancing can be used to distribute current equally and avoid channel burnout. There are still many important issues regarding current balancing. Summary of the invention

[0003] According to one example, a circuit that can be used for current balancing in a power converter is provided. In one example, the circuit includes: an error amplifier configured to generate a first control voltage signal based on a reference voltage and a power converter output voltage; a synchronization terminal; and a clock generator configured to generate an outgoing clock signal having an outgoing clock frequency. The circuit further includes an encoder coupled to the clock generator and the synchronization terminal, the encoder configured to encode the outgoing clock signal based on the first control voltage signal to provide an outgoing encoded clock signal at the synchronization terminal. The circuit further includes a frequency detector coupled to the synchronization terminal and configured to derive an incoming clock frequency from the incoming encoded clock signal. The circuit further includes a decoder coupled to the synchronization terminal and configured to derive a second control voltage signal from the incoming encoded clock signal.

[0004] According to another example, a multiphase DC-DC converter includes a first DC-DC converter and a second DC-DC converter. The first DC-DC converter includes a first input terminal for receiving an input voltage, a first synchronization terminal, a feedback terminal, and a first output terminal. The second DC-DC converter includes a second input terminal for receiving an input voltage, a second synchronization terminal coupled to the first synchronization terminal, and a second output terminal coupled to the first output terminal. The first DC-DC converter may include: an amplifier having an input terminal coupled to the feedback terminal; a clock generator; a level shifter having an input coupled to the output of the clock generator and the output of the amplifier and an output coupled to the first synchronization terminal. The second DC-DC converter may include: a frequency detector coupled to the second synchronization terminal; an envelope detector coupled to the second synchronization terminal; and a control circuit coupled to the frequency detector and the envelope detector.

[0005] According to another example, a multiphase DC-DC converter system includes a first DC-DC converter and a second DC-DC converter. The first DC-DC converter includes a first input terminal for receiving an input voltage, a first synchronization terminal, a feedback terminal, and a first output terminal. The second DC-DC converter includes a second input terminal for receiving an input voltage, a second synchronization terminal coupled to the first synchronization terminal, and a second output terminal coupled to the first output terminal. In one example, the first DC-DC converter includes: an amplifier having an input terminal coupled to a feedback terminal; a clock generator; and a ramp generator coupled to a clock output terminal of the clock generator. The first DC-DC converter may further include a comparator having a first comparator input terminal coupled to an amplifier output terminal of the amplifier, a second comparator input terminal coupled to a ramp output terminal of the ramp generator, and a comparator output terminal coupled to the first synchronization terminal. In one example, the second DC-DC converter further includes a frequency detector coupled to the second synchronization terminal, a low-pass filter coupled to the second synchronization terminal, and a control circuit coupled to the frequency detector and the low-pass filter. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1A is a block diagram of an integrated circuit that includes current balancing circuitry in an example.

[0007] Figure 1B is a block diagram of a DC-DC converter including current balancing circuitry in an example.

[0008] Figure 2 is a block diagram of a multi-phase DC-DC converter including current balancing circuitry in an example.

[0009] Figure 3 is a schematic diagram showing a current balancing circuit system in a multi-phase DC-DC converter in an example.

[0010] Figure 4 To show in the example Figure 3 Timing diagram of various signals in the circuit system.

[0011] Figure 5 FIG. 1 is a schematic diagram showing a current balancing circuit system in a multi-phase DC-DC converter in another example.

[0012] Figure 6 To show in the example Figure 5 Timing diagram of various signals in the circuit system. DETAILED DESCRIPTION

[0013] The present invention describes techniques for current balancing. The techniques can be used in a variety of circuits including, for example, multiphase power converters, such as multiphase DC-DC converters. As described in more detail below, some examples take advantage of the synchronous timing signal used in the multiphase power converter as a carrier to pass current balancing information from one device to another. This method can avoid the complexity associated with some other current balancing methods and can be advantageously applied in multiphase DC-DC converters using internal compensation components.

[0014] In some embodiments, a circuit includes a synchronization terminal, an error amplifier and a clock generator. The error amplifier is configured to generate a first control voltage signal based on a reference voltage and a power converter output voltage. The clock generator is configured to generate an outgoing clock signal with an outgoing clock frequency. The outgoing clock signal can be used to synchronize the timing of current transfer from multiple power converters in a multi-phase power converter system. As further described below, in some instances, the circuit further includes an encoder coupled to the clock generator and the synchronization terminal. The encoder is configured to encode the outgoing clock signal based on the first control voltage signal to provide an outgoing encoded clock signal at the synchronization terminal. In some instances, in addition to or in place of the encoder, the circuit also includes a frequency detector and a decoder. The frequency detector is coupled to the synchronization terminal and is configured to derive the incoming clock frequency from the incoming encoded clock signal. The decoder is coupled to the synchronization terminal and is configured to derive the second control voltage signal from the incoming encoded clock signal. In a multi-phase power converter, for example, the second control voltage can be used by one or more auxiliary power converters to replicate the current generated by the main power converter so as to achieve current balance between two (or more) power converters.

[0015] General Overview

[0016] Many important issues are related to current balancing in multiphase circuits, such as multiphase power converters. A possible current balancing technique in a multiphase DC-DC converter may involve detecting current magnitude and calculating average current. The difference between the magnitude (or phase) of the current in each channel and the calculated average current may then be used to generate a current error signal. This current error signal may be added to the voltage error signal to control the output voltage in each channel and correct the current imbalance. However, combining the output voltage regulation and current balancing control of the voltage error signal makes the control more complicated. Another method may involve connecting the error amplifier outputs of each channel together to share a common control voltage. However, this method will also involve the use of an external trimming circuit because the conversion ratio from the control voltage to the corresponding inductor current is usually unique for each channel. In addition, some multiphase power converters are internal compensation devices, in which the control voltage is not presented at the external pin. This control voltage sharing method is therefore incompatible with such devices.

[0017] Thus, current balancing circuits are described herein that avoid the complexity associated with some other approaches and provide solutions that are compatible with internal compensation devices. As described in more detail below, examples of current balancing circuits and methods described herein can be configured to take advantage of an internal synchronization (clock) signal that is used to share timing information between channels in a multiphase power converter to encode control voltage information that can be used to accurately (or otherwise adequately for a given application) replicate the inductor current between channels. Various encoding methods can be used, including amplitude modulation or duty cycle modulation (e.g., pulse width modulation) of the clock signal. These encoding techniques can be applied to transmit control voltage information from one device to another without compromising or otherwise disrupting the synchronous transmission of timing (e.g., clock frequency) information. Complementary decoding methods can be used to extract encoded control voltage information that can then be used by a receiving device to replicate the current, as further described below.

[0018] Current balancing circuit and method

[0019] Figure 1A 1 is a block diagram of a device 100 that includes a current balancing circuit 112 in one example. For example, the device 100 can be a power converter such as a DC-DC power converter (e.g., a buck or boost converter). In some examples, the device 100 is an integrated circuit. The device 100 includes a circuit that receives an input voltage V IN voltage input terminal 102, and the device provides an output voltage V thereat OUT 104. In the example shown, the device 100 further includes a synchronization (SYNC) terminal 106 at which a clock signal can be received and / or provided, as further described below. In addition, in some examples, the device 100 includes: a feedback (FB) terminal 108, which can be coupled to an error amplifier, as further described below; and a switch (SW) terminal 110. In an example where the device 100 is used in a multi-phase power converter, the switch terminal 110 can be coupled to an inductor in which a corresponding channel current is generated. The multi-phase power converter may include a plurality of individually stackable single-phase power converters (e.g., buck converters, boost converters, etc.).

[0020] Figure 1B An example of a device 100 is shown that includes a current balancing circuit 112 in one example. In this example, the device 100 includes an error amplifier 114 having a first amplifier input coupled to the FB terminal 108, as described above. The error amplifier 114 also has a second amplifier input coupled to a reference terminal to receive a reference voltage V REFThe error amplifier 114 may be configured to compare the signal received via the FB terminal 108 with a reference voltage V REF 106. The current balancing circuit 112 includes an encoder 116 coupled between an amplifier output terminal of the error amplifier 114 and the SYNC terminal 106. A clock generator 118 may be coupled to the encoder 116. As described in more detail below, the encoder 116 may be configured to encode information corresponding to the control voltage VC onto a clock signal generated by the clock generator 118 to generate an encoded outgoing clock signal at the SYNC terminal 106.

[0021] exist Figure 1B In an example of the present invention, the current balancing circuit 112 further includes a decoder 120 coupled to the SYNC terminal 106 and a frequency detector 122 also coupled to the SYNC terminal 106. The decoder 120 can be used to decode an incoming encoded clock signal (e.g., from another device 100) to extract control voltage information, as further described below. The frequency detector 122 can be used to recover the clock frequency of the incoming encoded clock signal, as further described below. The outputs of the decoder 120 and the frequency detector 122 are coupled to the control circuit 124. In some examples, the control circuit is configured to control at least some functions of the device 100 based on the control voltage information and the clock frequency derived from the incoming encoded clock signal.

[0022] In some examples, depending on the configuration of the device 100 in a larger circuit or system, the encoder 116 or the combination of the decoder 120 and the frequency detector 122 may be enabled. For example, if the device 100 is configured as a primary power converter in a multi-phase power converter system, the encoder 116 may be enabled, while at least some functions of the decoder 120, the frequency detector 122, and the control circuit 124 may be disabled. In such cases, the device 100 may be configured to generate an outgoing encoded clock signal at the SYNC terminal 106. In another example, if the device 100 is configured as an auxiliary power converter in a multi-phase power converter system, the encoder 116 may be disabled, while the decoder 120, the frequency detector 122, and the control circuit 124 may be enabled. In such cases, the device 100 may be configured to receive an incoming encoded clock signal at the SYNC terminal 106 and derive a control voltage VC and a clock frequency from the incoming encoded clock signal. Providing a device 100 with both an encoder 116 and a decoder 120 may allow flexibility in device configuration and use, as noted above. However, in other examples, the device 100 may be constructed to include either the encoder 116 or the decoder 120 but not both. Figure 1B Various additional components and / or circuitry are not shown and / or may be otherwise configured in a different manner.

[0023] As described above, one application for the device 100 is a multiphase power converter, such as a multiphase DC-DC converter. In modern computing environments, various devices including central processing units (CPUs), field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), and / or peripheral devices have become more complex, which in some cases increases their power delivery needs. Multiphase power converters can have several advantages in being able to deliver greater power with smaller transients, reducing input and / or output capacitance, and / or improving thermal performance and efficiency at higher load currents compared to some high-power single-phase designs.

[0024] Figure 2 is a block diagram of a multiphase DC-DC converter 200 in an example. The multiphase DC-DC converter 200 includes a plurality of power converters 208 and 210 (e.g., buck or boost converters) coupled together in parallel between a system voltage input terminal 202 and a system voltage output terminal 204. A load 206 is coupled to the system voltage output terminal 204. Figure 2 In the example of , the multiphase DC-DC converter 200 includes two power converters 208, 210; however, in other examples, the multiphase DC-DC converter 200 may include additional power converters, for example, 6, 8, 12 or more power converters coupled in parallel. Thus, the individual voltage input terminals 102 of the power converters 208, 210 are coupled to the system voltage input terminal 202, and the individual voltage output terminals 104 of the power converters 208, 210 are coupled to the system voltage output terminal 204. The individual power converters may be referred to as "phases", and each phase may include a set of power transistors, such as power MOSFETs (e.g., Figure 2 During steady-state operation, the individual power converters are active at phase intervals equally spaced 360° / n during a switching cycle, where n is the number of power converters in the system. Figure 2 In the arrangement of , power converters 208, 210 generate respective output currents that are 180° out of phase. In some examples, power converters 208 and / or 210 may be implemented using the apparatus 100 described above. The switching period is determined by the switching frequency of the multi-phase DC-DC converter 200.

[0025] The parallel connected power converter group, in this case power converters 208 and 210, share a common output capacitor 212 coupled to the system voltage output terminal 204. In some examples, the power converters 208, 210 may also share a common input capacitor ( Figure 2204 via a voltage divider that includes a pair of resistors 214, 216 coupled in series between the system voltage output terminal 204 and a reference terminal (e.g., a ground terminal). In addition, the individual SW terminals 110 of the power converters 208, 210 are coupled to the system input voltage terminal 202 via respective inductors 218, 220, as shown in FIG. Figure 2 as shown in .

[0026] According to some embodiments, a power converter, such as Figure 2 The power converter 208 in the example of FIG. 1 is shown as the main power converter, while the remaining power converters (in Figure 2 The power converter 210 in the example of FIG. 1 is shown as an auxiliary (slave) power converter. Figure 2 In the example of , only one auxiliary power converter 210 is shown; however, in other examples, the multi-phase DC-DC converter 200 may include any number of additional auxiliary power converters. The main power converter 208 generates a control voltage VC, which sets the characteristics or parameters of the output current to be supplied to the load 206. The auxiliary power converter 210 replicates the output current of the phase shift as described above. Therefore, in some examples, the auxiliary power converter 210 receives information from the main power converter 208 to replicate the control voltage VC, and thus generates an output current balanced with the output current generated by the main power converter 208.

[0027] like Figure 2 As shown, the SYNC terminals 106 of the main power converter 208 and the auxiliary power converter 210 are coupled together so that the auxiliary power converter 210 can receive information from the main power converter 208 via the SYNC terminal 106. In some examples, the main power converter 208 includes an encoder 116 coupled to the SYNC terminal 106 and configured to encode the clock signal with the control voltage information to generate an encoded clock signal, as described above with reference to Figure 1B The auxiliary power converter 210 includes a decoder 120 coupled to the SYNC terminal 106 and configured to extract control voltage information from the encoded clock signal, as described above with reference to Figure 1B described.

[0028] In some examples of implementing the main power converter 208 and the auxiliary power converter 210 using the device 100, both the main power converter 208 and the auxiliary power converter 210 may include both the encoder 116 and the decoder 120, along with Figure 1B. In such cases, in the main power converter 208, the decoder 120 may be disabled, while in the auxiliary power converter 210, the encoder 116 may be disabled. Thus, while for simplicity the main power converter 208 is shown and described as including circuitry associated with encoding functionality, the main power converter 208 may also include circuitry associated with decoding functionality that is not used when the device is configured as the main power converter 208. Similarly, while for simplicity the auxiliary power converter 210 is shown and described as including circuitry associated with decoding functionality, the auxiliary power converter 210 may also include circuitry associated with encoding functionality that is not used when the device is configured as the auxiliary power converter 208.

[0029] According to some examples, the main power converter 208 uses amplitude modulation to encode the control voltage information onto the clock signal. An example of this method is Figure 3 Shown in. Figure 4 To illustrate the Figure 3 A timing diagram of an example of signals generated in a circuit system.

[0030] See also Figure 3 In one example, the main power converter 208 includes an error amplifier 114 that generates an error signal based on a signal received via the FB terminal 108 and a reference voltage V REF The combination of generates a control voltage VC; and encoder 116. An example of the control voltage VC is Figure 4 The main power converter 208 further includes a clock generator 118 that generates a clock signal 302. In some examples, the clock signal 302 is a square wave signal, such as Figure 4 As shown, its frequency is consistent with the switching frequency of the multi-phase DC-DC converter 200. The encoder 116 is coupled to the outputs of the error amplifier 114 and the clock generator 118.

[0031] In this example, encoder 116 includes a level shifter 304, a multiplier 306, and a bias voltage adjustment element 308. Multiplier 306 and bias voltage adjustment element 308 together form a first voltage regulator that operates on control voltage VC output from error amplifier 114 to generate modulation signal 310. An example of modulation signal 310 is shown in FIG. Figure 4. In one example, multiplier 306 multiplies control voltage VC by constant k. Constant k can be any positive integer or non-integer value. In some examples, multiplier 306 is used to provide noise immunity by increasing the voltage level of the control voltage VC signal before the control voltage VC signal is used to modulate clock signal 302. Bias voltage adjustment element 308 superimposes the bias voltage on the control voltage VC signal whose level is adjusted (e.g., multiplied by k) to generate modulation signal 310.

[0032] In some examples, the level shifter 304 level shifts the clock signal 302 and modulates the amplitude of the level-shifted clock signal 302 to generate the encoded clock signal 312. Prior to modulation with the modulation signal 310, the level shifter 304 increases the amplitude (level shift) of the clock signal 302 so that the applied amplitude modulation does not cause the high level of the square wave (e.g., corresponding to a logic 1) to potentially drop so low that it is confused with the low level (e.g., corresponding to a logic 0), which could cause a frequency error in the auxiliary power converter 210. The encoded clock signal 312 generated at the SYNC terminal 106 of the main power converter 208 thus has a voltage that is proportional to the control voltage VC and superimposed with the bias voltage Vbias. In an example, the amplitude modulation affects only the high level of the square wave, and thus the encoding of the control voltage information does not change the frequency of the clock signal 302. An example of the encoded clock signal 312 is shown in FIG. Figure 4 Shown in.

[0033] Still viewing Figure 3 In this example, the auxiliary power converter 201 includes a frequency detector 122, a decoder 120, and a control circuit 124. The frequency detector 122 is coupled to the SYNC terminal 106 of the auxiliary power converter 210, which is coupled to the SYNC terminal 106 of the main power converter 208, as shown in FIG. Figure 2 . The frequency detector 122 is configured to recover the frequency of the clock signal 302 from the encoded clock signal 312. To achieve this function, in one example, the frequency detector 122 includes a threshold detection circuit that can be configured to detect the rising edge or the falling edge of the pulse in the square wave and thereby recover the frequency.

[0034] According to certain examples, the decoder 120 includes an envelope detector 314, a bias voltage adjustment element 316, and a divider 318. The envelope detector 314 is coupled to the SYNC terminal 106 and receives the encoded clock signal 312. The envelope detector recovers the voltage envelope of the encoded clock signal, thereby generating a signal having a voltage proportional to the control voltage VC of the main power converter 208 and superimposed with the bias voltage Vbias. Therefore, the bias voltage adjustment element 316 is configured to subtract the bias voltage Vbias from the signal output by the envelope detector. The divider 318 can divide the resulting signal output from the bias voltage adjustment element 316 by a constant k. Therefore, the bias voltage adjustment element 316 and the divider 318 together form a second voltage regulator, which can recover the control voltage VC of the main power converter 208 using the envelope detector 314.

[0035] In some examples, the recovered control voltage VC and the recovered frequency of the clock signal 302 are input to the control circuit 124. Using this information, the control circuit can control the various components and circuitry of the auxiliary power converter 210 to produce an output current that accurately or otherwise substantially replicates (e.g., within a tolerance of 5% or less) the current output by the main power converter 208.

[0036] According to another example, the main power converter 208 encodes the control voltage information onto the clock signal 302 by modulating the duty cycle of the clock signal 302 instead of the amplitude. Figure 5 Shown in. Figure 6 To illustrate the Figure 5 A timing diagram of an example of signals generated in a circuit system.

[0037] See also Figure 5 In this example, the encoder 116 in the primary device 208 includes a ramp generator 502 coupled to the output of the clock generator 118 and configured to generate a ramp signal 504 based on the clock signal 302. In one example, the ramp signal 504 has a voltage Vm, such as Figure 6 The encoder 116 further includes a multiplier 306 and a bias voltage adjustment element 308 that together generate a modulation signal 310, as described above with reference to Figure 3 Therefore, the modulation signal 310 has a voltage Ve that is proportional to the control voltage VC and superimposed with the bias voltage Vbias, as shown in FIG. Figure 6 as shown in .

[0038] exist Figure 5In the example of , the encoder 116 further includes a comparator 506 having one input coupled to the output of the ramp generator 502 and another input coupled to the output of the bias voltage adjustment element 308. The comparator 506 can be configured to compare the voltage Ve of the modulation signal 310 with the voltage Vm of the ramp signal 502 to generate the encoded clock signal 508. In one example, the encoded clock signal 508 is a square wave signal with a variable duty cycle, such as Figure 6 The frequency 602 of the encoded clock signal 508 is the same as the frequency of the clock signal 302 because the ramp signal 504 is generated based on the clock signal 302. However, the duty cycle is modulated by the modulation signal 310 to encode the control voltage VC. Figure 6 As shown, in this example, the duty cycle increases (more time at a high or logic 1 level) as voltage Ve increases (and therefore as VC increases).

[0039] Furthermore, in this example, the auxiliary power converter 210 includes a frequency detector 122 coupled to the SYNC terminal 106, as described above. Since the frequency of the encoded clock signal 508 corresponds to the frequency of the clock signal 302, the frequency detector 122 can recover the frequency of the clock signal 302, as described above. The control circuit 124 can use the recovered frequency to synchronize the timing of the operation of the auxiliary power converter with the main power converter 208, as described above. Figure 3 The situation in the example.

[0040] In some examples, the decoder 120 includes a low pass filter 510 and a bias voltage adjustment element 316, and a divider 318. The low pass filter 510 is coupled to the SYNC terminal 106 and filters the encoded clock signal 508 to recover a signal representing the modulation signal 310, and thus has a voltage proportional to the control voltage VC of the main power converter 208 and superimposed with the bias voltage Vbias. Therefore, the bias voltage adjustment element 316 is configured to subtract the bias voltage Vbias from the signal output by the low pass filter 510. The divider 318 can divide the resulting signal output from the bias voltage adjustment element 316 by a constant k, as described above. Therefore, the decoder 120 can recover the control voltage VC of the main power converter 208, which can then be provided to the control circuit 124.

[0041] As described above, the control circuit can use the recovered control voltage VC and the frequency of the clock signal 302 to control various components and circuit systems of the auxiliary power converter 210 to produce an output current that accurately or otherwise sufficiently replicates (e.g., within a tolerance of 5% or less) the current output by the main power converter 208.

[0042] Thus, using amplitude or duty cycle modulation, the clock signal 302 of the main power converter 208 can be programmed with the control voltage of the main power converter 208 and used to communicate the control voltage information to the auxiliary power converter 210 (and any additional auxiliary power converters that may be used in the multi-phase DC-DC converter 200). In this way, accurate current balancing can be achieved between the individual power converters of the multi-phase DC-DC converter 200 without the need for complex control schemes or external pins / terminals to access the control voltages.

[0043] Other Examples

[0044] Example 1 is a circuit comprising: an error amplifier configured to generate a first control voltage signal based on a reference voltage and a power converter output voltage; a synchronization terminal; a clock generator configured to generate an outgoing clock signal having an outgoing clock frequency; and an encoder coupled to the clock generator and the synchronization terminal, the encoder configured to encode the outgoing clock signal based on the first control voltage signal to provide an outgoing encoded clock signal at the synchronization terminal. In this example, the circuit further comprises: a frequency detector coupled to the synchronization terminal and configured to derive an incoming clock frequency from an incoming encoded clock signal; and a decoder coupled to the synchronization terminal and configured to derive a second control voltage signal from the incoming encoded clock signal.

[0045] Example 2 includes the circuit of Example 1, further comprising a control circuit coupled to the frequency detector and the decoder and configured to control the DC-DC converter based on the second control voltage signal and the incoming clock frequency.

[0046] Example 3 includes the circuit of one of Examples 1 or 2, wherein the encoder is configured to modulate at least one of an amplitude of the outgoing clock signal or a duty cycle of the outgoing clock signal based on the first control voltage signal to generate the outgoing encoded clock signal.

[0047] Example 4 includes the circuit of any of Examples 1-3, wherein the encoder comprises a level shifter configured to modulate an amplitude of an outgoing clock signal based on the first control voltage signal to generate an outgoing encoded clock signal.

[0048] Example 5 includes the circuit described in Example 4, wherein the encoder includes a voltage regulator coupled to the output of the error amplifier and the level shifter, the voltage regulator is configured to generate a modulation signal by superimposing a bias voltage on the first control voltage signal, and wherein the level shifter is configured to modulate the amplitude of the clock signal based on the modulation signal.

[0049] Example 6 includes the circuit of Example 5, wherein the voltage regulator is a first voltage regulator, and wherein the decoder includes an envelope detector and a second voltage regulator coupled to an output of the envelope detector and configured to subtract a bias voltage from a signal output by the envelope detector to recover a second control voltage signal.

[0050] Example 7 includes the circuit of Example 6, wherein the first voltage regulator multiplies the amplitude of the first control voltage signal by a constant to generate a modulation signal, and the second voltage regulator divides by the constant to restore the second control voltage signal.

[0051] Example 8 includes the circuit of Example 4, wherein the decoder comprises an envelope detector.

[0052] Example 9 includes the circuit of any one of Examples 1 to 3, wherein the encoder comprises: a ramp generator coupled to the clock generator and configured to generate a ramp signal based on an outgoing clock signal; and a comparator configured to compare the ramp signal with a modulation signal to generate an outgoing encoded clock signal, wherein the modulation signal is based on a first control voltage signal.

[0053] Example 10 includes the circuit of Example 9, wherein the decoder comprises a low pass filter.

[0054] Example 11 includes the circuit of Example 10, wherein the encoder includes a voltage regulator coupled to the output of the error amplifier and configured to generate the modulation signal by superimposing a bias voltage on the first control voltage signal.

[0055] Example 12 includes the circuit of Example 11, wherein the voltage regulator is a first voltage regulator and the decoder includes a second voltage regulator coupled to the output of the low pass filter and configured to subtract a bias voltage from a signal output from the low pass filter to recover a second control voltage signal.

[0056] Example 13 includes the circuit of Example 12, wherein the first voltage regulator multiplies the amplitude of the first control voltage signal by a constant to generate the modulation signal, and the second voltage regulator divides by the constant to recover the second control voltage signal.

[0057] Example 14 includes the circuit of any of Examples 1-13, wherein the frequency detector includes a threshold detection circuit.

[0058] Example 15 includes the circuit of any of Examples 1-14, wherein the first control voltage signal is associated with the first current, the second control voltage signal is associated with the second current, and the second current matches the first current within a tolerance of 5% or less.

[0059] Example 16 includes the circuit of any of Examples 1-15, wherein the first control voltage signal is associated with the first current, the second control voltage signal is associated with the second current, and the second current is 180 degrees out of phase with the first current within a tolerance of 2 degrees.

[0060] Example 17 is a multi-phase DC-DC converter including the circuit of any one of Examples 1 to 16.

[0061] Example 18 includes the multiphase DC-DC converter of Example 17, wherein the multiphase DC-DC converter includes at least one buck converter.

[0062] Example 19 is a multi-phase DC-DC converter system, which includes a first DC-DC converter having a first input terminal for receiving an input voltage, a first synchronization terminal, a feedback terminal, and a first output terminal. The first DC-DC converter includes: an amplifier having an input terminal coupled to the feedback terminal; a clock generator; and a level shifter having an input coupled to the output of the clock generator and the output of the amplifier and an output coupled to the first synchronization terminal. The multi-phase DC-DC converter further includes a second DC-DC converter having a second input terminal for receiving an input voltage, a second synchronization terminal coupled to the first synchronization terminal, and a second output terminal coupled to the first output terminal. The second DC-DC converter includes: a frequency detector coupled to the second synchronization terminal; an envelope detector coupled to the second synchronization terminal; and a control circuit coupled to the frequency detector and the envelope detector.

[0063] Example 20 includes the system described in Example 19, wherein the first DC-DC converter is configured to generate a first output signal having an output voltage and a first current at a first output terminal; and wherein the control circuit is configured to control the second DC-DC converter to generate a second output signal having an output voltage and a second current at a second output terminal, the second current being phase-shifted relative to the first current.

[0064] Example 21 includes the system of Example 20, wherein the phase shift is 180° with a tolerance within 2°.

[0065] Example 22 includes the system of any of Examples 19 to 21, wherein the amplifier is configured to generate a control voltage based on a signal received at a feedback terminal; wherein the clock generator is configured to generate a clock signal having a clock frequency; and wherein the level shifter is configured to generate a synchronization signal at a first synchronization terminal based on the clock signal and the control voltage.

[0066] Example 23 includes the system described in Example 22, wherein the frequency detector is configured to recover a clock frequency from a synchronization signal; and wherein the control circuit is configured to synchronize a second output signal generated at a second output terminal of the second DC-DC converter with a first output signal generated at a first output terminal of the first DC-DC converter based on the clock frequency.

[0067] Example 24 includes the system of one of examples 22 or 23, wherein the first DC-DC converter comprises a first voltage regulator coupled between the amplifier and the level shifter.

[0068] Example 25 includes the system of Example 24, wherein the second DC-DC converter includes a second voltage regulator coupled to the envelope detector, and wherein the envelope detector and the second voltage regulator are configured to recover the control voltage from the synchronization signal.

[0069] Example 26 includes the system of Example 25, wherein the first voltage regulator comprises: a multiplier configured to multiply the control voltage by a constant to generate a modified control voltage; and a summing block configured to superimpose the bias voltage on the modified control voltage.

[0070] Example 27 includes the system of Example 26, wherein the second voltage regulator comprises: a subtraction block configured to subtract the bias voltage from the signal output by the envelope detector to generate an intermediate signal; and a divider configured to divide the intermediate signal by a constant to recover the control voltage.

[0071] Example 28 is a multi-phase DC-DC converter system, which includes a first DC-DC converter having a first input terminal for receiving an input voltage, a first synchronization terminal, a feedback terminal, and a first output terminal. The first DC-DC converter includes: an amplifier having an input terminal coupled to the feedback terminal; a clock generator; a ramp generator coupled to a clock output terminal of the clock generator; and a comparator having a first comparator input terminal coupled to an amplifier output terminal of the amplifier, a second comparator input terminal coupled to a ramp output terminal of the ramp generator, and a comparator output terminal coupled to the first synchronization terminal. The system further includes a second DC-DC converter having a second input terminal for receiving an input voltage, a second synchronization terminal coupled to the first synchronization terminal, and a second output terminal coupled to the first output terminal. The second DC-DC converter includes a frequency detector coupled to the second synchronization terminal, a low-pass filter coupled to the second synchronization terminal, and a control circuit coupled to the frequency detector and the low-pass filter.

[0072] Example 29 includes the system of Example 28, wherein the first DC-DC converter further comprises a first voltage regulator coupled between the amplifier and the first comparator input terminal.

[0073] Example 30 includes the system of Example 29, wherein the second DC-DC converter comprises a second voltage regulator coupled between a filter output terminal of the low pass filter and the control circuit.

[0074] Example 31 includes the system of any of Examples 28 to 30, wherein the amplifier is configured to generate a control voltage based on a signal received at a feedback terminal, wherein the clock generator is configured to generate a clock signal having a clock frequency, and wherein the ramp generator is configured to generate a ramp signal based on the clock signal.

[0075] Example 32 includes the system of Example 31, wherein the comparator is configured to generate a synchronization signal at the first synchronization terminal based on the control voltage and the ramp signal.

[0076] Example 33 includes the system of Example 32, wherein the low pass filter is configured to filter the synchronization signal to recover the control voltage.

[0077] Example 34 includes the system of Example 33, wherein the frequency detector is configured to recover the clock frequency based on the synchronization signal.

[0078] Example 35 includes the system described in Example 34, wherein the first DC-DC converter is configured to generate a first output signal having an output voltage and a first current at a first output terminal, and wherein the control circuit is configured to control the second DC-DC converter based on a clock frequency and a control voltage to generate a second output signal having an output voltage and a second current at a second output terminal, wherein the second current is phase-shifted relative to the first current.

[0079] Example 36 is a circuit comprising: an error amplifier configured to generate a first control voltage signal based on a reference voltage and a power converter output voltage; a synchronization terminal; a clock generator configured to generate an outgoing clock signal having an outgoing clock frequency; and an encoder coupled to the clock generator and the synchronization terminal, the encoder configured to encode the outgoing clock signal based on the first control voltage signal to provide an outgoing encoded clock signal at the synchronization terminal.

[0080] Example 37 is a circuit comprising: a synchronization terminal; a frequency detector coupled to the synchronization terminal and configured to derive an incoming clock frequency from an incoming encoded clock signal; a decoder coupled to the synchronization terminal and configured to derive a control voltage signal from the incoming encoded clock signal; and a control circuit coupled to the frequency detector and the decoder and configured to control a DC-DC converter based on the control voltage signal and the incoming clock frequency.

[0081] Example 38 is a multiphase DC-DC converter, comprising: a first DC-DC converter having a synchronization terminal and a first output terminal, and configured to generate a first output signal having a first current and an output voltage at the first output terminal; and a second DC-DC converter having a second output terminal. The first DC-DC converter comprises: a clock generator configured to generate a clock signal having a clock frequency; and an encoder coupled to the clock generator and the synchronization terminal, the encoder configured to encode the clock signal based on a control voltage of the first DC-DC converter to provide an encoded clock signal at the synchronization terminal. The second DC-DC converter comprises: a frequency detector coupled to the synchronization terminal of the first DC-DC converter and configured to derive the clock frequency from the encoded clock signal; a decoder coupled to the synchronization terminal of the first DC-DC converter and configured to derive the control voltage from the encoded clock signal; and a control circuit coupled to the frequency detector and the decoder, and configured to control the second DC-DC converter to generate a second output signal having an output voltage and a second current at a second output terminal based on the control voltage and the clock frequency, the second current being balanced and synchronized with the first current.

[0082] Example 39 includes the multi-phase DC-DC converter of Example 38, wherein the encoder is configured to modulate at least one of an amplitude of the clock signal or a duty cycle of the clock signal based on the control voltage to generate an encoded clock signal.

[0083] Example 40 includes the multiphase DC-DC converter of one of Examples 38 or 39, wherein the encoder comprises a level shifter configured to modulate an amplitude of the clock signal based on a control voltage to generate an encoded clock signal.

[0084] Example 41 includes the multi-phase DC-DC converter described in Example 40, wherein the first DC-DC converter further includes an error amplifier configured to generate a control voltage, and wherein the encoder includes a first voltage regulator coupled to the output of the error amplifier and a level shifter, the first voltage regulator is configured to generate a modulation signal by superimposing a bias voltage on the control voltage, and wherein the level shifter is configured to modulate the amplitude of the clock signal based on the modulation signal.

[0085] Example 42 includes the multiphase DC-DC converter of Example 41, wherein the decoder comprises an envelope detector and a second voltage regulator coupled to an output of the envelope detector and configured to subtract a bias voltage from a signal output by the envelope detector to recover the control voltage.

[0086] Example 43 includes the multi-phase DC-DC converter of Example 42, wherein the first voltage regulator multiplies the amplitude of the control voltage signal by a constant to generate a modulation signal, and the second voltage regulator divides by the constant to recover the control voltage.

[0087] Example 44 includes a multi-phase DC-DC converter as described in one of Examples 38 or 39, wherein the encoder comprises: a ramp generator coupled to a clock generator and configured to generate a ramp signal based on a clock signal; and a comparator configured to compare the ramp signal with a modulation signal to generate an outgoing encoded clock signal, wherein the modulation signal is based on a control voltage.

[0088] Example 45 includes the multi-phase DC-DC converter of Example 44, wherein the decoder comprises a low pass filter.

[0089] Example 46 includes the multi-phase DC-DC converter described in Example 45, wherein the first DC-DC converter further includes an error amplifier configured to generate a control voltage, and wherein the encoder includes a first voltage regulator coupled to an output of the error amplifier and a level shifter, the first voltage regulator is configured to generate a modulation signal by superimposing a bias voltage on the control voltage, and wherein the level shifter is configured to modulate the amplitude of the clock signal based on the modulation signal.

[0090] Example 47 includes the multiphase DC-DC converter of Example 46, wherein the decoder further comprises a second voltage regulator coupled to the output of the low-pass filter and configured to subtract a bias voltage from a signal output by the low-pass filter to recover the control voltage.

[0091] Example 48 includes the multi-phase DC-DC converter of Example 47, wherein the first voltage regulator multiplies the amplitude of the control voltage signal by a constant to generate a modulation signal, and the second voltage regulator divides by the constant to recover the control voltage.

[0092] Example 49 includes the multi-phase DC-DC converter of any of Examples 38-48, wherein the frequency detector includes a threshold detection circuit.

[0093] Example 50 is an integrated circuit (IC) comprising the circuit of any one of Examples 1 to 16, 36, or 37, or the multiphase DC-DC converter of any one of Examples 17, 18, or 38 to 49, or the multiphase DC-DC converter system of any one of Examples 19 to 35.

[0094] Example 51 is a printed circuit board (PCB) comprising the circuit of any one of Examples 1 to 16, 36 or 37, or the multiphase DC-DC converter of any one of Examples 17, 18 or 38 to 49, or the multiphase DC-DC converter system of any one of Examples 19 to 35.

[0095] In this specification, the term "coupled" may encompass connections, communications, or signal paths that enable a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B through a direct connection; or (b) in a second instance, device A is coupled to device B through an intermediate component C, provided that the intermediate component C does not change the functional relationship between device A and device B, so that device B is controlled by device A through the control signal generated by device A.

[0096] A device "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function when manufactured by a manufacturer, and / or may be configurable (or reconfigurable) by a user after manufacture to perform the function and / or other additional or alternative functions. Configuration may be through firmware and / or software programming of the device, through the construction and / or layout of the device's hardware components and interconnections, or a combination thereof.

[0097] As used herein, the terms "terminal", "node", "interconnection", "pin" and "lead" are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to refer to the interconnections or their ends between device elements, circuit elements, integrated circuits, devices or other electronic devices or semiconductor components.

[0098] A circuit or device described herein as including certain components may actually be adapted to be coupled to those components to form the described circuit system or device. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) may actually include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package), and may be adapted to be coupled to at least some of the passive elements and / or sources to form the described structure at the time of manufacture or after manufacture, for example, by an end user and / or a third party.

[0099] Although the use of specific transistors is described herein, other transistors (or equivalent devices) may be used alternatively. For example, a p-channel field effect transistor (PFET) may be used instead of an n-channel field effect transistor (NFET) with little or no change to the circuit. In addition, other types of transistors (e.g., bipolar junction transistors (BJTs)) may be used. In addition, the device may be implemented in / on a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN), or a gallium arsenide substrate (GaAs). In addition, references to transistor features such as gates, sources, or drains are not intended to exclude any appropriate transistor technology. For example, features such as source, drain, and gate are commonly used to refer to FETs, while emitters, collectors, and bases are commonly used to refer to BJTs. Such features may be used interchangeably herein. For example, a reference to the gate of a transistor may refer to the gate of a FET or the base of a BJT, and vice versa. In some instances, a control terminal may refer to the gate of a FET or the base of a BJT. Any other suitable transistor technology may be used. Any such transistor may be used as a switch, with the gate or base or other comparable feature acting as a switch select input that can be driven to connect the source and drain (or emitter and collector as the case may be).

[0100] Reference herein to a field effect transistor (FET) being "on" (or the switch being closed) means that there is a conductive channel of the FET and drain current can flow through the FET. Reference herein to a FET being "off" (or the switch being open) means that there is no conductive channel and drain current does not flow through the FET. However, an off FET may have current flowing through the body diode of the transistor.

[0101] The circuits described herein may be reconfigured to include additional components or different components to provide functionality at least partially similar to functionality available prior to component replacement. Unless otherwise specified, components shown as resistors generally represent any one or more elements coupled in series and / or in parallel to provide the amount of impedance represented by the resistor shown. For example, a resistor or capacitor shown and described herein as a single component may alternatively be a plurality of resistors or capacitors coupled in parallel between the same nodes, respectively. For example, a resistor or capacitor shown and described herein as a single component may actually be a plurality of resistors or capacitors coupled in series between the same two nodes as a single resistor or capacitor, respectively.

[0102] The use of the phrase "ground" in the foregoing description includes chassis ground, ground line ground, floating ground, virtual ground, digital ground, universal ground, and / or any other form of ground connection that is applicable or suitable for the teachings of this specification. In this specification, unless otherwise specified, "about", "substantially" or "generally" before a parameter means within the range of + / -10% of the parameter.

[0103] Modifications may be made in the described examples and other examples may be made within the scope of the claims.

Claims

1. A circuit comprising: an error amplifier configured to generate a first control voltage signal based on a reference voltage and a power converter output voltage; Synchronous terminal; a clock generator configured to generate an outgoing clock signal having an outgoing clock frequency; an encoder coupled to the clock generator and the synchronization terminal, the encoder configured to encode the outgoing clock signal based on the first control voltage signal to provide an outgoing encoded clock signal at the synchronization terminal; a frequency detector coupled to the synchronization terminal and configured to derive an incoming clock frequency from an incoming encoded clock signal; as well as A decoder is coupled to the synchronization terminal and configured to derive a second control voltage signal from the incoming encoded clock signal.

2. The circuit of claim 1, further comprising a control circuit coupled to the frequency detector and the decoder and configured to control a DC-DC converter based on the second control voltage signal and the incoming clock frequency. 3 . The circuit of claim 1 , wherein the encoder is configured to modulate at least one of an amplitude of the outgoing clock signal or a duty cycle of the outgoing clock signal based on the first control voltage signal to generate the outgoing encoded clock signal. 4 . The circuit of claim 1 , wherein the encoder comprises a level shifter configured to modulate an amplitude of the outgoing clock signal based on the first control voltage signal to generate the outgoing encoded clock signal.

5. The circuit of claim 4 , wherein the encoder comprises a first voltage regulator coupled to an output of the error amplifier and the level shifter, the first voltage regulator being configured to generate a modulation signal by superimposing a bias voltage on the first control voltage signal, and wherein the level shifter is configured to modulate the amplitude of the clock signal based on the modulation signal; and Wherein the decoder comprises an envelope detector and a second voltage regulator, the second voltage regulator being coupled to an output of the envelope detector and configured to subtract the bias voltage from a signal output by the envelope detector to recover the second control voltage signal. 6 . The circuit of claim 5 , wherein the first voltage regulator multiplies the amplitude of the first control voltage signal by a constant to generate the modulation signal, and the second voltage regulator divides by the constant to restore the second control voltage signal.

7. The circuit of claim 4, wherein the decoder comprises an envelope detector.

8. The circuit of claim 1 , wherein the encoder comprises: a ramp generator coupled to the clock generator and configured to generate a ramp signal based on the outgoing clock signal; as well as A comparator is configured to compare the ramp signal with a modulation signal to generate the outgoing encoded clock signal, the modulation signal being based on the first control voltage signal.

9. The circuit of claim 8, wherein the decoder comprises a low pass filter.

10. The circuit of claim 9, wherein the encoder comprises a first voltage regulator coupled to an output of the error amplifier and configured to generate the modulation signal by superimposing a bias voltage on the first control voltage signal; and Wherein the decoder includes a second voltage regulator coupled to the output of the low pass filter and configured to subtract the bias voltage from a signal output from the low pass filter to recover the second control voltage signal.

11. The circuit of claim 10, wherein the first voltage regulator multiplies the amplitude of the first control voltage signal by a constant to generate the modulation signal, and the second voltage regulator divides by the constant to restore the second control voltage signal.

12. A multi-phase DC-DC converter system, comprising: A first DC-DC converter having a first input terminal for receiving an input voltage, a first synchronization terminal, a feedback terminal and a first output terminal, the first DC-DC converter comprising an amplifier having an input terminal coupled to the feedback terminal, clock generator, and a level shifter having an input coupled to the output of the clock generator and the output of the amplifier, and an output coupled to the first synchronization terminal; as well as a second DC-DC converter having a second input terminal for receiving the input voltage, a second synchronization terminal coupled to the first synchronization terminal, and a second output terminal coupled to the first output terminal, the second DC-DC converter comprising a frequency detector coupled to the second synchronization terminal, an envelope detector coupled to the second synchronization terminal, and A control circuit is coupled to the frequency detector and the envelope detector.

13. The multiphase DC-DC converter system of claim 12 , wherein the first DC-DC converter is configured to generate a first output signal having an output voltage and a first current at the first output terminal; and wherein the control circuit is configured to control the second DC-DC converter to generate a second output signal having the output voltage and a second current at the second output terminal, the second current being phase-shifted relative to the first current.

14. The multiphase DC-DC converter system of claim 12, wherein the amplifier is configured to generate a control voltage based on a signal received at the feedback terminal; wherein the clock generator is configured to generate a clock signal having a clock frequency; and wherein the level shifter is configured to generate a synchronization signal at the first synchronization terminal based on the clock signal and the control voltage.

15. The multi-phase DC-DC converter system of claim 14 , wherein the frequency detector is configured to recover the clock frequency from the synchronization signal; and wherein the control circuit is configured to synchronize a second output signal generated by the second DC-DC converter at the second output terminal with a first output signal generated by the first DC-DC converter at the first output terminal based on the clock frequency.

16. The multiphase DC-DC converter system of claim 14, wherein the first DC-DC converter comprises a first voltage regulator coupled between the amplifier and the level shifter; and wherein the second DC-DC converter comprises a second voltage regulator coupled to the envelope detector; wherein the envelope detector and the second voltage regulator are configured to recover the control voltage from the synchronization signal.

17. The multi-phase DC-DC converter system of claim 16, wherein the first voltage regulator comprises: a multiplier configured to multiply the control voltage by a constant to generate a modified control voltage; and a summing block configured to superimpose a bias voltage onto the modified control voltage; and wherein the second voltage regulator comprises: a subtraction block configured to subtract the bias voltage from a signal output by the envelope detector to generate an intermediate signal; and a divider configured to divide the intermediate signal by the constant to restore the control voltage.

18. A multi-phase DC-DC converter system comprising: A first DC-DC converter having a first input terminal for receiving an input voltage, a first synchronization terminal, a feedback terminal and a first output terminal, the first DC-DC converter comprising an amplifier having an input terminal coupled to the feedback terminal, Clock generator, a ramp generator coupled to a clock output terminal of the clock generator, and a comparator having a first comparator input terminal coupled to an amplifier output terminal of the amplifier, a second comparator input terminal coupled to a ramp output terminal of the ramp generator, and a comparator output terminal coupled to the first synchronization terminal; as well as a second DC-DC converter having a second input terminal for receiving the input voltage, a second synchronization terminal coupled to the first synchronization terminal, and a second output terminal coupled to the first output terminal, the second DC-DC converter comprising a frequency detector coupled to the second synchronization terminal, a low pass filter coupled to the second sync terminal, and A control circuit is coupled to the frequency detector and the low pass filter.

19. The multiphase DC-DC converter system of claim 18, wherein the first DC-DC converter further comprises a first voltage regulator coupled between the amplifier and the first comparator input terminal; and wherein the second DC-DC converter comprises a second voltage regulator coupled between a filter output terminal of the low-pass filter and the control circuit.

20. The multiphase DC-DC converter system of claim 18, wherein the amplifier is configured to generate a control voltage based on a signal received at the feedback terminal; wherein the clock generator is configured to generate a clock signal having a clock frequency; and wherein the ramp generator is configured to generate a ramp signal based on the clock signal. 21 . The multi-phase DC-DC converter system of claim 20 , wherein the comparator is configured to generate a synchronization signal at the first synchronization terminal based on the control voltage and the ramp signal.

22. The multi-phase DC-DC converter system of claim 21, wherein the low pass filter is configured to filter the synchronization signal to recover the control voltage.

23. The multi-phase DC-DC converter system of claim 22, wherein the frequency detector is configured to recover the clock frequency based on the synchronization signal.

24. The multi-phase DC-DC converter system of claim 23, wherein the first DC-DC converter is configured to generate a first output signal having an output voltage and a first current at the first output terminal; and wherein the control circuit is configured to control the second DC-DC converter to generate a second output signal having the output voltage and a second current at the second output terminal based on the clock frequency and the control voltage, the second current being phase-shifted relative to the first current.

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