Silicon-based millimeter-wave digital attenuator and millimeter-wave active phased array antenna

Abstract

The present invention provides a silicon-based millimeter-wave digital attenuator and a millimeter-wave active phased array antenna, relating to the technical field of phased array antennas. The attenuation function of the silicon-based millimeter-wave digital attenuator is realized by switching between two sets of differential circuits, namely set A and set B, which are exactly the same in each core attenuation unit. That is, in the entire attenuation range, only one set of circuits in each working core attenuation unit is conducting. Whether viewed from the perspective of RF small signals or the DC working circuit, the attenuator circuit composed of all units remains unchanged. That is, it can achieve very small changes in the RF input and output impedance within the entire attenuation range, making it easy to maintain the matching between the attenuator circuit and the front and rear stage circuits. At the same time, the working current remains basically unchanged, thereby making the phase fluctuation very small when the attenuator is working.

Description

Technical Field

[0001] The present invention relates to the technical field of phased array antennas, and in particular, to a silicon-based millimeter-wave digital attenuator and a millimeter-wave active phased array antenna. Background Art

[0002] In millimeter-wave low-cost active phased array antennas, chip integration technology based on silicon-based RF-CMOS process is usually adopted to achieve single-chip integration of multi-channel and multi-functional active sub-arrays. Taking a silicon-based 8-channel receiving active sub-array chip applied in a millimeter-wave satellite communication phased array receiving antenna as an example, a single silicon-based chip integrates 8 receiving channels, 8 beam synthesis networks, and function units such as combined path drive amplification. Among them, a single receiving channel includes a receiving low-noise amplifier, six-bit digital phase shifter, and five-bit digital attenuator. The attenuation function of a millimeter-wave satellite communication phased array receiving antenna is mainly used to provide corresponding amplitude weighting (i.e., signal attenuation) to channels at different positions of the radiation aperture according to certain algorithm requirements when the phased array antenna suppresses the spatial beam sidelobe. According to the continuity of the attenuation action and the control method, it can be divided into an analog attenuator and a digital attenuator. The analog attenuation control signal is usually an analog signal, providing a continuously variable attenuation amount within a certain range; while the digital attenuator is usually controlled by a digital signal, providing a discretely variable attenuation amount within a certain range according to the set step. Since the digital attenuator has high control precision, strong anti-interference ability, and good compatibility with the silicon-based CMOS process and is easy to integrate and implement, digital attenuators are usually adopted in phased array silicon-based CMOS chips at present.

[0003] In the above application scenarios, considering factors such as the cascade requirements of the front and rear stage circuits and the impact of the attenuator on other core indicators during operation, the existing millimeter-wave digital attenuators are difficult to meet the following requirements: 1. When the attenuation circuit is working, the input and output impedances do not change significantly to avoid affecting the matching of the front and rear stages and causing fluctuations in the in-band gain. 2. The phase fluctuations caused by setting different attenuation levels should be as small as possible, that is, the orthogonality of phase modulation and amplitude modulation in the RF link is achieved. 3. The circuit chip occupies a small area, is easy to integrate, and both control and implementation are compatible with the silicon-based CMOS process. Summary of the Invention

[0004] The present invention aims to solve at least one of the above technical problems existing in the prior art.

[0005] To this end, in the first aspect of the present invention, a silicon-based millimeter-wave digital attenuator is provided.

[0006] In the second aspect of the present invention, a millimeter-wave active phased array antenna is provided.

[0007] The present invention provides a silicon-based millimeter-wave digital attenuator, including a plurality of core attenuation units connected in parallel between a differential input port and a differential output port; the core attenuation unit includes:

[0008] A first transistor, having a first terminal, a second terminal, and a control terminal, wherein the control terminal of the first transistor receives a DC bias signal and is coupled to a differential input port to feed a first RF differential input signal;

[0009] A second transistor, having a first terminal, a second terminal, and a control terminal, wherein the control terminal of the second transistor receives a DC bias signal and is coupled to the differential input port to feed a second RF differential input signal;

[0010] A third transistor, having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the third transistor is coupled to the first terminal of the second transistor, and a common node of the two is coupled to a first sub-differential output terminal, and the control terminal of the third transistor is coupled to the control terminal of the first transistor;

[0011] A fourth transistor, having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the fourth transistor is coupled to the first terminal of the first transistor, and a common node of the two is coupled to a second sub-differential output terminal, and the control terminal of the fourth transistor is coupled to the control terminal of the second transistor;

[0012] A fifth transistor, having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the fifth transistor is respectively coupled to the second terminal of the first transistor and the second terminal of the second transistor, the second terminal of the fifth transistor is coupled to ground, and the control terminal of the fifth transistor receives a switching signal;

[0013] A sixth transistor, having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the sixth transistor is respectively coupled to the second terminal of the third transistor and the second terminal of the fourth transistor, the second terminal of the sixth transistor is coupled to ground, and the control terminal of the sixth transistor receives an inverted signal of the switching signal;

[0014] Wherein, the switching signal is used to control the fifth transistor and the sixth transistor to switch between an amplification state and a cut-off state; the first RF differential input signal and the second RF differential input signal are opposite.

[0015] The silicon-based millimeter-wave digital attenuator according to the above technical solution of the present invention may further have the following additional technical features:

[0016] In the above technical solution, the first transistor, the second transistor, the third transistor, and the fourth transistor are defined as the upper transistors of the core attenuation unit, and the fifth transistor and the sixth transistor are defined as the lower transistors of the core attenuation unit;

[0017] Wherein, the sizes of all the upper transistors in a single core attenuation unit are the same and the sizes of all the lower transistors are the same, the size of the lower transistors has a fixed ratio to the size of the upper transistors, and the value of the fixed ratio is the same in each core attenuation unit.

[0018] In the above technical solution, the value of the fixed ratio is 2;

[0019] Among several core attenuation units, the size structures of the first core attenuation unit and the second core attenuation unit are exactly the same, the size of the upper transistor is w, and the size of the lower transistor is 2w;

[0020] The size of the upper transistor in the i-th core attenuation unit is , and the size of the lower transistor is , where i is greater than or equal to 3 and less than or equal to n, and n represents the total number of core attenuation units.

[0021] In the above technical solution, the core attenuation unit further includes:

[0022] A first inductor, one end of which is coupled to the second end of the first transistor and the other end is coupled to the first end of the fifth transistor;

[0023] A second inductor, one end of which is coupled to the second end of the second transistor and the other end is coupled to the first end of the fifth transistor;

[0024] A third inductor, one end of which is coupled to the second end of the third transistor and the other end is coupled to the first end of the sixth transistor;

[0025] A fourth inductor, one end of which is coupled to the second end of the fourth transistor and the other end is coupled to the first end of the sixth transistor.

[0026] In the above technical solution, the core attenuation unit further includes:

[0027] A first capacitor, one end of which is coupled to the first end of the fifth transistor and the other end is coupled to the second end of the fifth transistor;

[0028] A second capacitor, one end of which is coupled to the first end of the sixth transistor and the other end is coupled to the second end of the sixth transistor.

[0029] In the above technical solution, each core attenuation unit adopts different switching signals to achieve independent control of each core attenuation unit.

[0030] In the above technical solution, the differential input port includes a positive terminal of an input differential radio frequency signal and a negative terminal of the input differential radio frequency signal, and the differential output port includes a positive terminal of an output differential radio frequency signal and a negative terminal of the output differential radio frequency signal;

[0031] The positive terminal of the input differential radio frequency signal receives a first radio frequency differential input signal and is coupled to the control terminals of the first transistor and the third transistor in each core attenuation unit;

[0032] The negative terminal of the input differential RF signal receives a second RF differential input signal and is coupled to the control terminals of the second transistor and the fourth transistor in each core attenuation unit;

[0033] The second sub-differential output terminals of each core attenuation unit are connected in parallel to the positive terminal of the output differential RF signal;

[0034] The first sub-differential output terminals of each core attenuation unit are connected in parallel to the negative terminal of the output differential RF signal.

[0035] In the above technical solution, the differential input port includes a positive terminal of the input differential RF signal and a negative terminal of the input differential RF signal, and the differential output port includes a positive terminal of the output differential RF signal and a negative terminal of the output differential RF signal;

[0036] The positive terminal of the input differential RF signal receives a second RF differential input signal and is coupled to the control terminals of the second transistor and the fourth transistor in each core attenuation unit;

[0037] The negative terminal of the input differential RF signal receives a first RF differential input signal and is coupled to the control terminals of the first transistor and the third transistor in each core attenuation unit;

[0038] The second sub-differential output terminals of each core attenuation unit are connected in parallel to the negative terminal of the output differential RF signal;

[0039] The first sub-differential output terminals of each core attenuation unit are connected in parallel to the positive terminal of the output differential RF signal.

[0040] In the above technical solution, the first sub-differential output terminal and the second sub-differential output terminal of each core attenuation unit also receive a DC feeding signal;

[0041] The silicon-based millimeter-wave digital attenuator further includes:

[0042] A circuit compensation unit, which adopts the same circuit structure and pipe component size as the nth core attenuation unit, where the nth core attenuation unit is the core attenuation unit that can provide the maximum number of RF current shares; the difference between the circuit compensation unit and the nth core attenuation unit is that the first sub-differential output terminal and the second sub-differential output terminal of the circuit compensation unit only receive a DC feeding signal and are not connected to the differential output port.

[0043] A millimeter-wave active phased array antenna provided by the present invention includes the silicon-based millimeter-wave digital attenuator according to any one of the above technical solutions.

[0044] In summary, due to the adoption of the above technical features, the beneficial effects of the present invention are:

[0045] In the present invention, the attenuation function is realized by switching between two sets of exactly the same differential circuits, namely A and B, in each core attenuation unit. That is, within the entire attenuation range, only one set of differential circuits in each working core attenuation unit is conducting. Whether viewed from the perspective of RF small signals or the DC working circuit, the attenuator circuit composed of all units remains unchanged. Specifically, for the digital attenuator adopting the circuit structure of the present invention, the RF input and output impedance varies very little within the entire attenuation range, which is conducive to maintaining the matching between the attenuator circuit and the front and rear stage circuits; the working current remains basically unchanged; and based on the first two conditions, the phase fluctuation brought by the entire attenuator during operation is very small.

[0046] The source-degenerate series inductance introduced in each core attenuation unit can effectively reduce the impedance at the input of the differential cross-conduction tube gate, improving the matching condition, which is exactly the input port of the RF differential signal of the attenuator. This is beneficial to the cascade matching of the circuit in the chip.

[0047] When one of the A / B groups of circuits in each core attenuation unit is working and the other is in the off state, since the two sets of differential circuit structures have exactly the same size and are cross-connected in the gate-drain direction, the equivalent gate-drain parasitic capacitance of the off-group tubes just plays the role of the neutralizing capacitance of the working-group tubes, effectively improving the reverse isolation of the differential cross-conduction tube and enhancing the stability.

[0048] Due to the fact that the paired tubes and peripheral traces in each core attenuation unit cannot be made absolutely symmetrical, and the tail current tube (lower tube) also has the channel modulation effect, the virtual ground effect of the Q point (common terminal of the upper tubes) relying on symmetry is not good. The capacitor connected in parallel to the ground provides a forced virtual ground effect, improving the RF performance of the circuit from the perspective of the small-signal circuit.

[0049] The introduction of the circuit compensation unit can maintain the magnitude of the working current when the attenuator circuit is in the downshift mode of use, greatly reducing the change in the working state in this mode.

[0050] The differential cross-conduction tube can provide a certain amount of active gain, which can compensate for the small-signal gain in the entire link.

[0051] What determines the attenuation amount in the circuit is the ratio of the current shares corresponding to different core attenuation units, that is, the ratio of the tube size w. Although process fluctuations occur during the actual processing, the ratio can be well maintained unchanged, thus providing the attenuation accuracy of the attenuation circuit.

[0052] The additional aspects and advantages of the present invention will become apparent in the following description section or be understood through the practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] The above and / or additional aspects and advantages of the present invention will become apparent and be readily understood from the description of the embodiments in conjunction with the following drawings, wherein:

[0054] Figure 1 It is a schematic circuit diagram of the core attenuation unit in the silicon-based millimeter-wave digital attenuator according to an embodiment of the present invention;

[0055] Figure 2 It is a schematic circuit diagram of the silicon-based millimeter-wave digital attenuator according to an embodiment of the present invention. Detailed implementation manners

[0056] In order to more clearly understand the above objects, features and advantages of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific implementation manners. It should be noted that, without conflict, the embodiments of the present application and the features in the embodiments can be combined with each other.

[0057] Throughout the specification, the reference to "an embodiment" or "an embodiment" means that the specific features, structures or characteristics described in connection with that embodiment are included in at least one embodiment of the present invention. Thus, the phrases "in an embodiment" or "in embodiments" that appear throughout the specification do not necessarily all refer to the same embodiment. The verbs "comprise" and "have" are used herein as open limitations, which neither exclude nor require the existence of unrecited features. Unless otherwise expressly stated, the features recited in the dependent claims can be freely combined with each other. Throughout the document, an element defined by "a" or "an" (i.e., the singular form) does not exclude the possibility of a plurality of such elements. Further, the described features, structures or characteristics can be combined in any suitable manner in one or more embodiments. Unless otherwise specified, the term "connected" is used to specify a direct electrical connection between circuit elements, while the terms "coupled" and "coupled to" are used to specify an electrical connection between circuit elements that can be direct or can be via one or more other elements. In contrast, when an element is said to be "directly connected to" or "directly coupled to" another element, there is no intermediate element. The term "and / or" used herein includes any and all combinations of one or more of the related listed items. When referring to the voltage of a node or terminal, unless otherwise indicated, the voltage is considered to be the voltage between the node and the reference potential (usually ground). Further, when referring to the potential of a node or terminal, unless otherwise indicated, the potential is considered to refer to the reference potential. The voltage and potential of a given node or given terminal will further be designated by the same reference numeral. A signal that alternates between a first logic state (e.g., a logic low state) and a second logic state (e.g., a logic high state) is referred to as a "logic signal". The high and low states of different logic signals in the same electronic circuit may be different. In particular, the high and low states of a logic signal can correspond to voltages or currents that may not be completely constant in the high or low state.

[0058] The following refers to Figure 1 andFigure 2 To describe a silicon-based millimeter-wave digital attenuator provided according to some embodiments of the present invention.

[0059] Some embodiments of the present application provide a silicon-based millimeter-wave digital attenuator.

[0060] As Figure 1 shown, the first embodiment of the present invention proposes a silicon-based millimeter-wave digital attenuator, including a plurality of core attenuation units connected in parallel between a differential input port and a differential output port; the core attenuation unit at least includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, and a sixth transistor M6.

[0061] It should be noted that, in this disclosure, except for the transistors specifically specified by model, the remaining transistors can all select any suitable semiconductor switching device, such as a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), a Junction Field Effect Transistor (JFET), or a suitable power switching device such as an Insulated Gate Bipolar Transistor (IGBT).

[0062] For ease of explanation, in this disclosure, it is assumed that the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are all MOS transistors for illustration. Each of the above transistors has a first end, a second end, and a control end. Among them, the first end corresponds to the drain of the MOS transistor, the second end corresponds to the source of the MOS transistor, and the control end corresponds to the gate of the MOS transistor. It can be understood that the corresponding relationship between the ends of the above transistors and the poles of the MOS transistor is only a schematic representation, and those skilled in the art can adjust the above corresponding relationship according to the pipe fitting model and polarity requirements with reference to the circuit structure of the present invention.

[0063] As Figure 1 shown, in the core attenuation unit proposed in this disclosure, the first transistor M1, the second transistor M2, and the fifth transistor M5 form a group A differential circuit, and the third transistor M3, the fourth transistor M4, and the sixth transistor M6 form a group B differential circuit. The two differential circuits are consistent in structure, and the specific connection relationship is as follows:

[0064] The control terminal of the first transistor M1 receives a DC bias signal and is coupled to the differential input port to feed in a first RF differential input signal; the control terminal of the second transistor M2 receives a DC bias signal and is coupled to the differential input port to feed in a second RF differential input signal. The first RF differential input signal and the second RF differential input signal are opposite to each other, specifically two signals with the same amplitude and opposite polarities.

[0065] The first terminal of the third transistor M3 is coupled to the first terminal of the second transistor M2, and the common node of the two is coupled to the first sub-differential output terminal DN. The control terminal of the third transistor M3 is coupled to the control terminal of the first transistor M1; the first terminal of the fourth transistor M4 is coupled to the first terminal of the first transistor M1, and the common node of the two is coupled to the second sub-differential output terminal DP. The control terminal of the fourth transistor M4 is coupled to the control terminal of the second transistor M2; the first sub-differential output terminal DN and the second sub-differential output terminal DP are coupled to the differential output port of the attenuator.

[0066] Wherein, the DC bias signal is used to bias the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 in the amplification region, so that the four transistors are in the amplification state.

[0067] The first terminal of the fifth transistor M5 is respectively coupled to the second terminal of the first transistor M1 and the second terminal of the second transistor M2. The second terminal of the fifth transistor M5 is coupled to the ground. The control terminal of the fifth transistor M5 receives a switching signal Vct; the first terminal of the sixth transistor M6 is respectively coupled to the second terminal of the third transistor M3 and the second terminal of the fourth transistor M4. The second terminal of the sixth transistor M6 is coupled to the ground. The control terminal of the sixth transistor M6 receives the inverted signal of the switching signal ; The switching signal is used to control the fifth transistor M5 and the sixth transistor M6 to switch between the amplification state and the cut-off state. It can be understood that the states of the fifth transistor M5 and the sixth transistor M6 are opposite, that is, when the fifth transistor M5 is in the amplification state, the sixth transistor M6 is in the cut-off state.

[0068] The differential input port includes a positive terminal GPi of the input differential RF signal and a negative terminal GNi of the input differential RF signal. The differential output port includes a positive terminal DPo of the output differential RF signal and a negative terminal DNo of the output differential RF signal.

[0069] In one embodiment, the positive terminal GPi of the input differential RF signal receives a first RF differential input signal and is coupled to the control terminals of the first transistor M1 and the third transistor M3 in each core attenuation unit. The common node of the control terminals of the first transistor M1 and the third transistor M3 is defined as the first sub-differential input terminal GP. The negative terminal GNi of the input differential RF signal receives a second RF differential input signal and is coupled to the control terminals of the second transistor M2 and the fourth transistor M4 in each core attenuation unit. The common node of the control terminals of the second transistor M2 and the fourth transistor M4 is defined as the second sub-differential input terminal GN. The second sub-differential output terminals DP of each core attenuation unit are connected in parallel to the positive terminal DPo of the output differential RF signal. The first sub-differential output terminals DN of each core attenuation unit are connected in parallel to the negative terminal DNo of the output differential RF signal.

[0070] It can be understood that the connection positions of the positive terminal GPi and the negative terminal GNi of the input differential RF signal in the above embodiment can be swapped, but when swapping, the connection positions of the positive terminal DPo and the negative terminal DNo of the output differential RF signal should also be adjusted accordingly.

[0071] Specifically, in another embodiment, the positive terminal of the input differential RF signal receives a second RF differential input signal and is coupled to the control terminals of the second transistor M2 and the fourth transistor M4 in each core attenuation unit. The negative terminal of the input differential RF signal receives a first RF differential input signal and is coupled to the control terminals of the first transistor M1 and the third transistor M3 in each core attenuation unit. The second sub-differential output terminals of each core attenuation unit are connected in parallel to the negative terminal of the output differential RF signal. The first sub-differential output terminals of each core attenuation unit are connected in parallel to the positive terminal of the output differential RF signal.

[0072] In the above core attenuation unit, taking the A-group differential circuit as an example for illustration, the A-group differential circuit constitutes a differential transconductance pair tube structure with a tail current source. Among them, the first transistor M1 and the second transistor M2 constitute a differential transconductance pair tube. The RF differential input signals enter the gates of the first transistor M1 and the second transistor M2 respectively. The common terminal of the first transistor M1 and the second transistor M2 serves as the RF virtual ground node Q. Whether each group of differential circuits is turned on and the current magnitude when turned on are determined by the tail current source tube (the lower tube, which is the fifth transistor M5 for the A-group differential circuit). The lower tube operating in the saturation region can form a tail current source structure, that is, the voltage loaded at the gate terminal of the lower tube under the control of the switching signal Vct switches between the saturation region bias voltage and the ground potential. It can be understood that the switching signal Vct is a high-low level digital control signal.

[0073] Define the ground state when the differential circuit of group A of each core attenuation unit in the attenuator is turned on and the differential circuit of group B is turned off (i.e., at the output terminals, there is forward current sinking, and at this time, the attenuation is the smallest). If any core attenuation unit is switched to turn on the differential circuit of group B and turn off the differential circuit of group A, then this core attenuation unit provides reverse RF amplification current. From the perspective of the final differential output port, it switches from providing forward enhancement current to negative cancellation current, thereby reducing the total RF current at the output node.

[0074] In some embodiments, the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 are defined as the upper transistors of the core attenuation unit, and the fifth transistor M5 and the sixth transistor M6 are defined as the lower transistors of the core attenuation unit;

[0075] Among them, the sizes of all upper transistors in a single core attenuation unit are the same and the sizes of all lower transistors are the same. The size of the lower transistors has a fixed ratio to the size of the upper transistors, and the value of this fixed ratio is the same in each core attenuation unit. What determines the attenuation amount in the circuit is the current fraction ratio corresponding to different core attenuation units, that is, the ratio of the size of the upper transistors to the size of the lower transistors. Even if there are process fluctuations during the actual processing, the ratio can be well maintained, thereby ensuring the attenuation accuracy of the attenuation circuit.

[0076] Among them, the DC bias signal of the upper transistors is biased to an appropriate voltage position according to the amplification requirement. In some embodiments, each core attenuation unit adopts a different switching signal Vct to achieve independent control of each core attenuation unit.

[0077] In a specific implementation, the value of the fixed ratio is 2;

[0078] Among several core attenuation units, the size structures of the first core attenuation unit and the second core attenuation unit are exactly the same. The size of the upper transistors is w, and the size of the lower transistors is 2w;

[0079] The size of the upper transistors in the i-th core attenuation unit is , and the size of the lower transistors is , where i is greater than or equal to 3 and less than or equal to n, and n represents the total number of core attenuation units.

[0080] Taking Figure 2 the illustrated embodiment as an example for illustration, Figure 2In the digital attenuator shown, it includes core attenuation units K1, K2, K3... Kn placed side by side. Among them, w = 2 μm (micrometers), n = 7, and the structural dimensions of core attenuation unit K1 and core attenuation unit K2 are exactly the same. Assume that the number of RF current shares provided by core attenuation unit K1 and core attenuation unit K2 is 1. The A-group differential circuit of each core attenuation unit corresponds to the forward current, and the B-group differential circuit corresponds to the reverse current. Then the total number of current shares of the entire attenuator is 1, 1, 2, 4, 8, 16, 32 respectively, and the symbol is determined by the activation of the A / B-group differential circuit. By configuring the control signal of the tail current source tube (lower tube), discrete current share (intensity) combinations can be obtained at the output end (i.e., the differential output port) of the digital attenuator, including 32, 31, 30... 3, 2, 1 (in units of shares). Taking the RF signal power as the amplitude measurement standard, the attenuation amounts provided from small to large relative to the ground state are 20lg(32 / 31), 20lg(32 / 30),... 20lg(32 / 2), 20lg(32 / 1), 20lg(0). Note that the attenuation amount of 20lg(0) is used to represent an infinite attenuation amount.

[0081] In some embodiments, the core attenuation unit further includes a first inductor L1, a second inductor L2, a third inductor L3, and a fourth inductor L4.

[0082] One end of the first inductor L1 is coupled to the second end of the first transistor M1, and the other end is coupled to the first end of the fifth transistor M5; one end of the second inductor L2 is coupled to the second end of the second transistor M2, and the other end is coupled to the first end of the fifth transistor M5; one end of the third inductor L3 is coupled to the second end of the third transistor M3, and the other end is coupled to the first end of the sixth transistor M6; one end of the fourth inductor L4 is coupled to the second end of the fourth transistor M4, and the other end is coupled to the first end of the sixth transistor M6.

[0083] The above-mentioned first inductor L1, second inductor L2, third inductor L3, and fourth inductor L4 serve as source degeneration series inductors, effectively reducing the impedance of the differential transconductance pair to the gate input, improving the matching conditions, and the gate of the differential transconductance pair is exactly the input port of the RF differential signal of the attenuator, which will be beneficial to the cascade matching of this circuit in the chip.

[0084] In some embodiments, the core attenuation unit further includes a first capacitor C1 and a second capacitor C2.

[0085] One end of the first capacitor C1 is coupled to the first end of the fifth transistor M5, and the other end is coupled to the second end of the fifth transistor M5; one end of the second capacitor C2 is coupled to the first end of the sixth transistor M6, and the other end is coupled to the second end of the sixth transistor M6.

[0086] The above-mentioned first capacitor C1 and second capacitor C2 are both capacitors connected in parallel to the ground. Since the tubes paired correspondingly in each core attenuation unit, the peripheral traces, etc. cannot achieve absolute symmetry, and the tail current source tube also has a channel modulation effect, the virtual ground effect of the RF virtual ground node Q by symmetry is not good. Utilizing the capacitors connected in parallel to the ground can provide a forced virtual ground effect, which improves the RF performance of the circuit from the perspective of the small-signal circuit.

[0087] Furthermore, the first sub-differential output terminal DN and the second sub-differential output terminal DP of each core attenuation unit both receive the DC feeding signal Vdd. In some embodiments, the silicon-based millimeter-wave digital attenuator further includes a circuit compensation unit Kc.

[0088] The circuit compensation unit Kc adopts the same circuit structure and component dimensions as the nth core attenuation unit, and the nth core attenuation unit is the core attenuation unit that can provide the maximum number of RF current shares; as Figure 2 shown, the circuit structure of the circuit compensation unit Kc is the same as that of the core attenuation unit Kn, and the dimensions of the corresponding components are the same. The difference is that the first sub-differential output terminal DN and the second sub-differential output terminal DP of the circuit compensation unit Kc only receive the DC feeding signal Vdd and are not connected to the differential output port. That is, the drain terminals of the differential transconductance pair tubes in the circuit compensation unit Kc are not connected to the positive terminal DPo of the output differential RF signal and the negative terminal DNo of the output differential RF signal, and are only connected to the drain DC feeding terminal to receive the DC feeding signal Vdd.

[0089] When the core attenuation units K1~K7 are all working, both sets of internal A / B differential circuits in the current compensation unit are in the off state. When the K7 core attenuation unit (A / B group) is all turned off, one set of the current compensation unit is turned on. At this time, the attenuator changes to the downshift working state, that is, the attenuator composed of the core attenuation units K1~K6 works according to the aforementioned principle, and the current compensation unit provides a current compensation function, that is, the RF input impedance, output impedance, and working current outside the attenuator remain unchanged.

[0090] The second embodiment of the present invention proposes a millimeter-wave active phased array antenna, including the silicon-based millimeter-wave digital attenuator as described in any of the above embodiments.

[0091] In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiments or examples. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.

[0092] Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A silicon-based millimeter-wave digital attenuator, characterized in that: It includes a plurality of core attenuation units connected in parallel between the differential input port and the differential output port; The core attenuation unit comprises: A first transistor having a first end, a second end and a control end, wherein the control end of the first transistor is fed with a DC bias signal and is coupled to the differential input port to receive a first RF differential input signal; A second transistor having a first end, a second end and a control end, wherein the control end of the second transistor is fed with a DC bias signal and is coupled to the differential input port to receive a second RF differential input signal; a third transistor having a first end, a second end and a control end, the first end of the third transistor being coupled to the first end of the second transistor, a common node of the third transistor and the second transistor being coupled to the first sub-differential output end, and the control end of the third transistor being coupled to the control end of the first transistor; a fourth transistor having a first end, a second end and a control end, the first end of the fourth transistor being coupled to the first end of the first transistor, a common node of the fourth transistor and the first end of the first transistor being coupled to the second sub-differential output end, and the control end of the fourth transistor being coupled to the control end of the second transistor; a fifth transistor having a first end, a second end and a control end, the first end of the fifth transistor being coupled to the second end of the first transistor and the second end of the second transistor respectively, the second end of the fifth transistor being coupled to the ground, and the control end of the fifth transistor receiving a switching signal; a sixth transistor, having a first end, a second end and a control end, wherein the first end of the sixth transistor is coupled to the second end of the third transistor and the second end of the fourth transistor respectively, the second end of the sixth transistor is coupled to the ground, and the control end of the sixth transistor receives an inverted signal of the switching signal; wherein the switching signal is used to control the fifth transistor and the sixth transistor to switch between an amplification state and a cut-off state; and the first RF differential input signal is opposite to the second RF differential input signal; A first inductor, one end of which is coupled to the second end of the first transistor, and the other end of which is coupled to the first end of the fifth transistor; a second inductor, one end of which is coupled to the second end of the second transistor, and the other end of which is coupled to the first end of the fifth transistor; a third inductor, one end of which is coupled to the second end of the third transistor, and the other end of which is coupled to the first end of the sixth transistor; The fourth inductor has one end coupled to the second end of the fourth transistor and the other end coupled to the first end of the sixth transistor.

2. The silicon-based millimeter-wave digital attenuator according to claim 1, characterized in that: The first transistor, the second transistor, the third transistor and the fourth transistor are defined as upper transistors of the core attenuation unit, and the fifth transistor and the sixth transistor are defined as lower transistors of the core attenuation unit; Among them, the sizes of all upper tubes in a single core attenuation unit are the same and the sizes of all lower tubes are the same, the size of the lower tube has a fixed ratio with the size of the upper tube, and the value of the fixed ratio is the same in each core attenuation unit.

3. The silicon-based millimeter-wave digital attenuator according to claim 2, characterized in that: The fixed ratio has a value of 2; Among the core attenuation units, the first core attenuation unit and the second core attenuation unit have the same size structure, the size of the upper tube is w, and the size of the lower tube is 2w; The size of the upper tube in the i-th core attenuation unit is , the size of the lower tube is , where i is greater than or equal to 3 and less than or equal to n, and n represents the total number of core attenuation units.

4. The silicon-based millimeter-wave digital attenuator according to claim 1, characterized in that: The core attenuation unit also includes: A first capacitor, one end of which is coupled to the first end of the fifth transistor, and the other end of which is coupled to the second end of the fifth transistor; The second capacitor has one end coupled to the first end of the sixth transistor and the other end coupled to the second end of the sixth transistor.

5. The silicon-based millimeter-wave digital attenuator according to claim 1, characterized in that: Each core attenuation unit uses a different switching signal to achieve independent control of each core attenuation unit.

6. The silicon-based millimeter-wave digital attenuator according to claim 1, characterized in that: The differential input port includes a positive terminal for inputting differential radio frequency signals and a negative terminal for inputting differential radio frequency signals, and the differential output port includes a positive terminal for outputting differential radio frequency signals and a negative terminal for outputting differential radio frequency signals; The input differential RF signal positive terminal receives the first RF differential input signal and is coupled to the control terminal of the first transistor and the control terminal of the third transistor in each core attenuation unit; The negative terminal of the input differential RF signal receives the second RF differential input signal and is coupled to the control terminal of the second transistor and the control terminal of the fourth transistor in each core attenuation unit; The second sub-differential output end of each core attenuation unit is connected in parallel to the output differential RF signal positive end; The first sub-differential output terminal of each core attenuation unit is connected in parallel to the output differential RF signal negative terminal.

7. The silicon-based millimeter-wave digital attenuator according to claim 1, characterized in that: The differential input port includes a positive terminal for inputting differential radio frequency signals and a negative terminal for inputting differential radio frequency signals, and the differential output port includes a positive terminal for outputting differential radio frequency signals and a negative terminal for outputting differential radio frequency signals; The input differential RF signal positive terminal receives the second RF differential input signal and is coupled to the control terminal of the second transistor and the control terminal of the fourth transistor in each core attenuation unit; The input differential RF signal negative terminal receives the first RF differential input signal and is coupled to the control terminal of the first transistor and the control terminal of the third transistor in each core attenuation unit; The second sub-differential output terminal of each core attenuation unit is connected in parallel to the output differential RF signal negative terminal; The first sub-differential output terminal of each core attenuation unit is connected in parallel to the positive terminal of the output differential RF signal.

8. The silicon-based millimeter-wave digital attenuator according to claim 6 or 7, characterized in that: The first sub-differential output terminal and the second sub-differential output terminal of each core attenuation unit also receive a DC feed signal; The silicon-based millimeter-wave digital attenuator further includes: The circuit compensation unit adopts the same circuit structure and pipe size as the nth core attenuation unit, wherein the nth core attenuation unit is a core attenuation unit capable of providing a maximum number of radio frequency current components; the difference between the circuit compensation unit and the nth core attenuation unit is that the first sub-differential output end and the second sub-differential output end of the circuit compensation unit only receive a DC feed signal and are not connected to the differential output port.

9. A millimeter wave active phased array antenna, characterized in that: It comprises the silicon-based millimeter-wave digital attenuator as claimed in any one of claims 1 to 8.

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