Low-power-consumption decimation filter and low-power-consumption decimation method

Abstract

The invention discloses a low-power-consumption decimation filter and a low-power-consumption decimation method, the low-power-consumption decimation filter comprises a multi-stage CIC filter and a compensation filter, the multi-stage CIC filter is connected with the compensation filter, the multi-stage CIC filter is used for extracting a signal after analog-to-digital conversion to obtain an extracted signal, and the compensation filter is connected with the multi-stage CIC filter; the compensation filter is used for compensating the passband of the multi-stage CIC filter, each stage of the multi-stage CIC filter is formed by cascade connection of an FIR filter and 2 extraction operation, and low-power-consumption extraction of digital signals can be achieved.

Description

Technical Field

[0001] The present invention relates to the field of low-power extraction, and in particular to a low-power extraction filter and a low-power extraction method. Background Art

[0002] Since smart grid monitoring sensors mostly work in energy-constrained scenarios such as battery power or fiber optic power supply, reducing power consumption becomes an important indicator.

[0003] The sigma-delta modulation and demodulation circuit in the monitoring sensor converts the input analog signal into a digital code stream output. The rate of the sampled data stream is very high, which will cause the subsequent signal processing speed to be fast and power consumption to be high. The extraction filter can reduce the frequency of high-speed data. The traditional filtering and extraction circuit has high power consumption and cannot work for a long time in energy-constrained scenarios. Summary of the invention

[0004] The purpose of the present invention is to provide a low-power extraction filter and a low-power extraction method, aiming to solve the problem.

[0005] The present invention provides a low-power decimation filter, comprising:

[0006] A multi-stage CIC filter and a compensation filter, wherein the multi-stage CIC filter and the compensation filter are connected, the multi-stage CIC filter is used to extract the signal after analog-to-digital conversion to obtain an extracted signal, and the compensation filter is used to compensate the passband of the multi-stage CIC filter. Each stage of the multi-stage CIC filter is composed of a cascade of an FIR filter and a 2-extraction operation.

[0007] The present invention also provides a low-power consumption extraction filtering method, comprising:

[0008] A low-power extraction filtering method comprises: extracting a signal after analog-to-digital conversion through a multi-stage CIC filter to obtain an extraction signal, and compensating the passband of the multi-stage CIC filter through a compensation filter, wherein each stage of the multi-stage CIC filter is composed of a cascade of an FIR filter and a 2-extraction operation.

[0009] By adopting the embodiments of the present invention, low-power consumption extraction filtering can be achieved.

[0010] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it is implemented in accordance with the contents of the specification, and in order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are specifically listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0012] Figure 1 is a schematic diagram of the structure of a low-power decimation filter according to an embodiment of the present invention;

[0013] Figure 2 is the amplitude-frequency characteristic of the CIC filter of the low power consumption decimation filter according to an embodiment of the present invention;

[0014] Figure 3 It is a 2-fold decimation evolution path diagram of the low-power decimation filter according to an embodiment of the present invention;

[0015] Figure 4 It is a 2-fold decimation basic circuit unit of the low-power decimation filter of the embodiment of the present invention. DETAILED DESCRIPTION

[0016] The technical solution of the present invention will be clearly and completely described below in conjunction with the embodiments. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0017] Method Embodiment

[0018] According to an embodiment of the present invention, a low power consumption decimation filter is provided. Figure 1 is a flow chart of a low power consumption decimation filter according to an embodiment of the present invention. Figure 1 As shown, specifically including:

[0019] A multi-stage CIC filter and a compensation filter, wherein the multi-stage CIC filter and the compensation filter are connected, the multi-stage CIC filter is used to extract the signal after analog-to-digital conversion to obtain an extracted signal, and the compensation filter is used to compensate the passband of the multi-stage CIC filter. Each stage of the multi-stage CIC filter is composed of a cascade of an FIR filter and a 2-extraction operation.

[0020] The compensation filter is a FIR filter, and the multiplier in the FIR filter is a CSD coded multiplier.

[0021] The specific implementation methods are as follows:

[0022] The invention discloses a low-power consumption extraction filter circuit for high-precision analog-to-digital conversion applied to a smart grid.

[0023] The sigma-delta modulation and demodulation circuit converts the input analog signal into a digital code stream output. The rate of the sampled data stream is very high, which will lead to high speed and high power consumption of subsequent signal processing. Therefore, it is necessary to slow down the data stream after analog-to-digital conversion to achieve sampling rate conversion.

[0024] To meet this demand, a low-power configurable cascade integral comb (CIC) filter structure is proposed. This structure uses a minimum 2x extraction cascade algorithm to optimize the ASIC circuit, reduce the operation logic and storage logic units, and uses canonical signed digit (CSD) coded multiplication instead of full-bit width binary complement multiplication in the gain compensation part, effectively reducing the multiplication and addition operation units, thereby reducing power consumption.

[0025] The low power consumption decimation filter circuit includes: a 5-stage CIC filter 32 decimation module and a compensation filter module;

[0026] The 5-level CIC filter 32 extraction module is used to match the noise suppression filter and downsample the sampled data to complete the extraction function, reducing the frequency of high-speed data for subsequent processing;

[0027] The compensation filter module is used for the passband compensation of the CIC filter. Since the CIC filter has a roll-off in the passband, a compensation filter needs to be connected to align the passband for compensation. The compensation filter is essentially a FIR filter with multi-tap multiplication and addition operations.

[0028] The above compensation filter circuit can reduce the number of multiplication units and lower the power consumption by using CSD encoding and then performing multiplication and addition operations.

[0029] The CIC filter group adopts a 2-fold extraction cascade and reuses the operation unit to reduce the power consumption of the circuit. Its characteristic is that the recursive structure is eliminated, and each stage is composed of a cascade of FIR filters and a 2-extraction operation. Because the structure is simplified, the power consumption is reduced. At the same time, the structure has strong consistency and can be reused, which further reduces the power consumption.

[0030] The compensation filter is a FIR filter, which is composed of a series of multipliers and adders. CSD coding is mainly used in multiplication, and its main function is to reduce the number of partial products. Multiplication operation is composed of addition, and multiplication itself can be regarded as a kind of addition. The multiplier is completed by the adder. The multiplier composed of many adders is very resource-intensive. How to reduce the area of ​​the multiplier is very helpful to improve the integration, and also reduce the power consumption.

[0031] The CIC filter is composed of two parts: an integrator and a comb filter.

[0032] The integral part transfer function expression is:

[0033]

[0034] The transfer function expression of the comb part is:

[0035] H C (z) = (1-z -RM ) N

[0036] The transfer function expression of the entire filter is:

[0037]

[0038] The amplitude spectrum expression of CIC filter is:

[0039]

[0040] The amplitude-frequency characteristic of the CIC filter is shown in the figure, where [0, 2π / RM] is its main lobe and the other intervals are side lobes. When RM>>1, the level of the first side lobe is 2RM / 3π, and the difference between it and the main lobe level is:

[0041]

[0042] With N-stage cascade, the stopband attenuation is N times the single-stage attenuation, that is, 13.36*N (dB). In the present invention, the cascade is 5 stages, so the stopband attenuation is 66.5 dB.

[0043] If B in is the number of bits of input data, then the maximum internal bit width is:

[0044] B out =B in +Nlg2(RM)

[0045] Where Nlg2(RM) is the maximum dynamic range growth. To prevent data overflow and save FPGA hardware resources to the maximum extent, the integral part of the integrator and the comb register bit width should be expanded to B out The present invention adopts 5-stage cascade, 32 extraction, 1-stage delay, 1-bit input bit, and 26-bit output calculation.

[0046] After the CIC filter, the amplitude-frequency response in the baseband is attenuated. In order to make the passband signal flat, a CIC compensation filter needs to be added after the CIC filter to compensate for the passband attenuation of the output signal of the CIC filter. Its essence is a multi-order FIR filter.

[0047] The decimation factor is set to an integer power of 2, and the delay coefficient is set to 1. The transfer function H(z) can be expressed as:

[0048]

[0049] When the extraction multiple is 32, log232 is 5, and the number of stages N is 5, then

[0050]

[0051] The conversion process is shown in the figure. The recursive structure is eliminated, and each stage consists of a cascade of FIR filters and a 2-decimation operation. Because the structure is streamlined, power consumption is reduced. At the same time, the structure is highly consistent and can be reused, which further reduces power consumption.

[0052] Realization of compensation filter using CSD coding principle

[0053] The compensation filter is a FIR filter, which is composed of a series of multipliers and adders. CSD coding is mainly used in multiplication, and its main function is to reduce the number of partial products. Multiplication operation is composed of addition, and multiplication itself can be regarded as a kind of addition. The multiplier is completed by the adder. The multiplier composed of many adders is very resource-intensive. How to reduce the area of ​​the multiplier is very helpful to improve the integration, and also reduce the power consumption.

[0054] The CSD encoding method is as follows:

[0055] (1) Starting from the least significant bit, replace all sequences of 1s greater than 2 with 102 (2 represents negative 1);

[0056] (2) Starting from the least significant bit, replace 1011 with 1102;

[0057] (3) Starting from the most significant bit, replace 101 with 022 to obtain more zero bits in the coefficient.

[0058] From the above CSD code encoding method, we can conclude that any two adjacent bits must contain 1 0, so the number of non-0 elements in the CSD representation will not exceed half of the bit width. Therefore, using the CSD encoding representation to encode the multiplier coefficients can obtain more 0 bits, which can optimize the area of ​​the multiplier and reduce power consumption.

[0059] The essence of CSD coding is to change the original addition into a subtraction operation. Take binary code as an example. If a binary number is 0110, then this binary number can be written as 1020, where 2 represents -1, which is equivalent to a borrow operation. This encoding method does not affect the data itself and can also be used in the operation rules. Moreover, after using CSD coding, the number of adders in multiplication operations can be greatly reduced.

[0060] To further illustrate the advantages of CSD coding, we will take the binary multiplication operation 1001*0101_1011 as an example. The following data are all binary data.

[0061]

[0062] The CSD encoding process of 01011011 is: 01011011 01011102 01100202 10200202

[0067] The encoded operation is

[0068]

[0069] From the above calculations, it can be seen that after CSD encoding, one adder is reduced, and the result is the same. For the compensation filter with many multiplication units, the reduced adder is quite objective, which plays a great role in improving integration and reducing power consumption.

[0070] Method Embodiment

[0071] According to an embodiment of the present invention, a low-power consumption decimation filtering method is provided. Figure 3 is a schematic diagram of a low power consumption decimation filtering method according to an embodiment of the present invention, such as Figure 3 As shown, specifically including:

[0072] A low-power extraction filtering method comprises: extracting a signal after analog-to-digital conversion through a multi-stage CIC filter to obtain an extraction signal, and compensating the passband of the multi-stage CIC filter through a compensation filter, wherein each stage of the multi-stage CIC filter is composed of a cascade of an FIR filter and a 2-extraction operation.

[0073] The compensation filter is a FIR filter, and the multiplier in the FIR filter is a CSD coded multiplier.

[0074] The embodiment of the present invention is a system embodiment corresponding to the above-mentioned method embodiment. The specific operations of each module can be understood by referring to the description of the method embodiment, which will not be repeated here.

[0075] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. These modifications or replacements of the technical solutions of the embodiments of the present invention do not cause the essence of the corresponding technical solutions to deviate from the scope of this solution.

Claims

1. A low power consumption decimation filter, characterized in that: include: A multi-stage CIC filter and a compensation filter, wherein the multi-stage CIC filter and the compensation filter are connected, the multi-stage CIC filter is used to extract the signal after analog-to-digital conversion to obtain an extracted signal, and the compensation filter is used to compensate the passband of the multi-stage CIC filter. Each stage of the multi-stage CIC filter is composed of a cascade of an FIR filter and a 2-extraction operation.

2. The low power consumption decimation filter according to claim 1, characterized in that: The compensation filter is a FIR filter.

3. The low power consumption decimation filter according to claim 1, characterized in that: The multiplier in the FIR filter is a CSD coded multiplier.

4. A low power consumption decimation filtering method, characterized in that: include: The analog-to-digital converted signal is extracted by a multi-stage CIC filter to obtain an extracted signal, and the passband of the multi-stage CIC filter is compensated by a compensation filter. Each stage of the multi-stage CIC filter is composed of a cascade of an FIR filter and a 2-extraction operation.

5. The method according to claim 4, characterized in that The compensation filter is a FIR filter.

6. The method according to claim 4, characterized in that The multiplier in the FIR filter is a CSD coded multiplier.

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