Data generation circuit for high-speed transmitter

Abstract

This application relates to the field of integrated circuit technology and discloses a data generation circuit for a high-speed transmitter. The circuit utilizes a two-stage design. The first-stage circuit unit generates a narrow pulse signal through the coordination of an input transistor, a pre-discharge control transistor, a reset control transistor, and a pre-charge control transistor. The second-stage circuit unit converts the non-full-swing pulse signal into a full-swing output signal through a pull-down transistor and multiple pull-up transistors. This application achieves stable and reliable signal generation and shaping in ultra-high-speed scenarios with unit time intervals of less than or equal to 10 picoseconds. It is suitable for high-speed transmitters operating at 1 / 4 or 1 / 8 rates and features a simple structure and precise timing.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a data generation circuit for an ultra-high-speed transmitter. Background Art

[0002] With the rapid development of communication technology and the continuous increase in data transmission rates, modern high-speed communication systems are placing increasingly stringent demands on signal quality and transmission reliability. In ultra-high-speed transmitters, 1 / 4 or 1 / 8 rate architectures are widely used. Their core concept is to use multi-phase clock signals to combine multiple low-rate data channels into full-rate data for transmission. While this architecture reduces the transmission rate requirements for a single data channel, it still faces significant technical challenges in the data synthesis process.

[0003] Especially with the trend of ever-increasing data transmission rates, the unit time interval (1-UI) has been shortened to the order of 10 picoseconds. Traditional data generation circuits struggle to fully charge and discharge MOS transistors within such a short timeframe, which directly impacts signal quality and system reliability. Existing data generation circuits typically employ simple charge-discharge structures, which can easily lead to problems such as insufficient signal amplitude, blunt edges, and inaccurate timing in ultra-high-speed scenarios. Furthermore, due to the lack of an effective pre-charge and discharge mechanism, the circuit's response speed struggles to meet the requirements of ultra-high-speed transmission.

[0004] Another prominent issue is signal swing control. In ultra-high-speed scenarios, due to the extremely limited charge and discharge time, the generated signal often fails to achieve the ideal full swing (0 to VDD). This not only reduces the signal's noise margin but also increases the difficulty of decision-making at the receiver. Existing signal shaping circuits have complex structures and cumbersome control logic, making it difficult to effectively shape the signal in an ultra-short time.

[0005] Furthermore, precise timing control between various signals in high-speed transmitters driven by multi-phase clocks is a critical issue. Traditional circuit structures struggle to ensure accurate synchronization between narrow pulse signals and control signals, which can easily lead to signal distortion and data transmission errors. Ensuring precise control of each timing node during the coordinated operation of pre-charging, pre-discharging, and signal shaping has long been a challenge plaguing the industry.

[0006] Therefore, a new data generation circuit is urgently needed that can achieve reliable signal generation and shaping within ultra-short unit time intervals, while also possessing simple structure, precise timing, and ease of implementation. This circuit should address the charging and discharging efficiency issues in ultra-high-speed scenarios, ensure the full swing characteristics of the output signal, and guarantee accurate signal transmission through a reasonable timing control mechanism, thus meeting the ever-increasing performance requirements of modern high-speed communication systems. Summary of the Invention

[0007] The purpose of this application is to provide a data generating circuit for a high-speed transmitter to solve the problems raised in the above background technology.

[0008] The present application discloses a data generating circuit for a high-speed transmitter, comprising a first-stage circuit unit and a second-stage circuit unit, wherein:

[0009] The first-stage circuit unit is used to generate a narrow pulse signal, including:

[0010] Input tube (M1), the gate is used to receive input data signals;

[0011] A pre-discharge control tube (M2), whose source is connected to the drain of the input tube (M1) to form a first intermediate node, and whose gate is used to receive the A-phase clock signal;

[0012] A reset control tube (M3), whose drain is connected to the drain of the pre-discharge control tube (M2) to form an output node, and whose gate is used to receive the A-phase clock signal;

[0013] A pre-charge control tube (M4) has a drain connected to the output node, a source for receiving a power supply voltage, and a gate for receiving a B-phase clock signal; wherein the B-phase clock signal has a predetermined time delay compared to the A-phase clock signal; the pre-discharge control tube (M2) and the pre-charge control tube (M4) respond to the A-phase clock signal and the B-phase clock signal to sequentially pre-charge and pre-discharge the output node, thereby generating a pulse signal;

[0014] The second-stage circuit unit is used to shape the pulse signal into a full-swing signal, including:

[0015] The pull-down transistor (M5) is connected between the final output node and the lowest potential, and its control terminal is used to receive a reset signal;

[0016] A plurality of pull-up tubes (M6, M7) have drains and sources respectively connected between the final output node and the power supply voltage, and a control end is used to receive the pulse signal output by the first-stage circuit unit; the pull-down tube (M5) cooperates with the pull-up tubes (M6, M7) to convert the non-full-swing pulse signal into a full-swing signal output in response to the reset signal and the pulse signal.

[0017] In a preferred example, the time width of the narrow pulse signal is 1-UI, where UI is a unit time interval, and the unit time interval UI is less than or equal to 10 picoseconds.

[0018] In a preferred example, the A-phase clock signal and the B-phase clock signal are two phases in the same group of multi-phase clock signals, wherein the multi-phase clock signal includes at least 4-phase clock signals, and the time interval between the rising edges of each adjacent two-phase clock signals is 1-UI; wherein the B-phase clock signal is 3-UI ahead of the A-phase clock signal.

[0019] In a preferred example, the gate of the input tube (M1) is connected to the input end to receive the input data signal, the source is grounded, and the drain is connected to the source of the pre-discharge control tube (M2) to form a first intermediate node (Data_int).

[0020] In a preferred embodiment, the working process of the first-stage circuit unit includes: (1) before the rising edge of the A-phase clock signal arrives, the reset control tube (M3) is turned on to pre-charge the output node (Dout_int) to the power supply voltage; before the rising edge of the A-phase clock signal arrives and after the falling edge of the B-phase clock signal arrives, the pre-charge control tube (M4) is turned on to pre-charge the output node (Dout_int) and maintain it at the power supply voltage; (2) when the rising edge of the A-phase clock signal arrives, the pre-discharge control tube (M2) is turned on to discharge the output node to a preset level; (3) when the rising edge of the B-phase clock signal arrives, the pre-charge control tube (M4) is turned off, and the output node is further discharged to the lowest potential; (4) when the falling edge of the A-phase clock signal arrives, the reset control tube (M3) is turned on and the pre-discharge control tube (M2) is turned off to reset and charge the output node to the power supply voltage.

[0021] In a preferred example, it also includes at least one group of reset signal generating circuits for generating a reset signal synchronized with the pulse signal based on a multi-phase clock signal, and the reset signal generating circuit includes: a first AND gate, whose input ends are respectively connected to the second clock signal and the fourth clock signal, for performing an AND operation on the two; a second AND gate, whose input ends are respectively connected to the sixth clock signal and the eighth clock signal, for performing an AND operation on the two; and a NOR gate, whose input ends are respectively connected to the output ends of the first AND gate and the second AND gate, for performing an NOR operation on the output signals of the two, and whose output end is used to output the reset signal.

[0022] In a preferred embodiment, the reset signal generating circuit receives an 8-phase clock signal as an input signal, and the time interval between rising edges of two adjacent clock signals is 1-UI.

[0023] In a preferred embodiment, the operation process of the second-stage circuit unit includes:

[0024] When the reset signal is at a high level and the pulse signal output by the first-stage circuit unit is at a high level, the pull-down tube (M5) is turned on to discharge the final output node to the zero potential;

[0025] When the reset signal is at a low level and the pulse signal output by the first-stage circuit unit is at a low level, the plurality of pull-up tubes (M6, M7) are alternately turned on to charge the final output node to the power supply voltage.

[0026] In a preferred embodiment, the data generating circuit is used for a high-speed transmitter of 1 / 4 rate or 1 / 8 rate.

[0027] The embodiments of this application have the following technical effects:

[0028] The data generation circuit proposed in this application adopts a two-stage structure design, which successfully solves the key problems of signal generation and shaping in ultra-high-speed scenarios. The first-stage circuit realizes the efficient generation of narrow pulse signals through the ingenious cooperation of the input tube (M1), the pre-discharge control tube (M2), the reset control tube (M3) and the pre-charge control tube (M4). Especially in the extremely short 1-UI with a time interval of less than or equal to 10 picoseconds, the reliable generation of the signal is ensured through multiple precisely controlled stages such as pre-charge and pre-discharge. The second-stage circuit converts the non-full-swing pulse signal into a full-swing signal through the coordinated work of the pull-down tube (M5) and multiple pull-up tubes (M6, M7), significantly improving the signal quality.

[0029] In terms of timing control, the present application utilizes the delay relationship between the A-phase clock signal and the B-phase clock signal, in conjunction with the synchronous RST signal output by the reset signal generation circuit, to achieve precise timing coordination. For a 1 / 8 rate structure, the A-phase and B-phase clock signals differ by 3-UI; for a 1 / 4 rate structure, the A-phase and B-phase clock signals differ by 1-UI. Specifically, in the first-stage circuit, the pre-charge control tube and the pre-discharge control tube work alternately to complete the signal's pre-charge, pre-discharge, full discharge, and reset charge processes. This carefully designed timing arrangement ensures that all necessary signal processing steps are completed in an ultra-short time.

[0030] It is noteworthy that the reset signal generation circuit of the present application generates a reset signal synchronized with the 1-UI pulse by using a simple combination of two AND gates and a NOR gate, utilizing specific phase combinations in a multi-phase clock signal. It should be noted that the specific number of groups and clock combinations in the reset signal generation circuit will vary depending on the rate used by the transmitter.

[0031] Taking a 1 / 8 rate transmitter as an example, since an 8-phase clock (CK1 / CK2 / … / CK7 / CK8) is used, four sets of reset signals are required. In addition to the CK2 / CK4 / CK6 / CK8 set mentioned above, the generation logic of the remaining three sets of reset signals are as follows:

[0032] The second group: perform AND operation on CK2 and CK8, and perform AND operation on CK4 and CK6, and then perform NOR operation on the two AND operation results.

[0033] The third group: perform AND operation on CK3 and CK5, and perform AND operation on CK1 and CK7, and then perform NOR operation on the two AND operation results.

[0034] The fourth group: CK5 and CK7 are ANDed, CK1 and CK3 are ANDed, and then the two ANDed results are NORed.

[0035] Each reset signal group consists of two AND gates and a NOR gate, with different clock combinations as inputs. The four reset signals are staggered by 1 UI and synchronized with the corresponding 1 UI data pulses, achieving precise timing control.

[0036] For a 1 / 4 rate transmitter, since a 4-phase clock is used, only two reset signals are required. The generation logic for these signals can refer to the 1 / 8 rate case, and the appropriate clock combination can be selected.

[0037] The introduction of multiple sets of reset signals is an important innovation in timing control of this application. By utilizing different clock combinations, the phases of each set of reset signals are cleverly staggered, avoiding signal conflicts while ensuring that each 1-UI data pulse can be reset synchronously. This design not only simplifies the circuit structure but also greatly improves the reliability of the system. In ultra-high-speed scenarios, this multiple-set reset signal solution undoubtedly provides greater flexibility and adaptability for the implementation of data generation circuits.

[0038] In summary, the reset signal generation scheme described above fully demonstrates the innovative approach of this application in timing optimization. By designing multiple reset signal groups tailored to specific conditions, it effectively solves the critical timing issues in ultra-high-speed data transmission. This design, together with the 1-UI pulse generation circuit and full-swing conversion circuit, constitutes the complete technical solution of this application, demonstrating strong feasibility and practical value.

[0039] This design not only simplifies the circuit structure but also ensures the accuracy of signal shaping. In particular, in the second-stage circuit, the RST signal cooperates with the pulse signal to control the conduction state of the pull-down and pull-up transistors, achieving a stable full-swing signal output.

[0040] Overall, this application is applicable to high-speed transmitters operating at 1 / 4 or 1 / 8 rates, achieving complex signal processing capabilities through a simple circuit structure. The operating processes of all MOS transistors in the circuit are closely coordinated and mutually interactive, ensuring both signal quality and reliable circuit operation. This design not only solves the signal processing challenges in ultra-high-speed scenarios but also has strong engineering practicality, providing important technical support for the development of high-speed communication systems.

[0041] The specification of this application records a large number of technical features, which are distributed in various technical solutions. If all possible combinations of technical features of this application (i.e., technical solutions) are to be listed, the specification will be too lengthy. In order to avoid this problem, the various technical features disclosed in the above-mentioned invention content of this application, the various technical features disclosed in the various embodiments and examples below, and the various technical features disclosed in the accompanying drawings can be freely combined with each other to form various new technical solutions (these technical solutions are all deemed to have been recorded in this specification), unless such a combination of technical features is technically infeasible. For example, in one example, feature A+B+C is disclosed, and in another example, feature A+B+D+E is disclosed. Features C and D are equivalent technical means that play the same role. Technically, only one of them can be used, and it is impossible to use them at the same time. Feature E can be technically combined with feature C. Then, the solution of A+B+C+D should not be considered as having been recorded because it is technically infeasible, while the solution of A+B+C+E should be considered as having been recorded. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 1-UI data and RST signal generation timing diagram according to an embodiment of the present application.

[0043] Figure 2 1-UI data generation circuit according to an embodiment of the present application, wherein: Figure 2 (a) is a schematic diagram of the structure of a 1-UI data circuit, which is an example of a plurality of 1-UI data generation circuits (a 1 / 8 rate transmitter requires 8 such 1-UI data generation circuits, and a 1 / 4 rate transmitter requires 4 such 1-UI data generation circuits); Figure 2 (b) is a schematic diagram of the voltage waveform of the key node; Figure 2 (c) is a schematic diagram of the node voltage timing, which shows the detailed change process of the Dout_int node voltage under the control of the clock signals CK1 and CK6 and the corresponding relationship between the two.

[0044] Figure 3 1-UI data full swing circuit diagram according to an embodiment of the present application, wherein: Figure 3 (a) is a schematic diagram of the full-swing conversion circuit; Figure 3 (b) is a schematic diagram of the structure of the RST signal generating circuit, which is an example of multiple reset signal generating circuits; Figure 3 (c) is a schematic diagram of the voltage waveform of the key node. DETAILED DESCRIPTION

[0045] In the following description, many technical details are provided to help readers better understand this application. However, those skilled in the art will understand that even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in this application can be implemented.

[0046] Description of some concepts:

[0047] In digital communication systems, a unit interval (UI) represents the duration of a data bit. In this application, 1-UI refers to the minimum time unit required to transmit a single data bit, which can be as small as 10 picoseconds in ultra-high-speed scenarios. This fundamental time unit plays a key role in signal generation and processing.

[0048] A full-swing signal is one whose voltage swings completely between the power supply voltage (VDD) and ground (0V). Compared to non-full-swing signals, full-swing signals offer greater noise tolerance and better signal integrity, which are crucial for ensuring reliable data transmission.

[0049] Pre-charging is the process of precharging the output node to the power supply voltage VDD before actual data transmission. In this application, this process is achieved by turning on the M4 transistor to prepare for subsequent signal generation. The introduction of pre-charging significantly improves the circuit's response speed.

[0050] Pre-discharge is the process of discharging the node voltage to a specific level (Vout_precharge) before fully discharging. This process is controlled by the M2 transistor and is one of the key steps in achieving high-speed signal generation in this application, laying the foundation for obtaining the ideal signal waveform.

[0051] Quarter-rate and eighth-rate modes operate in which the transmitter's maximum clock frequency is 1 / 4 or 1 / 8 of the full-rate, respectively. This structure, widely used in high-speed transmitters, uses a multi-phase clock to combine multiple low-rate data channels into full-rate data, effectively reducing the transmission rate requirements for a single data channel.

[0052] A multi-phase clock is a set of clock signals with a fixed phase difference. This application uses eight phase clocks (CK1-CK8), where the phase difference between adjacent clock signals is 1-UI. The precise coordination of these clock signals is the basis for achieving high-speed data transmission.

[0053] A multi-phase clock is a set of clock signals with a fixed phase difference. This application uses different numbers of phase clocks depending on the transmitter rate requirements: for a 1 / 8 rate transmitter, 8 phase clocks (CK1-CK8) are used; for a 1 / 4 rate transmitter, 4 phase clocks (CK1-CK4) are used. In both cases, the phase difference between adjacent clock signals is 1-UI. The precise coordination of these clock signals is the basis for achieving high-speed data transmission.

[0054] The RST signal (Reset Signal) is a reset control signal used to control signal shaping. It is synchronized with the 1-UI pulse and controls the critical operating timing in the full-swing conversion circuit to ensure accurate signal shaping.

[0055] Reset Charge is the process of restoring the output node voltage to its initial level. This process is achieved by turning on the M3 transistor, making full preparations for the signal generation of the next cycle and ensuring continuous and stable operation of the circuit.

[0056] Pull-up and pull-down transistors are MOS transistors used to pull node voltages up to VDD or down to ground, respectively. In this application's full-swing conversion circuit, M5 acts as a pull-down transistor, while M6 / M7 act as pull-up transistors. Their coordinated operation enables full-swing signal conversion.

[0057] A non-full swing pulse is a pulse signal whose voltage swing does not reach 0 to VDD. This signal is an original signal that needs to be shaped. After the processing of this application, it can be converted into an ideal full swing signal, thereby improving the reliability of the system.

[0058] The following is a summary of some of the innovative features of this application:

[0059] In general, this application relates to a 1-UI data generation circuit for an ultra-high-speed transmitter. In the field of ultra-high-speed data transmission, as the unit time interval (1-UI) has been shortened to approximately 10 ps, ​​achieving complete charging and discharging of MOS transistors in such a short period of time has become a major technical challenge. Therefore, as one of the most critical modules in an ultra-high-speed transmitter, the performance of the 1-UI data generation circuit directly affects the reliability of the entire system.

[0060] To address this technical challenge, this application proposes an innovative circuit solution that achieves reliable generation of 1-UI data through the sophisticated coordination of four MOS transistors. The basic operating process of the circuit is as follows: first, input transistor M1 is used to control the input data. When the input data is at a high level, M1 turns on to ensure data readiness; before the rising edge of the B-phase clock signal (such as CK1), the output node is precharged to the VDD level through transistor M4; when the rising edge of the A-phase clock signal (such as CK6) arrives, transistor M2 turns on and causes the output node to begin pre-discharging until it reaches the preset Vout_precharge level; then, when the rising edge of the B-phase clock signal (CK1) arrives, transistor M4 turns off, and the circuit enters the full discharge phase; finally, after the falling edge of the A-phase clock signal (CK6), transistor M2 turns off and transistor M3 turns on, resetting and charging the output node to VDD, preparing for the next cycle. By continuously cycling these steps, a 1-UI pulse signal can be reliably generated. To further improve signal quality, this application also introduces an RST control signal and a shaping amplifier circuit consisting of three MOS tubes at the output stage to convert the non-full-swing pulse signal into a full-swing signal from 0 to VDD. The innovation of this design is mainly reflected in three aspects: first, through the precise coordination of four MOS tubes and a multi-phase clock, a complete pre-charge, pre-discharge, full discharge, and reset charging process is achieved in an extremely short 1-UI time; second, the RST signal and the shaping amplifier circuit of the three MOS tubes are used to ensure the full-swing characteristics of the output signal; finally, the overall circuit structure is simple and does not require complex control logic, making it very suitable for applications in ultra-high-speed scenarios.

[0061] This application successfully achieves the generation and shaping of ultra-short 1-UI pulses by cleverly utilizing the on-off timing of MOS tubes and the coordination of multi-phase clocks, significantly improving the circuit's response speed. This design not only solves the signal generation problem in ultra-high-speed scenarios, but also has the advantages of simple structure and high reliability, representing a practical and feasible ultra-high-speed signal processing solution.

[0062] Figure 1 This is a timing diagram of the 1-UI data generation circuit of this application, which focuses on showing how to use a multi-phase clock to accurately control the generation of 1-UI pulse signals and the synchronization of reset signals in ultra-high-speed data transmission scenarios.

[0063] As shown in the figure, the present application uses an 8-phase clock signal (CK1 to CK8), where the time interval between the rising edges of two adjacent clocks is 1 unit interval (UI). These 8-phase clocks serve as both the timing control signal of the present application circuit and the reference clock for data splicing.

[0064] It should be noted that in the description of this application, the above-mentioned 8-phase clock signal is represented by symbols such as CK1 and CK2, where the numbers represent the serial numbers of the clock phases. It should be noted that the multi-phase clock signal used in this application is not limited to 8 phases, and it can be flexibly set according to the rate requirements of the transmitter in actual applications (such as 1 / 4 rate or 1 / 8 rate). For example, in a 1 / 4 rate application scenario, a total of 4-phase clock signals from CK1 to CK4 can be used; and in a 1 / 8 rate application scenario, a total of 8-phase clock signals from CK1 to CK8 can be used. For ease of description, this application takes 1 / 8 rate and 8-phase clock signals as an example for explanation, but the embodiments are not limited to this.

[0065] When an 8-phase clock signal is used, the definitions of each clock signal are as follows:

[0066] CK1 represents the first clock signal

[0067] CK2 represents the second clock signal

[0068] CK3 represents the third clock signal

[0069] CK4 represents the fourth clock signal

[0070] CK5 represents the fifth clock signal

[0071] CK6 represents the sixth clock signal

[0072] CK7 represents the seventh clock signal

[0073] CK8 represents the eighth clock signal

[0074] In the following description, the above symbols will be used uniformly to refer to the corresponding clock signals to maintain consistency and simplicity. This unified description method helps to understand the key technical points of this application, such as using multi-phase clocks to accurately control signal timing and achieve data splicing.

[0075] Taking D1_LOW as an example, after this low-speed data signal is processed by the 1-UI data generation circuit of this application, a narrow pulse signal D1_UI with a width of only 1-UI is generated in coordination with the rising edges of CK6 and CK1. Using a similar method, other low-speed data signals can also generate corresponding 1-UI pulse signals.

[0076] To further improve the quality of the 1-UI pulse signal, this application also introduces an RST reset signal. Taking RST1 as an example, this reset signal is generated by the combinational logic of CK2 to CK8. It remains low during the D1_UI pulse and high at other times. RST1 is strictly synchronized with D1_UI in time and is used to control the subsequent shaping circuit to shape the 1-UI pulse into a full-swing signal.

[0077] Finally, all 1-UI pulse signals (i.e., D1_UI, D2_UI, ..., D8_UI) are alternately spliced ​​in sequence in a time-division multiplexing manner to form a complete high-speed data output signal DOUT_HIGH. It can be seen that each data bit in DOUT_HIGH corresponds to a 1-UI pulse.

[0078] In summary, the present application cleverly utilizes the time interval characteristics of multi-phase clocks and the precise coordination between different clocks to reliably generate and shape 1-UI pulse signals, thereby realizing ultra-high-speed serial transmission of data. Figure 1 It vividly demonstrates the timing control relationship of this application and intuitively reveals its core innovative ideas.

[0079] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0080] The first embodiment of the present application relates to a data generating circuit for a high-speed transmitter, such as Figure 2 and Figure 3 As shown, it includes a first-level circuit unit and a second-level circuit unit.

[0081] The first-stage circuit unit is used to generate a narrow pulse signal, including:

[0082] Input tube (M1), the gate is used to receive input data signals;

[0083] A pre-discharge control tube (M2), whose source is connected to the drain of the input tube (M1) to form a first intermediate node, and whose gate is used to receive the A-phase clock signal;

[0084] A reset control tube (M3), whose drain is connected to the drain of the pre-discharge control tube (M2) to form an output node, and whose gate is used to receive the A-phase clock signal;

[0085] A pre-charge control tube (M4) has a drain connected to the output node, a source for receiving a power supply voltage, and a gate for receiving a B-phase clock signal; wherein the B-phase clock signal has a predetermined time interval compared to the A-phase clock signal; the pre-discharge control tube (M2) and the pre-charge control tube (M4) respond to the A-phase clock signal and the B-phase clock signal to sequentially pre-charge and pre-discharge the output node, thereby generating a pulse signal;

[0086] The second-stage circuit unit is used to shape the pulse signal into a full-swing signal, including:

[0087] The pull-down transistor (M5) is connected between the final output node and the lowest potential, and its control terminal is used to receive a reset signal;

[0088] A plurality of pull-up tubes (M6, M7) have their source and drain electrodes respectively connected between the final output node and the power supply voltage, and a control terminal is used to receive the pulse signal output by the first-stage circuit unit; the pull-down tube (M5) cooperates with the pull-up tubes (M6, M7) to convert the non-full-swing pulse signal into a full-swing signal output in response to the reset signal and the pulse signal.

[0089] Optionally, the time width of the narrow pulse signal is 1-UI, where UI is a unit time interval, and the unit time interval UI is less than or equal to 10 picoseconds.

[0090] Optionally, the A-phase clock signal and the B-phase clock signal are two phases in the same group of multi-phase clock signals, wherein the multi-phase clock signal includes at least 4-phase clock signals, and the time interval between the rising edges of each adjacent two-phase clock signals is 1-UI; wherein the B-phase clock signal is 3-UI ahead of the A-phase clock signal.

[0091] Optionally, the gate of the input tube (M1) is connected to the input end to receive the input data signal, the source is grounded, and the drain is connected to the source of the pre-discharge control tube (M2) to form a first intermediate node (Data_int).

[0092] Optionally, the working process of the first-stage circuit unit includes: (1) before the rising edge of the A-phase clock signal arrives, the reset control tube (M3) is turned on to pre-charge the output node (Dout_int) to the power supply voltage; in the time period before the rising edge of the A-phase clock signal arrives and after the falling edge of the B-phase clock signal arrives, the pre-charge control tube (M4) is turned on, and the output node (Dout_int) is pre-charged and maintained at the power supply voltage; (2) when the rising edge of the A-phase clock signal arrives, the pre-discharge control tube (M2) is turned on to discharge the output node to a preset level; (3) when the rising edge of the B-phase clock signal arrives, the pre-charge control tube (M4) is turned off, and the output node is further discharged to the lowest potential; (4) when the falling edge of the A-phase clock signal arrives, the reset control tube (M3) is turned on, the pre-discharge tube (M2) is turned off, and the output node is reset and charged to the power supply voltage.

[0093] Optionally, the circuit further includes at least one reset signal generating circuit for generating a reset signal synchronized with the pulse signal based on a multi-phase clock signal. For ease of understanding, the structure of one of the reset signal generating circuits is described below using one of the reset signal generating circuits as an example. The reset signal generating circuit includes: a first AND gate, whose inputs are connected to the second clock signal and the fourth clock signal, respectively, for performing an AND operation on the two; a second AND gate, whose inputs are connected to the sixth clock signal and the eighth clock signal, respectively, for performing an AND operation on the two; and a NOR gate, whose inputs are connected to the outputs of the first AND gate and the second AND gate, respectively, for performing an NOR operation on the output signals of the two, and whose output is used to output the reset signal. The structures of the other reset signal generating circuits are the same, differing only in the different clock signal combinations selected.

[0094] Optionally, the reset signal generating circuit receives an 8-phase clock signal as an input signal, and the time interval between rising edges of two adjacent clock signals is 1-UI.

[0095] Optionally, the working process of the second-stage circuit unit includes:

[0096] When the reset signal is at a high level and the pulse signal output by the first-stage circuit unit is at a high level, the pull-down tube (M5) is turned on to discharge the final output node to the zero potential;

[0097] When the reset signal is at a low level and the pulse signal output by the first-stage circuit unit is at a low level, the plurality of pull-up tubes (M6, M7) are alternately turned on to charge the final output node to the power supply voltage.

[0098] Optionally, the data generating circuit is used for a high-speed transmitter with a 1 / 4 rate or a 1 / 8 rate.

[0099] The following further Figure 2 and Figure 3 Provide explanation.

[0100] Figure 2 This is a specific implementation diagram of the 1-UI data generation circuit. When the input data is high, M1 is turned on and the voltage of the node Data_int is pulled down to 0, preparing for the subsequent discharge process. When the input data is low, M1 is turned off. At this time, even if the CK6 and CK1 clock signals work normally, the Dout_int node will always remain at the pre-charged high level VDD and no 1-UI pulse will be generated. Figure 2 (a) and Figure 2 In (b), its working principle is as follows:

[0101] (1) In the pre-charge phase, the input data signal needs to be considered. When the input data is high, M1 is turned on and the node Data_int is pulled down to a low level. At this time, if CK1 is high and CK6 is low, M3 is turned on, M2 is turned off, and the output node Dout_int is charged to the VDD level; after CK1 becomes low and before the rising edge of CK6 arrives, M4 is turned on and the output node Dout_int is maintained at the VDD level. It should be noted that the above pre-charge process is based on the premise that the input data signal is high. When the input data is low, M1 is turned off and the node Data_int always remains at a high level. At this time, regardless of the levels of CK1 and CK6, since the M2 source is not driven at a low level, the Dout_int node cannot be discharged and will always remain at the VDD level.

[0102] (2) When the rising edge of CK6 arrives (CK1 is at a high level at this time), M2 and M4 are turned on (M3 is turned off). Under the joint action of M2 and M4, Dout_int begins to pre-discharge, and the voltage drops to a certain value Vout_precharge. This process is the pre-discharge achieved by M2 and M4.

[0103] (3) When the rising edge of CK1 arrives (CK6 is still high at this time), M3 / M4 are turned off. With M2 continuously turned on, Dout_int enters the full discharge stage and the voltage further drops to close to VSS. At this time, the 1-UI pulse is generated.

[0104] (4) When the falling edge of CK6 arrives, M2 is turned off, M3 is turned on, and Dout_int is reset and charged back to VDD, preparing for the next cycle.

[0105] (5) Input data Data is controlled by M1 and is ready at the Data_int node. M1 is equivalent to an input switch, and its working conditions can be divided into two types:

[0106] When the input data is high, M1 is turned on and the Data_int node is pulled down to a low level. This low-level signal is transmitted to the source of M2. Under the coordination of the CK6 and CK1 clocks, the Dout_int node will generate a narrow pulse signal with a width of 1-UI.

[0107] When the input data is low, M1 is off, and the Data_int node is in a high-impedance state. Its voltage is determined by parasitic capacitance and is typically near VDD. Even if the CK6 and CK1 clocks are operating normally, the Dout_int node cannot discharge because the M2 source is not driving low, and remains in its precharged high state. In other words, the output node does not generate a 1-UI pulse, and the circuit is in a silent state.

[0108] In summary, the conduction status of transistor M1 directly affects the operation of subsequent circuits. The Dout_int node generates a 1-UI pulse in sync with the clock signal only during periods when the input data is high. When the input data is low, the output node remains static. This design ensures accurate control of the output pulse by the input data.

[0109] (6) During the entire process, M1, M2, M3, and M4 cooperate with the timing of CK1 and CK6 to reliably generate a pulse signal within the 1-UI time.

[0110] (7) Figure b shows a schematic diagram of the voltage waveforms of each key node, which intuitively shows the working process of the circuit within 1-UI.

[0111] In summary, this circuit utilizes the on / off switching of four MOS transistors, combined with the timing coordination of a two-phase clock, to efficiently generate a 1-UI pulse. Its key innovation lies in cleverly integrating multiple stages—pre-charge, pre-discharge, full discharge, and reset charge—into the 8UI timeframe, fully utilizing limited time resources.

[0112] Further, Figure 2(c) is a schematic diagram of the voltage waveform timing of the key node Dout_int in the data generation circuit of the present invention, which further shows the details of the changes in the node voltage under the control of the clock signals CK1 and CK6. As shown in the figure, the voltage of Dout_int goes through three main stages: reset, pre-discharge, and generation of 1-UI pulses. Specifically, it can be seen in the figure that when the falling edge of CK6 arrives (at this time, the rising edge of CK1 has already changed to a high level 1UI in advance), the Dout_int node will be reset (also called pre-charge) to the VDD level, and the reset time lasts for 4UI. This sufficient time can ensure complete reset. Subsequently, when the rising edge of CK6 arrives (at this time CK1 is a low level), Dout_int starts pre-discharge (pre-discharge), and the 3UI time between the rising edge of CK6 and the falling edge of CK1 is used to realize the drop of the node voltage. After the rising edge of CK1 arrives, Dout_int is further pulled down for 1UI time to form a narrow pulse signal with a width of 1-UI. Finally, the arrival of the next falling edge of CK6 (at this time CK1 has recovered to a high level) starts the reset of Dout_int again, and the circuit repeats the above waveform change cycle. Figure 2 The precise correspondence between the Dout_int node voltage and the CK1 and CK6 clock signals in (c) intuitively reflects the innovative idea of ​​the circuit of the present invention to reliably generate 1-UI pulse signals within limited time resources through carefully designed timing control.

[0113] Figure 3 (a) is a schematic diagram of a 1-UI data full swing circuit, which is used to Figure 2 The 1-UI pulse signal generated in the circuit is shaped into a signal with full swing (i.e. 0 to VDD).

[0114] Its main circuit structure and working principle are as follows:

[0115] 1. Introduce an RST control signal and three MOS tubes (M5, M6, M7) to realize the shaping and amplification of the 1-UI pulse signal.

[0116] 2. When the falling edge of the 1-UI pulse signal (Dout_int1 or Dout_int2) arrives, the RST signal is at a low level. At this time, M5 is turned off and M6 or M7 is turned on, charging the final output node Dout to the VDD level.

[0117] 3. When the rising edge of the 1-UI pulse signal (Dout_int1 or Dout_int2) arrives, the RST signal is at a high level. At this time, M6 and M7 are both turned off, and M5 is turned on, discharging the final output node Dout to 0 (VSS).

[0118] 4. By coordinating the timing of the RST signal and the 1-UI pulse signal through M5, M6, and M7, the non-full-swing 1-UI pulse can be reliably converted into a rail-to-rail full-swing signal output.

[0119] so Figure 3 The circuit in (a) is used as Figure 2 The subsequent stage of the circuit further improves the swing and quality of the output signal and is an important component of the 1-UI data generation circuit. The RST signal is generated by a multi-phase clock combination to ensure synchronization with the 1-UI pulse.

[0120] Figure 3 (b) is a schematic diagram of the RST signal generation circuit. Its function is to generate the RST control signal synchronized with the 1-UI pulse based on the multi-phase clock signal. Figure 3 The shaping circuit in (a) provides appropriate control timing.

[0121] The specific circuit structure is as follows:

[0122] 1. Two AND gates, performing AND operations on CK2 and CK4, and CK6 and CK8 respectively.

[0123] 2. A NOR gate that performs a NOR operation on the output results of the two AND gates to obtain the final RST signal.

[0124] Its working principle is:

[0125] 1. Assume that the input is an 8-phase clock signal (CK1 to CK8), and the interval between the rising edges of each adjacent clock is 1-UI.

[0126] 2. The first AND gate performs AND operation on CK2 and CK4. Its output is high when and only when CK2 and CK4 are both high, and the corresponding RST signal should be low.

[0127] 3. Similarly, the second AND gate performs AND operation on CK6 and CK8. When and only when CK6 and CK8 are both high, its output is high, and the corresponding RST signal should be low.

[0128] 4. The last NOR gate performs a NOR operation on the outputs of the two AND gates. The RST signal is high only when the outputs of both AND gates are low, otherwise it is low.

[0129] 5. This generates an RST control signal synchronized with the 1-UI pulse, which is low when CK2 / CK4 are simultaneously high or CK6 / CK8 are simultaneously high, and high at other times.

[0130] so Figure 3 The circuit in (b) uses the combinational logic of multi-phase clocks to cleverly generate the required RST control signal. Figure 3 The shaping circuit in (a) provides precise control timing, thereby reliably achieving shaping and amplification of the 1-UI pulse signal.

[0131] Figure 3 (c) shows the voltage waveforms of the key nodes of the 1-UI data full swing circuit, which clearly reflects the complete working process of the circuit within the 1-UI time. Figure 3 (a) The shaping effect of the M5-M7 tubes on the input pulse signal, and the control timing of the RST signal.

[0132] First, from the waveform (red) of the Dout_int node, this is caused by Figure 2 The initial 1-UI pulse signal generated by the circuit. This waveform illustrates the complete charge and discharge process: starting from the VDD level, dropping to the Vout_precharge voltage through the pre-discharge phase, and then entering the full discharge phase until it reaches near ground, forming a characteristic narrow pulse shape. This process demonstrates the precise timing control of the previous stage circuit.

[0133] Secondly, the waveform of the RST signal (green) shows the timing characteristics of the reset control. Figure 3 The control signal generated by the circuit in (b) remains low during the 1-UI pulse. Its falling edge arrives 1 UI ahead of the falling edge of the 1-UI pulse, and its rising edge is strictly synchronized with the rising edge of the 1-UI pulse. The RST signal controls the conduction state of transistor M5, achieving precise timing control of the output node: when RST is high, M5 turns on and pulls down the output; when RST is low, M5 turns off and allows the output to be pulled up.

[0134] Finally, the Dout output waveform (red) after shaping clearly shows the full-swing characteristic.

[0135] The working process can be divided into three stages:

[0136] 1. When RST is low (the 1-UI pulse has not yet arrived), M6 and M7 are turned off, and M5 is turned on, discharging Dout to the ground level.

[0137] 2. When 1UI time passes before the falling edge of the 1-UI pulse, RST becomes low, M5 turns off, and Dout remains at the ground level; after the falling edge of the 1-UI pulse, M6 or M7 turns on, and Dout is charged to VDD.

[0138] 3.1-When the UI pulse ends (rising edge arrives), the rising edge of RST also arrives synchronously, M6 / M7 is turned off, M5 is turned on, and Dout is discharged to a low level under the action of M5.

[0139] It's worth noting that due to the strong pull-down capability of M5, the falling edge of Dout exhibits a sharp slope. However, the rising edge is relatively flat due to the alternating conduction of M6 and M7 and the parasitic RC effect. Despite this, the final output Dout signal still achieves a stable full swing from 0 to VDD, significantly improving signal quality.

[0140] This set of waveforms fully captures the shaping process of the 1-UI pulse signal, demonstrating the circuit's precise timing control and reliable operation. The coordinated changes in the voltages at three key nodes intuitively demonstrate the application's innovative design concept for ultra-high-speed signal processing.

[0141] Working principle:

[0142] The operation of the above embodiment can be divided into two core components: the first-stage circuit generates 1-UI pulses, and the second-stage circuit completes the full-swing conversion of the signal. The first-stage circuit operates under the control of a multi-phase clock through the precise coordination of four MOS transistors; the second-stage circuit uses three MOS transistors and the RST signal to achieve signal shaping.

[0143] First, the working process of the first stage circuit is as follows Figure 2 As shown. Due to the 1 / 8 rate structure, the input data signal is relatively slow, which can ensure that the input tube M1 is fully turned on and the level of the node Data_int is stable. The operation of the circuit can be divided into two cases:

[0144] When the input data is high, M1 turns on, pulling Data_int down to a low level. During the precharge phase, clock CK1 is low, and precharge control transistor M4 turns on, charging the output node Dout_int to the VDD level. When the rising edge of CK6 arrives, pre-discharge control transistor M2 turns on and reset control transistor M3 turns off, causing Dout_int to begin pre-discharge, with the voltage dropping to the preset Vout_precharge level. Subsequently, when the rising edge of CK1 arrives, pre-charge control transistor M4 turns off, and the circuit enters the full discharge phase, causing the Dout_int voltage to drop further. Finally, when the falling edge of CK6 arrives, M2 turns off and M3 turns on, resetting Dout_int to VDD and preparing for the next cycle. This precise timing control ensures the reliable generation of narrow pulse signals within the 1-UI time.

[0145] When the input data is low, M1 is off, and the Data_int node remains high. Regardless of how the CK6 and CK1 clocks change, the Dout_int node cannot discharge because M2's source is not driving it low, maintaining the Dout_int node at VDD. In other words, during periods when the input is low, the output node does not generate a 1-UI pulse, and the circuit is in a silent state.

[0146] In summary, only when the input data is high does the first-stage circuit initiate a series of actions, such as pre-charging and pre-discharging, generating a narrow pulse within the 1-UI time. During periods when the input data is low, the circuit remains idle. The high and low levels of the input data directly control the generation of the output pulse.

[0147] Secondly, the working process of the second stage circuit is as follows Figure 3 As shown. The RST signal is Figure 3 The combinational logic circuit shown in (b) is generated by performing logical operations on the four even-phase clock signals CK2 / CK4 / CK6 / CK8. When RST is low and Dout_int1 or Dout_int2 is low, pull-up transistor M6 or M7 turns on, while pull-down transistor M5 turns off. At this time, output node Dout is charged to VDD. When RST is high (Dout_int1 or Dout_int2 also goes high), M5 turns on and M6 / M7 turns off, pulling Dout down to ground. In this way, the non-full-swing Dout_int signal is converted to a full-swing signal from 0 to VDD.

[0148] The RST signal generation circuit adopts a simple combinational logic structure, such as Figure 3 As shown in (b), two AND gates perform AND operations on CK2 / CK4 and CK6 / CK8, respectively, and then pass through a NOR gate to generate the final RST signal. This design ensures precise synchronization of the RST signal with the 1-UI pulse, thereby ensuring accurate signal shaping.

[0149] The working waveform of the entire circuit is as follows Figure 3 As shown in Figure (c), it can be clearly seen that after the second-stage circuit processes the non-full-swing pulse of Dout_int, a good full-swing square wave signal is obtained at the output node Dout. This signal has a larger noise tolerance and better signal integrity, making it ideal for transmission in ultra-high-speed systems.

[0150] The above embodiment successfully realizes signal generation and shaping in an ultra-short time through ingenious circuit design and precise timing control, providing a reliable technical solution for ultra-high-speed data transmission.

[0151] Furthermore, the above embodiment proposes an innovative two-stage ultra-high-speed data generation circuit. The first-stage circuit achieves reliable narrow pulse signal generation in an extremely short time of less than 10 picoseconds by precisely coordinating the input tube, pre-discharge control tube, reset control tube and pre-charge control tube, and utilizing the phase difference of the two-phase clock signals CK1 and CK6; the second-stage circuit innovatively introduces multiple sets of RST reset signal mechanisms, and further reshapes the non-full-swing signal into an ideal full-swing signal through the precise driving of the pull-down tube and the pull-up tube. The collaborative innovation of the two-stage circuit not only breaks through the key bottleneck of ultra-high-speed data transmission, but also can flexibly adapt to different application scenarios such as 1 / 4 rate and 1 / 8 rate, and has broad application prospects in the fields of optical fiber communication, chip interconnection, etc.

[0152] Technical effect:

[0153] The data generation circuit proposed in the above embodiment adopts a two-stage structural design, which successfully solves the key problems of signal generation and shaping in ultra-high-speed scenarios. The first-stage circuit realizes the efficient generation of narrow pulse signals through the ingenious cooperation of the input tube (M1), the pre-discharge control tube (M2), the reset control tube (M3) and the pre-charge control tube (M4). In particular, within the extremely short 1-UI with a time interval of less than or equal to 10 picoseconds, the reliable generation of the signal is ensured through multiple precisely controlled stages such as pre-charge and pre-discharge. The second-stage circuit converts the non-full-swing pulse signal into a full-swing signal through the coordinated work of the pull-down tube (M5) and multiple pull-up tubes (M6, M7), significantly improving the signal quality.

[0154] In terms of timing control, the present application utilizes the delay relationship between the A-phase clock signal and the B-phase clock signal, in conjunction with the synchronous RST signal output by the reset signal generation circuit, to achieve precise timing coordination. For a 1 / 8 rate structure, the A-phase and B-phase clock signals differ by 3-UI; for a 1 / 4 rate structure, the A-phase and B-phase clock signals differ by 1-UI. Specifically, in the first-stage circuit, the pre-charge control tube and the pre-discharge control tube work alternately to complete the signal's pre-charge, pre-discharge, full discharge, and reset charge processes. This carefully designed timing arrangement ensures that all necessary signal processing steps are completed in an ultra-short time.

[0155] Those skilled in the art will appreciate that the technical solution of the present application is applicable to both 1 / 4-rate and 1 / 8-rate high-speed transmitters. For ease of description and understanding, the detailed description of the circuit structure, operating process, and timing relationship in the specification uses a 1 / 8-rate transmitter as an example. In the 1 / 8-rate structure, an 8-phase clock signal (CK1 to CK8) is used, and the A-phase and B-phase clock signals differ by 3-UI, requiring four sets of reset signal generation circuits. In the 1 / 4-rate structure, only a 4-phase clock signal is used, and the A-phase and B-phase clock signals differ by 1-UI, correspondingly requiring only two sets of reset signal generation circuits. Although the specific number of clock phases and timing relationships vary, the core circuit structure, pre-charge and discharge mechanism, and signal shaping principles remain unchanged. In other words, the two-stage circuit structure proposed in this application (including a 1-UI pulse generation circuit in the first stage and a full-swing conversion circuit in the second stage) can flexibly adapt to application requirements of different rates by adjusting the clock phase configuration and the number of reset signal groups. This design not only ensures the versatility of the technical solution but also provides sufficient flexibility for practical applications.

[0156] It is worth noting that the above embodiment demonstrates the implementation of a set of reset signal generating circuits. Taking this set as an example, through a simple combination of two AND gates and one NOR gate, a reset signal synchronized with the corresponding 1-UI pulse is generated using CK2, CK4, CK6, and CK8 in the 8-phase clock signal. Several other similar reset signal generating circuits are required in the 1 / 8 rate transmitter, using different clock phase combinations but the same circuit structure. This design not only simplifies the circuit structure but also ensures the accuracy of signal shaping. In particular, in the second-stage circuit, the RST signal cooperates with the pulse signal to control the conduction state of the pull-down and pull-up transistors, achieving a stable full-swing signal output.

[0157] Overall, the above embodiment is applicable to high-speed transmitters operating at 1 / 4 or 1 / 8 rates, achieving complex signal processing functions through a simple circuit structure. The operating processes of all MOS transistors in the circuit are closely coordinated and mutually interactive, ensuring both signal quality and reliable circuit operation. This design not only solves the signal processing challenges in ultra-high-speed scenarios but also demonstrates strong engineering practicality, providing important technical support for the development of high-speed communication systems.

[0158] In order to better understand the technical solution of the present application, a specific example is provided below for illustration. The details listed in the example are mainly for ease of understanding and are not intended to limit the scope of protection of the present application.

[0159] This example proposes a 1-UI full-swing data generation circuit with integrated pre-charge and discharge functions, which greatly improves the circuit response speed and is suitable for use in ultra-high-speed transmitters.

[0160] Specifically, this example proposes a design such as Figure 2 As shown, 4 MOS tubes are used to realize the function of generating 1-UI data ( Figure 2 As shown in (a)). If we take 1 / 8 rate as an example ( Figure 2 As shown in (b), the rising edge of clock CK6 precedes the rising edge of CK1 by 3-UI time. Since the input data is a relatively low-rate signal, it can be assumed that the input data is fully prepared, M1 is fully turned on, and the voltage at node Data_int is 0. During the pre-charge phase, CK6 is low, M3 is turned on, and node Dout_int is charged to VDD. After the falling edge of CK1, M4 turns on, and Dout_int remains at VDD. After the rising edge of CK6, M2 turns on (M3 turns off), and Dout_int begins pre-discharging. When the voltage reaches vout_precharge, the rising edge of CK1 arrives, M4 turns off, and the full discharge phase begins. After the falling edge of CK6 arrives, M2 turns off, and M3 turns on, resetting Dout_int to VDD. This process then repeats. It should be noted that the above analysis is based on the case where the input data signal is high. When the input data is low, M1 is off, and node Data_int remains at VDD. At this point, regardless of the changes in CK1 and CK6, the Dout_int node will not discharge and will remain at the VDD level. In other words, when the input data is low, the output node will not generate narrow pulses, and the circuit will be in a silent state. In this case, since there is no high current charging or discharging, the charging and discharging speed is not an issue. The circuit timing is completely determined by the high-level period of the input data.

[0161] In the above circuit, the Dout_int signal cannot reach the full swing (0→VDD); combined with Figure 3 The circuit shown in the figure can achieve full swing of the output signal Dout, where the RST signal comes from the combinational logic implementation of the previous clock signal (CK2 / CK4 / CK6 / CK8). The circuit diagram is shown in the figure. Figure 3 As shown in (b); the signal timing is as follows Figure 1 shown.

[0162] like Figure 3As shown in (c), when the Dout_int1 or Dout_int2 pulse signal has a falling edge, the RST signal is low, the M5 tube is turned off, and the M6 ​​or M7 tube charges the output node Dout to VDD; when the Dout_int1 or Dout_int2 pulse signal has a rising edge, the RST signal is high, the M6 / M7 tubes are both turned off, and the M5 tube discharges the output node Dout to zero; after this processing, the Dout_int1 or Dout_int2 pulse signal is shaped to a full-swing signal.

[0163] In summary, this application achieves ultra-high-speed, low-power, and high-precision pulse signal generation through system optimization in areas such as pre-charge and pre-discharge control, MOS tube size ratios, and second-stage shaping circuits, significantly expanding the application space for ultra-high-speed serial communications. This technical solution is simple to operate and easy to integrate, and can be widely used in high-speed fiber-optic communications, chip interconnects, radar, and other fields, with significant technical advantages and commercial value.

[0164] It should be noted that in this patent application, relational terms such as first and second, etc., are used solely to distinguish one entity or operation from another, and do not necessarily require or imply any actual relationship or order between these entities or operations. Furthermore, the terms "comprise," "include," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a list of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. Without further limitation, an element specified by the phrase "comprising a" does not preclude the presence of additional identical elements in the process, method, article, or apparatus comprising the element. In this patent application, reference to performing an action in accordance with an element means performing the action in accordance with at least that element, including two situations: performing the action in accordance with that element alone, and performing the action in accordance with that element and other elements. Expressions such as "plurality," "multiple times," and "many" include "two," "twice," "two kinds," and "more than two," "more than two times," and "more than two kinds."

[0165] All documents mentioned in this application are considered to be included in their entirety in the disclosure of this application so that they can be used as a basis for modification when necessary. In addition, it should be understood that after reading the above disclosure of this application, those skilled in the art may make various changes or modifications to this application, and these equivalent forms also fall within the scope of protection claimed in this application.

Claims

1. A data generating circuit for a high-speed transmitter, characterized in that: It includes a first-stage circuit unit and a second-stage circuit unit, wherein: The first-stage circuit unit is used to generate a narrow pulse signal, including: Input tube M1, the gate is used to receive input data signals; A pre-discharge control tube M2, whose source is connected to the drain of the input tube M1 to form a first intermediate node, and whose gate is used to receive the A-phase clock signal; A reset control tube M3, whose drain is connected to the drain of the pre-discharge control tube M2 to form an output node, and whose gate is used to receive the A-phase clock signal; a pre-charge control transistor M4 having a drain connected to the output node, a source for receiving a power supply voltage, and a gate for receiving a B-phase clock signal; wherein the B-phase clock signal has a predetermined time delay relative to the A-phase clock signal; and wherein the pre-discharge control transistor M2 and the pre-charge control transistor M4 sequentially pre-charge and pre-discharge the output node in response to the A-phase clock signal and the B-phase clock signal, thereby generating a pulse signal. The second-stage circuit unit is used to shape the pulse signal into a full-swing signal, including: The pull-down transistor M5 is connected between the final output node and the lowest potential, and its control terminal is used to receive a reset signal; Multiple pull-up tubes M6 and M7 have drains and sources connected between the final output node and the power supply voltage, respectively, and control terminals for receiving pulse signals output by the first-stage circuit unit; the pull-down tube M5 cooperates with the pull-up tubes M6 and M7 to convert the non-full-swing pulse signal into a full-swing signal for output in response to the reset signal and the pulse signal.

2. The data generating circuit according to claim 1, wherein: The time width of the narrow pulse signal is 1 unit time interval UI, where UI is a unit time interval, and the unit time interval UI is less than or equal to 10 picoseconds.

3. The data generating circuit according to claim 2, wherein: The A-phase clock signal and the B-phase clock signal are two phases in the same group of multi-phase clock signals, wherein the multi-phase clock signal includes at least 4-phase clock signals, and the time interval between the rising edges of each two adjacent phase clock signals is 1 unit time interval UI; wherein the B-phase clock signal leads the A-phase clock signal by 3 unit time intervals UI.

4. The data generating circuit according to claim 3, wherein: The gate of the input transistor M1 is connected to the input terminal to receive the input data signal, the source is grounded, and the drain is connected to the source of the pre-discharge control transistor M2 to form a first intermediate node.

5. The data generating circuit according to claim 4, wherein: The working process of the first-stage circuit unit includes: before the rising edge of the A-phase clock signal arrives, the pre-charge control tube M4 is turned on to pre-charge the output node to the power supply voltage; when the rising edge of the A-phase clock signal arrives, the pre-discharge control tube M2 is turned on to discharge the output node to a preset level; when the rising edge of the B-phase clock signal arrives, the pre-charge control tube M4 is turned off, and the output node is further discharged to the lowest potential; when the falling edge of the A-phase clock signal arrives, the reset control tube M3 is turned on and the pre-discharge control tube M2 is turned off, and the output node is reset and charged to the power supply voltage.

6. The data generating circuit according to claim 3, wherein: It also includes at least one set of reset signal generating circuits for generating a reset signal synchronized with the pulse signal based on a multi-phase clock signal, the reset signal generating circuit including: a first AND gate, whose input ends are respectively connected to the second clock signal and the fourth clock signal, for performing an AND operation on the two; a second AND gate, whose input ends are respectively connected to the sixth clock signal and the eighth clock signal, for performing an AND operation on the two; and a NOR gate, whose input ends are respectively connected to the output ends of the first AND gate and the second AND gate, for performing an NOR operation on the output signals of the two, and whose output end is used to output the reset signal.

7. The data generating circuit according to claim 6, wherein: The reset signal generating circuit receives an 8-phase clock signal as an input signal, and the time interval between rising edges of two adjacent clock signals is a unit time interval UI.

8. The data generating circuit according to claim 7, wherein: The working process of the second-stage circuit unit includes: When the reset signal is at a high level and the pulse signal output by the first-stage circuit unit is at a high level, the pull-down transistor M5 is turned on to discharge the final output node to zero potential; When the reset signal is at a low level and the pulse signal output by the first-stage circuit unit is at a low level, the plurality of pull-up transistors M6 and M7 are alternately turned on to charge the final output node to the power supply voltage.

9. The data generating circuit according to claim 8, wherein: The data generating circuit is used for a high-speed transmitter with a 1 / 4 rate or a 1 / 8 rate.

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