Analog switch circuit with overvoltage protection and chip

Abstract

The invention discloses an analog switch circuit with overvoltage protection and a chip. The analog switch circuit comprises a switch unit, a substrate selection unit and an overvoltage detection unit, wherein the output end of the substrate selection unit is connected with the switch unit and the overvoltage detection unit, and the output end of the overvoltage detection unit is connected with the control end of the switch unit. The overvoltage detection unit is used for generating and outputting a second control signal and a third control signal according to a first control signal, an input analog signal and a power supply voltage, and controlling the on-off state of the switch unit. The analog switch circuit can be kept or converted into an off state, and the problems that an analog switch cannot be turned off, devices are damaged and performance becomes poor due to input overvoltage are solved.

Description

Technical Field

[0001] The invention relates to an analog switch circuit with overvoltage protection, and also relates to an integrated circuit chip including the analog switch circuit, belonging to the technical field of analog integrated circuits. Background Art

[0002] The function of analog switches is to switch on and off the transmission paths of various analog signals or power signals to achieve transmission control of analog signals or power signals. It has the characteristics of low on-resistance and fast transmission time. In some SOC (System on Chips) chips, such as MCU (Microcontroller Unit) chips, in order to save the number of io (Input / Output) ports of the chip, internal analog switches are usually used to multiplex digital io ports into analog gpio (General Purpose Input / Output) ports as input ports of internal analog circuits such as ADC (Analog-to-Digital Converter). This multiplexed port usually needs to interface with other peripheral chips on the PCB (Printed Circuit Board) to achieve data transmission and device control.

[0003] In the prior art, Figure 1 As shown, the multiplexed port PAD_IN is connected to the input end of the internal analog circuit through an analog switch. The analog switch is composed of a PMOS tube M1 and an NMOS tube M2, assuming that the working voltage VDD of the chip is 3.3V. When the control voltage ENB of M1 is 0V and the control voltage EN of M2 is 3.3V, the analog switch is closed. At this time, if a 5V voltage is applied to the PAD_IN port by the peripheral chip, the voltage exceeds the normal working voltage 3.3V of the internal analog circuit, which will cause damage to the components in the internal analog circuit. When the control voltage ENB of M1 is 3.3V and the control voltage EN of M2 is 0V, the analog switch is turned off. At this time, if a 5V voltage is applied to the PAD_IN port, on the one hand, the gate-source voltage Vgs of the PMOS tube M1 is -1.7V, which makes M1 conductive, which will also cause damage to the components in the internal analog circuit; on the other hand, the gate-source voltage Vgs of the NMOS tube M2 is 5V, which also exceeds the normal working voltage 3.3V, so M2 will also have an overvoltage problem. In addition, when a 5V voltage is applied to the PAD_IN port, the voltage is greater than the body voltage of the PMOS tube M1 (i.e., VDD), which destroys the reverse bias voltage of the PMOS tube substrate, resulting in a body effect phenomenon, causing problems such as increased threshold voltage, leakage current, and deterioration of PMOS performance. Therefore, it is necessary to solve the technical problems such as the inability to turn off the analog switch, device damage, and performance degradation caused by the overvoltage introduced by the PAD_IN port and the mismatch with the operating voltage of the SOC chip.

[0004] In the Chinese patent application with application number 202210055351.7, an analog switch circuit with bidirectional overvoltage protection is disclosed. The analog switch circuit includes a switch control circuit, an overvoltage current limiting protection circuit and a switch circuit; the switch control circuit is connected to the switch circuit for controlling the switch circuit; the overvoltage current limiting protection circuit is connected to the switch circuit for protecting the switch circuit in the case of bidirectional overvoltage at the analog input port and the analog output port. Summary of the invention

[0005] The primary technical problem to be solved by the present invention is to provide an analog switch circuit with overvoltage protection.

[0006] Another technical problem to be solved by the present invention is to provide an integrated circuit chip including the above analog switch circuit.

[0007] In order to achieve the above object, the present invention adopts the following technical solutions:

[0008] According to a first aspect of an embodiment of the present invention, there is provided an analog switch circuit with overvoltage protection, comprising a switch unit, a substrate selection unit and an overvoltage detection unit; wherein:

[0009] The output end of the substrate selection unit is connected to the switch unit and the overvoltage detection unit, and the output end of the overvoltage detection unit is connected to the control end of the switch unit;

[0010] The substrate selection unit is used to provide a body-end bias voltage for the PMOS tube in the switch unit and the overvoltage detection unit;

[0011] The overvoltage detection unit is used to generate and output a second control signal and a third control signal according to the first control signal, the input analog signal and the power supply voltage, and provide them to the switch unit;

[0012] The switch unit switches on or off the transmission path of the input analog signal according to the first control signal, the second control signal and the third control signal;

[0013] When an overvoltage appears at the input end of the analog switch circuit in the off state, the analog switch circuit remains in the off state. When an overvoltage appears at the input end of the analog switch circuit in the on state, the analog switch circuit turns to the off state, thereby realizing overvoltage protection for the analog switch circuit and subsequent analog circuits.

[0014] Preferably, the switch unit includes a fifth PMOS tube, a sixth PMOS tube, a sixth NMOS tube and a seventh NMOS tube; wherein,

[0015] The drain end of the fifth PMOS tube is connected in series with the source end of the sixth PMOS tube, and the drain end of the sixth NMOS tube is connected in series with the source end of the seventh NMOS tube;

[0016] The source end of the fifth PMOS tube and the source end of the sixth NMOS tube are connected in parallel to serve as the input end of the switch unit;

[0017] The drain end of the sixth PMOS tube and the drain end of the seventh NMOS tube are connected in parallel to serve as the output end of the switch unit;

[0018] The gate end of the fifth PMOS tube is connected to the second output end of the overvoltage detection unit, and the gate end of the sixth PMOS tube is connected to the first output end of the overvoltage detection unit;

[0019] The gate terminal of the sixth NMOS tube is connected to the power supply voltage terminal, and the gate terminal of the seventh NMOS tube is connected to the first control signal terminal.

[0020] Preferably, the overvoltage detection unit includes a second control signal subunit and a third control signal subunit, wherein:

[0021] The output end of the second control signal subunit is connected to the input end of the third control signal subunit;

[0022] The second control signal subunit is used to generate and output the second control signal according to the first control signal, the input analog signal and the power supply voltage;

[0023] The third control signal subunit is used to generate and output the third control signal according to the first control signal, the input analog signal, the power supply voltage and the second control signal.

[0024] Preferably, the two control signal sub-units include a third PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a first inverter and a first OR gate; wherein,

[0025] The third PMOS tube, the first NMOS tube, the second NMOS tube and the third NMOS tube are sequentially connected in series to form a series branch to provide an input signal for the first input end of the first OR gate; the first NMOS tube is a native NMOS tube.

[0026] Preferably, the source terminal of the third PMOS tube is connected to the input terminal of the input analog signal, the gate terminal is connected to the power supply voltage terminal, and the drain terminal is connected to the drain terminal of the first NMOS tube;

[0027] The gate terminal of the first NMOS tube is connected to the power supply voltage terminal, and the source terminal is connected to the drain terminal of the second NMOS tube and the first input terminal of the first OR gate;

[0028] The gate terminal of the second NMOS tube is connected to the bias voltage terminal, and the source terminal is connected to the drain terminal of the third NMOS tube;

[0029] The gate terminal of the third NMOS tube is connected to the first control signal terminal, and the source terminal is connected to the ground potential terminal;

[0030] The input terminal of the first inverter is connected to the first control signal terminal, and the output terminal is connected to the second input terminal of the first OR gate;

[0031] The output end of the first OR gate is connected to the switch unit as the first output end of the overvoltage detection unit on the one hand, and is connected to the third control signal subunit on the other hand.

[0032] Preferably, the third control signal subunit includes a fourth PMOS transistor, a fourth NMOS transistor and a fifth NMOS transistor; wherein,

[0033] The source end of the fourth NMOS tube is connected to the output end of the second control signal sub-unit, the gate end of the fourth NMOS tube is connected to the first control signal end, and the drain end is connected to the source end of the fifth NMOS tube;

[0034] The gate terminal of the fifth NMOS tube is connected to the power supply voltage terminal, and the drain terminal is connected to the switch unit as the second output terminal of the overvoltage detection unit on the one hand, and is connected to the drain terminal of the fourth PMOS tube on the other hand;

[0035] The gate terminal of the fourth PMOS tube is connected to the power supply voltage terminal, and the source terminal is connected to the input terminal of the input analog signal.

[0036] Preferably, when an overvoltage appears at the input end when the analog switch circuit is in the disconnected state, the second control signal output by the overvoltage detection unit is in a high level state; the third control signal is in a high level state, and the voltage of the third control signal is equal to the voltage of the input analog signal.

[0037] Preferably, when an overvoltage appears at the input end when the analog switch circuit is in the on state, the second control signal output by the overvoltage detection unit is in a high level state; the third control signal is in a high level state, and the voltage of the third control signal is equal to the voltage of the input analog signal.

[0038] Preferably, the substrate selection unit includes a first PMOS tube and a second PMOS tube; wherein,

[0039] The body terminal and the drain terminal of the first PMOS tube are short-circuited, the gate terminal is connected to the power supply voltage terminal, and the source terminal is connected to the input terminal of the input analog signal;

[0040] The body terminal and the drain terminal of the second PMOS tube are short-circuited, the gate terminal is connected to the input terminal of the input analog signal, and the source terminal is connected to the power supply voltage terminal;

[0041] The drain ends of the first PMOS tube and the second PMOS tube are connected to each other and serve as the output end of the substrate selection unit.

[0042] According to a second aspect of an embodiment of the present invention, an integrated circuit chip is provided, comprising the above-mentioned analog switch circuit with overvoltage protection.

[0043] Compared with the prior art, the analog switch circuit with overvoltage protection provided by the present invention adopts a substrate selection unit to provide a bias voltage for the PMOS tube body end, and an overvoltage detection unit generates a second control signal and a third control signal to provide to the switch unit. When an overvoltage appears at the input end of the analog switch circuit in the disconnected or connected state, the analog switch circuit can maintain or turn to the disconnected state, thereby avoiding the problems of the analog switch being unable to turn off, device damage, and performance degradation caused by the input overvoltage, and realizing overvoltage protection for the analog switch circuit and subsequent analog circuits. Therefore, the analog switch circuit with overvoltage protection provided by the present invention has the beneficial effects of ingenious and reasonable structural design, low design cost, high reliability, and excellent circuit performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 A schematic diagram of a typical analog switch circuit in the prior art;

[0045] Figure 2 A structural block diagram of an analog switch circuit with overvoltage protection provided by the present invention;

[0046] Figure 3 is a circuit schematic diagram of a substrate selection unit in an embodiment of the present invention;

[0047] Figure 4 is a circuit schematic diagram of an overvoltage detection unit in an embodiment of the present invention;

[0048] Figure 5 FIG. 4 is a circuit schematic diagram of a switch unit in an embodiment of the present invention. DETAILED DESCRIPTION

[0049] The technical content of the present invention is described in detail below with reference to the accompanying drawings and specific embodiments.

[0050] like Figure 2As shown, an analog switch circuit with overvoltage protection provided by an embodiment of the present invention includes a switch unit, a substrate selection unit and an overvoltage detection unit; wherein the output end of the substrate selection unit is connected to the switch unit and the overvoltage detection unit, and the output end of the overvoltage detection unit is connected to the control end of the switch unit; the input end of the switch unit is connected to the PAD_IN port, and the output end OUT of the switch unit is connected to the input end of the application circuit. The PAD_IN port is the input port of the external analog signal VIN. In the application scenario where the digital io port is multiplexed as an analog gpio port, the PAD_IN port is the multiplexed io port.

[0051] The switch unit turns on or off the transmission path of the input analog signal VIN according to the first control signal SWC, the second control signal SWCX_OR and the third control signal SWCX_H. The first control signal SWC is a switch on / off control signal provided by the application system, and usually, its voltage in the high level state is the same as the power supply voltage VDD. The power supply voltage VDD is the working power supply voltage of the analog switch circuit and the application circuit connected to its output terminal.

[0052] The substrate selection unit is used to provide a body-end bias voltage for the PMOS tube in the switch unit and the overvoltage detection unit; when the input analog signal voltage VIN is less than or equal to the difference between the power supply voltage VDD and the threshold voltage Vth (i.e., VIN≤VDD-Vth), and when the input analog signal voltage VIN is greater than or equal to the sum of the power supply voltage VDD and the threshold voltage Vth (i.e., VIN≥VDD+Vth), the substrate selection unit selects the larger voltage value between the input analog signal and the power supply voltage and outputs it to the switch unit and the overvoltage detection unit as the body-end bias voltage of the PMOS tube.

[0053] The overvoltage detection unit is used to generate and output a second control signal SWCX_OR and a third control signal SWCX_H according to the first control signal SWC, the input analog signal VIN and the power supply voltage VDD, and provide them to the switch unit.

[0054] When an overvoltage appears at the input end of the analog switch circuit in the off state, the analog switch circuit remains in the off state. When an overvoltage appears at the input end of the analog switch circuit in the on state, the analog switch circuit turns to the off state, thereby realizing overvoltage protection for the analog switch circuit and subsequent analog circuits.

[0055] In one embodiment of the present invention, Figure 3As shown, the substrate selection unit includes a first PMOS tube P0 and a second PMOS tube P1. The body terminal and the drain terminal of the first PMOS tube P0 are short-circuited, the gate terminal is connected to the power supply voltage VDD terminal, and the source terminal is connected to the PAD_IN port; the body terminal and the drain terminal of the second PMOS tube P1 are short-circuited, the gate terminal is connected to the PAD_IN port, and the source terminal is connected to the power supply voltage VDD terminal; the drain terminals of the first PMOS tube P0 and the second PMOS tube P1 are connected to each other as the output terminal of the substrate selection unit.

[0056] When the input analog signal voltage VIN at the PAD_IN port is less than or equal to the difference between the power supply voltage VDD and the threshold voltage Vth (ie, VIN≤VDD-Vth), the first PMOS tube P0 is turned off and the second PMOS tube P1 is turned on, so the output voltage BULK_HV is equal to the power supply voltage VDD. When the input analog signal voltage VIN is greater than or equal to the sum of the power supply voltage VDD and the threshold voltage Vth (ie, VIN≥VDD+Vth), the first PMOS tube P0 is turned on and the second PMOS tube P1 is turned off, so the output voltage BULK_HV is equal to the input analog signal voltage VIN. In addition, when the input analog signal voltage VIN is near the power supply voltage VDD, that is, VDD+Vth>VIN>VDD-Vth, the first PMOS tube P0 and / or the second PMOS tube P1 is in a weak conduction state (that is, a subthreshold state), and the output voltage BULK_HV is between the power supply voltage VDD and the input analog signal voltage VIN. At this time, since the input analog signal voltage VIN is very close to the power supply voltage VDD, the analog switch circuit operates in a normal working state.

[0057] Through the above analysis, it can be seen that when the magnitude of the input analog signal voltage VIN deviates greatly from the power supply voltage VDD, the substrate selection unit uses the larger voltage value of the input analog signal voltage VIN and the power supply voltage VDD as the output voltage BULK_HV, and provides it to the switch unit and the overvoltage detection unit as the body-end bias voltage of the PMOS tube in the unit, ensuring that the body end of the PMOS tube is always at the highest potential, so that the parasitic diode inside the PMOS tube is in a reverse bias state, so as to avoid leakage current and performance degradation caused by overvoltage of the input analog signal VIN.

[0058] In one embodiment of the present invention, Figure 4As shown, the overvoltage detection unit includes a second control signal subunit and a third control signal subunit, wherein the output end of the second control signal subunit is connected to the input end of the third control signal subunit. The second control signal subunit is used to generate and output a second control signal SWCX_OR according to the first control signal SWC, the input analog signal VIN and the power supply voltage VDD; the third control signal subunit is used to generate and output a third control signal SWCX_H according to the first control signal SWC, the input analog signal VIN, the power supply voltage VDD and the second control signal SWCX_OR.

[0059] The second control signal subunit includes a third PMOS tube P2, a first NMOS tube N0, a second NMOS tube N1, a third NMOS tube N2, a first inverter INV1 and a first OR gate OR1. Among them, the first NMOS tube N0 adopts a native NMOS tube, which has a characteristic of close to zero threshold voltage. The third PMOS tube P2, the first NMOS tube N0, the second NMOS tube N1 and the third NMOS tube N2 are connected in series in sequence to form a series branch, which acts as a source input comparator, which compares the source terminal voltage and the gate terminal voltage, and the output signal PAD_DET is provided to the first input terminal of the first OR gate OR1.

[0060] In the second control signal sub-unit, the source end of the third PMOS transistor P2 is connected to the PAD_IN port, the gate end is connected to the power supply voltage VDD end, and the drain end is connected to the drain end of the first NMOS transistor N0; the gate end of the first NMOS transistor N0 is connected to the power supply voltage VDD end, the source end is connected to the drain end of the second NMOS transistor N1 and the first input end of the first OR gate OR1; the gate end of the second NMOS transistor N1 is connected to the bias voltage VBIAS end, and the source end is connected to the drain end of the third NMOS transistor N2; the gate end of the third NMOS transistor N2 is connected to the first control signal SWC end, and the source end is connected to the ground potential end. The input end of the first inverter INV1 is connected to the first control signal SWC end, and the output end is connected to the second input end of the first OR gate OR1; the output end of the first OR gate OR1 is connected to the switch unit as the first output end of the overvoltage detection unit (i.e., the second control signal SWCX_OR output end), and is connected to the third control signal sub-unit on the other hand.

[0061] The third control signal subunit includes a fourth PMOS transistor P3, a fourth NMOS transistor N3 and a fifth NMOS transistor N4. Among them, the source end of the fourth NMOS transistor N3 is connected to the output end of the first OR gate OR1 in the second control signal subunit; the gate end of the fourth NMOS transistor N3 is connected to the first control signal SWC end, and the drain end is connected to the source end of the fifth NMOS transistor N4; the gate end of the fifth NMOS transistor N4 is connected to the power supply voltage VDD end, and the drain end is connected to the switch unit as the second output end of the overvoltage detection unit (i.e., the third control signal SWCX_H output end), and is connected to the drain end of the fourth PMOS transistor P3 on the other hand; the gate end of the fourth PMOS transistor P3 is connected to the power supply voltage VDD end, and the source end is connected to the PAD_IN port.

[0062] The body terminals of all PMOS tubes in the overvoltage detection unit are connected to the output terminal of the substrate selection unit; usually, the body terminals of NMOS tubes are connected to the ground potential terminal.

[0063] The following describes the working principle of the overvoltage detection unit and the state changes of the second control signal SWCX_OR and the third control signal SWCX_H output by the overvoltage detection unit through working scenarios of the first control signal SWC and the input analog signal VIN in different states.

[0064] In the first working scenario, when the first control signal SWC is in a low level state, and the input analog signal voltage VIN is less than or equal to the difference between the power supply voltage VDD and the threshold voltage Vth (i.e., VIN≤VDD-Vth), the third PMOS tube P2 and the third NMOS tube N2 in the series branch are both in the off state, and the second NMOS tube N1 is also in the off state, so there is no signal input to the first input end of the first OR gate OR1. At the same time, since the first control signal SWC is in a low level state, after passing through the first inverter INV1, the input signal SWCX at the second input end of the first OR gate OR1 is in a high level state, so the second control signal SWCX_OR output by the first OR gate OR1 is in a high level state. At this time, the fourth NMOS tube N3 is in the off state, and the fifth NMOS tube N4 and the fourth PMOS tube P3 are also in the off state, so there is no signal output from the second output end of the overvoltage detection unit.

[0065] In the second working scenario, when the first control signal SWC is in a low level state, and the input analog signal voltage VIN is greater than or equal to the sum of the power supply voltage VDD and the threshold voltage Vth (i.e., VIN ≥ VDD + Vth), the third NMOS tube N2 in the series branch is in a cut-off state, the second NMOS tube N1 is also in a cut-off state, and the third PMOS tube P2 is in a conducting state. Since the first NMOS tube N0 is a native NMOS tube, its threshold voltage Vth is close to 0, therefore, the first NMOS tube N0 is turned on, so that the input signal PAD_DET at the first input end of the first OR gate OR1 is in a high level state. At the same time, since the first control signal SWC is in a low level state, after passing through the first inverter INV1, the input signal SWCX at the second input end of the first OR gate OR1 is in a high level state, therefore, the second control signal SWCX_OR output by the first OR gate OR1 is in a high level state. At this time, the fourth NMOS tube N3 and the fifth NMOS tube N4 are in the cut-off state, and the fourth PMOS tube P3 is in the on state. Therefore, the third control signal SWCX_H outputted from the second output end of the overvoltage detection unit is in a high level state, and the voltage of the third control signal SWCX_H is equal to the input analog signal voltage VIN.

[0066] In the third working scenario, when the first control signal SWC is in a high level state, and the input analog signal voltage VIN is less than or equal to the difference between the power supply voltage VDD and the threshold voltage Vth (i.e., VIN≤VDD-Vth), the third PMOS tube P2 is in a cut-off state, the first NMOS tube N0 is turned on, and the third NMOS tube N2 is in a turned-on state. After the second NMOS tube N1 (equivalent to the power source) is turned on under the action of the bias voltage VBIAS, the input signal PAD_DET at the first input end of the first OR gate OR1 is in a low level state. At the same time, since the first control signal SWC is in a high level state, after passing through the first inverter INV1, the input signal SWCX at the second input end of the first OR gate OR1 is in a low level state, so the second control signal SWCX_OR output by the first OR gate OR1 is in a low level state. At this time, the fourth NMOS tube N3 and the fifth NMOS tube N4 are in a turned-on state, and the fourth PMOS tube P3 is in a cut-off state, so the third control signal SWCX_H output by the second output end of the overvoltage detection unit is also in a low level state.

[0067] In the fourth working scenario, when the first control signal SWC is in a high level state, and the input analog signal voltage VIN is greater than or equal to the sum of the power supply voltage VDD and the threshold voltage Vth (i.e., VIN≥VDD+Vth), the third PMOS tube P2 and the first NMOS tube N0 are in a conducting state, and the third NMOS tube N2 and the second NMOS tube N1 are also in a conducting state. At this time, the pull-up capability of the third PMOS tube P2 and the first NMOS tube N0 is greater than the pull-down capability of the third NMOS tube N2 and the second NMOS tube N1. The first NMOS tube N0 is a native NMOS tube, and its source terminal voltage is close to the gate terminal voltage VDD, so that the input signal PAD_DET at the first input terminal of the first OR gate OR1 is in a high level state. At the same time, since the first control signal SWC is in a high level state, after passing through the first inverter INV1, the input signal SWCX at the second input terminal of the first OR gate OR1 is in a low level state, so the second control signal SWCX_OR output by the first OR gate OR1 is in a high level state. At this time, the fourth NMOS tube N3 and the fifth NMOS tube N4 are in the cut-off state, and the fourth PMOS tube P3 is in the on state. Therefore, the third control signal SWCX_H outputted by the second output terminal of the overvoltage detection unit is also in a high level state, and the voltage of the third control signal SWCX_H is equal to the input analog signal voltage VIN.

[0068] In one embodiment of the present invention, Figure 5 As shown, the switch unit includes a fifth PMOS transistor P4, a sixth PMOS transistor P5, a sixth NMOS transistor N5 and a seventh NMOS transistor N6. Among them, the drain end of the fifth PMOS transistor P4 is connected in series with the source end of the sixth PMOS transistor P5, and the drain end of the sixth NMOS transistor N5 is connected in series with the source end of the seventh NMOS transistor N6; the source end of the fifth PMOS transistor P4 and the source end of the sixth NMOS transistor N5 are connected in parallel to each other and then used as the input end of the switch unit and connected to the PAD_IN port; the drain end of the sixth PMOS transistor P5 and the drain end of the seventh NMOS transistor N6 are connected in parallel to each other and then used as the output end OUT of the switch unit; the gate end of the fifth PMOS transistor P4 is connected to the second output end of the overvoltage detection unit, the gate end of the sixth PMOS transistor P5 is connected to the first output end of the overvoltage detection unit, the gate end of the sixth NMOS transistor N5 is connected to the power supply voltage VDD end, and the gate end of the seventh NMOS transistor N6 is connected to the first control signal SWC end.

[0069] The body terminals of all PMOS tubes in the switch unit are connected to the output terminal of the substrate selection unit; usually, the body terminals of NMOS tubes are connected to the ground potential terminal.

[0070] In the first working scenario, the analog switch circuit is in a normal disconnected state, that is, the first control signal SWC is in a low level state, and the input analog signal voltage VIN is less than or equal to the difference between the power supply voltage VDD and the threshold voltage Vth (that is, VIN≤VDD-Vth). At this time, in the switch unit, the second control signal SWCX_OR is in a high level state, and there is no signal output at the second output end of the overvoltage detection unit, that is, the third control signal SWCX_H is not output, so the fifth PMOS tube P4 and the sixth PMOS tube P5 are both in a cut-off state; because the first control signal SWC is in a low level state, the seventh NMOS tube N6 is in a cut-off state; whether the sixth NMOS tube N5 is turned on depends on whether the difference between VDD and VIN reaches the threshold voltage. Therefore, the switch unit is in a cut-off state as a whole.

[0071] In the second working scenario, the analog switch circuit is in the disconnected state of input overvoltage, that is, the first control signal SWC is in the low level state, and the input analog signal voltage VIN is greater than or equal to the sum of the power supply voltage VDD and the threshold voltage Vth (that is, VIN≥VDD+Vth). At this time, in the switch unit, the second control signal SWCX_OR is in the high level state; the third control signal SWCX_H is in the high level state, and the third control signal SWCX_H voltage is equal to the input analog signal voltage VIN; therefore, the gate terminal voltage and the source terminal voltage of the fifth PMOS tube P4 are equal to VIN, and are still in the cut-off state; the sixth PMOS tube P5 is also in the cut-off state; because the first control signal SWC is in the low level state, the seventh NMOS tube N6 is in the cut-off state; the gate terminal voltage VDD of the sixth NMOS tube N5 is less than the source terminal voltage VIN, and is also in the cut-off state, and its gate-source voltage Vgs is the difference between VIN and VDD, and no overvoltage phenomenon occurs. Therefore, the switch unit as a whole is still in the off state, which solves the problem that the analog switch cannot be turned off and the device is damaged by overvoltage when overvoltage is introduced into the PAD_IN port.

[0072] In the third working scenario, the analog switch circuit is in a normal on state, that is, the first control signal SWC is in a high level state, and the input analog signal voltage VIN is less than or equal to the difference between the power supply voltage VDD and the threshold voltage Vth (that is, VIN≤VDD-Vth). At this time, in the switch unit, the second control signal SWCX_OR is in a low level state, the third control signal SWCX_H is also in a low level state, the fifth PMOS tube P4 and the sixth PMOS tube P5 are both in a conducting state, and at the same time, the sixth NMOS tube N5 and the seventh NMOS tube N6 are also in a conducting state, so the switch unit as a whole is in a closed state.

[0073] In the fourth working scenario, the analog switch circuit is in the "on state" of input overvoltage, that is, the analog switch circuit is in the normal on state, and the input analog signal voltage VIN suddenly increases and exceeds the power supply voltage VDD. At this time, the first control signal SWC is in a high level state, and the input analog signal voltage VIN is greater than or equal to the sum of the power supply voltage VDD and the threshold voltage Vth (ie, VIN ≥ VDD + Vth). In the switch unit, the second control signal SWCX_OR is in a high level state, the third control signal SWCX_H is also in a high level state, and the third control signal SWCX_H voltage is equal to the input analog signal voltage VIN. The sixth PMOS tube P5 is in the off state, and the gate terminal voltage and source terminal voltage of the fifth PMOS tube P4 are equal to VIN, and are also in the off state; because the input analog signal voltage VIN is greater than the power supply voltage VDD, the sixth NMOS tube N5 and the seventh NMOS tube N6 are both in the off state, and the gate-source voltage Vgs of the sixth NMOS tube N5 is the difference between VIN and VDD, and no overvoltage phenomenon occurs. Therefore, the switch unit changes from a closed state to an off state, which solves the problem that the analog switch cannot be turned off and the device is damaged by overvoltage when overvoltage is introduced into the PAD_IN port.

[0074] In addition, it should be noted that, when the analog switch circuit is in normal working state, the input analog signal voltage VIN is less than or equal to the power supply voltage DVV. The overvoltage state of the analog switch circuit in this embodiment refers to the input analog signal voltage VIN being greater than or equal to the sum of the power supply voltage VDD and the threshold voltage Vth (i.e., VIN≥VDD+Vth). Therefore, when the input analog signal voltage VIN is near the power supply voltage VDD, i.e., VDD+Vth>VIN>VDD-Vth, even if the third PMOS transistor P2 and / or the fourth PMOS transistor P3 in the overvoltage detection unit are in a weak conduction state, so that the third control signal SWCX_H is erroneous, resulting in a change in the state of the fifth PMOS transistor P4 in the switch unit, the maximum output voltage of the analog switch circuit will not exceed VDD+Vth, and it does not belong to the overvoltage working condition, and will not cause harm to the analog switch circuit and subsequent analog circuits.

[0075] Through the detailed analysis of the above working states, it can be seen that the analog switch circuit with overvoltage protection provided by the present invention, in addition to being able to work normally in normal disconnection and normal connection states, can also keep or turn the switch unit as a whole to the off state when an overvoltage appears at the input end in the disconnection or connection state, thereby avoiding technical problems such as the inability to shut down the analog switch, device damage, and performance degradation caused by input overvoltage.

[0076] It should be noted that the analog switch circuit provided by the present invention does not limit the circuit structure of the above-mentioned functional units. In other embodiments of the present invention, each functional unit can adopt other different circuit structures to complete the same function of the unit and ultimately achieve the same analog switch overvoltage protection function.

[0077] Based on the above analog switch circuit with overvoltage protection, an embodiment of the present invention further provides an integrated circuit chip, which includes the above analog switch circuit with overvoltage protection, and the analog switch circuit is used to provide on-off control of analog signals for the chip system, or, when the digital io port of the SOC chip is multiplexed as an analog gpio port, the analog switch circuit is used to control the on-off of the external analog signal, and can turn off the analog switch in time when the input analog signal is overvoltage, so as to realize overvoltage protection for the analog switch and subsequent analog circuits. The specific structure of the analog switch circuit with overvoltage protection in the integrated circuit chip will not be described in detail here.

[0078] In summary, compared with the prior art, the analog switch circuit with overvoltage protection provided by the present invention adopts a substrate selection unit to provide a bias voltage for the PMOS tube body end, and an overvoltage detection unit generates a second control signal and a third control signal to provide to the switch unit. When an overvoltage appears at the input end of the analog switch circuit in the disconnected or connected state, the analog switch circuit can maintain or turn to the disconnected state, thereby avoiding the problems of the analog switch being unable to turn off, device damage, and performance degradation caused by the input overvoltage, and realizing overvoltage protection for the analog switch circuit and subsequent analog circuits. Therefore, the analog switch circuit with overvoltage protection provided by the present invention has the beneficial effects of ingenious and reasonable structural design, low design cost, high reliability, and excellent circuit performance.

[0079] It should be noted that, in addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0080] The above is a detailed description of the analog switch circuit and chip with overvoltage protection provided by the present invention. For those skilled in the art, any obvious changes made to it without departing from the essence of the present invention will constitute an infringement of the patent right of the present invention and will bear corresponding legal responsibilities.

Claims

1. An analog switch circuit with overvoltage protection, characterized in that It includes a switch unit, a substrate selection unit and an overvoltage detection unit; wherein, The output end of the substrate selection unit is connected to the switch unit and the overvoltage detection unit, and the output end of the overvoltage detection unit is connected to the control end of the switch unit; The substrate selection unit is used to provide a body-end bias voltage for the PMOS tube in the switch unit and the overvoltage detection unit; The overvoltage detection unit is used to generate and output a second control signal and a third control signal according to the first control signal, the input analog signal and the power supply voltage, and provide them to the switch unit; The switch unit switches on or off the transmission path of the input analog signal according to the first control signal, the second control signal and the third control signal; When an overvoltage appears at the input end of the analog switch circuit in the off state, the analog switch circuit remains in the off state. When an overvoltage appears at the input end of the analog switch circuit in the on state, the analog switch circuit turns to the off state, thereby realizing overvoltage protection for the analog switch circuit and subsequent analog circuits.

2. The analog switch circuit with overvoltage protection according to claim 1, characterized in that: The switch unit includes a fifth PMOS tube, a sixth PMOS tube, a sixth NMOS tube and a seventh NMOS tube; wherein, The drain end of the fifth PMOS tube is connected in series with the source end of the sixth PMOS tube, and the drain end of the sixth NMOS tube is connected in series with the source end of the seventh NMOS tube; The source end of the fifth PMOS tube and the source end of the sixth NMOS tube are connected in parallel to serve as the input end of the switch unit; The drain end of the sixth PMOS tube and the drain end of the seventh NMOS tube are connected in parallel to serve as the output end of the switch unit; The gate end of the fifth PMOS tube is connected to the second output end of the overvoltage detection unit, and the gate end of the sixth PMOS tube is connected to the first output end of the overvoltage detection unit; The gate terminal of the sixth NMOS tube is connected to the power supply voltage terminal, and the gate terminal of the seventh NMOS tube is connected to the first control signal terminal.

3. The analog switch circuit with overvoltage protection according to claim 1, characterized in that: The overvoltage detection unit includes a second control signal subunit and a third control signal subunit, wherein: The output end of the second control signal subunit is connected to the input end of the third control signal subunit; The second control signal subunit is used to generate and output the second control signal according to the first control signal, the input analog signal and the power supply voltage; The third control signal subunit is used to generate and output the third control signal according to the first control signal, the input analog signal, the power supply voltage and the second control signal.

4. The analog switch circuit with overvoltage protection as claimed in claim 3, characterized in that: The second control signal subunit includes a third PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a first inverter and a first OR gate; wherein, The third PMOS tube, the first NMOS tube, the second NMOS tube and the third NMOS tube are sequentially connected in series to form a series branch to provide an input signal for the first input end of the first OR gate; the first NMOS tube is a native NMOS tube.

5. The analog switch circuit with overvoltage protection as claimed in claim 4, characterized in that: The source terminal of the third PMOS tube is connected to the input terminal of the input analog signal, the gate terminal is connected to the power supply voltage terminal, and the drain terminal is connected to the drain terminal of the first NMOS tube; The gate terminal of the first NMOS tube is connected to the power supply voltage terminal, and the source terminal is connected to the drain terminal of the second NMOS tube and the first input terminal of the first OR gate; The gate terminal of the second NMOS tube is connected to the bias voltage terminal, and the source terminal is connected to the drain terminal of the third NMOS tube; The gate terminal of the third NMOS tube is connected to the first control signal terminal, and the source terminal is connected to the ground potential terminal; The input terminal of the first inverter is connected to the first control signal terminal, and the output terminal is connected to the second input terminal of the first OR gate; The output end of the first OR gate is connected to the switch unit as the first output end of the overvoltage detection unit on the one hand, and is connected to the third control signal subunit on the other hand.

6. The analog switch circuit with overvoltage protection as claimed in claim 3, characterized in that: The third control signal subunit includes a fourth PMOS transistor, a fourth NMOS transistor and a fifth NMOS transistor; wherein, The source end of the fourth NMOS tube is connected to the output end of the second control signal sub-unit, the gate end of the fourth NMOS tube is connected to the first control signal end, and the drain end is connected to the source end of the fifth NMOS tube; The gate terminal of the fifth NMOS tube is connected to the power supply voltage terminal, and the drain terminal is connected to the switch unit as the second output terminal of the overvoltage detection unit on the one hand, and is connected to the drain terminal of the fourth PMOS tube on the other hand; The gate terminal of the fourth PMOS tube is connected to the power supply voltage terminal, and the source terminal is connected to the input terminal of the input analog signal.

7. The analog switch circuit with overvoltage protection as claimed in claim 3, characterized in that: When overvoltage appears at the input end when the analog switch circuit is in the disconnected state, the second control signal output by the overvoltage detection unit is in a high level state; the third control signal is in a high level state, and the voltage of the third control signal is equal to the voltage of the input analog signal.

8. The analog switch circuit with overvoltage protection as claimed in claim 3, characterized in that: When an overvoltage appears at the input end when the analog switch circuit is in the on state, the second control signal output by the overvoltage detection unit is in a high level state; the third control signal is in a high level state, and the voltage of the third control signal is equal to the voltage of the input analog signal.

9. The analog switch circuit with overvoltage protection as claimed in claim 1, characterized in that: The substrate selection unit includes a first PMOS tube and a second PMOS tube; wherein, The body terminal and the drain terminal of the first PMOS tube are short-circuited, the gate terminal is connected to the power supply voltage terminal, and the source terminal is connected to the input terminal of the input analog signal; The body terminal and the drain terminal of the second PMOS tube are short-circuited, the gate terminal is connected to the input terminal of the input analog signal, and the source terminal is connected to the power supply voltage terminal; The drain ends of the first PMOS tube and the second PMOS tube are connected to each other and serve as the output end of the substrate selection unit.

10. An integrated circuit chip, characterized in that An analog switch circuit with overvoltage protection comprising any one of claims 1 to 9.

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