Heterogeneous Implementation Method, System, Device and Storage Medium of LDPC Encoder

Abstract

The present invention relates to the field of communication coding technologies, and particularly to a heterogeneous implementation method, system, device, and storage medium for an LDPC encoder. In the heterogeneous implementation method of the LDPC encoder, a central processing unit (CPU) receives and stores information bits, code length, code rate, and a base matrix selection index table and a bit list, obtains a parity-check matrix and parameters, and stores them in the global memory of a parallel computing chip; after being converted into a parallel form, it is stored in the shared memory of the parallel computing chip, and parallel encoding calculations are performed to obtain parity-bit information; the parity-bit information is sent back to the central processing unit (CPU), and together with the information bits, it forms the final encoded information. The heterogeneous implementation method, system, device, and storage medium for the LDPC encoder utilize the flexible development feature of the CPU and the parallel computing ability of the parallel computing chip to parallelize the parity-bit calculation process, further accelerating the encoding process and greatly improving the throughput rate of the encoder.

Description

Technical Field

[0001] The present invention relates to the field of communication coding technologies, and particularly to a heterogeneous implementation method, system, device, and storage medium for an LDPC encoder. Background Art

[0002] In the process of the continuous evolution of modern communication systems, 5G communication has become a key force driving the digital development of society with its characteristics of high speed, low latency, and large connection. In the 5G communication system, in order to ensure the accurate transmission of data in a complex wireless environment, the 5G low-density parity-check code LDPC (Low-Density Parity-Check Code) coding protocol is adopted. As an excellent linear block code, the low-density parity-check code LDPC has excellent error correction ability approaching the Shannon limit, which makes it play a core role in the physical layer data transmission of 5G communication.

[0003] There are many limitations in the traditional implementation methods of low-density parity-check code LDPC encoders. Although the software implementation approach has a certain degree of flexibility, its coding speed far fails to meet the real-time requirements, resulting in data processing delays and affecting communication quality. The implementation scheme based on a specific hardware circuit, such as an application-specific integrated circuit ASIC (Application Specific Integrated Circuit), can provide a relatively high coding rate, but it faces the problem of a long design cycle, and the application-specific integrated circuit ASIC has extremely poor flexibility. Once the 5G communication standard adjusts or upgrades the low-density parity-check code LDPC coding algorithm in subsequent development, the application-specific integrated circuit ASIC almost needs to be redesigned and manufactured; the field-programmable gate array FPGA (Field Programmable Gate Array) is also used in the implementation of the low-density parity-check code LDPC encoder. However, the field-programmable gate array FPGA needs to face problems such as insufficient logic resources, high development difficulty, and high cost.

[0004] Based on the above problems, the present invention proposes a heterogeneous implementation method, system, device, and storage medium for an LDPC encoder. Summary of the Invention

[0005] In order to make up for the defects of the prior art, the present invention provides a simple and efficient heterogeneous implementation method, system, device, and storage medium for an LDPC encoder.

[0006] The present invention is implemented by the following technical solutions:

[0007] A heterogeneous implementation method for an LDPC encoder, characterized in that:

[0008] Step S1: The central processing unit (CPU) receives and stores information bits, code length k, code rate R, and the base matrix selection index table and bit list specified by the 5G low-density parity-check (LDPC) code standard.

[0009] Step S2: In the central processing unit (CPU), obtain the parity-check matrix and the required parameter data by using the information received in Step S1.

[0010] In Step S2, perform parity-check matrix calculation in the central processing unit (CPU), and adjust the obtained parity-check matrix and corresponding parameters in real time according to the transformation of the code length k and the code rate R. The implementation process is as follows:

[0011] Step S2.1: Determine the base matrix and the number of columns of its information bits.

[0012] Based on the input code length k, code rate R, and the base matrix selection index table and bit list specified by the 5G low-density parity-check (LDPC) code standard, determine the corresponding base matrix, and at the same time, clarify the number of columns L of the information bits in this matrix.

[0013] Step S2.2: Calculate the expansion factor Z.

[0014] Calculate the expansion factor Z of the low-density parity-check (LDPC) code. The calculation formula is as follows:

[0015] ;

[0016] Combined with the calculation result, custom-select the value of the expansion factor Z from the input expansion factor index list specified by the 5G low-density parity-check (LDPC) code standard.

[0017] Step S2.3: Determine the number of rows m and the number of columns n of the base matrix.

[0018] The calculation formula for the number of columns n of the base matrix is as follows:

[0019] ;

[0020] Among them, represents the ceiling of the quotient of the number of columns L of the information bits in the base matrix divided by the code rate R;

[0021] The calculation formula for the number of rows m of the base matrix is as follows:

[0022] ;

[0023] Step S2.4: Obtain the cyclic shift matrix A.

[0024] According to the value of the expansion factor Z, and combined with the cyclic shift matrix list specified by the 5G low-density parity-check (LDPC) code standard, obtain a cyclic shift matrix A with m rows and L columns.

[0025] Step S2.5: Obtain the parity-check matrix H;

[0026] According to the expansion factor Z, determine the cyclic shift matrix list of the base matrix B region specified by the 5G low-density parity-check code LDPC standard to obtain the cyclic shift matrix B, and then horizontally splice the cyclic shift matrix A and the cyclic shift matrix B to obtain the parity-check matrix H in the form of [A B].

[0027] Step S3: The central processing unit CPU transfers the parity-check matrix, information bits, and required parameter data to the global memory of the parallel computing chip;

[0028] Step S4: Read the corresponding serial information bit data from the global memory of the parallel computing chip, convert it into parallel form according to relevant parameters, and store it in the shared memory;

[0029] By using the shared memory, reduce the number of accesses to the global memory, thereby improving the data access efficiency;

[0030] In the said Step S4, the process of storing and segmenting the information bits in the parallel computing chip is as follows:

[0031] Step S4.1: Under the provisions of the 5G standard, divide the input information bits with a length of k into L segments according to the scale parameter in the base matrix, and the size of each segment of information bits is fixed at Z bits;

[0032] Step S4.2: The information bits divided into L segments form L-way parallel information bits, and the L-way parallel information bits carry their respective segment information bits and are stored in the shared memory in parallel.

[0033] Step S5: Perform parallel encoding calculation in the parallel computing chip to obtain parity-check bit information; through the parallel computing ability of the parallel computing chip, parallelize the parity-check bit calculation process to improve the throughput rate of the encoder;

[0034] In the said Step S5, the process of calculating the parity-check matrix in the parallel computing chip is as follows:

[0035] Step S5.1: In the parallel computing chip, the parity-check matrix H is pre-stored in the global memory of the parallel computing chip. Each thread is responsible for processing a part of the operations related to the calculation of a parity-check bit, and obtains the corresponding operation vector coefficient from the parity-check matrix H according to the thread index;

[0036] Step S5.2: The L-way parallel information bits are stored in the shared memory of the parallel computing chip. After obtaining the operation vector coefficient, the thread performs matrix multiplication and addition operations on the L-way parallel information bits according to the obtained operation vector coefficient;

[0037] Step S5.3: Obtain the values of the parity check bits [X1, X2, ……, Xm-1, Xm] through exclusive-or operation.

[0038] Step S6: Send the parity check bit information back to the central processing unit (CPU), and form the final encoded information with the information bits.

[0039] In the said Step S6, the process of generating the final encoded information in the central processing unit (CPU) is as follows:

[0040] Step S6.1: The central processing unit (CPU) receives the parity check bits [X1, X2, ……, Xm-1, Xm] calculated in the parallel computing chip.

[0041] Step S6.2: Adopt a serial splicing method for the received parity check bits and the information bits [Data1, Data2, …, DataL - 1, DataL] pre-stored in the memory space of the central processing unit (CPU), and connect the information bits and the parity check bits in sequence to generate the final encoded information [Data1, Data2, …, DataL - 1, DataL, X1, X2,……, Xm-1, Xm].

[0042] A heterogeneous implementation system of an LDPC encoder for implementing the above method, including a central processing unit (CPU) and a parallel computing chip;

[0043] The central processing unit (CPU) is responsible for receiving and storing information bits, code length k, code rate R, and the base matrix selection index table and bit list specified by the 5G low-density parity-check (LDPC) code standard, obtaining the parity check matrix and the required parameter data by using the received information, and transmitting the parity check matrix, information bits, and the required parameter data to the parallel computing chip; in addition, the central processing unit (CPU) is also responsible for forming the final encoded information with the information bits and the parity check bits;

[0044] The memory of the parallel computing chip is divided into global memory and shared memory, which is responsible for implementing the storage and segmented processing of information bits, obtaining the segmented information bits and their segment information bits, and performing parallel encoding calculations to obtain the parity check bit information, and sending the parity check bit information back to the central processing unit (CPU);

[0045] Among them, the global memory is responsible for storing the received parity check matrix, information bits, and the required parameter data;

[0046] The shared memory is responsible for storing the segmented information bits and their segment information bits in parallel.

[0047] A heterogeneous implementation device of an LDPC encoder, characterized by including:

[0048] One or more processors, one or more memories, and one or more programs, wherein the one or more programs are stored in the one or more memories and configured to be executed by the one or more processors, and the one or more programs include instructions for performing any of the above methods.

[0049] A readable storage medium, characterized in that: a computer program is stored on the readable storage medium, and when the computer program is executed by a processor, the above-mentioned method is implemented.

[0050] The beneficial effect of the present invention is that: the heterogeneous implementation method, system, device and storage medium of the LDPC encoder not only have the characteristic of development flexibility, but also can parallelize the parity bit calculation process by utilizing the parallel computing power of the parallel computing chip, further accelerating the encoding process and greatly improving the throughput rate of the encoder. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0052] FIG Figure 1 It is a schematic diagram of the heterogeneous implementation method of the LDPC encoder of the present invention.

[0053] FIG Figure 2 It is a schematic diagram of the parity check matrix calculation method in the CPU of the present invention.

[0054] FIG Figure 3 It is a schematic diagram of the storage and segmented processing method of information bits in the GPGPU of the present invention.

[0055] FIG Figure 4 It is a schematic diagram of the implementation method of parity bit calculation in the GPGPU of the present invention.

[0056] FIG Figure 5 It is a schematic diagram of the combination of information bits and encoded bits in the CPU of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0057] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in combination with the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0058] With the rapid development of parallel computing chip technology, its application in the field of general computing shows great potential. Parallel computing chips have numerous computing cores, can simultaneously process a large number of data threads in parallel, and can achieve a relatively high coding rate. The central processing unit (CPU) has the characteristics of flexible development, and the CPU is good at processing complex logical control and serial tasks. This heterogeneous mode can give full play to the respective advantages of the CPU and parallel computing chips, realize the optimal allocation of resources, and avoid the performance bottleneck caused by the functional limitations of a single processor. At the same time, the heterogeneous system also has advantages in terms of flexibility. When the 5G communication standard or coding algorithm changes, tasks can be flexibly redistributed between the CPU and parallel computing chips through software adjustment to meet new requirements. Therefore, an implementation method of a 5G low-density parity-check (LDPC) encoder can be developed based on parallel computing chips and the CPU.

[0059] As shown in the appendix Figure 1 The heterogeneous implementation method of this LDPC encoder includes the following steps:

[0060] Step S1: The CPU receives and stores information bits, code length k, code rate R, and the base matrix selection index table and bit list specified by the 5G LDPC standard.

[0061] Step S2: Obtain the parity-check matrix and the required parameter data in the CPU by using the information received in step S1.

[0062] As shown in the appendix Figure 2 In step S2 as shown, the parity-check matrix calculation is performed in the CPU, and the obtained parity-check matrix and corresponding parameters are adjusted in real time according to the transformation of the code length k and code rate R. The implementation process is as follows:

[0063] Step S2.1: Determine the base matrix and the number of columns of its information bits.

[0064] According to the input code length k, code rate R, and the base matrix selection index table and bit list specified by the 5G LDPC standard, determine the corresponding base matrix, and at the same time determine the number of columns L of information bits in this matrix.

[0065] Step S2.2: Calculate the expansion factor Z.

[0066] Calculate the expansion factor Z of the LDPC, and the calculation formula is as follows:

[0067] ;

[0068] Customize and select the value of the expansion factor Z from the list of expansion factor indices specified in the input 5G low-density parity-check code LDPC standard in combination with the calculation results;

[0069] Step S2.3: Determine the number of rows m and the number of columns n of the base matrix;

[0070] The calculation formula for the number of columns n of the base matrix is as follows:

[0071] ;

[0072] Among them, represents the ceiling value of the quotient of the number of columns L of the information bits in the base matrix divided by the code rate R;

[0073] The calculation formula for the number of rows m of the base matrix is as follows:

[0074] ;

[0075] Step S2.4: Obtain the cyclic shift matrix A;

[0076] According to the value of the expansion factor Z and in combination with the list of cyclic shift matrices specified in the 5G low-density parity-check code LDPC standard, obtain a cyclic shift matrix A with m rows and L columns;

[0077] Step S2.5: Calculate the parity-check matrix H;

[0078] According to the expansion factor Z, determine the cyclic shift matrix B according to the list of cyclic shift matrices in the B area of the base matrix specified by the 5G low-density parity-check code LDPC standard, and then horizontally splice the cyclic shift matrix A and the cyclic shift matrix B to obtain the parity-check matrix H in the form of [A B].

[0079] Step S3: The central processing unit CPU transfers the parity-check matrix, information bits, and required parameter data to the global memory of the parallel computing chip;

[0080] Step S4: Read the corresponding serial information bit data from the global memory of the parallel computing chip, convert it into a parallel form according to relevant parameters, and store it in the shared memory;

[0081] By using the shared memory, reduce the number of accesses to the global memory, thereby improving the data access efficiency;

[0082] As shown in the appendix Figure 3 In the step S4, the process of storing and segmenting the information bits in the parallel computing chip is as follows:

[0083] Step S4.1: Under the provisions of the 5G standard, divide the input information bits with a length of k into L segments according to the scale parameter in the base matrix, and the size of each segment of information bits is fixed at Z bits;

[0084] Step S4.2: The information bits divided into L segments form L-way parallel information bits, and the L-way parallel information bits carry their respective segment information bits and are stored in the shared memory in parallel.

[0085] Because the information bits need to be repeatedly called when calculating the parity bits, storing them in the shared memory can reduce the number of accesses to the global memory and improve the data access efficiency.

[0086] Step S5: Perform parallel encoding calculation in the parallel computing chip to obtain the parity bit information; through the parallel computing ability of the parallel computing chip, parallelize the parity bit calculation process to improve the throughput rate of the encoder;

[0087] As shown in the appendix Figure 4 In step S5, the process of calculating the parity matrix in the parallel computing chip is as follows:

[0088] Step S5.1: In the parallel computing chip, the parity matrix H is pre-stored in the global memory of the parallel computing chip. Each thread is responsible for processing a part of the operation related to the calculation of a parity bit, and obtains the corresponding operation vector coefficient from the parity matrix H according to the thread index;

[0089] The Thread class is the basic class for implementing multithreaded programming. Each thread is described by an instance of the Thread class. For example, Thread 1 obtains the operation vector coefficient related to the calculation of parity bit 1 from the first row of matrix H, and Thread 2 obtains the coefficient related to the calculation of parity bit 2 from the first row of matrix A, and so on.

[0090] Step S5.2: The L-way parallel information bits are stored in the shared memory of the parallel computing chip. After obtaining the operation vector coefficient, the thread performs matrix multiplication and addition operation on the L-way parallel information bits according to the obtained operation vector coefficient;

[0091] Step S5.3: Obtain the value of the parity bits [X1, X2, ……, Xm-1, Xm] through exclusive OR operation.

[0092] Step S6: Send the parity bit information back to the central processing unit CPU, and form the final encoded information with the information bits.

[0093] As shown in the appendix Figure 5 In step S6, the process of generating the final encoded information in the central processing unit CPU is as follows:

[0094] Step S6.1: The central processing unit (CPU) receives the parity bits [X1, X2, ……, Xm-1, Xm] calculated in the parallel computing chip.

[0095] Step S6.2: The received parity bits and the information bits [Data1, Data2, …, DataL - 1, DataL] pre-stored in the memory space of the central processing unit (CPU) are serially concatenated, and the information bits and the parity bits are connected in sequence to generate the final encoded information [Data1, Data2, …, DataL - 1, DataL,X1, X2,……, Xm-1, Xm].

[0096] The heterogeneous implementation system of this LDPC encoder is used to implement the above method, including a central processing unit (CPU) and a parallel computing chip;

[0097] The central processing unit (CPU) is responsible for receiving and storing information bits, code length k, code rate R, and the basic matrix selection index table and bit list specified by the 5G low-density parity-check (LDPC) standard, obtaining the parity-check matrix and the required parameter data using the received information, and transmitting the parity-check matrix, information bits, and the required parameter data to the parallel computing chip; in addition, the central processing unit (CPU) is also responsible for forming the final encoded information using the information bits and the parity bits;

[0098] The memory of the parallel computing chip is divided into global memory and shared memory, which is responsible for implementing the storage and segmented processing of information bits, obtaining the segmented information bits and their segment information bits, and performing parallel encoding calculations to obtain parity bit information, and sending the parity bit information back to the central processing unit (CPU);

[0099] Among them, the global memory is responsible for storing the received parity-check matrix, information bits, and the required parameter data;

[0100] The shared memory is responsible for parallelly storing the segmented information bits and their segment information bits.

[0101] The heterogeneous implementation device of this LDPC encoder includes:

[0102] One or more processors, one or more memories, and one or more programs, where one or more programs are stored in the one or more memories and are configured to be executed by the one or more processors, and the one or more programs include instructions for executing any of the above methods.

[0103] This readable storage medium stores a computer program, and when the computer program is executed by a processor, it implements the method as described above.

[0104] In summary, for the heterogeneous implementation method, system, device and storage medium of the LDPC encoder, the central processing unit (CPU) can efficiently complete data preprocessing, obtain the required parameters, and complete the splicing of the final serial encoded information data. The parallel computing chip uses its fast parallel computing ability to parallelize the calculation process of the parity bits, greatly shortening the encoding time and further improving the throughput rate of the encoder.

[0105] The above-described embodiments are only one of the specific implementation manners of the present invention. Those skilled in the art should include the usual changes and substitutions within the scope of the technical solution of the present invention in the protection scope of the present invention.

Claims

1. A heterogeneous implementation method of an LDPC encoder, characterized in that: It includes the following steps: Step S1: The central processing unit (CPU) receives and stores information bits, code length k, code rate R, and the base matrix selection index table and bit list specified by the 5G low-density parity-check (LDPC) code standard. Step S2: In the central processing unit (CPU), the parity-check matrix and the required parameter data are obtained by using the information received in Step S1. In the central processing unit (CPU), parity-check matrix calculation is performed, and the obtained parity-check matrix and corresponding parameters are adjusted in real time according to the transformation of the code length k and the code rate R. The implementation process is as follows: Step S2.1: Determine the base matrix and the number of columns of its information bits. Based on the input code length k, code rate R, and the base matrix selection index table and bit list specified by the 5G low-density parity-check (LDPC) code standard, the corresponding base matrix is determined, and at the same time, the number of columns L of the information bits in this matrix is clarified. Step S2.2: Calculate the expansion factor Z. Calculate the expansion factor Z of the low-density parity-check (LDPC) code. The calculation formula is as follows: Combined with the calculation result, the value of the expansion factor Z is customarily selected from the expansion factor index list specified by the 5G low-density parity-check (LDPC) code standard input. Step S2.3: Determine the number of rows m and the number of columns n of the base matrix. The calculation formula for the number of columns n of the base matrix is as follows: Among them, represents the ceiling of the quotient of the number of columns L of the information bits in the base matrix divided by the code rate R; The calculation formula for the number of rows m of the base matrix is as follows: m = n - L Step S2.4: Obtain the cyclic shift matrix A. According to the value of the expansion factor Z and combined with the cyclic shift matrix list specified by the 5G low-density parity-check (LDPC) code standard, a cyclic shift matrix A with m rows and L columns is obtained. Step S2.5: Obtain the parity-check matrix H. According to the expansion factor Z, the cyclic shift matrix list in the B area of the base matrix specified by the 5G low-density parity-check (LDPC) code standard is determined to obtain the cyclic shift matrix B, and then the cyclic shift matrix A and the cyclic shift matrix B are horizontally concatenated to obtain the parity-check matrix H in the form of [AB]. Step S3: The central processing unit (CPU) transfers the parity-check matrix, information bits, and the required parameter data to the global memory of the parallel computing chip. Step S4: Read the corresponding serial information bit data from the global memory of the parallel computing chip, convert it into a parallel form according to the relevant parameters, and store it in the shared memory. By using the shared memory, the number of accesses to the global memory is reduced, thereby improving the data access efficiency. Step S5: Perform parallel encoding calculation in the parallel computing chip to obtain parity-check bit information; through the parallel computing ability of the parallel computing chip, the parity-check bit calculation process is parallelized to improve the throughput rate of the encoder. The process of calculating the parity-check matrix in the parallel computing chip is as follows: Step S5.1: In the parallel computing chip, the parity-check matrix H is pre-stored in the global memory of the parallel computing chip. Each thread is responsible for processing a part of the operations related to the parity-check bit calculation, and obtains the corresponding operation vector coefficient from the parity-check matrix H according to the thread index. Step S5.2: The L-way parallel information bits are stored in the shared memory of the parallel computing chip. After obtaining the operation vector coefficient, the thread performs matrix multiplication and addition operation on the L-way parallel information bits according to the obtained operation vector coefficient. Step S5.3: Obtain the values of the parity check bits [X1, X2, ……, Xm-1, Xm] through exclusive-or operation; Step S6: Send the parity check bit information back to the central processing unit (CPU), and combine it with the information bits to form the final encoded information; The process of generating the final encoded information in the central processing unit (CPU) is as follows: Step S6.1: The central processing unit (CPU) receives the parity check bits [X1, X2, ……, Xm-1, Xm] calculated in the parallel computing chip; Step S6.2: Use the serial splicing method to combine the received parity check bits with the information bits [Data1, Data2, …, DataL-1, DataL] pre-stored in the memory space of the central processing unit (CPU), and connect the information bits and parity check bits in sequence to generate the final encoded information [Data1, Data2, …, DataL-1, DataL, X1, X2, ……, Xm-1, Xm].

2. The heterogeneous implementation method of the LDPC encoder according to claim 1, wherein: In the said Step S4, the process of storing and segmenting the information bits in the parallel computing chip is as follows: Step S4.1: Under the provisions of the 5G standard, divide the input information bits with a length of k into L segments according to the scale parameter in the base matrix, and the size of each segment of information bits is fixed at Z bits; Step S4.2: The L segments of information bits form L paths of parallel information bits, and the L paths of parallel information bits carry their respective segment information bits and are stored in the shared memory in parallel.

3. A heterogeneous implementation system of an LDPC encoder, characterized in that: For the method described in claim 1 or 2, It includes a central processing unit (CPU) and a parallel computing chip; The central processing unit (CPU) is responsible for receiving and storing the information bits, code length k, code rate R, and the base matrix selection index table and bit list specified by the 5G low-density parity-check (LDPC) code standard, obtaining the parity check matrix and the required parameter data using the received information, and transmitting the parity check matrix, information bits, and the required parameter data to the parallel computing chip; in addition, the central processing unit (CPU) is also responsible for forming the final encoded information using the information bits and parity check bits; The memory of the parallel computing chip is divided into global memory and shared memory, which is responsible for implementing the storage and segmentation processing of the information bits, obtaining the segmented information bits and their segment information bits, and performing parallel encoding calculations to obtain the parity check bit information, and sending the parity check bit information back to the central processing unit (CPU); Among them, the global memory is responsible for storing the received parity check matrix, information bits, and the required parameter data; The shared memory is responsible for storing the segmented information bits and their segment information bits in parallel.

4. A heterogeneous implementation device of an LDPC encoder, characterized in that: It includes: One or more processors, one or more memories, and one or more programs, where one or more programs are stored in the one or more memories and are configured to be executed by the one or more processors, and the one or more programs include instructions for executing the method described in claim 1 or 2.

5. A readable storage medium, characterized in that: A computer program is stored on the readable storage medium, and when the computer program is executed by a processor, it implements the method described in claim 1 or 2.

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