A wide-area super-multistable memristive chaotic circuit system

Abstract

The present invention discloses a wide-area super-multistable memristor chaotic circuit system, belonging to the field of circuit design technology. The chaotic circuit system is composed of a memristor, a capacitor, and an inductor. The equivalent circuit of the chaotic circuit system includes a memristor circuit, a resistor network, a voltage conveyor, an inverting proportional device, an inverting proportional adder, an inverting integrator, a multiplier, an external inductor, and a capacitor. The voltage conveyor is used to convey voltage values ​​and isolate current transmission; the inverting proportional device is used to perform a proportional operation between the output voltage and the input voltage and to make the polarity of the two opposite; the inverting proportional adder is used to perform an addition operation on multiple input voltages, so that the sum is used as the output voltage and is in antiphase; the inverting integrator is used to perform an integration operation on the input voltage signal; and the multiplier is used to perform a product operation on two input signals.

Description

Technical Field

[0001] The present invention belongs to the technical field of circuit design, and in particular relates to a wide-area super-multistable memristor chaotic circuit system. Background Art

[0002] Because memristors are nonlinear devices, they facilitate the construction of chaotic circuit systems. In recent years, the design of hyper-multistable chaotic systems based on memristors has become a hot topic in memristor research. As one of the most representative chaotic circuits, the Chua circuit, with its typical circuit structure, has become a paradigm for theoretical and experimental studies of chaos. Building on this foundation, memristors have been used to construct modified Chua circuits and multi-scroll Chua circuits, discovering numerous novel dynamical behaviors. In recent years, multistability and hyper-multistability have become hot topics in chaos-related research. Multistability refers to the phenomenon in which, when system parameters remain unchanged but initial conditions are changed, a system exhibits different stable states, such as point attractors, periodicity, quasi-periodicity, chaos, and hyperchaos. In particular, a system with an infinite number of coexisting attractors is said to exhibit hyper-multistability. If a system exhibits multistability or hyper-multistability, its dynamical behavior, within a specific parameter set, undergoes frequent state switching with changes in initial values, resulting in extremely rich and complex dynamical behavior. However, the systems constructed in existing research all exhibit super-multistability under a specific set of parameters, and there is a lack of research on super-multistability over a wide range of parameters. To this end, the present invention constructs a memristive chaotic system that exhibits super-multistability over a wide range of multiple parameters.

[0003] The present invention proposes a wide-area super-multistable memristor chaotic circuit system, which has unique characteristics not possessed by general super-multistable systems. It has rich dynamic behaviors and a certain cutting-edge nature, and is worthy of in-depth study. This research will lay the necessary foundation for further exploring the super-multistable operating mechanism of the memristor chaotic circuit system, promoting the commercial production of memristor devices, and its application in brain-like intelligence. At the same time, when each parameter in the designed memristor chaotic circuit system parameter set takes a value within a large range, the system exhibits super-multistable states as the initial value changes, that is, the system has wide-area super-multistability. The system's extremely rich dynamic behavior will provide basic support for the engineering application and development of chaotic circuits and memristors. Therefore, the wide-area super-multistable memristor chaotic circuit system proposed in the present invention and its circuit implementation is a very valuable and meaningful work. Summary of the Invention

[0004] In response to the above technical problems existing in the prior art, the present invention proposes a wide-area super-multistable memristor chaotic circuit system, which has a reasonable design, solves the shortcomings of the prior art, and has good effects.

[0005] In order to achieve the above object, the present invention adopts the following technical solutions:

[0006] A wide-area super-multistable memristor chaotic circuit system, the chaotic circuit system consisting of a memristor, a capacitor, and an inductor, wherein the equivalent circuit of the chaotic circuit system comprises a memristor circuit, a resistor network, a voltage conveyor, an inverting proportional device, an inverting proportional adder, an inverting integrator, a multiplier, an external inductor, and a capacitor;

[0007] The voltage transmitter is used to transmit voltage values ​​and isolate current transmission, which is achieved through the operational amplifier U1;

[0008] The inverting proportional device is used to realize the proportional operation of the output voltage and the input voltage and make the polarities of the two opposite, including a first inverting proportional device U2 and a second inverting proportional device U5;

[0009] The inverting proportional adder is used to implement the addition operation of multiple input voltages so that their sum is used as the output voltage and is in antiphase, including an inverting proportional adder U4;

[0010] The inverting integrator is used to implement the integration operation of the input voltage signal, including an inverting integrator U3;

[0011] The multiplier is used to implement the product operation of two input signals, including a first multiplier M1, a second multiplier M2 and a third multiplier M3;

[0012] The external inductors and capacitors include capacitors C1, C2 and an inductor L.

[0013] Furthermore, the chaotic circuit system expression is:

[0014]

[0015] Where x and y are state variables converted from the voltages of capacitors C1 and C2, z and w are state variables converted from the current of inductor L and the conductance of the memristor, respectively. α, β, and γ are system parameters related to the capacitance and inductance values. K, D, E, and F are parameters of the memristor. τ represents time.

[0016] Furthermore, the first multiplier M1, the second multiplier M2 and the third multiplier M3 all use AD633JN chips;

[0017] The X pin and Y pin of the first multiplier M1 are commonly connected to the first end of the capacitor C0, the output end of the inverting integrator U3, and the Y pin of the third multiplier M3. The output end of the first multiplier M1 is connected to the first end of the resistor R1. The X pin of the third multiplier M3 is connected to the first end of the resistor R8, the X pin and Y pin of the second multiplier M2, and the negative input and output ends of the operational amplifier U1. The output end of the third multiplier M3 is connected to the first end of the resistor R4. The output end of the second multiplier M2 is connected to the first end of the resistor R3.

[0018] Furthermore, the operational amplifier U1 adopts an AD633JN chip, the positive input end of the operational amplifier U1 is connected to the first end of the resistor R13, the first end of the capacitor C1 and the first end of the inductor L, the second end of the inductor L is connected to the first end of the capacitor C2, and the second end of the capacitor C2 and the second end of the capacitor C1 are grounded together.

[0019] Furthermore, the first inverting proportional circuit U2 and the second inverting proportional circuit U5 both use OP07CP chips;

[0020] The positive input terminal of the first inverting proportional device U2 is grounded, the negative input terminal is connected to the second end of the resistor R1 and the first end of the resistor R2, and the output terminal of U2 is connected to the second end of the resistor R2 and the first end of the resistor R7; the positive input terminal of the second inverting proportional device U5 is grounded, the negative input terminal is connected to the first end of the resistor R9 and the first end of the resistor R10, and the output terminal of U5 is connected to the second end of the resistor R10 and the second end of the resistor R13.

[0021] Furthermore, the inverting proportional adder U4 adopts an OP07CP chip; the positive input end of the inverting proportional adder U4 is grounded, the negative input end is connected to the second end of the resistor R4, the second end of the resistor R8, and the first end of the resistor R5, and the output end of U4 is connected to the second end of the resistor R5 and the second end of the resistor R9.

[0022] Furthermore, the inverting integrator U3 adopts an OP07CP chip; the positive input end of the inverting integrator U3 is grounded, and the negative input end is connected to the second end of the capacitor C0, the second end of the resistor R7, the second end of the resistor R3, and the first end of the resistor R6; the second end of the resistor R6 is connected to the positive electrode of the power supply V1, and the negative electrode of V1 is grounded.

[0023] The beneficial technical effects brought about by the present invention are:

[0024] The present invention designs a wide-area super-multistable memristive chaotic circuit system and implements a physical circuit implementation. This circuit exhibits super-multistability within a specific parameter set as initial conditions change. When a parameter within the parameter set changes, the system maintains super-multistability when that parameter takes any specific value within a wide range. Simultaneously, when multiple parameters take specific values ​​within a wide range, the system maintains super-multistability. This provides flexible parameter selection for engineering applications, allowing for the selection of appropriate initial conditions and control operations using desired dynamic characteristics to achieve engineering objectives. Furthermore, the present invention provides a research approach for determining the distinct behavior of a system. Through analysis and research of this system, it will provide essential research tools for understanding the complex behavior of neural network systems and provide core support for uncovering the internal mechanisms that determine the complex dynamics of the system. Compared to methods for implementing super-multistable chaotic circuits, the method used in the present invention utilizes fewer multipliers and operational amplifiers, resulting in lower costs. The clear demarcation between the memristor and external components makes it easier to add or remove external components to reconstruct the memristive super-multistable chaotic circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The present invention will be further described below with reference to the accompanying drawings:

[0026] Figure 1 This is a structural diagram of the wide-area ultra-multi-stable-state memristor chaotic circuit system of the present invention;

[0027] Figure 2 This is a simulation circuit diagram of the memristor in the present invention;

[0028] Figure 3 This is a volt-ampere hysteresis curve diagram of the memristor simulation circuit in the present invention;

[0029] Figure 4 The volt-ampere hysteresis curves of the memristor simulation circuit in the present invention are shown when the AC power frequency is 200 Hz and the amplitudes are 4 V, 5 V, and 6 V respectively;

[0030] Figure 5 : is the equivalent circuit diagram of the wide-area super-multistable memristor chaotic circuit system in the present invention;

[0031] Figure 6 Phase trajectory diagram of the system in the xy plane as the initial component x(0) changes when the parameters α = 7, β = 6, γ = 1, D = 1.4, E = 0.6, F = -0.2, K = -2;

[0032] Among them, (a) is the arc attractor under eight initial values; (b) is the 7-shaped attractor under eight initial values; (c) is the s-shaped attractor under four initial values ​​and the trapezoidal attractor under eight initial values; (d) is the linear attractor under four initial values;

[0033] Figure 7 The circuit simulation results are shown when the parameters are α=7, β=6, γ=1, D=1.4, E=0.6, F=-0.2, and K=-2;

[0034] Among them, (a) is the circuit simulation result corresponding to the initial component x(0) of 10; (b) is the circuit simulation result corresponding to the initial component x(0) of -5; (c) is the circuit simulation result corresponding to the initial component x(0) of -2.7; (d) is the circuit simulation result corresponding to the initial component x(0) of 5.85;

[0035] Figure 8 Phase trajectory diagram of the system in the xy plane obtained with the change of initial component x(0) when parameters α = 500, β = 5, γ = 0.5, D = 1.4, E = 0.6, F = -0.2, K = -0.02;

[0036] Figure 9 The circuit simulation results are as follows: α = 500, β = 5, γ = 0.5, D = 1.4, E = 0.6, F = -0.2, K = -0.02;

[0037] Among them, (a) is the circuit simulation result corresponding to the initial component x(0) of 0.03; (b) is the circuit simulation result corresponding to the initial component x(0) of 0.17;

[0038] Figure 10 The circuit simulation results corresponding to the parameters α = 500, β = 5, γ = 0.5, D = 1.4, E = 0.6, F = -0.2, K = -0.02, and the initial component x(0) is 0.05, 0.08, and 0.68 respectively; DETAILED DESCRIPTION

[0039] The present invention proposes a wide-area super-multistable memristive chaotic circuit system. In order to make the advantages and technical solutions of the present invention clearer and more specific, the present invention is described in detail below with reference to specific embodiments.

[0040] A wide-area super-multistable memristor chaotic circuit system, such as Figure 1 As shown in Figure 1, the memristor chaotic circuit system consists of a memristor, two capacitors, and an inductor. The expression of the memristor is:

[0041]

[0042] in, is the conductance of the memristor, v is the voltage of the memristor, D, E, F, K are constant coefficients, and I is the current of the memristor.

[0043] The expression of memristor chaotic circuit system is:

[0044]

[0045] Among them, v1 is the voltage of the memristor, which is also the voltage of capacitor C1, v2 is the voltage of capacitor C2, i L is the current of the inductor L, and is also the current of the capacitor C2, is the conductance of the memristor, D, E, F, and K are constant coefficients, and C1, C2, and L are the values ​​of the capacitors C1, C2, and the inductor L, respectively.

[0046] Furthermore, the system expression can be transformed into:

[0047]

[0048] Where x and y are state variables converted from the voltages of capacitors C1 and C2, z and w are state variables converted from the current of inductor L and the conductance of the memristor, respectively. α, β, and γ are system parameters related to the capacitance and inductance values. K, D, E, and F are parameters of the memristor. τ represents time.

[0049] To speed up circuit simulation, a time transformation is introduced, i.e., τ = ηt, where η is the time scale transformation factor. Generally speaking, the larger the η value, the faster the system's time domain evolution and the denser the chaotic motion trajectory, making it easier to quickly obtain circuit simulation results. Properly adjusting the η value can reduce the resistance value of the integrated circuit, facilitating circuit debugging. Let η = 1000 and substitute τ = 1000t into Equation (3) to obtain:

[0050]

[0051] According to Equation 4, the equivalent circuit of the system is designed as follows: Figure 5 As shown, the equivalent circuit of the chaotic circuit system includes a resistor network, a voltage conveyor, an inverting proportional device, an inverting proportional adder, an inverting integrator, a multiplier, and external inductors and capacitors.

[0052] The voltage transmitter is used to transmit voltage values ​​and isolate current transmission, which is achieved through the operational amplifier U1;

[0053] The inverting proportional device is used to realize the proportional operation of the output voltage and the input voltage and make the polarities of the two opposite, including a first inverting proportional device U2 and a second inverting proportional device U5;

[0054] An inverting proportional adder, used to implement the addition operation of multiple input voltages so that their sum is used as the output voltage and is in antiphase, including an inverting proportional adder U4;

[0055] An inverting integrator, used to implement integration operation on the input voltage signal, including an inverting integrator U3;

[0056] A multiplier, used to implement a product operation of two input signals, including a first multiplier M1, a second multiplier M2 and a third multiplier M3;

[0057] The external capacitor and inductor are used to connect with the memristor circuit to form a chaotic circuit system, including capacitors C1 and C2 and inductor L.

[0058] The first multiplier M1, the second multiplier M2 and the third multiplier M3 all use AD633JN chips;

[0059] The X pin and Y pin of the first multiplier M1 are commonly connected to the first end of the capacitor C0, the output end of the inverting integrator U3, and the Y pin of the third multiplier M3. The output end of the first multiplier M1 is connected to the first end of the resistor R1. The X pin of the third multiplier M3 is connected to the first end of the resistor R8, the X pin and Y pin of the second multiplier M2, and the negative input and output ends of the operational amplifier U1. The output end of the third multiplier M3 is connected to the first end of the resistor R4. The output end of the second multiplier M2 is connected to the first end of the resistor R3.

[0060] The operational amplifier U1 uses an AD633JN chip. The positive input terminal of the operational amplifier U1 is connected to the first end of the resistor R13, the first end of the capacitor C1 and the first end of the inductor L. The second end of the inductor L is connected to the first end of the capacitor C2. The second end of the capacitor C2 and the second end of the capacitor C1 are grounded together.

[0061] The positive input terminal of the first inverting proportional device U2 is grounded, the negative input terminal is connected to the second end of the resistor R1 and the first end of the resistor R2, and the output terminal of U2 is connected to the second end of the resistor R2 and the first end of the resistor R7; the positive input terminal of the second inverting proportional device U5 is grounded, the negative input terminal is connected to the first end of the resistor R9 and the first end of the resistor R10, and the output terminal of U5 is connected to the second end of the resistor R10 and the second end of the resistor R13.

[0062] The inverting proportional adder U4 uses an OP07CP chip; the positive input terminal of the inverting proportional adder U4 is grounded, the negative input terminal is connected to the second end of the resistor R4, the second end of the resistor R8, and the first end of the resistor R5, and the output terminal of U4 is connected to the second end of the resistor R5 and the second end of the resistor R9.

[0063] The inverting integrator U3 uses an OP07CP chip; the positive input terminal of the inverting integrator U3 is grounded, and the negative input terminal is connected to the second end of the capacitor C0, the second end of the resistor R7, the second end of the resistor R3, and the first end of the resistor R6. The second end of the resistor R6 is connected to the positive electrode of the power supply V1, and the negative electrode of V1 is grounded.

[0064] The inverting proportional adder U4 is used to implement the addition operation of multiple input voltages, so that their sum is used as the output voltage and is inverted. The negative input terminal is connected to the output terminal of the third multiplier M3 through the resistor R4. The negative input terminal is also connected to the output terminal of the operational amplifier U1 through R8. The output voltage of the output terminal of the third multiplier M3 is defined as wx, and the output voltage of the output terminal of the operational amplifier U1 is defined as x. Then the output voltage of the output terminal of the inverting proportional adder U4 is:

[0065]

[0066] Operational amplifier U1 is used to transmit voltage values ​​while isolating current transmission. Its positive input terminal is connected to the output terminal of the second inverting proportional device U5 through resistor R13, and is also connected to the first terminal of capacitor C1 and the first terminal of inductor L. The voltage at the junction between the input terminal of operational amplifier U1 and resistor R13 is defined as x. The output voltage of the output terminal of operational amplifier U1 is:

[0067] v o1 =x; (6)

[0068] The first inverting proportional device U2 is used to realize that the output voltage is proportional to the input voltage and is in antiphase. The positive input terminal of the first inverting proportional device U2 is grounded, the negative input terminal is connected to the output terminal of the first multiplier M1 through the resistor R1 and is connected to its own output terminal through the resistor R2, and the output terminal is connected to the negative input terminal of the inverting integrator U3 through the resistor R7. The output voltage of the output terminal of the first inverting proportional device U2 is:

[0069] v o2 =-w 2 ; (7)

[0070] The second inverting proportional device U5 is configured to achieve a proportional operation relationship between the output voltage and the input voltage and in an inverted phase. The positive input terminal is grounded, the negative input terminal is connected to the output terminal of the inverting proportional adder U4 through the resistor R9 and is connected to the output terminal of the second inverting proportional device U5 through the resistor R10, and the output terminal is connected to the positive input terminal of the operational amplifier U1 through the resistor R13 and is connected to the first terminal of the capacitor C1 and the first terminal of the inductor L through the resistor R13. The output voltage of the output terminal of the first inverting proportional device U9 is:

[0071]

[0072] The X and Y pins of the first multiplier M1 are both connected to the output of the inverting integrator U3. The output of the first multiplier M1 is connected to the negative input of the first inverting proportional device U2 via a resistor R1. The output voltage of the inverting integrator is defined as w. The voltage of the output pin of the first multiplier M1 is:

[0073] v M1 =w2 ; (9)

[0074] The X pin and Y pin of the second multiplier M2 are both connected to the output of the operational amplifier U1. The output of the second multiplier M2 is connected to the negative input of the inverting integrator U3 through the resistor R3. The voltage of the output pin of the second multiplier M2 is:

[0075] v M2 =x 2 ; (10)

[0076] The X pin of the third multiplier M3 is connected to the output of the operational amplifier U1, the Y pin of the third multiplier M3 is connected to the output of the inverting integrator U3, and the output of the third multiplier M3 is connected to the negative input of the inverting proportional adder U4 via the resistor R4. The voltage at the output pin of the third multiplier M3 is:

[0077] v M3 =wx; (11)

[0078] The positive input terminal of the inverting integrator U3 is grounded, and the negative input terminal is connected to the DC power supply V1 through the resistor R6. The negative input terminal is also connected to the output terminal of the first inverting proportional device U2 through the resistor R7. The negative input terminal is also connected to the output terminal of the second multiplier M2 through the resistor R3. The negative input terminal is also connected to its own output terminal through the capacitor C. The output terminal is connected to the X pin and Y pin of the first multiplier M1. The output terminal is also connected to the Y pin of the third multiplier M3. The following relationship can be obtained from the inverting integrator U3:

[0079]

[0080] Then the expression of the memristor equivalent circuit is:

[0081]

[0082] The equivalent simulation circuit structure of the memristor is as follows Figure 2 As shown in Figure 1, by connecting an AC power supply v = Asin(2πft) to the outside and setting different amplitudes and frequencies, the characteristics of the memristor can be verified. The circuit simulation results of the memristor under the stimulation of the AC voltage signal are shown in Figure 1. Figure 3 、 Figure 4 shown. Figure 3 The volt-ampere hysteresis curves are shown in Figure 1 when the AC power amplitude A is 5V and the frequencies f are 200Hz, 400Hz, and 1000Hz respectively. It can be seen that the area of ​​the hysteresis curve gradually decreases as the power frequency increases. Figure 4 The volt-ampere hysteresis curves for AC power supply amplitudes A of 4V, 5V, and 6V, respectively, are shown when the power supply frequency is fixed at 200Hz. It can be seen that the area of ​​the hysteresis curve gradually increases with increasing power supply amplitude. The designed memristor simulator conforms to the characteristics of a memristor.

[0083] Capacitors C1, C2 and inductor L are connected to the outside of the memristor equivalent simulation circuit to form a super-multistable memristor chaotic circuit system. Its equivalent circuit is as follows: Figure 5 shown.

[0084] In summary, the equivalent circuit expression of the wide-area super-multistable memristive chaotic system is:

[0085]

[0086] Numerous numerical simulation results show that the system switches frequently with the change of initial conditions under different parameter sets, showing a phenomenon of super-multistability. Some trajectory phase diagrams are shown in Figure 2. Figures 6-10 When the parameters α=7、β=6、γ=1、D=1.4、E=0.6、F=-0.2、K=-2, the system obtains some numerical simulation diagrams as the initial conditions change ( Figure 6 ) and circuit simulation diagram ( Figure 7 ). When the parameters α=500、β=5、γ=0.5、D=1.4、E=0.6、F=-0.2、K=-0.02, some numerical simulation diagrams of the system obtained as the initial conditions change ( Figure 8 ) and circuit simulation diagram ( Figure 9 、 Figure 10 ).

[0087] In order to obtain the component parameters of the system equivalent circuit, the system parameters are first substituted into the system after time scale transformation, that is, formula (4), and then the coefficients of formula (4) are compared with the coefficients of formula (14) to obtain the component parameters of the equivalent circuit. When the memristor chaotic circuit system is α = 7, β = 6, γ = 1, D = 1.4, E = 0.6, F = -0.2, K = -2, the equivalent circuit of the corresponding system is C1 = 142.857μF, C2 = 166.667μF, L = 1mH, R13 = 1Ω, and other device parameters are as follows: Figure 2 As shown, the circuit simulation results under different initial conditions are as follows Figure 7 As shown, the circuit simulation results are consistent with the Matlab numerical simulation results (see Figure 6 ). When the memristor chaotic circuit system is α=500、β=5、γ=0.5、D=1.4、E=0.6、F=-0.2、K=-0.02, the equivalent circuit of the corresponding system is C1=2μF、C2=200μF、L=2mH、R13=100Ω, and the other device parameters are Figure 2 The parameter values ​​shown are the same. At this time, the circuit simulation results under different initial conditions are as follows Figure 9 and Figure 10 As shown, the circuit simulation results are consistent with the Matlab numerical simulation results (see Figure 8Numerous experiments have shown that when a parameter set is selected and varied within a specific range, the system exhibits multiple stable states. The xy-plane phase diagrams for the two parameter sets listed above, under different initial conditions, are consistent with the circuit simulations, demonstrating the correctness of the circuit design.

[0088] Of course, the above description is not a limitation of the present invention, and the present invention is not limited to the above examples. Changes, modifications, additions or substitutions made by technicians in this technical field within the essential scope of the present invention should also fall within the scope of protection of the present invention.

Claims

1. A wide-area super-multistable memristive chaotic circuit system, characterized in that: The chaotic circuit system is composed of a memristor, a capacitor and an inductor, and the equivalent circuit of the chaotic circuit system includes a memristor circuit, a resistor network, a voltage conveyor, an inverting proportional device, an inverting proportional adder, an inverting integrator, a multiplier, an external inductor and a capacitor; The voltage transmitter is used to transmit voltage values ​​and isolate current transmission, which is achieved through the operational amplifier U1; The inverting proportional device is used to realize the proportional operation of the output voltage and the input voltage and make the polarities of the two opposite, including a first inverting proportional device U2 and a second inverting proportional device U5; The inverting proportional adder is used to implement the addition operation of multiple input voltages so that their sum is used as the output voltage and is in antiphase, including an inverting proportional adder U4; The inverting integrator is used to implement the integration operation of the input voltage signal, including an inverting integrator U3; The multiplier is used to implement the product operation of two input signals, including a first multiplier M1, a second multiplier M2 and a third multiplier M3; The external inductor and capacitor include capacitors C1, C2 and inductor L; The first multiplier M1, the second multiplier M2 and the third multiplier M3 all use AD633JN chips; The X pin and Y pin of the first multiplier M1 are commonly connected to the first end of the capacitor C0, the output end of the inverting integrator U3, and the Y pin of the third multiplier M3. The output end of the first multiplier M1 is connected to the first end of the resistor R1. The X pin of the third multiplier M3 is connected to the first end of the resistor R8, the X pin and Y pin of the second multiplier M2, and the negative input and output ends of the operational amplifier U1. The output end of the third multiplier M3 is connected to the first end of the resistor R4. The output end of the second multiplier M2 is connected to the first end of the resistor R3. The operational amplifier U1 uses an AD633JN chip. The positive input terminal of the operational amplifier U1 is connected to the first end of the resistor R13, the first end of the capacitor C1, and the first end of the inductor L. The second end of the inductor L is connected to the first end of the capacitor C2. The second end of the capacitor C2 and the second end of the capacitor C1 are both grounded. The first inverting proportional circuit U2 and the second inverting proportional circuit U5 both use OP07CP chips; The positive input terminal of the first inverting proportional circuit U2 is grounded, the negative input terminal is connected to the second end of the resistor R1 and the first end of the resistor R2, and the output terminal of U2 is connected to the second end of the resistor R2 and the first end of the resistor R7; the positive input terminal of the second inverting proportional circuit U5 is grounded, the negative input terminal is connected to the first end of the resistor R9 and the first end of the resistor R10, and the output terminal of U5 is connected to the second end of the resistor R10 and the second end of the resistor R13; The inverting proportional adder U4 uses an OP07CP chip; the positive input terminal of the inverting proportional adder U4 is grounded, the negative input terminal is connected to the second end of the resistor R4, the second end of the resistor R8, and the first end of the resistor R5, and the output terminal of U4 is connected to the second end of the resistor R5 and the second end of the resistor R9; The inverting integrator U3 uses an OP07CP chip; the positive input end of the inverting integrator U3 is grounded, and the negative input end is connected to the second end of the capacitor C0, the second end of the resistor R7, the second end of the resistor R3, and the first end of the resistor R6. The second end of the resistor R6 is connected to the positive electrode of the power supply V1, and the negative electrode of V1 is grounded.

2. The wide-area super-multistable memristive chaotic circuit system according to claim 1, characterized in that: The chaotic circuit system expression is: Where x and y are state variables converted from the voltages of capacitors C1 and C2, z and w are state variables converted from the current of inductor L and the conductance of the memristor, respectively. α, β, and γ are system parameters related to the capacitance and inductance values. K, D, E, and F are parameters of the memristor. τ represents time.

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