Hardware-in-the-loop communication conversion method and communication conversion device

Abstract

The invention discloses a hardware-in-the-loop communication conversion method and device, and the method comprises the steps: obtaining a control instruction issued by a controller, and transmitting the control instruction to a semi-physical simulation platform, so as to control a simulation unit of the semi-physical simulation platform to execute a corresponding simulation task; and an operation result fed back by the semi-physical simulation platform is received, and after voltage frequency signal information of the simulation unit is calculated according to the operation result, the voltage frequency signal information is uploaded to the controller. According to the communication conversion method, on one hand, the number of serial ports can be effectively increased, and the flexibility and expansibility of the system are improved; and on the other hand, the generated voltage frequency signal has stronger anti-interference performance, high precision and high resolution, the stability of signal transmission is ensured, the communication conversion between the semi-physical simulation platform and the controller is realized, and the simulation debugging and program inspection functions of the semi-physical simulation platform are favorably realized.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a hardware-in-the-loop communication conversion method and a communication conversion device. Background Art

[0002] At present, electrical equipment is mostly modeled and simulated offline using Simulink in MATLAB, but this method has certain limitations in practical applications. The traditional Simulink modeling method cannot interact with hardware devices in real time to perform fast feedback control; and the simulation calculation speed is relatively slow, which is inefficient in dealing with actual large-scale product control problems. In comparison, the semi-physical simulation platform provides a more efficient solution. The semi-physical simulation platform not only supports real-time interaction with hardware devices, but also can use the models established in MATLAB / Simulink for semi-physical simulation, which is particularly critical for the simulation and control of electrical equipment.

[0003] In the existing hardware-in-the-loop technology, communication adapter boards mostly use communication packaging to solve the problem of limited interface resources. However, the packaging method cannot verify the factory program on the semi-physical simulation platform. At the same time, the controller and the semi-physical simulation platform cannot communicate directly due to inconsistent communication rates, interface mismatches and other reasons. Therefore, it is necessary to design a communication conversion product that meets the existing layout of the controller. Summary of the invention

[0004] In view of the above problems, the present application is proposed to provide a hardware-in-the-loop communication conversion method and a communication conversion device, so as to solve the communication conversion problem between the semi-physical simulation platform and the controller, improve the anti-interference ability and transmission stability of the voltage-frequency signal, and further realize the technical effect of the debugging function of the semi-physical simulation platform.

[0005] According to the first aspect of the present application, a hardware-in-the-loop communication conversion method is provided, which is executed by a communication conversion device. The conversion method includes: obtaining a control instruction issued by a controller, sending the control instruction to a semi-physical simulation platform to control the simulation unit of the semi-physical simulation platform to perform a corresponding simulation task; receiving an operation result fed back by the semi-physical simulation platform, calculating the voltage-frequency signal information of the simulation unit according to the operation result, and uploading the voltage-frequency signal information to the controller.

[0006] Optionally, the operation result fed back by the semi-physical simulation platform includes: a DC voltage signal of each simulation unit of the semi-physical simulation platform; and the voltage-frequency signal information of the simulation unit calculated according to the operation result includes:

[0007] According to the DC voltage signal of each simulation unit, a frequency parameter corresponding to the DC voltage value is calculated;

[0008] Determine the transmission clock period of a single voltage-frequency signal according to the frequency parameter, and calculate the number of clock periods of the single voltage-frequency signal;

[0009] According to the fixed value of the high-level clock period in the clock period, the number of clock periods in which the high level is maintained in the preset analysis period is calculated;

[0010] Calculating the number of clock cycles for low level maintenance according to the number of clock cycles of the single voltage-frequency signal and the number of clock cycles for high level maintenance;

[0011] According to the number of clock cycles for maintaining the high level and the number of clock cycles for maintaining the low level, the clock cycle for maintaining the low level under the DC voltage value is determined, and a voltage-frequency signal of the simulation unit is generated.

[0012] Optionally, the DC voltage signal includes a first DC voltage vol_in, and the method further includes:

[0013] Calculate the number of clock cycles required to transmit each first DC voltage vol_in according to the preset baud rate and the system clock cycle, and determine whether the voltage-frequency signal is within a low-level clock cycle;

[0014] When the voltage-frequency signal is not in a low-level clock cycle, the state indication signal tx_flag is pulled high, and the input DC voltage signal is converted into a corresponding frequency signal;

[0015] According to the state indication signal tx_flag, the level state of the counter enable signal cnt_en is determined, and the number of clock cycles in which the voltage-frequency signal is maintained at a low level is calculated.

[0016] Optionally, determining the level state of the counter enable signal cnt_en according to the state indication signal tx_flag includes:

[0017] The state indication signal tx_flag is delayed by one clock cycle to obtain a tx_flag0 signal, and the tx_flag0 signal is delayed by one clock cycle to obtain a tx_flag1 signal;

[0018] Determine the level state of the counter enable signal cnt_en according to the tx_flag0 signal and the tx_flag1 signal;

[0019] When it is detected that the tx_flag0 signal is pulled high and the tx_flag1 signal is not pulled high, the counter enable signal cnt_en is pulled high, and the number of clock cycles of the low level of the voltage-frequency signal is started to be counted;

[0020] When the number of clock cycles during which the voltage-frequency signal is maintained at a low level is calculated, the counter end signal cnt_end is pulled high.

[0021] Optionally, after the number of clock cycles during which the voltage-frequency signal is maintained at a low level is counted, the method further includes:

[0022] A second DC voltage is stored by a first register vol_reg, wherein the second DC voltage belongs to one or more voltage values ​​in a set constituted by the first DC voltage vol_in;

[0023] According to the change of the second DC voltage, the number of clock cycles of the low level maintained corresponding to the second voltage value is output in sequence and stored in the second register LOW_CNT_MAX.

[0024] Optionally, the method further comprises:

[0025] Determine the level states of the low-level flag signal low_flag and the high-level flag signal high_flag; wherein, when the low-level flag signal low_flag is at a high level, a low-level count is performed, and when the high-level flag signal high_flag is at a high level, a high-level count is performed;

[0026] The voltage-frequency signal is output according to the change of the low-level flag signal low_flag.

[0027] Optionally, when performing low level counting, the method includes:

[0028] When it is detected that the low level flag signal low_flag is at a high level, the low level counter low_cnt starts counting, and when counting reaches a first count value, the low level counter low_cnt is reset to zero, wherein the first count value is the number of clock cycles of the low level corresponding to the second voltage value stored in the second register LOW_CNT_MAX;

[0029] When performing high level counting, the method includes:

[0030] When the high level flag signal high_flag is detected to be at a high level, the high level counter high_cnt starts counting, and when counting reaches a second count value, the high level counter high_cnt is reset to zero; wherein the second count value is the number of clock cycles during which the high level is maintained in a preset analysis cycle.

[0031] Optionally, determining the level state of the low level flag signal low_flag further includes:

[0032] When it is detected that the counter end signal cnt_end is at a high level and the high level counter high_cnt is at a low level, or the count value of the high level counter high_cnt is the second count value minus one, the low level flag signal low_flag is pulled high;

[0033] When it is detected that the count value of the low level counter low_cnt is the first count value minus one, the low level flag signal low_flag is pulled low;

[0034] Determining the level state of the high-level flag signal high_flag also includes:

[0035] When it is detected that the count value of the low level counter low_cnt is the first count value minus one, the high level flag signal high_flag is pulled high;

[0036] When it is detected that the count value of the high level counter high_cnt is the second count value minus one, the high level flag signal high_flag is pulled low.

[0037] Optionally, outputting the voltage-frequency signal according to a change of the low-level flag signal low_flag includes:

[0038] The low-level flag signal low_flag is inverted, and the inverted signal is output as the voltage-frequency signal.

[0039] According to a second aspect of the present application, a communication conversion device is provided, which is used to execute the communication conversion method as described in any one of the first aspects above.

[0040] According to a third aspect of the present application, an electronic device is provided, comprising: a processor; and a memory arranged to store computer executable instructions, wherein when the executable instructions are executed, the processor executes a communication conversion method as described in any one of the first aspects above.

[0041] According to a fourth aspect of the present application, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores one or more programs, and when the one or more programs are executed by a processor, the communication conversion method as described in any one of the first aspects above is implemented.

[0042] As can be seen from the above, at least one of the above technical solutions adopted in the embodiment of the present application can achieve the following beneficial effects: a hardware-in-the-loop communication conversion method and a communication conversion device are provided, the communication conversion method is executed by the communication conversion device, and the conversion method includes: obtaining the control instruction issued by the controller, sending the control instruction to the semi-physical simulation platform to control the simulation unit of the semi-physical simulation platform to perform the corresponding simulation task; receiving the operation result fed back by the semi-physical simulation platform, calculating the voltage-frequency signal information of the simulation unit according to the operation result, and uploading the voltage-frequency signal information to the controller. Through the communication conversion method of the embodiment of the present application, on the one hand, it can effectively increase the number of serial ports, improve the flexibility and scalability of the system, and facilitate the multiplexing and data sharing between different products; on the other hand, the generated voltage-frequency signal has stronger anti-interference performance, high precision and high resolution, is easy to process signals, and can show higher reliability in long-distance transmission, ensuring the stability of signal transmission in various communication application scenarios. In this way, the communication conversion problem between the semi-physical simulation platform and the controller is solved, and the debugging and inspection functions of the semi-physical simulation platform are realized.

[0043] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present application. Also, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

[0045] Figure 1 A flowchart of a hardware-in-the-loop communication conversion method in one embodiment of the present application;

[0046] Figure 2 A schematic diagram of a data conversion process of a communication conversion device in one embodiment of the present application;

[0047] Figure 3 A schematic diagram of a clock cycle of a voltage-frequency signal in one embodiment of the present application;

[0048] Figure 4 It is a timing diagram of a voltage-frequency signal (partial signal) in one embodiment of the present application.

[0049] Figure 5 A schematic diagram of the structure of a communication conversion device in one embodiment of the present application;

[0050] Figure 6 It is a schematic diagram of the structure of an electronic device in one embodiment of the present application. DETAILED DESCRIPTION

[0051] The exemplary embodiments of the present application will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0052] In the related art, since the GPIO general input and output interfaces of the semi-physical simulation platform and the communication adapter board are limited, the existing communication adapter board mostly adopts the communication packaging method to solve the problem of limited interface resources, but the existing packaging method cannot verify the factory program on the semi-physical simulation platform. At the same time, the existing communication adapter board also has problems such as inconsistent communication rate and interface mismatch. Based on this, the present application provides a hardware-in-the-loop communication conversion method and a communication conversion device to solve the communication conversion problem between the semi-physical simulation platform and the controller, improve the anti-interference ability and transmission stability of the voltage-frequency signal, and thus achieve the technical effect of the debugging function of the semi-physical simulation platform.

[0053] The technical concept of the present application is to design a communication conversion method and device based on FPGA (field programmable gate array) architecture. On the one hand, the conversion function between serial port data and optical fiber data is realized through the communication conversion device to meet the requirements of transmission protocol and transmission rate; on the other hand, the stability of data transmission is improved by generating a voltage-frequency signal, thereby enabling the corresponding control, transmission and debugging functions to be realized between the controller and the semi-physical simulation platform through the communication conversion device.

[0054] It should be noted that the "hardware in the loop" in the embodiment of the present application refers to the semi-physical simulation technology of physical controller + virtual control object, and the "simulation unit" in the embodiment of the present application refers to the virtual unit of the semi-physical simulation platform, such as a virtual energy storage unit, etc., which is not limited here.

[0055] The technical solutions provided by various embodiments of the present application are described in detail below in conjunction with the accompanying drawings.

[0056] In one embodiment of the present application, Figure 1 As shown, a flowchart of a hardware-in-the-loop communication conversion method is provided; the hardware-in-the-loop communication conversion method of the embodiment of the present application is executed by a communication conversion device, such as Figure 2As shown, a data conversion process diagram of a communication conversion device is provided. The communication conversion device provided in an embodiment of the present application is implemented based on an FPGA architecture. The communication conversion device includes multiple serial ports and is connected to a controller via a UART bus (universal serial data bus). At the same time, the communication conversion device is connected to a semi-physical simulation platform via an optical fiber.

[0057] like Figure 1 As shown, the communication conversion method at least includes the following steps S110 to S120:

[0058] Step S110, obtaining a control instruction issued by the controller, and sending the control instruction to the semi-physical simulation platform to control the simulation unit of the semi-physical simulation platform to perform a corresponding simulation task.

[0059] Specifically, the communication conversion device of this embodiment can decode the communication frame sent by the controller. Figure 2 As shown, in the data flow between the controller and the communication conversion device, the controller can send control instructions of each simulation unit to the semi-physical simulation platform one by one through the universal input and output interface.

[0060] For example, after receiving the data frame containing control instructions sent by the controller, the multiple communication interfaces of the communication conversion device can decode the data frame, and then package the data using the packaging format pre-agreed with the semi-physical simulation platform. The sending unit Tx_Stream of the communication module sends the data packet containing the control instructions to the semi-physical simulation platform through the optical fiber interface. The communication interfaces of this embodiment include but are not limited to GPIO interface, serial communication interface, etc.

[0061] Step S120, receiving the operation result fed back by the semi-physical simulation platform, calculating the voltage-frequency signal information of the simulation unit according to the operation result, and uploading the voltage-frequency signal information to the controller.

[0062] Specifically, continue to refer to Figure 2 As shown, after receiving the control instruction, the semi-physical simulation platform can respond and control its corresponding simulation unit to perform related operations, such as controlling the simulation unit to perform function debugging, factory program inspection and other operations, and then the semi-physical simulation platform will feedback the operation results of the corresponding simulation unit to the communication conversion device.

[0063] For example, the semi-physical simulation platform can send the DC voltage information of the simulation unit to the communication conversion device through the optical fiber interface. After the communication conversion device captures the data packet containing the DC voltage information through the receiving unit Rx_Stream of the communication module, it unpacks and performs frequency conversion on the data packet. That is, it performs frequency conversion on the voltage value of each simulation unit in the data packet, calculates the clock cycle occupied by the low level under the voltage, and generates a corresponding frequency conversion signal, which is then uploaded to the controller through the serial port of the communication conversion device.

[0064] It can be seen that, different from the existing communication conversion scheme with inconsistent communication rates and mismatched interfaces, the hardware-in-the-loop communication conversion method of the embodiment of the present application can, on the one hand, effectively increase the number of serial ports, improve the flexibility and scalability of the system, and facilitate the reuse and data sharing between different products; on the other hand, it makes the generated voltage-frequency signal have stronger anti-interference performance, high precision and high resolution, easy signal processing, and can show higher reliability in long-distance transmission, ensuring the stability of signal transmission in a variety of communication application scenarios. This solves the communication conversion problem between the semi-physical simulation platform and the controller, and realizes the debugging and inspection functions of the semi-physical simulation platform.

[0065] In some embodiments, the operation results fed back by the semi-physical simulation platform include: the DC voltage signal of each simulation unit of the semi-physical simulation platform; the voltage-frequency signal information of the simulation unit calculated according to the operation results, including: according to the DC voltage signal of each simulation unit, calculating the frequency parameter corresponding to the DC voltage value; according to the frequency parameter, determining the transmission clock period of a single voltage-frequency signal, and calculating the number of clock periods of the single voltage-frequency signal; according to the fixed value of the high-level clock period within the clock period, calculating the number of clock periods maintained at a high level under a preset analysis period; according to the number of clock periods of the single voltage-frequency signal and the number of clock periods maintained at a high level, calculating the number of clock periods maintained at a low level; according to the number of clock periods maintained at a high level and the number of clock periods maintained at a low level, determining the clock period maintained at a low level under the DC voltage value, and generating the voltage-frequency signal of the simulation unit.

[0066] like Figure 3 As shown, a schematic diagram of the clock cycle of a voltage-frequency signal is provided; the following will be combined with Figure 3 The definition of voltage-frequency signal and key calculation process are explained.

[0067] First, the DC voltage signal, i.e. the DC voltage value U, is fed back to the communication conversion device through the semi-physical simulation platform. dc , the voltage unit is V. The relationship between the voltage and frequency of the voltage-frequency control chip is as follows:

[0068]

[0069] Wherein, f is the frequency of the pulse signal output by the voltage-frequency module of the communication conversion device.

[0070] See also Figure 2 As shown, the transmission clock period of a single voltage value of the voltage-frequency signal is T, that is, the transmission clock period of a complete voltage-frequency signal is:

[0071] The high-level transmission clock period is a known fixed value, that is, the fixed value of the high-level clock period is recorded as t H If the voltage-frequency signal is resolved at a known preset resolution period t, the number of clock cycles n during which the high level is maintained is H for:

[0072]

[0073] Since the number of transmission clock cycles n of a single voltage-frequency signal corresponding to a certain voltage T for:

[0074]

[0075] Therefore, the number of clock cycles n during which the low level is maintained can be calculated. L for:

[0076] n L =n T -n H

[0077] Thus, the clock cycle of the low level holding of the voltage-frequency signal can be solved by the difference between the number of clock cycles of a single voltage-frequency signal and the number of clock cycles of the high level holding, and then the clock cycle of the low level holding of the voltage-frequency signal can be solved according to the number of clock cycles n of the high level holding. H And the number of clock cycles n that the low level is maintained L , determine the clock period of low level maintenance under this DC voltage value, and the voltage-frequency signal solution is completed.

[0078] like Figure 4 As shown, a timing diagram of a voltage-frequency signal is provided. Since the calculation process of the voltage-frequency signal involves division, the voltage-frequency signal can be calculated by a lookup table to realize the timing diagram design in combination with the accuracy requirements and voltage range of the specific applicable scenario.

[0079] In some embodiments, the above calculation process and timing diagram design of the voltage-frequency signal are implemented based on the FPGA architecture; the DC voltage signal includes a first DC voltage vol_in, and the method further includes: according to the preset baud rate and the system clock cycle, calculating the number of clock cycles required to transmit each first DC voltage vol_in, and judging whether the voltage-frequency signal is in a low-level clock cycle, that is, judging whether the low-level flag signal low_flag is at a high level; when the voltage-frequency signal is not in a low-level clock cycle, pulling up the state indication signal tx_flag, and converting the input DC voltage signal into a corresponding frequency signal; according to the state indication signal tx_flag, determining the level state of the counter enable signal cnt_en, and calculating the number of clock cycles n during which the voltage-frequency signal is maintained at a low level L .

[0080] In some embodiments, the level state of the counter enable signal cnt_en is determined according to the state indication signal tx_flag, including: beating the state indication signal tx_flag, that is, delaying one clock cycle and obtaining the tx_flag0 signal, beating the tx_flag0 signal, that is, delaying one clock cycle and obtaining the tx_flag1 signal, the beating operation is used to eliminate the metastable state, and at the same time detect the rising edge of the tx_flag signal; according to the tx_flag0 signal and the tx_flag1 signal, the level state of the counter enable signal cnt_en is determined; wherein, when it is detected that the tx_flag0 signal is pulled high and the tx_flag1 signal is not pulled high, the counter enable signal cnt_en is pulled high, and the number of clock cycles in which the voltage-frequency signal is maintained at a low level is started to be counted; when the number of clock cycles n in which the voltage-frequency signal is maintained at a low level is n L After the calculation is completed, the counter end signal cnt_end is pulled high.

[0081] In some embodiments, after the number of clock cycles of the voltage-frequency signal being held at a low level is counted, the method further includes: saving a second DC voltage, such as vol1, vol2, ..., through a first register vol_reg, wherein the second DC voltage belongs to one or more voltage values ​​in a set consisting of the first DC voltage vol_in; and outputting the number of clock cycles n of the second voltage value being held at a low level in sequence by using a table lookup method according to a change in the second DC voltage. L , such as low1, low2, ..., and saved by the second register LOW_CNT_MAX.

[0082] In some embodiments, the method also includes: determining the level status of a low-level flag signal low_flag and a high-level flag signal high_flag; wherein, when the low-level flag signal low_flag is at a high level, a low-level count is performed, and when the high-level flag signal high_flag is at a high level, a high-level count is performed; and outputting the voltage-frequency signal according to the change of the low-level flag signal low_flag.

[0083] In some embodiments, when performing low-level counting, the method includes: when the low-level flag signal low_flag is detected to be at a high level, the low-level counter low_cnt starts counting, that is, it increases by 1 each time, and when the count reaches a first count value lown (n=1, 2,...), the low-level counter low_cnt is reset to zero, wherein the first count value lown is the number of clock cycles (e.g., low1, low2,...) of the low level maintained corresponding to the second voltage value (e.g., vol1, vol2,.....) stored in the second register LOW_CNT_MAX.

[0084] In some embodiments, when performing high-level counting, the method includes: when the high-level flag signal high_flag is detected to be at a high level, the high-level counter high_cnt starts counting, that is, it increases by 1 each time, and when the second count value high (the value is a positive integer) is counted, the high-level counter high_cnt is reset to zero; wherein the second count value high is a fixed known value calculated under a preset analysis period t, that is, the number of clock cycles n during which the high level is maintained H .

[0085] In some embodiments, determining the level state of the low-level flag signal low_flag further includes: when it is detected that the counter end signal cnt_end is at a high level and the high-level counter high_cnt is at a low level (the voltage-frequency signal has not started to be transmitted), or the count value of the high-level counter high_cnt is the second count value minus one, that is, the value of high_cnt is high-1, indicating that the previous voltage-frequency conversion process is about to be completed, then the low-level flag signal low_flag is pulled high; when it is detected that the count value of the low-level counter low_cnt is the first count value minus one, that is, the value of low_cnt is lown-1 (n=1, 2, ...), then the low-level flag signal low_flag is pulled low;

[0086] In some embodiments, determining the level state of the high-level flag signal high_flag also includes: when it is detected that the count value of the low-level counter low_cnt is the first count value minus one, that is, when low_cnt counts to lown-1, the high-level flag signal high_flag is pulled high; when it is detected that the count value of the high-level counter high_cnt is the second count value minus one, that is, when the value of high_cnt is high-1, it indicates that the process of transmitting the high-level signal of the voltage-frequency signal is about to be completed, and the high-level flag signal high_flag is pulled low.

[0087] In some implementations, outputting the voltage-frequency signal according to a change in the low-level flag signal low_flag includes: inverting the low-level flag signal low_flag, and outputting the inverted signal as the voltage-frequency signal.

[0088] The following will be combined Figure 4 The process of designing the timing diagram of the voltage-frequency signal in this embodiment is described as follows:

[0089] (1) First, the number of clock cycles required to transmit each DC voltage is calculated based on the relationship between the preset baud rate and the system clock cycle. Assuming that a first DC voltage value vol_in is transmitted in each clock cycle, it is determined whether the voltage-to-frequency signal is within the transmission low-level clock cycle (when low_flag is high, it indicates that it is within the low-level clock cycle). If not, the tx_flag signal is pulled high to indicate the start of the voltage-to-frequency signal conversion process.

[0090] (2) After that, the state indication signal tx_flag is tapped once to obtain the tx_flag0 signal, and then the tx_flag0 signal is tapped once to obtain the tx_flag1 signal. The tapping operation is used to eliminate the metastable state and detect the rising edge of the tx_flag signal at the same time.

[0091] (3) Afterwards, when the rising edge of the tx_flag signal is detected, the counter enable signal cnt_en is pulled high; at this time, the cnt_en signal is used to indicate the start of the calculation process of the number of low-level holding clock cycles of the voltage-frequency signal.

[0092] (4) Afterwards, the second DC voltage value to be converted into a voltage-frequency value is stored in the first register vol_reg, for example, vol1, vol2, ...

[0093] (5) Afterwards, the number of clock cycles low1, low2, ... of the low level maintenance corresponding to the second voltage value stored in the first register vol_reg is obtained by a table lookup method; and the number of clock cycles of the low level maintenance is stored in the second register LOW_CNT_MAX.

[0094] (6) Afterwards, the counter end signal cnt_end is pulled high, which is used to indicate that the calculation process of the number of low-level clock cycles has been completed; wherein, when the voltage-frequency signal has not started to be transmitted (when the high-level counter high_cnt and the low-level counter low_cnt are both low levels), or when the previous voltage-frequency conversion process is about to be completed (when the value of the high-level counter high_cnt is the second count value high-1), the cnt_end signal is pulled low; when cnt_end has a falling edge, it indicates that the voltage-frequency signal of the current DC voltage has started to be transmitted.

[0095] (7) When it is detected that the cnt_end signal of (6) is high and the voltage-frequency signal transmission has not started (when the high-level counter high_cnt is at a low level), or when the previous voltage-frequency conversion process is about to be completed (when the value of the high-level counter high_cnt is the second count value high-1), the low-level flag signal low_flag is pulled high; when the process of transmitting the low-level signal of the voltage-frequency signal is about to be completed (when the value of the low-level counter low_cnt is the first count value lown-1, n=1,2,...), the low_flag signal is pulled low.

[0096] (8) When it is detected that the low level flag signal low_flag in (7) is at a high level, the low level counter low_cnt starts counting, i.e., it increases by 1 each time, and when the count reaches the first count value lown (n=1, 2, ...), the low level counter low_cnt returns to zero; wherein lown is the number of low level hold clock cycles corresponding to the second voltage value in the first register vol_reg stored in the second register LOW_CNT_MAX.

[0097] (9) When it is detected that the low level counter low_cnt in step (7) counts to the first count value lown-1, the high level flag signal high_flag is pulled high. When the process of transmitting the high level signal of the voltage-frequency signal is about to be completed (when the value of the high level counter high_cnt is the second count value high-1), the high_flag signal is pulled low.

[0098] (10) When the high-level flag signal high_flag in step (9) is detected to be at a high level, the high-level counter high_cnt starts counting, that is, it increases by 1 each time, and when the maximum count value of the second count value high is calculated, the high-level counter high_cnt returns to zero. Wherein, high is the preset clock frequency of the resolved voltage-frequency signal, that is, the fixed known value calculated under the preset resolved period t.

[0099] (11) Finally, the low-level flag signal low_flag in step (7) is inverted to obtain the voltage-frequency signal vol_freq to be transmitted.

[0100] Of course, the above contents related to the voltage-frequency signal timing design are merely exemplary embodiments and should not be construed as limitations on the present application.

[0101] In other embodiments of the present application, Figure 5 As shown, a communication conversion device 500 is also proposed, which is used to execute the communication conversion method as described in any of the above embodiments. The communication conversion device 500 at least includes:

[0102] The TX transmission unit 510 is used to obtain the control instruction issued by the controller, and send the control instruction to the semi-physical simulation platform to control the simulation unit of the semi-physical simulation platform to perform the corresponding simulation task;

[0103] The RX receiving unit 520 is used to receive the operation result fed back by the semi-physical simulation platform, calculate the voltage-frequency signal information of the simulation unit according to the operation result, and upload the voltage-frequency signal information to the controller.

[0104] The communication conversion device 500 further includes:

[0105] The pressure-frequency unit 530 is used to generate pressure-frequency signal information;

[0106] The decoding unit 540 is used to decode the received data frame containing the control instruction.

[0107] In a preferred embodiment, the communication conversion device 500 can be implemented based on the FPGA adapter board of the Xilinx chip, the TX transmission unit 510 is implemented based on the sending module Tx_Stream of Aurora8b / 10b, and the RX receiving unit 520 is implemented based on the receiving module Rx_Stream of the Aurora8b / 10b module.

[0108] In a specific embodiment, the communication conversion device also includes: a JTAG connector, a DC switching power supply, an FPGA module and at least one SFP optical module. The function of the JTAG connector is to connect the FPGA chip to the host computer system to facilitate program burning and simulation debugging. The FPGA module is composed of a main control chip and its peripheral circuits, and the selected FPGA chip is connected to at least one SFP interface cage and a Flash storage module. After the bitstream data stream is burned into the Flash storage module, the FPGA chip can automatically load the program when powered on. The DC switching power supply is used to power the FPGA module. The SFP optical module is responsible for realizing the communication between the communication conversion device and the semi-physical simulation platform. It realizes the transmission of data between the channel and the application by calling and writing the user interface in the Aurora8b / 10b module.

[0109] It can be understood that the above-mentioned communication conversion device can implement each step of the hardware-in-the-loop communication conversion method provided in the aforementioned embodiment, and the relevant explanations about the hardware-in-the-loop communication conversion method are applicable to the communication conversion device and will not be repeated here.

[0110] In summary, this application has achieved at least the following technical effects: on the one hand, it can effectively increase the number of serial ports, improve the flexibility and scalability of the system, and facilitate the reuse and data sharing between different products; on the other hand, it makes the generated voltage-frequency signal have stronger anti-interference performance, high precision and high resolution, easy signal processing, and can show higher reliability in long-distance transmission, ensuring the stability of signal transmission in various communication application scenarios. This solves the communication conversion problem between the semi-physical simulation platform and the controller, and realizes the debugging and inspection function of the semi-physical simulation platform.

[0111] Figure 6 This is a schematic diagram of the structure of an electronic device according to an embodiment of the present application. Figure 6 At the hardware level, the electronic device includes a processor, and optionally also includes an internal bus, a network interface, and a memory. The memory may include a memory, such as a high-speed random access memory (RAM), and may also include a non-volatile memory (non-volatile memory), such as at least one disk storage. Of course, the electronic device may also include hardware required for other services.

[0112] The processor, network interface and memory can be interconnected through an internal bus, which can be an ISA (Industry Standard Architecture) bus, a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 6 Only one bidirectional arrow is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0113] The memory is used to store the program. Specifically, the program may include a program code, and the program code includes a computer operation instruction. The memory may include a memory and a non-volatile memory, and provides instructions and data to the processor.

[0114] The processor reads the corresponding computer program from the non-volatile memory into the memory and then runs it, forming a communication conversion device at the logical level. The processor executes the program stored in the memory and is specifically used to perform the following operations:

[0115] Obtaining a control instruction issued by a controller, and sending the control instruction to a semi-physical simulation platform to control a simulation unit of the semi-physical simulation platform to perform a corresponding simulation task;

[0116] The operation result fed back by the semi-physical simulation platform is received, and after the voltage-frequency signal information of the simulation unit is calculated according to the operation result, the voltage-frequency signal information is uploaded to the controller.

[0117] The above application Figure 5The method performed by the communication conversion device disclosed in the illustrated embodiment can be applied to a processor or implemented by a processor. The processor may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by an integrated logic circuit of hardware in the processor or an instruction in the form of software. The above processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The methods, steps and logic block diagrams disclosed in the embodiments of the present application can be implemented or executed. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc. The steps of the method disclosed in the embodiments of the present application can be directly embodied as a hardware decoding processor for execution, or a combination of hardware and software modules in the decoding processor for execution. The software module can be located in a storage medium mature in the art such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory, and the processor reads the information in the memory and completes the steps of the above method in combination with its hardware.

[0118] The electronic device may also perform Figure 5 The method executed by the communication conversion device in Figure 5 The functions of the illustrated embodiment will not be described in detail in the embodiments of the present application.

[0119] The present application also provides a computer-readable storage medium, which stores one or more programs, wherein the one or more programs include instructions, which, when executed by an electronic device including multiple application programs, enable the electronic device to execute Figure 1 The method performed by the communication conversion device in the illustrated embodiment is specifically used to perform:

[0120] Obtaining a control instruction issued by a controller, and sending the control instruction to a semi-physical simulation platform to control a simulation unit of the semi-physical simulation platform to perform a corresponding simulation task;

[0121] The operation result fed back by the semi-physical simulation platform is received, and after the voltage-frequency signal information of the simulation unit is calculated according to the operation result, the voltage-frequency signal information is uploaded to the controller.

[0122] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0123] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0124] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0125] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0126] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0127] The memory may include non-permanent storage in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0128] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0129] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0130] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0131] The above is only an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

Claims

1. A hardware-in-the-loop communication conversion method, characterized in that: Executed by a communication conversion device, the communication conversion method includes: Obtaining a control instruction issued by a controller, and sending the control instruction to a semi-physical simulation platform to control a simulation unit of the semi-physical simulation platform to perform a corresponding simulation task; The operation result fed back by the semi-physical simulation platform is received, and after the voltage-frequency signal information of the simulation unit is calculated according to the operation result, the voltage-frequency signal information is uploaded to the controller.

2. The communication conversion method according to claim 1, characterized in that: The operation result fed back by the semi-physical simulation platform includes: the DC voltage signal of each simulation unit of the semi-physical simulation platform; the voltage-frequency signal information of the simulation unit calculated according to the operation result includes: According to the DC voltage signal of each simulation unit, a frequency parameter corresponding to the DC voltage value is calculated; Determine the transmission clock period of a single voltage-frequency signal according to the frequency parameter, and calculate the number of clock periods of the single voltage-frequency signal; According to the fixed value of the high-level clock period in the clock period, the number of clock periods in which the high level is maintained in the preset analysis period is calculated; Calculating the number of clock cycles for low level maintenance according to the number of clock cycles of the single voltage-frequency signal and the number of clock cycles for high level maintenance; According to the number of clock cycles for maintaining the high level and the number of clock cycles for maintaining the low level, the clock cycle for maintaining the low level under the DC voltage value is determined, and a voltage-frequency signal of the simulation unit is generated.

3. The communication conversion method according to claim 2, characterized in that: The DC voltage signal includes a first DC voltage vol_in, and the method further includes: Calculate the number of clock cycles required to transmit each first DC voltage vol_in according to the preset baud rate and the system clock cycle, and determine whether the voltage-frequency signal is within a low-level clock cycle; When the voltage-frequency signal is not in a low-level clock cycle, the state indication signal tx_flag is pulled high, and the input DC voltage signal is converted into a corresponding frequency signal; According to the state indication signal tx_flag, the level state of the counter enable signal cnt_en is determined, and the number of clock cycles in which the voltage-frequency signal is maintained at a low level is calculated.

4. The communication conversion method according to claim 3, characterized in that: Determining the level state of the counter enable signal cnt_en according to the state indication signal tx_flag includes: The state indication signal tx_flag is delayed by one clock cycle to obtain a tx_flag0 signal, and the tx_flag0 signal is delayed by one clock cycle to obtain a tx_flag1 signal; Determine the level state of the counter enable signal cnt_en according to the tx_flag0 signal and the tx_flag1 signal; When it is detected that the tx_flag0 signal is pulled high and the tx_flag1 signal is not pulled high, the counter enable signal cnt_en is pulled high, and the number of clock cycles of the low level of the voltage-frequency signal is started to be counted; When the number of clock cycles during which the voltage-frequency signal is maintained at a low level is calculated, the counter end signal cnt_end is pulled high.

5. The communication conversion method according to claim 4, characterized in that: When the number of clock cycles during which the voltage-frequency signal is maintained at a low level is counted, the method further includes: A second DC voltage is stored by a first register vol_reg, wherein the second DC voltage belongs to one or more voltage values ​​in a set constituted by the first DC voltage vol_in; According to the change of the second DC voltage, the number of clock cycles of the low level maintained corresponding to the second voltage value is output in sequence and stored in the second register LOW_CNT_MAX.

6. The communication conversion method according to claim 5, characterized in that: The method further comprises: Determine the level states of the low-level flag signal low_flag and the high-level flag signal high_flag; wherein, when the low-level flag signal low_flag is at a high level, a low-level count is performed, and when the high-level flag signal high_flag is at a high level, a high-level count is performed; The voltage-frequency signal is output according to the change of the low-level flag signal low_flag.

7. The communication conversion method according to claim 6, characterized in that: When performing low level counting, the method includes: When it is detected that the low level flag signal low_flag is at a high level, the low level counter low_cnt starts counting, and when counting reaches a first count value, the low level counter low_cnt is reset to zero, wherein the first count value is the number of clock cycles of the low level corresponding to the second voltage value stored in the second register LOW_CNT_MAX; When performing high level counting, the method includes: When the high level flag signal high_flag is detected to be at a high level, the high level counter high_cnt starts counting, and when counting reaches a second count value, the high level counter high_cnt is reset to zero; wherein the second count value is the number of clock cycles during which the high level is maintained in a preset analysis cycle.

8. The communication conversion method according to claim 7, characterized in that: Determining the level state of the low level flag signal low_flag also includes: When it is detected that the counter end signal cnt_end is at a high level and the high level counter high_cnt is at a low level, or the count value of the high level counter high_cnt is the second count value minus one, the low level flag signal low_flag is pulled high; When it is detected that the count value of the low level counter low_cnt is the first count value minus one, the low level flag signal low_flag is pulled low; Determining the level state of the high-level flag signal high_flag also includes: When it is detected that the count value of the low level counter low_cnt is the first count value minus one, the high level flag signal high_flag is pulled high; When it is detected that the count value of the high level counter high_cnt is the second count value minus one, the high level flag signal high_flag is pulled low.

9. The communication conversion method according to claim 6, characterized in that: Outputting the voltage-frequency signal according to the change of the low-level flag signal low_flag includes: The low-level flag signal low_flag is inverted, and the inverted signal is output as the voltage-frequency signal.

10. A communication conversion device, characterized in that: Used to execute the communication conversion method as described in any one of claims 1 to 9.

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