Preparation method of semiconductor structure, semiconductor structure and device

Abstract

The invention provides a preparation method of a semiconductor structure, the semiconductor structure and a device. The method comprises the following steps: forming an active structure on a substrate; sequentially forming a first front-side transistor, a second front-side transistor and a front-side back-pass transistor which are stacked on the basis of the front-side active structure; a first front side source drain metal in the first front side transistor, a second front side source drain metal in the second front side transistor and a third front side source drain metal in the front side back channel transistor are connected; performing a back-end process on the front-side back-end transistor to form a front-side metal interconnection layer; reversing the wafer and thinning the substrate; based on the back active structure, sequentially forming a first back transistor, a second back transistor and a back back channel transistor which are stacked; a first back side source drain metal in the first back side transistor, a second back side source drain metal in the second back side transistor and a third back side source drain metal in the back side back channel transistor are connected; and performing a back-end process on the back-surface back-end transistor to form a back-surface metal interconnection layer.

Description

Technical Field

[0001] The present application relates to the semiconductor field, and in particular to a method for preparing a semiconductor structure, a semiconductor structure and a device. Background Art

[0002] The basic memory cell of SRAM is usually composed of 6 transistors, and this structure is called 6T SRAM. These transistors include two P-channel (PMOS) and four N-channel (NMOS) transistors. Each memory cell of SRAM usually requires more transistors to implement in order to maintain the stored data state. This makes SRAM relatively low in storage density, so it occupies a larger area, making the design layout area larger. Summary of the invention

[0003] The present application provides a method for preparing a semiconductor structure, a semiconductor structure, a device and an apparatus to reduce the layout area of ​​the semiconductor structure.

[0004] In a first aspect, an embodiment of the present application provides a method for preparing a semiconductor structure, wherein the semiconductor structure is a static random access memory unit, and the method comprises: forming an active structure on a substrate; the active structure comprises a front active structure, a sacrificial structure, and a back active structure stacked in sequence in a first direction; based on the front active structure, a first front transistor, a second front transistor, and a front back transistor stacked in sequence are formed in the first direction; a first front source-drain metal in the first front transistor, a second front source-drain metal in the second front transistor, and a third front source-drain metal in the front back transistor are connected; a back process is performed on the front back transistor to form a front metal interconnection layer; the substrate is flipped and thinned until the back active structure is exposed; based on the back active structure, a first back transistor, a second back transistor, and a back back transistor stacked in sequence are formed in the first direction. body tube; the first back source and drain metal in the first back transistor, the second back source and drain metal in the second back transistor and the third back source and drain metal in the back back transistor are connected; the back-end process is performed on the back back transistor to form a back metal interconnection layer; the above method also includes: removing the sacrificial structure to form a first gap, and filling the first gap with insulating material to form an intermediate isolation dielectric layer; the intermediate isolation dielectric layer is used to isolate the front active structure and the back active structure; symmetrically distributed first signal lines and second signal lines are buried on both sides of the intermediate isolation dielectric layer; the extension direction of the first signal line and the second signal line is consistent with the extension direction of the intermediate isolation dielectric layer; wherein the first signal line is respectively connected to the first front gate structure and the first back source and drain metal in the first front transistor, and the second signal line is respectively connected to the first back gate structure and the first front source and drain metal in the first back transistor.

[0005] In some possible implementations, a first front transistor, a second front transistor, and a front back-end transistor form a front semiconductor structure; based on the front active structure, a first front transistor, a second front transistor, and a front back-end transistor are stacked in sequence along a first direction, including: performing source-drain epitaxial growth in a front source-drain region of the front semiconductor structure to form a first front source-drain structure of the first front transistor; forming a first front source-drain metal and a first front insulating isolation layer on the first front source-drain structure; the first front insulating isolation layer is used to isolate the first front transistor from the second front transistor in the front source-drain region; in the front source-drain region, the first front insulating isolation layer The method comprises the following steps: performing epitaxial growth of source and drain on the layer to form a second front source and drain structure of the second front transistor; depositing metal material in the front gate region of the front semiconductor structure to form a first front gate structure; depositing metal material in the front gate region and on the first front gate structure to form a second front gate structure of the second front transistor; forming a second front source and drain metal of the second front transistor and a second front insulating isolation layer on the second front source and drain structure; the second front insulating isolation layer is used to isolate the second front transistor from the front back-end transistor; forming a front back-end transistor on the second front insulating isolation layer; performing back-end processing on the front back-end transistor to form a front metal interconnection layer.

[0006] In some possible embodiments, a front back-end transistor is formed on the second front insulating isolation layer, including: depositing an insulating material on the second front insulating isolation layer to form a front channel dielectric layer; forming a third front source-drain structure and a third front gate structure on the front channel dielectric layer; forming a third source-drain metal and a front gate lead-out structure on the third front source-drain structure and the third front gate structure, respectively; the front gate lead-out structure is used to connect the third front gate structure and the front metal interconnection layer.

[0007] In some possible implementations, a first back side transistor, a second back side transistor, and a back side back-end transistor form a back side semiconductor structure; based on the back side active structure, a first back side transistor, a second back side transistor, and a back side back-end transistor are stacked in sequence along a first direction, including: performing source and drain epitaxial growth in a back side source and drain region of the back side semiconductor structure to form a first back side source and drain structure of the first back side transistor; forming a first back side source and drain metal and a first back side insulating isolation layer on the first back side source and drain structure; the first back side insulating isolation layer is used to isolate the first back side transistor from the second back side transistor in the back side source and drain region; in the back side source and drain region, the first back side insulating isolation layer is used to isolate the first back side transistor from the second back side transistor ... The method comprises the following steps: performing epitaxial growth of source and drain on the back layer to form a second back source and drain structure of a second back transistor; depositing metal material in the back gate region of the back semiconductor structure to form a first back gate structure; depositing metal material in the back gate region and on the first back gate structure to form a second back gate structure of the second back transistor; forming a second back source and drain metal of the second back transistor and a second back insulating isolation layer on the second back source and drain structure; the second back insulating isolation layer is used to isolate the second back transistor from the back back transistor; forming a back back transistor on the second back insulating isolation layer; performing a back back transistor process on the back back transistor to form a back metal interconnection layer.

[0008] In some possible embodiments, a back-end transistor is formed on the second back insulating isolation layer, including: depositing an insulating material on the second back insulating isolation layer to form a back channel dielectric layer; forming a third back source-drain structure and a third back gate structure on the back channel dielectric layer; forming a third source-drain metal and a back gate lead-out structure on the third back source-drain structure and the third back gate structure, respectively; the back gate lead-out structure is used to connect the third back gate structure and the back metal interconnection layer.

[0009] In some possible implementations, the first front transistor is a first type transistor; the second front transistor is a second type transistor; the first back transistor is a first type transistor; the second back transistor is a second type transistor; wherein the first type transistor and the second type transistor are complementary transistors

[0010] In some possible implementations, the first front transistor, the second front transistor, the first back transistor, and the second back transistor are any of the following: a fin field effect transistor, a surround gate field effect transistor.

[0011] In some possible implementations, the front-side back-end transistor and the back-side back-end transistor are any of the following: an oxide thin film transistor, a planar field effect transistor, a fin field effect transistor, and a surround gate field effect transistor.

[0012] In a second aspect, an embodiment of the present application provides a semiconductor structure, which is prepared by the method described in the first aspect, and the semiconductor structure is a static random access memory unit, and the semiconductor structure includes: a front semiconductor structure; the front semiconductor structure includes a first front transistor, a second front transistor, and a front back-end transistor stacked in a first direction; the first front source-drain metal in the first front transistor, the second front source-drain metal in the second front transistor, and the third front source-drain metal in the front back-end transistor are connected; a back semiconductor structure; the front semiconductor structure and the back semiconductor structure are stacked in the first direction; the back semiconductor structure includes a first back transistor, a second back transistor, and a back back transistor stacked in the first direction; the first The first back source and drain metal in the back transistor, the second back source and drain metal in the second back transistor and the third back source and drain metal in the back transistor are connected; wherein an intermediate isolation dielectric layer is arranged between the front active structure of the front semiconductor structure and the back active structure of the back semiconductor structure; the intermediate isolation dielectric layer is used to isolate the front active structure and the back active structure; symmetrically distributed first signal lines and second signal lines are arranged on both sides of the intermediate isolation dielectric layer; the extension direction of the first signal line and the second signal line is consistent with the extension direction of the intermediate isolation dielectric layer; the first signal line is respectively connected to the first front gate structure and the first back source and drain metal in the first front transistor, and the second signal line is respectively connected to the first back gate structure and the first front source and drain metal in the first back transistor.

[0013] In a third aspect, an embodiment of the present application provides a semiconductor device, which includes: a semiconductor structure as described in the above embodiment.

[0014] In a fourth aspect, an embodiment of the present application provides an electronic device, which includes: a circuit board and a semiconductor device as described in the above embodiment, wherein the semiconductor device is arranged on the circuit board.

[0015] In the present application, the semiconductor structure includes six transistors stacked in the first direction, namely, a back-end transistor, a second back-end transistor, a first back-end transistor, a first front-end transistor, a second front-end transistor, and a front-end back-end transistor. Inside the semiconductor structure, by introducing buried metal wiring technology, namely, a first signal line and a second signal line, and connecting the first front gate structure and the first back source-drain metal, respectively, and connecting the second signal line and the first back gate structure and the first front source-drain metal, respectively, the semiconductor structure realizes internal interconnection while the projection area in the vertical direction only occupies the area of ​​one transistor, which can greatly reduce the area of ​​the layout.

[0016] Furthermore, the reduction in layout area makes the semiconductor structure more integrated and saves manufacturing costs; and it can be used in the manufacturing process of the next generation of integrated circuits. It is a new SRAM design with great application potential.

[0017] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0019] Figure 1 A schematic diagram of an implementation process of a method for preparing a semiconductor structure in an embodiment of the present application;

[0020] Figure 2 A design layout of a semiconductor structure in an embodiment of the present application;

[0021] Figure 3 A schematic diagram of a semiconductor structure in an embodiment of the present application;

[0022] FIG. 4A to FIG. 4I A schematic diagram of a preparation process of a semiconductor structure in an embodiment of the present application

[0023] The above pictures:

[0024] 10. semiconductor structure; 11. front semiconductor structure; 111. first front transistor; 1111. first front source-drain structure; 1112. first front source-drain metal; 1113. first front interlayer dielectric layer; 1114. first front gate structure; 112. second front transistor; 1121. second front source-drain structure; 1122. second front source-drain metal; 1123. second front interlayer dielectric layer; 1124. second front gate structure; 113. front back-end transistor; 1131. third front source-drain structure; 1132. third front source-drain metal; 1134. third front 12. Back semiconductor structure; 121. First back transistor; 1211. First back source-drain structure; 1212. First back source-drain metal; 1213. First back interlayer dielectric layer; 1214. First back gate structure; 122. Second back transistor; 1221. Second back source-drain structure; 1222. Second back source-drain metal; 1223. Second back interlayer dielectric layer; 1224. Second back gate structure; 123. Back transistor; 1231. Third back source-drain structure; 1232. Third back source-drain metal; 1234. Third back gate structure structure; 13, insulating layer; 14, wafer carrier; 21, substrate; 211, bottom substrate; 212, first stack; 213, sacrificial layer; 214, second stack; 22, active structure; 221, front active structure; 222, back active structure; 23, shallow trench isolation structure; 231, shallow trench isolation layer; 241, first signal line; 242, second signal line; 251, front pseudo-gate structure; 26, first gap; 27, intermediate isolation dielectric layer; 281, front gap wall; 282, back gap wall; 291, front source and drain sidewall; 292, back source and drain sidewall; 311, front Surface source and drain protection layer; 321, first front insulating isolation layer; 322, first back insulating isolation layer; 331, front gate dielectric layer; 332, back gate dielectric layer; 341, second front insulating isolation layer; 342, second back insulating isolation layer; 351, front channel dielectric layer; 352, back channel dielectric layer; 361, front gate lead-out structure; 362, back gate lead-out structure; 371, front metal interconnection layer; 372, back metal interconnection layer; 381, front gate cut-off structure; 382, ​​back gate cut-off structure; 391, front isolation belt; 392, back isolation belt. DETAILED DESCRIPTION

[0025] Here, exemplary embodiments will be described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application.

[0026] As Moore's Law continues to deepen, after the technology node of gate-all-around FET (GAA), continuing to promote the miniaturization of transistor size is a hot issue in the current industry research and development. Stacked transistors can achieve the integration of two or more layers of transistors in a vertical space through three-dimensional transistor stacking, which helps to further improve the integration density of transistors and improve circuit performance. It is considered to be one of the important technologies for continuing the miniaturization of integrated circuit size.

[0027] In one embodiment, there are two schemes for manufacturing a stacked transistor, the first is a monolithic stacking scheme, and the second is a sequential scheme.

[0028] The first solution is to make N-channel field effect transistors (NFET) and P-channel field effect transistors (PFET) on the same substrate without using wafer bonding technology. This determines that the transistors on the same layer must be of the same type, namely NFET or PFET. In addition, the upper and lower layer transistors must be strictly in the same plane space without alignment deviation. The advantage of this solution is that it has a better integration density. The disadvantages of this solution include the following two points: (1) The process is complex and requires a lot of process technology development and optimization; (2) The polarity of each layer of transistors is fixed, and two layers of transistors must be relied on to form a basic complementary metal-oxide-semiconductor (CMOS) circuit, which has poor design flexibility.

[0029] The second solution is based on wafer bonding and layer-by-layer processing. Specifically, the upper transistor is prepared by bonding a wafer on top of the already fabricated lower transistor, and the two transistors are stacked vertically. However, this solution requires strict temperature control during the thermal process of processing the upper transistor to avoid affecting the lower transistor and interconnects. The advantage of this solution is that thanks to wafer bonding, the device structure, channel crystal orientation and even channel material used by the upper and lower transistors can be optimized accordingly to obtain better and more matched device performance. This solution currently has the following technical challenges: (1) Preparation of high-quality upper transistor active layer; (2) Thinning and defect control of the upper bonded wafer; (3) There is an alignment error between the upper and lower transistors, which requires extremely high lithography accuracy.

[0030] Static random-access memory (SRAM) helps improve the performance of computer systems and occupies a considerable chip area in many computing chips. Based on various new structures and new wiring ideas, researchers have proposed many high-density SRAMs with smaller bit cell areas and stronger driving capabilities, such as backside power delivery network (BSPDN) SRAM design and complementary field effect transistor (CFET) SRAM design. Among them, BSPDN connects the front source and drain to the bottom buried power rail through the backside via (BS-Via), which can release some front wiring resources and reduce the layout area; the 6T SRAM structure designed with vertical GAA CFET and CAA IGZO pass gate reduces the area by single-sided vertical stacking.

[0031] However, for complex standard cells such as SRAM, the above-mentioned design still requires a relatively large area for layout of more than two transistors and interconnection lines in a horizontal plane, which is not conducive to the scaling of the SRAM layout area.

[0032] In order to solve the above technical problems, an embodiment of the present application provides a method for preparing a semiconductor structure to reduce the layout area of ​​the semiconductor structure.

[0033] In the embodiment of the present application, the semiconductor structure is an SRAM cell, wherein the SRAM cell includes six transistors, namely a first front transistor, a second front transistor, a front back-end transistor, a first back transistor, a second back transistor, and a back back transistor.

[0034] In some embodiments, the semiconductor structure can be divided into two parts, namely, a front semiconductor structure and a back semiconductor structure. The front semiconductor structure includes a first front transistor, a second front transistor, and a front back-end transistor, and the back semiconductor structure includes a first back transistor, a second back transistor, and a back back transistor.

[0035] In some embodiments, the front semiconductor structure and the back semiconductor structure are stacked in a "back-to-back" arrangement. During the preparation process, the front semiconductor structure is prepared first, and then the prepared front semiconductor structure is flipped, and the back semiconductor structure is prepared on the flipped structure.

[0036] In some embodiments, in the front semiconductor structure, a first front transistor, a second front transistor, and a front back-end transistor are stacked. A first front source-drain metal in the first front transistor, a second front source-drain metal in the second front transistor, and a third front source-drain metal in the front back-end transistor are connected.

[0037] It can be understood that in the front semiconductor structure, the three stacked transistors (ie, the first front transistor, the second front transistor, and the front back-end transistor) are connected by source-drain metals to achieve source-drain interconnection between the three transistors.

[0038] In some embodiments, in the back semiconductor structure, a first back transistor, a second back transistor, and a back back transistor are stacked, and a first back source-drain metal in the first back transistor, a second back source-drain metal in the second back transistor, and a third back source-drain metal in the back back transistor are connected.

[0039] It can be understood that in the back semiconductor structure, the three stacked transistors (ie, the first back transistor, the second back transistor and the back-end transistor) are connected by source-drain metals to achieve source-drain interconnection between the three transistors.

[0040] In some embodiments, an intermediate isolation dielectric layer is disposed between the front active structure of the front semiconductor structure and the back active structure of the back semiconductor structure; the intermediate isolation dielectric layer is used to isolate the front active structure from the back active structure.

[0041] In some embodiments, a first signal line and a second signal line are symmetrically distributed on both sides of the intermediate isolation dielectric layer; the extension direction of the first signal line and the second signal line is consistent with the extension direction of the intermediate isolation dielectric layer; the first signal line is respectively connected to the first front gate structure and the first back source and drain metal in the first front transistor, and the second signal line is respectively connected to the first back gate structure and the first front source and drain metal in the first back transistor.

[0042] It can be understood that the surface of the first signal line closest to the front semiconductor structure is connected to the first front gate structure through a gate through hole, and the surface of the first signal line closest to the back semiconductor structure is connected to the first back source and drain metal through a source and drain through hole. The surface of the second signal line closest to the front semiconductor structure is connected to the first front source and drain metal through a source and drain through hole, and the surface of the second signal line closest to the back semiconductor structure is connected to the first back gate structure through a gate through hole. The first signal line and the second signal line realize electrical interconnection between the front semiconductor structure and the back semiconductor structure inside the semiconductor structure.

[0043] In some embodiments, the first front transistor, the second front transistor, the first back transistor, and the second back transistor may be any of the following: a fin field-effect transistor (FinFET), a gate-all-around field-effect transistor (GAAFET). It should be noted that the first front transistor, the second front transistor, the first back transistor, and the second back transistor may also be designed as other types of transistors according to actual needs, and the embodiments of the present application do not specifically limit this.

[0044] In some embodiments, the front back-end transistor and the back back-end transistor may be any of the following: an oxide thin film transistor (IGZO transistor), a planar metal-oxide-semiconductor field-effect transistor, a fin field effect transistor, and a surround gate field effect transistor. It should be noted that the front back-end transistor and the back back-end transistor may also be designed as other types of transistors according to actual needs, and the embodiments of the present application do not specifically limit this.

[0045] In some embodiments, the first front transistor is a first type transistor; the second front transistor is a second type transistor; the first back transistor is a first type transistor; the second back transistor is a second type transistor; wherein the first type transistor and the second type transistor are complementary transistors.

[0046] It can be understood that the first type transistor can be an N-type transistor or a P-type transistor, and the second type transistor can be a P-type transistor or an N-type transistor. In the front semiconductor structure, the first front transistor and the second front transistor are complementary transistors. In the back semiconductor structure, the first back transistor and the second back transistor are complementary transistors.

[0047] In some embodiments, the front-side back-end transistor and the back-side back-end transistor are N-type transistors.

[0048] In some embodiments, the transistor type in the front semiconductor structure may be different from the transistor type in the back semiconductor structure. For example, the first front transistor and the second front transistor may be surround-gate field-effect transistors, and the first back transistor and the second back transistor may be fin field-effect transistors. The implementation of this application does not specifically limit the transistor type in the front semiconductor structure and the transistor type in the back semiconductor structure.

[0049] Figure 3 The semiconductor structure consists of a surrounding gate field effect transistor and an oxide thin film transistor. Figure 3 The schematic diagram of the semiconductor structure shown illustrates the method for preparing the semiconductor structure provided in the embodiment of the present application.

[0050] Figure 1 FIG. 1 is a schematic diagram of an implementation process of a method for preparing a semiconductor structure in an embodiment of the present application. Figure 1 As shown, the method for preparing the semiconductor structure may include:

[0051] S101, forming an active structure on a substrate, wherein the active structure includes a front active structure, a sacrificial structure, and a back active structure stacked in sequence in a first direction.

[0052] In some embodiments, when the first front transistor, the second front transistor, the first back transistor, and the second back transistor are all-around gate field effect transistors, before S101, the preparation method may include: providing an original silicon (Si) substrate, and alternately stacking silicon germanium (SiGe) materials and Si materials on the original Si substrate to form a stack. The stack and the original Si substrate together constitute a substrate.

[0053] In some embodiments, in order to isolate the front semiconductor structure from the back semiconductor structure in subsequent preparation, a layer of semiconductor material can be stacked in the middle of the stack to form a sacrificial layer. In the process of preparing the semiconductor structure, the sacrificial layer can play a role in dividing the area occupied by the front semiconductor structure and the area occupied by the back semiconductor structure.

[0054] In some embodiments, the sacrificial layer may be formed of SiGe material, and in order to distinguish it from the SiGe material in the stack during the subsequent etching process, the sacrificial layer may be prepared using SiGe material with a higher Ge concentration. That is, the stack uses SiGe1 material, and the sacrificial layer uses SiGe2 material, and the Ge concentration of SiGe2 material is higher than that of SiGe1 material.

[0055] In some embodiments, the above S101 may include: patterning an active structure on a substrate, etching the substrate to form an active structure. The active structure located above the sacrificial layer is a front active structure, and the active structure located below the sacrificial layer is a back active structure.

[0056] In some embodiments, when the first front transistor, the second front transistor, the first back transistor and the second back transistor are fin field effect transistors, the substrate is a Si substrate and does not include a stack; and the active structure is a fin structure.

[0057] S102, based on the front active structure, sequentially forming a first front transistor, a second front transistor, and a front back-end transistor stacked in a first direction, wherein the first front source-drain metal in the first front transistor, the second front source-drain metal in the second front transistor, and the third front source-drain metal in the front back-end transistor are connected.

[0058] It can be understood that in the process of preparing the front semiconductor structure, the first front transistor, the second front transistor and the front back-end transistor are formed in sequence. The source-drain metal between the first front transistor, the second front transistor and the front back-end transistor realizes the source-drain interconnection of the front semiconductor structure through the source-drain via.

[0059] In some embodiments, the source-drain interconnection scheme between the first front transistor, the second front transistor and the front back-end transistor can be: the first front source-drain metal and the second front source-drain metal are connected via a source-drain through hole, and the second front source-drain metal and the third front source-drain metal are connected via a source-drain through hole. The source-drain through hole is made of metal material.

[0060] In some embodiments, the source-drain interconnection scheme between the first front transistor, the second front transistor and the front back-end transistor can be: the first front source-drain metal and the third front source-drain metal are connected via source-drain vias, and the second front source-drain metal and the third front source-drain metal are connected via source-drain vias.

[0061] In some embodiments, the source-drain interconnection scheme between the first front transistor, the second front transistor and the front back-end transistor can be: the first front source-drain metal and the third front source-drain metal are connected via source-drain vias, and the second front source-drain metal and the first front source-drain metal are connected via source-drain vias.

[0062] S103, performing a back-end process on the front back-end transistor to form a front metal interconnection layer.

[0063] It can be understood that the front metal interconnect layer in the front semiconductor structure can be formed by performing processes such as inter-interconnect dielectric deposition, metal line formation, and lead pad formation above the front back-end transistor. The metal lines in the front metal interconnect layer can be connected to the third front gate structure, the first front source and drain metal, the second front source and drain metal, and the third front source and drain metal.

[0064] S104, flipping the wafer and thinning the substrate until the back active structure is exposed.

[0065] It is understandable that after forming the front semiconductor structure, the front semiconductor structure can be flipped over so that the substrate is placed upwards. Then, the substrate is thinned until the back active structure is exposed.

[0066] In some embodiments, before the above S104, the above preparation method may further include: depositing an insulating material (such as silicon oxide) on the front semiconductor structure to form an insulating layer, and bonding the insulating layer to the carrier wafer.

[0067] In the embodiment of the present application, the bonded carrier wafer can provide physical support for the flipped front semiconductor structure after inversion, thereby effectively preventing the front semiconductor structure from being broken by external force during the preparation of the back semiconductor structure.

[0068] S105, based on the back active structure, sequentially forming a first back transistor, a second back transistor, and a back back transistor in a stacked arrangement along a first direction, wherein the first back source and drain metal in the first back transistor, the second back source and drain metal in the second back transistor, and the third back source and drain metal in the back back transistor are connected.

[0069] It can be understood that, in the process of preparing the back semiconductor structure, the first back transistor, the second back transistor and the back back transistor are formed in sequence, which is the same as the process flow of preparing the front semiconductor structure. The source-drain metal between the first back transistor, the second back transistor and the back back transistor realizes the source-drain interconnection of the back semiconductor structure through the source-drain through-hole.

[0070] In some embodiments, the source-drain interconnection scheme between the first back-side transistor, the second back-side transistor and the back-side back-end transistor may be: the first back-side source-drain metal and the second back-side source-drain metal are connected via a source-drain through hole, and the second back-side source-drain metal and the third back-side source-drain metal are connected via a source-drain through hole. The source-drain through hole is made of metal material.

[0071] In some embodiments, the source-drain interconnection scheme between the first back side transistor, the second back side transistor and the back side back-end transistor can be: the first back side source-drain metal and the third back side source-drain metal are connected through source-drain through holes, and the second back side source-drain metal and the third back side source-drain metal are connected through source-drain through holes.

[0072] In some embodiments, the source-drain interconnection scheme between the first back side transistor, the second back side transistor and the back side back-end transistor can be: the first back side source-drain metal is connected to the third back side source-drain metal via a source-drain via, and the second back side source-drain metal is connected to the first back side source-drain metal via a source-drain via.

[0073] S106, performing a back-end process on the back-end transistor to form a back-end metal interconnection layer.

[0074] It can be understood that the back metal interconnect layer in the back semiconductor structure can be formed by performing processes such as inter-interconnect dielectric deposition, metal line formation, and lead pad formation above the back-end transistor. The metal lines in the back metal interconnect layer can be connected to the third back gate structure, the first back source and drain metal, the second back source and drain metal, and the third back source and drain metal.

[0075] In some possible embodiments, the above S102 may include: performing source-drain epitaxial growth in the front source-drain region of the front semiconductor structure to form a first front source-drain structure of the first front transistor; forming a first front source-drain metal and a first front insulating isolation layer on the first front source-drain structure; the first front insulating isolation layer is used to isolate the first front transistor and the second front transistor in the front source-drain region; performing source-drain epitaxial growth in the front source-drain region and on the first front insulating isolation layer to form a second front source-drain structure of the second front transistor; depositing metal material in the front gate region of the front semiconductor structure to form a first front gate structure; depositing metal material in the front gate region and on the first front gate structure to form a second front gate structure of the second front transistor; forming a second front source-drain metal and a second front insulating isolation layer of the second front transistor on the second front source-drain structure; the second front insulating isolation layer is used to isolate the second front transistor from the front back-end transistor; forming a front back-end transistor on the second front insulating isolation layer; performing a back-end process on the front back-end transistor to form a front metal interconnection layer.

[0076] It can be understood that the first front source-drain structure and the second front source-drain structure are sequentially formed in the front source-drain region of the front semiconductor structure, and the space where the front source-drain region is located can be exposed by etching the front active structure. The first front gate structure and the second front gate structure are sequentially formed in the front gate region of the front semiconductor structure, and the front gate region is opened by photolithography.

[0077] It should be noted that, for ease of explanation, the first front source-drain structure mentioned in the embodiments of the present application is an abbreviation, specifically referring to the first front source electrode structure and / or the first front drain electrode structure. In addition, the second front source-drain structure, the third front source-drain metal, the first back source-drain structure, etc. are similar to the first front source-drain structure, where "source-drain" is an abbreviation for "source and / or drain".

[0078] In some embodiments, after the front gate region is opened by photolithography, an insulating material (such as polysilicon (poly Si)) is first filled in the front gate region to form a front dummy gate structure; then, the front dummy gate structure is removed by selective etching to expose the front gate region, and different metal materials are sequentially deposited in the front gate region to form a first front gate structure and a second front gate structure.

[0079] In some possible embodiments, the above-mentioned formation of a front-side back-end transistor on the second front-side insulating isolation layer may include: depositing an insulating material on the second front-side insulating isolation layer to form a front-side channel dielectric layer; forming a third front-side source-drain structure and a third front-side gate structure on the front-side channel dielectric layer; forming a third source-drain metal and a front-side gate lead-out structure on the third front-side source-drain structure and the third front-side gate structure, respectively; the front-side gate lead-out structure is used to connect the third front-side gate structure and the front-side metal interconnection layer.

[0080] It can be understood that the front back-end transistor is not formed based on the front active structure like the first front transistor and the second front transistor, and the front back-end transistor is formed by stacking a multilayer structure above the second front transistor. The front back-end transistor and the second front transistor are isolated by a front channel dielectric layer.

[0081] In some possible embodiments, the above S105 may include: performing source-drain epitaxial growth in the back source-drain region of the back semiconductor structure to form a first back source-drain structure of the first back transistor; forming a first back source-drain metal and a first back insulating isolation layer on the first back source-drain structure; the first back insulating isolation layer is used to isolate the first back transistor and the second back transistor in the back source-drain region; performing source-drain epitaxial growth in the back source-drain region and on the first back insulating isolation layer to form a second back source-drain structure of the second back transistor; depositing metal material in the back gate region of the back semiconductor structure to form a first back gate structure; depositing metal material in the back gate region and on the first back gate structure to form a second back gate structure of the second back transistor; forming a second back source-drain metal and a second back insulating isolation layer of the second back transistor on the second back source-drain structure; the second back insulating isolation layer is used to isolate the second back transistor from the back back transistor; forming a back back transistor on the second back insulating isolation layer; performing a back process on the back back transistor to form a back metal interconnection layer.

[0082] It can be understood that the first back source and drain structure and the second back source and drain structure are sequentially formed in the back source and drain region of the back semiconductor structure, and the space where the back source and drain region is located can be exposed by etching the back active structure. The first back gate structure and the second back gate structure are sequentially formed in the back gate region of the back semiconductor structure, and the back gate region is opened by photolithography.

[0083] In some embodiments, after the back gate region is opened by photolithography, an insulating material (such as polysilicon) is first filled in the back gate region to form a back dummy gate structure; then, the back dummy gate structure is removed by selective etching to expose the back gate region, and different metal materials are sequentially deposited in the back gate region to form a first back gate structure and a second back gate structure.

[0084] In some possible embodiments, the above-mentioned formation of a back-end transistor on the second back insulating isolation layer may include: depositing an insulating material on the second back insulating isolation layer to form a back channel dielectric layer; forming a third back source and drain structure and a third back gate structure on the back channel dielectric layer; forming a third source and drain metal and a back gate lead-out structure on the third back source and drain structure and the third back gate structure, respectively; the back gate lead-out structure is used to connect the third back gate structure and the back metal interconnection layer.

[0085] It can be understood that the back side back-end transistor is not formed based on the back side active structure like the first back side transistor and the second back side transistor, and the back side back-end transistor is formed by stacking a multi-layer structure above the second back side transistor. The back side back-end transistor and the second back side transistor are isolated by a back side channel dielectric layer.

[0086] In some embodiments, the front semiconductor structure and the back semiconductor structure in the semiconductor structure can be prepared by a monolithic stacking scheme or a sequential scheme, and the embodiments of the present application do not specifically limit this.

[0087] Below, the semiconductor structure provided in the embodiment of the present application is described by taking the first front transistor, the second front transistor, the first back transistor and the second back transistor as fin field effect transistors, and the front back-end transistor and the back back-end transistor as oxide thin film transistors as an example. Figure 2 is a design layout of a semiconductor structure in an embodiment of the present application, wherein: Figure 2 (a) is a design layout of transistors (i.e., a first front transistor, a second front transistor, a first back transistor, and a second back transistor) in the semiconductor structure; Figure 2 (b) is a design layout of a front metal interconnection layer in a semiconductor structure; Figure 2 (c) is the design layout of the back metal interconnection layer in the semiconductor structure. Figure 3 is a schematic diagram of a semiconductor structure in an embodiment of the present application, Figure 3 (a) is a cross-sectional view of the semiconductor structure along the AA' direction in the design layout; Figure 3 (b) is a cross-sectional view of the semiconductor structure along the BB' direction in the design layout; Figure 3(c) is a cross-sectional view of the semiconductor structure along the CC' direction in the design layout; Figure 3 (d) is a cross-sectional view of the semiconductor structure along the DD' direction in the design layout.

[0088] In some embodiments, see Figure 2 As shown in the figure, the dotted box area represents an SRAM cell, and the first metal interconnect layer (M0) and the second metal interconnect layer (M1) are arranged in layers. The drain voltage (voltage at drain to drain, VDD) structure and the source voltage (voltage at the source to source, VSS) structure are symmetrically arranged. The positions of the word line (wordline, WL), bit line (bit line, BL) and base-to-emitter voltage (base-to-emitter voltage, BLB) structures are shown in the figure.

[0089] In combination with the above preparation method, Figure 3 The preparation process of the semiconductor structure 10 is described below. Figure 3 The semiconductor structure 10 shown may be FIG. 4A to FIG. 4I The process shown is prepared FIG. 4A to FIG. 4I It is a schematic diagram of a preparation process of a semiconductor structure in an embodiment of the present application.

[0090] Step 1: Provide a substrate 21. The substrate 21 includes a bottom substrate 211, a first stack 212, a sacrificial layer 213, and a second stack 214 (see Figure 4A (a) in the figure). The first stack 212 and the second stack 214 are both formed by sequentially stacking Si material and SiGe1 material, and the sacrificial layer 213 is made of SiGe2 material.

[0091] in, Figure 4A The structures of the AA' section diagram, BB' section diagram and CC' section diagram are the same, and only one structure diagram is shown as an example.

[0092] Step 2: Etching the substrate 21 to form an active structure 22. The active structure 22 includes a front active structure 221 and a back active structure 222. The etched sacrificial layer 213 is located between the front active structure 221 and the back active structure 222 (see FIG. Figure 4A (b) in the figure.

[0093] Step 3: Deposit insulating material on the bottom substrate 211 and the active structure 22 to form a shallow trench isolation structure 23. The shallow trench isolation structure 23 wraps the active structure 22 and covers the bottom substrate 211; at this time, the height of the shallow trench isolation structure 23 in the horizontal direction is greater than the height of the active structure 22. Then, a portion of the shallow trench isolation structure 23 is removed by etching until the front active structure 221 is exposed; at this time, the sacrificial layer 213 and the back active structure 222 are still wrapped by the shallow trench isolation structure 23 (see Figure 4A (b) in the figure.

[0094] In some embodiments, after forming the shallow trench isolation structure 23, a chemical-mechanical planarization (CMP) process may be performed on the shallow trench isolation structure 23, so that when the shallow trench isolation structure 23 is subsequently etched, the etching depths corresponding to the shallow trench isolation structure 23 in different regions are the same, so that the heights of the exposed active structures are the same.

[0095] Step 4: In the shallow trench isolation structure 23, the first signal line 241 and the second signal line 242 are buried on both sides of the sacrificial layer 213 (see Figure 4B (a) in the figure). The first signal line 241 and the second signal line 242 are made of metal material.

[0096] In some embodiments, the method for preparing the first signal line 241 and the second signal line 242 includes: coating a photoresist on the shallow trench isolation structure 23 to form a photoresist plate having a preset photolithography pattern; etching the shallow trench isolation structure 23 under the mask of the photoresist plate to form two grooves, wherein the two grooves are located on both sides of the sacrificial layer 213, and the extension direction of the grooves is consistent with the extension direction of the active structure (i.e., the DD' direction); removing the photoresist plate, and depositing a metal material of a preset height in the grooves to form the first signal line 241 and the second signal line 242; and depositing insulating material above the first signal line 241 and the second signal line 242 until the two grooves are filled.

[0097] It should be noted that the first signal line 241 and the second signal line 242 can be formed in the process of preparing the front semiconductor structure 11, or in the process of preparing the back semiconductor structure 12. The above-mentioned formation of the first signal line 241 and the second signal line 242 in the process of preparing the front semiconductor structure 11 is only one example, and does not limit the timing of preparing the first signal line 241 and the second signal line 242 in the embodiment of the present application.

[0098] Step 5: Photolithography opens the front gate region, and polysilicon is deposited in the front gate region to form a front pseudo gate structure 251 (see Figure 4B (b) in the figure.

[0099] Step 6: Etch down the shallow trench isolation structure 23 to a preset height until a portion of the sacrificial layer 213 is exposed (see Figure 4B (c) in FIG. 1 ). It should be noted that, during the etching process, it is necessary to ensure that the first signal line 241 and the second signal line 242 are not exposed.

[0100] It should be noted that in Figure 4B In (b) and (c), the structures of the BB' section view and the CC' section view are the same, and only one structure view is shown as an example.

[0101] Step 7: Remove the sacrificial layer 213 to form the first gap 26 (see Figure 4C (a) in the figure.

[0102] Step 8: Deposit an insulating material (such as a low K material) in the first gap 26 to form an intermediate isolation dielectric layer 27; at the same time, form a front side spacer 281 on both sides of the front pseudo gate structure 251 (see Figure 4C (b) in the figure.

[0103] It should be noted that the intermediate isolation dielectric layer 27 and the front spacer 281 can be formed in the same deposition process. In the process of forming the intermediate isolation dielectric layer 27 and the front spacer 281, an insulating material is first deposited in the first gap 26 and on the shallow trench isolation structure 23, the front active structure 221 and the front dummy gate structure 251; then, the insulating material located on the shallow trench isolation structure 23 and the front active structure 221 and the upper surface of the front dummy gate structure 251 is removed, and the insulating material that is not removed forms the intermediate isolation dielectric layer 27 and the front spacer 281.

[0104] It should be noted that the intermediate isolation dielectric layer 27 can be formed in the process of preparing the front semiconductor structure 11, or in the process of preparing the back semiconductor structure 12. The above-mentioned formation of the intermediate isolation dielectric layer 27 in the process of preparing the front semiconductor structure 11 is only one example, and does not limit the timing of preparing the intermediate isolation dielectric layer 27 in the embodiment of the present application.

[0105] Step 9: Etch a portion of the front active structure 221 to form a front source and drain region; fill the sidewalls of the front source and drain region with an insulating material (such as silicon nitride (SiN)) to form a front source and drain sidewall 291 (see Figure 4C (c) in the figure.

[0106] Step 10: On the sidewalls of the front source / drain sidewall 291 and the front spacer 281, a layer of insulating material is isotropically deposited to form a front source / drain protection layer 311 (see Figure 4D(a) in FIG. 3 ). The front source-drain protection layer 311 can protect the front active structure 221 during the process of growing the source-drain epitaxy.

[0107] Step 11: Continue to etch downward a portion of the front active structure 221 to increase the height of the front source and drain region, and stop etching at the Si layer above the intermediate isolation dielectric layer 27; fill the sidewalls of the newly formed front source and drain region with insulating material (such as silicon nitride) to form new front source and drain sidewalls 291 (see Figure 4D (b) in the figure.

[0108] It should be noted that the Si layer located on the upper surface and the lower surface of the intermediate isolation dielectric layer 27 plays a role in protecting the intermediate isolation dielectric layer 27 during the etching process, but does not limit the specific structure of the first stack 212 and the second stack 214 in the embodiment of the present application. The embodiment of the present application may also not set the Si layer on the upper surface and the lower surface of the intermediate isolation dielectric layer 27, that is, the upper surface and the lower surface of the intermediate isolation dielectric layer 27 are both made of SiGe1 material.

[0109] Step 12: Grow source and drain epitaxy in the front source and drain region to form a first front source and drain structure 1111 in the first front transistor 111 (see Figure 4D (c) in the figure). The first front source-drain structure 1111 is a P-type source-drain structure.

[0110] Step 13: Remove the front source and drain protection layer 311 by selective etching (see Figure 4E (a) in the figure.

[0111] Step 14: Form a first front source-drain metal 1112 on the first front source-drain structure 1111, and connect the first front source-drain metal 1112 to the second signal line 242 through the first source-drain through hole; and deposit an interlayer dielectric in the corresponding front source-drain region of the first front transistor 111 to form a first front interlayer dielectric layer 1113 (see Figure 4E (b) in the figure.

[0112] It should be noted that the source and drain metals may be formed before or after the gate structure is formed, and this embodiment of the present application does not specifically limit this.

[0113] Step 15: Deposit an insulating material in the front source / drain region and on the first front source / drain metal 1112 to form a first front insulating isolation layer 321 (see Figure 4E (c) in the figure). The first front insulating isolation layer 321 is used to isolate the first front transistor 111 and the second front transistor 112 in the front source and drain region.

[0114] Step 16: Grow source and drain epitaxy in the front source and drain region and on the first front insulating isolation layer 321 to form a second front source and drain structure 1121 in the second front transistor 112 (see Figure 4F (a) in FIG. 1 ). The second front source-drain structure 1121 is an N-type source-drain structure.

[0115] Step 17: deposit an interlayer dielectric in the front source and drain region corresponding to the second front transistor 112 to form a second front interlayer dielectric layer 1123; remove the front pseudo gate structure 251 to expose the front gate region, deposit a layer of insulating material to form a front gate dielectric layer 331; deposit a metal material in the front gate region corresponding to the first front transistor 111 to form a first front gate structure 1114; deposit a metal material on the first front gate structure 1114 and in the front gate region corresponding to the second front transistor 112 to form a second front gate structure 1124 (see Figure 4F (b) in FIG. 1 ). The first front gate structure 1114 is connected to the first signal line 241 through a first gate through hole.

[0116] Step 18: Form a second front source-drain metal 1122 on the second front source-drain structure 1121; deposit an insulating material on the second front gate structure 1124 and on both sides of the second front source-drain metal 1122 to form a second front insulating isolation layer 341 (see Figure 4F (c) in which the second front source-drain metal 1122 is connected to the first front source-drain metal 1112 through the second source-drain through hole.

[0117] Step 19: Deposit an insulating material on the second front insulating isolation layer 341 to form a front channel dielectric layer 351; form a third front source-drain structure 1131 and a third front gate structure 1134 of the front back-end transistor 113 on the front channel dielectric layer 351 (see Figure 4G (a) in the figure.

[0118] Step 20: Form a third front source-drain metal 1132 on the third front source-drain structure 1131; and form a front gate lead-out structure 361 on the third front gate structure 1134 (see Figure 4G (b) in the figure). The third front source-drain metal 1132 is connected to the second front source-drain metal 1122 through the third source-drain through hole.

[0119] Step 21: Perform a back-end process on the third front source-drain metal 1132 and the front gate lead-out structure 361 to form a front metal interconnection layer 371 (see Figure 4G(c) in which the metal wires in the front metal interconnect layer 371 are respectively connected to the first front source-drain metal 1112 , the second front source-drain metal 1122 , the third front source-drain metal 1132 and the front gate lead-out structure 361 .

[0120] Step 22: Deposit insulating material on the front metal interconnect layer 371 to form an insulating layer 13; bond the insulating layer 13 to the carrier wafer 14; then, flip the front semiconductor structure 11 so that the bottom substrate 211 is placed upward (see Figure 4H (a) in the figure.

[0121] Step 23: Thin the bottom substrate 211 until the surface of the shallow trench isolation structure 23 and the back active structure 222 away from the front active structure 221 is exposed (see Figure 4H (b) in the figure.

[0122] Step 24: Thin the shallow trench isolation structure 23 and the back active structure 222 by CMP treatment, and stop the CMP to the SiGe1 layer closest to the bottom substrate 211 (see Figure 4H (c) in the figure.

[0123] Step 25: Continue to thin the shallow trench isolation structure 23 and the backside active structure 222 through CMP treatment, and stop CMP to the Si layer closest to the SiGe1 layer in the above step 24 (see Fig. 4I (a) in the figure.

[0124] Step 26: Etch the shallow trench isolation structure 23 of a preset height, and stop etching until the back active structure 222 is exposed. The shallow trench isolation structure 23 located around the middle isolation dielectric layer 27 is not etched, and the retained shallow trench isolation structure 23 is the shallow trench isolation layer 231 (see Fig. 4I (b) in the figure.

[0125] Step 27: Prepare the back semiconductor structure 12 according to the method for preparing the front semiconductor structure 11. Perform gate cutting treatment on the first front gate structure 1114, the second front gate structure 1124, the first back gate structure 1214 and the second back gate structure 1224 in the semiconductor structure 10 to form a front gate cutting structure 381 and a back gate cutting structure 382; and remove the first front gate structure 1114, the second front gate structure 1124, the first back gate structure 1214 and the second back gate structure 1224 located on both sides of the source and drain structure to form a first groove, and fill the first groove with insulating material to form a front isolation zone (single fusion break, SDB) 391 and a back isolation zone 392 (see Fig. 4I (c) in the figure.

[0126] Among them, the back semiconductor structure 12 includes: a first back transistor 121, a second back transistor 122, a back back-end transistor 123, a back spacer 282, a back source and drain sidewall 292, a first back source and drain structure 1211, a first back source and drain metal 1212, a first back interlayer dielectric layer 1213, a first back insulating isolation layer 322, a second back source and drain structure 1221, a second back source and drain metal 1222, a second back interlayer dielectric layer 1223, a back gate dielectric layer 332, a first back gate structure 1214, a second back gate structure 1224, a second back insulating isolation layer 342, a back channel dielectric layer 352, a third back source and drain structure 1231, a third back source and drain metal 1232, a third back gate structure 1234, a back gate lead-out structure 362, and a back metal interconnection layer 372. The first back side source-drain structure 1211 is a P-type source-drain structure; the second back side source-drain structure 1221 is an N-type source-drain structure; the first back side source-drain metal 1212 is connected to the first signal line 241 through the fourth source-drain through-hole; the second back side source-drain metal 1222 is connected to the first back side source-drain metal 1212 through the fifth source-drain through-hole; the third back side source-drain metal 1232 is connected to the second back side source-drain metal 1222 through the sixth source-drain through-hole; the metal wires in the back side metal interconnection layer 372 are respectively connected to the first back side source-drain metal 1212, the second back side source-drain metal 1222, the third back side source-drain metal 1232 and the back side gate lead-out structure 362; the first back side gate structure 1214 is connected to the second signal line 242 through the second gate through-hole.

[0127] At this point, the semiconductor structure 10 is completed.

[0128] In an embodiment of the present application, the semiconductor structure includes six transistors stacked in the first direction, namely, a back-end transistor, a second back-end transistor, a first back-end transistor, a first front-end transistor, a second front-end transistor, and a front-end transistor. Inside the semiconductor structure, by introducing buried metal wiring technology, namely, a first signal line and a second signal line, and connecting the first front gate structure and the first back source-drain metal, respectively, and connecting the second signal line and the first back gate structure and the first front source-drain metal, respectively, the semiconductor structure realizes internal interconnection while the projection area in the vertical direction only occupies the area of ​​one transistor, which can greatly reduce the area of ​​the layout.

[0129] Furthermore, the reduction in layout area makes the semiconductor structure more integrated and saves manufacturing costs; and it can be used in the manufacturing process of the next generation of integrated circuits. It is a new SRAM design with great application potential.

[0130] Furthermore, the semiconductor structure provided in the embodiment of the present application can be detected using a detection and analysis instrument, such as a scanning electron microscope (SEM), a transmission electron microscope (TEM), a scanning transmission electron microscope (STEM), etc. Taking TEM as an example, the semiconductor structure provided in the embodiment of the present application can be detected by TEM slicing. For example, it can be observed that there are a first signal line and a second signal line in the semiconductor structure, and the first signal line is respectively connected to the first front gate structure and the first back source and drain metal, and the second signal line is respectively connected to the first back gate structure and the first front source and drain metal; it can also be observed that an intermediate isolation dielectric layer is set in the middle position of the semiconductor structure to achieve isolation between the front semiconductor structure and the back semiconductor structure.

[0131] The present application embodiment provides a semiconductor device, including: a semiconductor structure as described in the above embodiment. The specific definition of the semiconductor structure can be found in the above Figure 3 The semiconductor structure shown will not be described in detail here.

[0132] The present application embodiment provides an electronic device, including: a circuit board and a semiconductor device as described in the above embodiment, wherein the semiconductor device is arranged on the circuit board. The semiconductor device includes the above semiconductor structure. The specific definition of the semiconductor structure can be found in the above Figure 3 , I will not go into details here.

[0133] In the description of the present application, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the embodiments of the present application. In the present application, the schematic representation of the above terms is not necessarily for the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine different embodiments or examples described in the present application and the features of different embodiments or examples without contradiction.

[0134] The above are only preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for preparing a semiconductor structure, characterized in that: The semiconductor structure is a static random access memory (SRAM) cell, and the method comprises: An active structure is formed on a substrate; the active structure comprises a front active structure, a sacrificial structure, and a back active structure stacked in sequence in a first direction; Based on the front active structure, a first front transistor, a second front transistor and a front back-end transistor are stacked in sequence along the first direction; a first front source-drain metal in the first front transistor, a second front source-drain metal in the second front transistor and a third front source-drain metal in the front back-end transistor are connected; Performing a back-end process on the front back-end transistor to form a front metal interconnection layer; Flipping and thinning the substrate until the back active structure is exposed; Based on the back active structure, a first back transistor, a second back transistor and a back back transistor are stacked in sequence along the first direction; a first back source-drain metal in the first back transistor, a second back source-drain metal in the second back transistor and a third back source-drain metal in the back back transistor are connected; Performing a back-end process on the back-end transistor to form a back-end metal interconnection layer; The method further comprises: removing the sacrificial structure to form a first gap, and filling the first gap with an insulating material to form an intermediate isolation dielectric layer; the intermediate isolation dielectric layer is used to isolate the front active structure and the back active structure; burying symmetrically distributed first signal lines and second signal lines on both sides of the intermediate isolation dielectric layer; the extension direction of the first signal line and the second signal line is consistent with the extension direction of the intermediate isolation dielectric layer; Among them, the first signal line is respectively connected to the first front gate structure and the first back source and drain metal in the first front transistor, and the second signal line is respectively connected to the first back gate structure and the first front source and drain metal in the first back transistor.

2. The method according to claim 1, characterized in that The first front side transistor, the second front side transistor and the front side back-end transistor form a front side semiconductor structure; Based on the front active structure, a first front transistor, a second front transistor and a front back-end transistor are sequentially formed in a stacked arrangement along the first direction, including: Performing source and drain epitaxial growth in a front source and drain region of the front semiconductor structure to form a first front source and drain structure of the first front transistor; forming the first front source-drain metal and the first front insulating isolation layer on the first front source-drain structure; the first front insulating isolation layer is used to isolate the first front transistor and the second front transistor in the front source-drain region; performing source and drain epitaxial growth in the front source and drain region and on the first front insulating isolation layer to form a second front source and drain structure of the second front transistor; Depositing a metal material in a front gate region of the front semiconductor structure to form the first front gate structure; depositing a metal material in the front gate region and on the first front gate structure to form a second front gate structure of the second front transistor; A second front source-drain metal and a second front insulating isolation layer of a second front transistor are formed on the second front source-drain structure; the second front insulating isolation layer is used to isolate the second front transistor from the front back-end transistor; forming a front-side back-end transistor on the second front-side insulating isolation layer; A back-end process is performed on the front-side back-end transistor to form a front-side metal interconnection layer.

3. The method according to claim 2, characterized in that The forming of a front-side back-end transistor on the second front-side insulating isolation layer comprises: Depositing an insulating material on the second front insulating isolation layer to form a front channel dielectric layer; forming a third front source-drain structure and a third front gate structure on the front channel dielectric layer; A third source-drain metal and a front gate lead-out structure are formed on the third front source-drain structure and the third front gate structure, respectively; the front gate lead-out structure is used to connect the third front gate structure and the front metal interconnection layer.

4. The method according to claim 1, characterized in that: The first back side transistor, the second back side transistor and the back side back-end transistor form a back side semiconductor structure; Based on the back active structure, a first back transistor, a second back transistor and a back-end transistor are sequentially formed in a stacked arrangement along the first direction, including: performing source and drain epitaxial growth in a back source and drain region of the back semiconductor structure to form a first back source and drain structure of the first back transistor; forming the first back side source / drain metal and the first back side insulating isolation layer on the first back side source / drain structure; the first back side insulating isolation layer is used to isolate the first back side transistor and the second back side transistor in the back side source / drain region; performing source-drain epitaxial growth in the back source-drain region and on the first back insulating isolation layer to form a second back source-drain structure of the second back transistor; depositing a metal material in a back gate region of the back semiconductor structure to form the first back gate structure; depositing a metal material in the back gate region and on the first back gate structure to form a second back gate structure of the second back transistor; Forming a second back side source / drain metal and a second back side insulating isolation layer of a second back side transistor on the second back side source / drain structure; the second back side insulating isolation layer is used to isolate the second back side transistor from the back side back-end transistor; forming a back-end transistor on the second back-end insulating isolation layer; A back-end process is performed on the back-end transistor to form a back-end metal interconnection layer.

5. The method according to claim 4, characterized in that The forming of a back-end transistor on the second back-end insulating isolation layer comprises: Depositing an insulating material on the second back insulating isolation layer to form a back channel dielectric layer; forming a third back source-drain structure and a third back gate structure on the back channel dielectric layer; A third source-drain metal and a back gate lead-out structure are formed on the third back source-drain structure and the third back gate structure, respectively; the back gate lead-out structure is used to connect the third back gate structure and the back metal interconnection layer.

6. The method according to claim 1, characterized in that The first front transistor is a first type transistor; the second front transistor is a second type transistor; the first back transistor is a first type transistor; the second back transistor is a second type transistor; The first type transistor and the second type transistor are complementary transistors.

7. The method according to claim 1, characterized in that The first front side transistor, the second front side transistor, the first back side transistor and the second back side transistor are any one of the following: a fin field effect transistor and a surround gate field effect transistor.

8. The method according to claim 1, characterized in that The front back-end transistor and the back back-end transistor are any one of the following: an oxide thin film transistor, a planar field effect transistor, a fin field effect transistor, and a surround gate field effect transistor.

9. A semiconductor structure, characterized in that: The semiconductor structure is prepared by the method according to any one of claims 1 to 8, the semiconductor structure is a static random access memory SRAM unit, and the semiconductor structure comprises: A front semiconductor structure; the front semiconductor structure comprises a first front transistor, a second front transistor and a front back-end transistor stacked in a first direction; a first front source-drain metal in the first front transistor, a second front source-drain metal in the second front transistor and a third front source-drain metal in the front back-end transistor are connected; A back semiconductor structure; the front semiconductor structure and the back semiconductor structure are stacked in the first direction; the back semiconductor structure comprises a first back transistor, a second back transistor and a back back transistor stacked in the first direction; a first back source-drain metal in the first back transistor, a second back source-drain metal in the second back transistor and a third back source-drain metal in the back back transistor are connected; Among them, an intermediate isolation dielectric layer is arranged between the front active structure of the front semiconductor structure and the back active structure of the back semiconductor structure; the intermediate isolation dielectric layer is used to isolate the front active structure from the back active structure; symmetrically distributed first signal lines and second signal lines are arranged on both sides of the intermediate isolation dielectric layer; the extension direction of the first signal line and the second signal line is consistent with the extension direction of the intermediate isolation dielectric layer; the first signal line is respectively connected to the first front gate structure and the first back source and drain metal in the first front transistor, and the second signal line is respectively connected to the first back gate structure and the first front source and drain metal in the first back transistor.

10. A semiconductor device, characterized in that: include: The semiconductor structure as claimed in claim 9.

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