Semiconductor device having capacitor array and method of forming same

Abstract

A method of forming a semiconductor device having a capacitor array includes forming a top electrode plate of the capacitor array in an active region and a peripheral region of a substrate, depositing a first oxide layer over the top electrode plate in the active region and the peripheral region, removing the top electrode plate in the peripheral region, and forming a second oxide layer over the first oxide layer. Forming a nitride film on the first oxide layer in the active region and the peripheral region; depositing a second oxide layer on the nitride film in the active region and the peripheral region; and grinding the second oxide layer to expose the nitride film in the active region. Such a semiconductor device has a uniform interface beneficial to structures formed thereon in the next process due to the improvement of the chemical mechanical polishing process.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device having a capacitor array and a method for forming the semiconductor device having a capacitor array. Background Art

[0002] In the process of forming capacitor arrays, thick oxides need to be removed by chemical mechanical processes. However, the thickness of the oxide can reach more than 10,000 angstroms. Generally speaking, the range of loss increases with the amount removed, so the range of loss can reach 1,000 angstroms. Therefore, the uniformity of the CMP process is poor, and in addition, endpoint detection cannot be used. Therefore, the average standard deviation is poor. Summary of the invention

[0003] The present disclosure provides a method of forming a semiconductor device having a capacitor array.

[0004] In one embodiment, the method includes forming a top electrode plate of a capacitor array in an active area and a peripheral area of ​​a substrate, depositing a first oxide layer above the top electrode plate in the active area and in the peripheral area, removing the top electrode plate in the peripheral area, forming a nitride film on the first oxide layer in the active area and in the peripheral area, depositing a second oxide layer on the nitride film in the active area and in the peripheral area, and grinding the second oxide layer to expose the nitride film in the active area.

[0005] In one embodiment, forming a top electrode plate of a capacitor array in the active area and the peripheral area further includes forming a titanium nitride (TiN) layer on the bottom electrode plate and the capacitor dielectric layer in the active area and the peripheral area and forming a polymer layer on the titanium nitride (TiN) layer in the active area and the peripheral area.

[0006] In one embodiment, the first oxide layer includes a first portion extending laterally, a second portion extending longitudinally, and a third portion extending laterally, the first portion and the second portion are located in an active area, the third portion is located in a peripheral area, and the method for forming a capacitor array includes forming a hard mask covering the first portion and the second portion of the first oxide layer in the active area before removing the top electrode plate in the peripheral area.

[0007] In one embodiment, a method for forming a semiconductor device having a capacitor array further includes forming a contact that passes through a first portion of an oxide layer and a nitride film and contacts a top electrode plate, wherein depositing a first oxide layer over the top electrode plate in an active region and a peripheral region further includes depositing a first oxide layer such that a total thickness of the first portion of the first oxide layer and the nitride film in the active region is substantially the same as a length of the contact.

[0008] In one embodiment, forming a nitride film on the first oxide layer in the active region and the peripheral region further includes forming a nitride film covering at least the first portion and the second portion of the first oxide layer in the active region and covering the substrate in the peripheral region.

[0009] In one embodiment, depositing a second oxide layer on the nitride film in the active region and the peripheral region further includes depositing the second oxide layer such that a top surface of the second oxide layer in the peripheral region is higher than a top surface of the nitride film in the active region.

[0010] In one embodiment, polishing the second oxide layer to expose the nitride film in the active region further includes performing endpoint detection mode control so that the top surface of the nitride film in the active region is flush with the top surface of the remaining second oxide layer in the peripheral region.

[0011] In one embodiment, the method for forming a semiconductor device having a capacitor array further includes removing the nitride film in the active region so that a top surface of the first oxide layer in the active region is flush with a top surface of a remaining second oxide layer in the peripheral region.

[0012] In one embodiment, removing the nitride film further includes etching the nitride film in the active region to expose the first oxide layer in the active region and grinding the second oxide layer in the peripheral region.

[0013] In one embodiment, removing the nitride film further includes simultaneously etching the nitride film in the active region and the second oxide layer in the peripheral region.

[0014] In one embodiment, the method of forming a semiconductor device having the capacitor array also includes forming a contact passing through the first oxide layer and contacting the top electrode plate, wherein depositing the first oxide layer above the top electrode plate in the active area and the peripheral area also includes depositing the first oxide layer so that the thickness of the first oxide layer in the active area is substantially the same as the length of the contact.

[0015] The present disclosure provides a semiconductor device having a capacitor array.

[0016] In one embodiment, a semiconductor device having a capacitor array includes a substrate having an active region and a peripheral region, a capacitor array in the active region, a first oxide layer, and a nitride film. The capacitor array includes a bottom electrode plate, a capacitor dielectric layer covering the bottom electrode plate, and a top electrode plate covering the capacitor dielectric layer. The first oxide layer covers the top electrode plate in the active region. The nitride film is at least adjacent to the first oxide layer, and the nitride film includes a first portion extending in a longitudinal direction.

[0017] In one embodiment, the semiconductor device having a capacitor array further includes a contact penetrating through the first oxide layer and contacting the top electrode plate.

[0018] In one embodiment, the semiconductor device having a capacitor array further includes a second oxide layer in the peripheral region, wherein a top surface of the second oxide layer is flush with a top surface of the first oxide layer.

[0019] In one embodiment, the nitride film further includes a second portion extending laterally in the active region.

[0020] In one embodiment, the semiconductor device having a capacitor array further includes a contact passing through the first oxide layer and the second portion of the nitride film and contacting the top electrode plate, wherein the total thickness of the first portion of the first oxide layer and the second portion of the nitride film is substantially the same as the length of the contact.

[0021] In one embodiment, the semiconductor device having a capacitor array further includes a second oxide layer in the peripheral region, wherein a top surface of the second oxide layer is flush with a top surface of the second portion of the nitride film.

[0022] In one embodiment, the nitride film further includes a first portion extending in a lateral direction in the active region and a second portion extending in a longitudinal direction in the active region.

[0023] In one embodiment, the top electrode plate includes a first portion extending in a laterally direction and a second portion extending in a longitudinal direction.

[0024] In one embodiment, the nitride film further includes a third portion extending laterally in the peripheral region.

[0025] The semiconductor device with the capacitor array has a uniform interface that is beneficial to the structure formed thereon in the subsequent process due to the improvement of the chemical mechanical polishing process. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] When accompanied by Figure 1 When read together, the aspects of the present disclosure can be best understood from the following embodiments. Note that according to standard practice in this industry, various features are not drawn to scale. In fact, the size of various features can be arbitrarily increased or reduced for clarity of discussion.

[0027] Figure 1 The figure is a flow chart of a method for forming a semiconductor device having a capacitor array according to an embodiment of the present disclosure.

[0028] Figures 2 to 9 According to an embodiment of the present disclosure Figure 1 A method of forming a semiconductor device having a capacitor array is shown in cross-sectional views at several stages.

[0029] Fig.10 A semiconductor device having a capacitor array is formed according to another embodiment of the present disclosure.

[0030] Fig.11 and Fig.12 To form a Fig.10 A cross-sectional view of a method of making a semiconductor device having a capacitor array at various stages. DETAILED DESCRIPTION

[0031] Reference will now be made in detail to the present embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Throughout the drawings and the description, the same reference numerals are used wherever possible to refer to the same or like parts.

[0032] Figure 1 The present invention is a flow chart of a method M1 for forming a semiconductor device having a capacitor array according to an embodiment of the present disclosure. The method begins with step S1, and in step S1, a top electrode plate is formed in the active area and the peripheral area of ​​the substrate. Then, in step S2, a first oxide layer is deposited above the top electrode plate in the active area and the peripheral area. Next, in step S3, a hard mask is formed to cover the first and second portions of the first oxide layer in the active area. Then, in step S4, the top electrode plate in the peripheral area is removed. Therefore, in step S5, a nitride film is formed on the first oxide layer in the active area and the peripheral area. Next, in step S6, a second oxide layer is deposited on the nitride film in the active area and the passive area. Then, in step S7, the second oxide layer is polished to expose the nitride film in the active area. Finally, in step S8, a contact is formed through the first portion of the first oxide layer to contact the top electrode plate. In the following description, the aforementioned steps will be described in detail.

[0033] Figures 2 to 9 According to an embodiment of the present disclosure Figure 1 A cross-sectional view of a method M1 for forming a semiconductor device having a capacitor array at several stages. Figure 2 and Figure 1 In step S1 of the embodiment, a bottom electrode plate 210, a capacitor dielectric layer 220, and a top electrode plate 230 of a capacitor array 200 are formed on a substrate 100. The substrate 100 includes an active region AR and a peripheral region PR disposed along a lateral direction X. The bottom electrode plate 210 and the capacitor dielectric layer 220 are formed in the active region AR, and the top electrode plate 230 is formed in both the active region AR and the peripheral region PR.

[0034] The substrate 100 includes a plurality of contact pads 110 and an insulating material 120. The contact pads 110 contact the bottom electrode plate 210 of the capacitor array 200. The substrate 100 also includes active devices (not shown), such as metal oxide semiconductors (MOS) under the contact pads. The capacitor array 200 also includes a dielectric layer 240 to support the capacitors.

[0035] Forming the top electrode plate includes sequentially depositing a titanium nitride layer 232, a polymer layer 234, and a tungsten layer 236 along the longitudinal direction Y. The titanium nitride layer 232 is formed on the capacitor dielectric layer 220 in the active region AR and in the peripheral region PR. The polymer layer 234 is formed on the titanium nitride layer 232 in the active region AR and in the peripheral region PR. The tungsten layer 236 is formed on the polymer layer 234.

[0036] The top electrode plate 230 includes a first portion 230A, a second portion 230B, and a third portion 230C. The first portion 230A is a lateral portion located in the active region AR. The second portion 230B is a longitudinal portion located in the active region AR. The third portion 230C is a lateral portion mainly located in the peripheral region PR. The second portion 230B is connected to the first portion 230A and the third portion 230C.

[0037] Reference Figure 3 and Figure 1 The first oxide layer 300 is deposited on the top electrode plate 230 in the active region AR and the peripheral region PR. The first oxide layer 300 is conformally formed on the top electrode plate 230. The material of the first oxide layer 300 includes tetraethoxysilane (TEOS).

[0038] The first oxide layer 300 includes a first portion 310, a second portion 320, and a third portion 330. The first portion 310 is a lateral portion located in the active region AR and above the first portion 230A of the top electrode plate 230. The second portion 320 is a longitudinal portion located in the active region AR and adjacent to the second portion 230B of the top electrode plate 230. The third portion is a lateral portion located in the peripheral region PR and above the third portion 230C of the top electrode plate 230. The second portion 320 is connected to the first portion 310 and the third portion 330.

[0039] Reference Figure 4 and Figure 1 In step S3 of the embodiment, a hard mask 400 is formed to cover the first portion 310 and the second portion 320 of the first oxide layer 300 in the active region AR. Specifically, the hard mask 400 includes a longitudinal portion covering the sidewall 322 of the second portion 320 of the first oxide layer 300 .

[0040] Reference Figure 4 , Figure 5 and Figure 1 Step S4 in the process. The top electrode plate 230 in the peripheral region PR is removed. Specifically, the third portion 330 of the first oxide layer 300 and the third portion 230C of the top electrode plate 230 are removed until the substrate 100 is exposed. The third portion 330 of the first oxide layer 300 and the third portion 230C of the top electrode plate 230 are removed by dry etching. In other words, the hard mask 400 protects the first portion 310 and the second portion 320 of the remaining first oxide layer 300'. After removing the top electrode plate 230 in the peripheral region PR, the hard mask 400 is removed.

[0041] Reference Figure 6 and Figure 1In step S5 of the embodiment, a nitride film 500 is formed on the remaining first oxide layer 300' in the active region AR and on the substrate 100 in the peripheral region PR. The nitride film 500 at least covers the first portion 310 and the second portion 320 of the remaining first oxide layer 300' in the active region AR. The thickness of the nitride film 500 is about 20 nanometers.

[0042] Specifically, the nitride film 500 is conformally formed on the remaining first oxide layer 300' and the substrate 100. The nitride film 500 includes a first portion 510, a second portion 520, and a third portion 530. The first portion 510 is a lateral portion located in the active region AR and above the first portion 310 of the remaining first oxide layer 300'. The second portion 520 is a longitudinal portion located in the active region AR. The third portion 530 is a lateral portion located above the peripheral region PR and the substrate 100. The nitride film 500 is deposited to serve as a stop layer for the following process.

[0043] Reference Figure 7 and Figure 1 Step S6 in the above. A second oxide layer 600 is deposited on the nitride film 500 in the active region AR and the peripheral region PR. The second oxide layer 600 is formed to fill the gap between the active region AR and the peripheral region PR. In other words, the top surface 610 of the second oxide layer 600 in the peripheral region PR is at least higher than the top surface 512 of the first portion 510 of the nitride film 500 in the active region AR. Specifically, the top surface 620 of the second oxide layer 600 in the active region AR is higher than the top surface 610 of the second oxide layer 600. The material of the second oxide layer 600 includes tetraethoxysilane (TEOS).

[0044] Reference Figure 8 and Figure 1 In step S7 of the present invention, the second oxide layer 600 is polished to expose the nitride film 500 in the active region. Specifically, the top surface 512 of the first portion 510 of the nitride film 500 is exposed. The second oxide layer 600 is polished by chemical mechanical polishing (CMP). In this step, an endpoint detection (EPD) mode is used so that the polishing process stops at the interface between the nitride film 500 and the second oxide layer 600. The top surface 512 of the first portion 510 of the nitride film 500 is flush with the top surface 630 of the remaining second oxide layer 600'. In this way, the average standard deviation after chemical mechanical polishing is better and the range is reduced. Therefore, even if the thickness of the second oxide layer 600 is greater than 10,000 angstroms (for example, up to 14,000 angstroms), the thickness uniformity of the CMP process can be improved, and there is no need to use an additional etch-back process to first reduce the stage height. In addition, by using the nitride film as a stop layer, a high-speed abrasive can be introduced.

[0045] Reference Fig. 9 and Figure 1The contact 700 is formed through the first portion 310 of the first oxide layer 300 and the first portion 510 of the nitride film 500. The contact 700 is electrically connected to the first portion 230A of the top electrode plate 230. The total thickness T3 of the first portion 310 of the first oxide layer 300 and the first portion 510 of the nitride film 500 is substantially equal to the length L1 of the contact 700. In other words, the thickness T2 of the first portion 310 of the first oxide layer 300 and the thickness T1 of the first portion 510 of the nitride film 500 are predetermined in step S2 and step S5, respectively, according to the length L1 of the contact 700. In this way, there is no need to deposit an additional oxide layer in the active region AR in order to adjust the total thickness T3 to a target thickness before the step of forming the nitride film 500 or the contact 700.

[0046] For example, the target thickness of the total thickness T3 may be 5000 angstroms (500 nanometers). Therefore, the step of depositing the first oxide layer 300 is performed so that the thickness T2 is approximately 480 nanometers and the thickness T1 of the nitride film 500 is approximately 20 nanometers.

[0047] According to the method M1, the capacitor array 200 of the semiconductor device 10 is completed. The semiconductor device 10 includes a substrate 100, a capacitor array 200, a first oxide layer 300' in the active region AR (i.e., the remaining first oxide layer 300'), a nitride film 500, a second oxide layer 600' in the peripheral region PR (i.e., the remaining second oxide layer 600'), and a contact 700. Due to the improvement of the CMP process, the semiconductor device 10 has a uniform interface that is beneficial to the structure formed thereon in the subsequent process.

[0048] Fig.10 A semiconductor device having a capacitor array is formed according to another embodiment of the present disclosure. Steps S1 to S7 of method M2 are substantially the same as steps S1 to S7 of method M1. Method M2 also includes steps S9 and S10 after step S7. Method M2 includes the advantages of method M1 described above and is therefore not reiterated here. In step S9, the nitride film is removed. In step S10, a contact is formed through a first portion of the first oxide layer to contact the top electrode plate. In the following description, the aforementioned steps S9 and S10 will be described in detail.

[0049] Fig.11 and Fig.12 To form a Fig.10 A method of manufacturing a semiconductor device 200a having a capacitor array in FIG. Fig. 9 , Fig.11 and Fig.10Step S9 in the embodiment. The first portion 510 of the nitride film 500 is removed. Specifically, a portion of the second oxide layer 600 in the peripheral region PR is removed so that the top surface 312 of the first portion 310 of the remaining first oxide layer 300' is flush with the top surface 640 of the remaining second oxide layer 600" in the peripheral region PR. After this step, the remaining nitride film 500' includes the second portion 520 and the third portion 530.

[0050] In some embodiments, the first portion 510 of the nitride film 500 is first etched. Next, the upper portion of the second oxide layer 600 in the peripheral region PR is polished to smooth the top surface 640 until the top surface 640 is flush with the top surface 312.

[0051] In some embodiments, the first portion 510 of the nitride film 500 in the active region AR and the second oxide layer 600 in the peripheral region PR are etched simultaneously. For example, the etching selectivity between the material of the nitride film 500 and the material of the second oxide layer 600 is 1:1.

[0052] Reference Fig.12 and Fig.10 The step S10 in the embodiment of the present invention is to form a contact 800 passing through the first portion 310 of the first oxide layer 300. The contact 800 is electrically connected to the first portion 230A of the top electrode plate 230. The thickness T2 of the first portion 310 of the first oxide layer 300 is substantially the same as the length L2 of the contact 800. In other words, the thickness T2 of the first portion 310 of the first oxide layer 300 is predetermined in step S2 according to the length of the contact 800. In this way, there is no need to deposit an additional oxide layer in the active region AR in order to adjust the thickness T2 to a target thickness before the step of forming the nitride film 500 or after the step of removing the nitride film 500.

[0053] According to the method M2, the capacitor array 200 of the semiconductor device 10a is completed. The semiconductor device 10a includes a substrate 100, a capacitor array 200, a first oxide layer 300' in the active region AR (i.e., the remaining first oxide layer 300'), a nitride film 500, a second oxide layer 600' in the peripheral region PR (i.e., the remaining second oxide layer 600'), and a contact 800. Due to the improvement of the CMP process, the semiconductor device 10a has a uniform interface that is beneficial to the structure formed thereon in the subsequent process.

[0054] In summary, by forming a nitride film between the first oxide layers, the CMP process for removing the second oxide layer can use the EPD mode. Therefore, the average standard deviation after chemical mechanical polishing is better and the range is reduced. Therefore, even if the thickness of the second oxide layer 600 is greater than 10,000 angstroms, the thickness uniformity of the CMP process can be improved, and there is no need to use an additional etch-back process to first reduce the step height. In addition, by using the nitride film as a stop layer, a high-speed abrasive can be introduced.

[0055] Even though the present disclosure has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the claims appended hereto should not be limited to the description of the embodiments contained herein.

[0056] Those skilled in the art will recognize that various modifications and changes may be made to the structure of the present disclosure without departing from the spirit and scope of the present disclosure. Various changes, substitutions and modifications may be made herein without departing from the spirit and scope of the present disclosure. In view of the above, if such modifications and changes are within the scope of the following claims, the present disclosure includes such modifications and changes.

[0057]

Explanation of symbols

[0058] 10,10a:Semiconductor devices

[0059] 100:Substrate

[0060] 110: Contact pad

[0061] 120: Insulation material

[0062] 200:Capacitor array

[0063] 210: Bottom electrode plate

[0064] 220: Capacitor dielectric layer

[0065] 230: Top electrode plate

[0066] 230A: Part I

[0067] 230B: Part 2

[0068] 230C: Part 3

[0069] 232:Titanium nitride layer

[0070] 234: polymer layer

[0071] 236: Tungsten layer

[0072] 300,300': First oxide layer

[0073] 310: Part 1

[0074] 320: Part 2

[0075] 322: Side wall

[0076] 330: Part 3

[0077] 400:Hard cover

[0078] 500: Nitride film

[0079] 510: Part 1

[0080] 512: Top

[0081] 520: Part 2

[0082] 530: Part 3

[0083] 600,600',600": Second oxide layer

[0084] 610,620,630,640: Top

[0085] 700,800:Contact

[0086] L1, L2: Length

[0087] M1,M2: Method

[0088] S1~S10: Steps

[0089] T1, T2, T3: thickness

[0090] AR: Active Area

[0091] PR: Peripheral area.

Claims

1. A method for forming a semiconductor device having a capacitor array, characterized in that: Include: forming a top electrode plate of the capacitor array in the active region and the peripheral region of the substrate; depositing a first oxide layer over the top electrode plate in the active region and the peripheral region; removing the top electrode plate in the peripheral region; forming a nitride film on the first oxide layer in the active region and the peripheral region; depositing a second oxide layer on the nitride film in the active region and the peripheral region; as well as The second oxide layer is polished to expose the nitride film in the active region.

2. The method for forming a semiconductor device having the capacitor array according to claim 1, wherein: The top electrode plate forming the capacitor array in the active region and the peripheral region further comprises: forming a titanium nitride layer on the bottom electrode plate and the capacitor dielectric layer in the active region and the peripheral region; and A polymer layer is formed on the titanium nitride layer in the active region and the peripheral region.

3. The method for forming a semiconductor device having the capacitor array according to claim 1, wherein: The first oxide layer includes a first portion extending in a lateral direction, a second portion extending in a longitudinal direction, and a third portion extending in the lateral direction, the first portion and the second portion are located in the active region, the third portion is located in the peripheral region, and the method for forming the capacitor array includes: Before removing the top electrode plate in the peripheral region, a hard mask is formed covering the first portion and the second portion of the first oxide layer in the active region.

4. The method for forming a semiconductor device having the capacitor array according to claim 3, wherein: Also includes: Forming a contact through the first portion of the oxide layer and the nitride film and contacting the top electrode plate, wherein depositing the first oxide layer on the top electrode plate in the active region and the peripheral region further comprises: The first oxide layer is deposited such that a total thickness of the first portion of the first oxide layer and the nitride film in the active region is substantially the same as a length of the contact.

5. The method for forming a semiconductor device having the capacitor array according to claim 3, wherein: Forming the nitride film on the first oxide layer in the active region and the peripheral region further comprises: The nitride film is formed to cover at least the first portion and the second portion of the first oxide layer in the active region and the substrate in the peripheral region.

6. The method for forming a semiconductor device having the capacitor array according to claim 1, wherein: Depositing the second oxide layer on the nitride film in the active region and the peripheral region further comprises: The second oxide layer is deposited so that a top surface of the second oxide layer in the peripheral region is higher than a top surface of the nitride film in the active region.

7. The method for forming a semiconductor device having the capacitor array according to claim 1, wherein: Grinding the second oxide layer to expose the nitride film in the active region further comprises: An endpoint detection mode control is implemented so that a top surface of the nitride film in the active region is flush with a top surface of the remaining second oxide layer in the peripheral region.

8. The method for forming a semiconductor device having the capacitor array according to claim 1, wherein: Also includes: The nitride film in the active region is removed so that a top surface of the first oxide layer in the active region is flush with a top surface of the remaining second oxide layer in the peripheral region.

9. The method for forming a semiconductor device having the capacitor array according to claim 8, wherein: Removing the nitride film further comprises: Etching the nitride film in the active region to expose the first oxide layer in the active region; and The second oxide layer in the peripheral region is polished.

10. The method for forming a semiconductor device having the capacitor array according to claim 8, wherein: Removing the nitride film further comprises: The nitride film in the active region and the second oxide layer in the peripheral region are etched simultaneously.

11. The method for forming a semiconductor device having the capacitor array according to claim 8, wherein: Also includes: Forming contacts through the first oxide layer and contacting the top electrode plate, wherein depositing the first oxide layer on the top electrode plate in the active region and the peripheral region further comprises: The first oxide layer is deposited such that a thickness of the first oxide layer in the active region is substantially the same as a length of the contact.

12. A semiconductor device having a capacitor array, characterized in that: Include: a substrate, comprising an active region and a peripheral region; A capacitor array, located in the active region, includes: Bottom electrode plate; a capacitor dielectric layer covering the bottom electrode plate; and a top electrode plate covering the capacitor dielectric layer; A first oxide layer covering the top electrode plate in the active region; as well as The nitride film at least adjoins the first oxide layer, wherein the nitride film includes a first portion extending in a longitudinal direction.

13. The semiconductor device having the capacitor array according to claim 12, wherein: Also included is a contact that passes through the first oxide layer and contacts the top electrode plate.

14. The semiconductor device having the capacitor array according to claim 12, wherein: Also included is a second oxide layer in the peripheral region, wherein a top surface of the second oxide layer is flush with a top surface of the first oxide layer.

15. The semiconductor device having the capacitor array according to claim 12, wherein: The nitride film further includes a second portion extending laterally in the active region.

16. The semiconductor device having the capacitor array according to claim 15, wherein: A contact is also included, which passes through the first oxide layer and the second portion of the nitride film and contacts the top electrode plate, wherein the total thickness of the first portion of the first oxide layer and the second portion of the nitride film is substantially the same as the length of the contact.

17. The semiconductor device having the capacitor array according to claim 15, wherein: A second oxide layer is also included in the peripheral region, wherein a top surface of the second oxide layer is flush with a top surface of the second portion of the nitride film.

18. The semiconductor device having the capacitor array according to claim 12, wherein: The nitride film further includes a first portion extending laterally in the active region and a second portion extending longitudinally in the active region.

19. The semiconductor device having the capacitor array according to claim 12, wherein: The top electrode plate includes a first portion extending in a lateral direction and a second portion extending in a longitudinal direction.

20. The semiconductor device having the capacitor array according to claim 12, wherein: The nitride film also includes a third portion extending laterally in the peripheral region.

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