A process for increasing the cell density of a double-groove MOSFET

Abstract

The present invention relates to the field of MOS semiconductor technology, and discloses a process for improving the cell density of double-groove MOSFETs, including the following steps: using extreme ultraviolet lithography technology to etch grooves on the surface of an N substrate; depositing two gates G1 and one gate G0 in the trenches of a single MOS cell; forming P-well layers, N-well layers, and P+ layers by ion implantation between gate G1 and gate G0, and between the gate G1 of adjacent MOS cells; and using polysilicon nanowires grown perpendicular to the surface of the substrate as gates inside the trenches. By deploying multiple gates inside the trenches, the present invention can help disperse the electric field intensity applied to the channel, reduce the electric field concentration phenomenon in local areas, thereby improving the long-term reliability and stability of the device. Moreover, this multi-gate design makes full use of the vertical space of the trenches, achieving a higher integration level and improving the performance without significantly increasing the chip area.

Description

Technical Field

[0001] The present invention relates to the field of MOS semiconductor technology, and particularly to a process for increasing the cell density of double-groove MOSFETs. Background Art

[0002] The main purpose of the process for the cell density of double-groove MOSFETs is to increase more MOSFET units within a limited chip area to improve the overall performance of the device. This generally involves optimizing the design and manufacturing process of the grooves, ensuring high precision and quality while minimizing the space occupied by each unit.

[0003] A prior patent discloses a process for increasing the cell density of trench MOSFETs and a trench MOSFET (Publication No. CN117650181A), belonging to the field of semiconductor technology. The trench MOSFET includes a filled conductive layer having at least one of protrusions and / or depressions on at least one of the lateral sides. In the technology disclosed in this patent, the following defects exist:

[0004] 1) The introduced protrusion and depression structures may change the strength and thermal stability of the filled conductive layer. Especially when subjected to external stress, it may affect the overall performance of the device.

[0005] 2) This patent compares the changes in the space gaps under different designs through experiments, but more data is needed to support the reliability and durability of this new structure under long-term working conditions. Summary of the Invention

[0006] The main technical problem to be solved by the present invention is to provide a process for increasing the cell density of double-groove MOSFETs, solving the problems in the above background art.

[0007] To solve the above technical problem, according to one aspect of the present invention, more specifically, a process for increasing the cell density of double-groove MOSFETs includes the following steps:

[0008] S1. Use extreme ultraviolet lithography technology to etch a groove on the surface of the N substrate;

[0009] S2. Deposit two gates G1 and one gate G0 in the trench of a single MOS cell;

[0010] S3. Form a P-well layer, an N-well layer, and a P+ layer by ion implantation between gate G1 and gate G0, and between gate G1 of adjacent MOS cells;

[0011] S4. And use polysilicon nanowires grown perpendicular to the surface of the substrate as the gate inside the trench;

[0012] S5. After completing the double-groove structure and performing surface passivation treatment, the electrical performance of the MOSFET device is then detected.

[0013] Furthermore, the specific steps in the steps S2 to S3 are as follows:

[0014] 1). After oxidizing the groove surface, polysilicon and photoresist are deposited.

[0015] 2). Lithography is performed inside the groove to form two gates G1 and one gate G0.

[0016] 3). After ion implantation, oxidation is carried out and photoresist is covered.

[0017] 4). At this time, lithography is performed on the covered photoresist to form the gate oxide layers on the gates G1 and G0.

[0018] Furthermore, during the process of performing lithography inside the groove to form two gates G1 and one gate G0, it is necessary to retain the oxide layer covering the N substrate layer to carry out the ion implantation step.

[0019] Furthermore, in the step S4, the gate G1 serves as the polysilicon nanowire on one side, and the gate G0 serves as the polysilicon nanowire on the other side.

[0020] Furthermore, in the step S5, according to the resistance between the source and the drain when the MOSFET device is fully turned on, the maximum voltage that can be tolerated between the drain and the source when the gate is grounded, and the thermal resistance, it is determined whether the electrical performance of the MOSFET device meets the standard, and there is:

[0021]

[0022] In the formula, represents the condition coefficient for the electrical performance of the MOSFET device to meet the standard, represents the resistance between the source and the drain when the MOSFET device is fully turned on, represents the maximum voltage that can be tolerated between the drain and the source when the gate is grounded, represents the magnitude of the thermal resistance of the MOSFET device.

[0023] Furthermore, the magnitude of the thermal resistance of the MOSFET device is calculated according to the temperature change of the MOSFET device from one measurement point to another measurement point and the heat transfer power passing through the path between the two points. Then there is:

[0024]

[0025] In the formula, represents the magnitude of the thermal resistance of the MOSFET device, Indicates the temperature change of the MOSFET device from one measurement point to another. Indicates the transmitted thermal power between the two-point paths.

[0026] Furthermore, when it indicates that the electrical performance of the detected MOSFET device meets the usage requirements;

[0027] When it indicates that the electrical performance of the detected MOSFET device does not meet the usage requirements.

[0028] Furthermore, in step S5, during the source deposition process, photoresist needs to be covered on gate G1 and gate G0 again. After lithography of the photoresist, the N substrate layer needs to be exposed to deposit metal to form the source.

[0029] A process for improving the cell density of double-groove MOSFET provided by the present invention, compared with the prior art, the effects achieved by this method are:

[0030] 1. The design of setting multiple gates in the same groove in the present invention is equivalent to increasing the effective width of the channel, enabling more current to flow through the same area, thereby increasing the current density. And multiple gates help to distribute the current more evenly, reduce the formation of hot spots, and improve the overall thermal performance of the device.

[0031] 2. The present invention can directly achieve single exposure of these fine features through extreme ultraviolet lithography technology, simplifying the manufacturing process and reducing potential error sources.

[0032] 3. Deploying multiple gates inside the groove in the present invention can help disperse the electric field intensity applied to the channel, reduce the electric field concentration phenomenon in local areas, thereby improving the long-term reliability and stability of the device. And this multi-gate design makes full use of the vertical space of the groove, achieves higher integration, and improves the performance without significantly increasing the chip area.

[0033] 4. By the resistance between the source and the drain when the MOSFET device is fully turned on, the maximum voltage that can be borne between the drain and the source when the gate is grounded, and the thermal resistance, it can be quickly and simply determined whether the electrical performance of the MOSFET device meets the standards. Brief Description of the Drawings

[0034] Figure 1 Is the process flow chart of the MOSFET structure in the present invention;

[0035] Figure 2 Is the planar structure schematic diagram of the present invention;

[0036] Figure 3This is a schematic diagram of the distribution of MOS cells, gate G1, and gate G0 in the present invention. Detailed implementation mode

[0037] To make the technical solution of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0038] Embodiment 1

[0039] As Figure 1 - 3 shows, according to one aspect of the present invention, a process for improving the cell density of double-groove MOSFETs is provided, including the following steps:

[0040] Step 1: Use extreme ultraviolet lithography technology to etch grooves on the surface of the N substrate. In traditional lithography processes, in order to achieve smaller feature sizes, multiple patterning techniques (such as double or quadruple patterning) are usually required, which increases process complexity and cost. And extreme ultraviolet lithography technology can directly achieve single exposure of these fine features, simplifying the manufacturing process and reducing potential error sources.

[0041] Step 2: Deposit two gates G1 and one gate G0 in the trench of a single MOS cell. By setting multiple gates in the same trench, it is equivalent to increasing the effective width of the channel, enabling more current to flow through the same area, thereby increasing the current density. And multiple gates help to distribute the current more evenly, reduce the formation of hot spots, and improve the overall thermal performance of the device.

[0042] Deploying multiple gates inside the trench can help disperse the electric field intensity applied to the channel, reduce the electric field concentration phenomenon in local areas, thereby improving the long-term reliability and stability of the device. This multi-gate design makes full use of the vertical space of the trench, achieves higher integration, and improves performance without significantly increasing the chip area.

[0043] Step 3: Form P-well layer, N-well layer, and P+ layer by ion implantation between gate G1 and gate G0, and between gate G1 of adjacent MOS cells.

[0044] Step 4: And use polysilicon nanowires grown perpendicular to the surface of the substrate inside the trench as gates, where gate G1 is used as the polysilicon nanowire on one side, and gate G0 is used as the polysilicon nanowire on the other side.

[0045] Step 5: After completing the double-groove structure and performing surface passivation treatment, then detect the electrical performance of the MOSFET device. During the source deposition process, photoresist needs to be covered on gates G1 and G0 again. After photolithography of the photoresist, the N substrate layer needs to be exposed to deposit metal to form the source.

[0046] In this embodiment, the specific steps in steps 2 to 3 are as follows:

[0047] 1. After oxidizing the surface of the groove, deposit polysilicon and photoresist.

[0048] 2. Perform photolithography on the inside of the groove to form two gates G1 and one gate G0; and during the process of performing photolithography on the inside of the groove to form two gates G1 and one gate G0, it is necessary to retain the oxide layer covering the N substrate layer before the ion implantation step can be carried out.

[0049] 3. After ion implantation, perform oxidation and cover with photoresist.

[0050] 4. At this time, perform photolithography on the covered photoresist to form the gate oxide layers on gates G1 and G0.

[0051] Embodiment 2

[0052] As Figure 2 shown, according to the resistance between the source and the drain when the MOSFET device is fully turned on, the maximum voltage that can be withstood between the drain and the source when the gate is grounded, and the thermal resistance, it is determined whether the electrical performance of the MOSFET device meets the standard, and there is:

[0053]

[0054] In the formula, represents the condition coefficient for the electrical performance of the MOSFET device to meet the standard, represents the resistance between the source and the drain when the MOSFET device is fully turned on, represents the maximum voltage that can be withstood between the drain and the source when the gate is grounded, represents the magnitude of the thermal resistance of the MOSFET device.

[0055] The magnitude of the thermal resistance of the MOSFET device is calculated based on the temperature change of the MOSFET device from one measurement point to another and the heat transfer power passing through the path between these two points. Then there is:

[0056]

[0057] In the formula, represents the magnitude of the thermal resistance of the MOSFET device, represents the temperature change of the MOSFET device from one measurement point to another, represents the heat transfer power passing through the path between these two points.

[0058] Among them, the thermal resistance of the collected MOSFET device is calculated. The temperature change of the MOSFET device from one measurement point to another takes (unit: °C). The heat transfer power between these two points is taken as (unit: W). Then we have:

[0059]

[0060] From the above calculations, it can be known that the thermal resistance of the MOSFET device is (unit: °C / W). Then when calculating the condition coefficient for the collected MOSFET device, the resistance between the source and the drain when the MOSFET device is fully turned on is taken as (unit: mΩ). The maximum voltage that can be withstood between the drain and the source with the gate grounded is taken as (unit: V). Then we have:

[0061]

[0062] From the above calculations, it can be known that the electrical performance of the detected MOSFET device meets the usage requirements.

[0063] Embodiment 3

[0064] When determining whether the electrical performance of the MOSFET device meets the standard based on the resistance between the source and the drain when the MOSFET device is fully turned on, the maximum voltage that can be withstood between the drain and the source with the gate grounded, and the thermal resistance, after comparing multiple groups of data samples, we have:

[0065] Table 1 Partial implementation parameters and usage standards of the MOSFET device

[0066]

[0067] From the data in Table 1 above, it can be known that when the sample approaches infinity, there will be a dividing line to determine whether the MOSFET device meets the usage requirements with the condition coefficient w, that is, when then it indicates that the electrical performance of the detected MOSFET device meets the usage requirements.

[0068] The above-described embodiments only represent several implementation manners of the present invention. The description is relatively specific and detailed, but it should not be construed as a limitation to the scope of the patent of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention should be subject to the appended claims.

Claims

1. A process for increasing the cell density of a double trench MOSFET, characterized in that: The following steps are involved: S1, using extreme ultraviolet lithography technology to etch a groove on the surface of the N substrate; S2. Two gates G1 and one gate G0 are deposited in the groove of a single MOS cell, the gate G0 is located between the two gates G1, and the distances between the gate G0 and the two gates G1 are equal, wherein a double trench structure is formed between the gate G0 and the two gates G1; S3, forming a P well layer, an N well layer and a P+ layer between the gate G1 and the gate G0, and between the gates G1 of adjacent MOS cells by ion implantation; S4, and using a polysilicon nanowire perpendicular to the substrate surface as a gate inside the trench, wherein the polysilicon nanowire is located on one side of the MOS cell and is vertically connected to both the gate G1 and the gate G0; S5. After completing the double trench structure and performing surface passivation treatment, the electrical performance of the MOSFET device is tested.

2. The process for increasing the cell density of a dual trench MOSFET according to claim 1, characterized in that: The specific steps in steps S2 to S3 are: 1) After the groove surface is oxidized, polysilicon and photoresist are deposited; 2) Photolithography is performed inside the groove to form two gates G1 and one gate G0; 3) After ion implantation, oxidation is performed and the photoresist is covered; 4) At this time, the covering photoresist is photolithographically processed to form a gate oxide layer on the gate G1 and the gate G0.

3. The process for increasing the cell density of a dual trench MOSFET according to claim 2, characterized in that: In the process of photolithography to form two gates G1 and one gate G0 inside the groove, it is necessary to keep the oxide layer covering the N substrate layer before the ion implantation step can be performed.

4. The process for increasing the cell density of a dual trench MOSFET according to claim 1, characterized in that: In the step S4, the gate G1 serves as the polysilicon nanowire on one side, and the gate G0 serves as the polysilicon nanowire on the other side.

5. The process for increasing the cell density of a dual trench MOSFET according to claim 1, characterized in that: The step S5 determines whether the electrical performance of the MOSFET device meets the standard according to the resistance between the source and the drain when the MOSFET device is fully turned on, the maximum voltage that the drain and the source can withstand when the gate is grounded, and the thermal resistance, which includes: In the formula, w represents the condition coefficient for the electrical performance of the MOSFET device to meet the standard, r represents the resistance between the source and the drain when the MOSFET device is fully turned on, u represents the maximum voltage that the drain and the source can withstand when the gate is grounded, and a represents the thermal resistance of the MOSFET device.

6. The process for increasing the cell density of a dual trench MOSFET according to claim 5, characterized in that: The thermal resistance of the MOSFET device is calculated based on the temperature change of the MOSFET device from one measurement point to another, and the heat power transferred between the two points. Then: Where a represents the thermal resistance of the MOSFET device, ΔT represents the temperature change of the MOSFET device from one measurement point to another, and P represents the heat power transferred between the two points.

7. The process for increasing the cell density of a dual trench MOSFET according to claim 5, characterized in that: When w ≥ 66%, it means that the electrical performance of the tested MOSFET device meets the use requirements; When w<66%, it means that the electrical performance of the tested MOSFET device does not meet the usage requirements.

8. The process for increasing the cell density of a dual trench MOSFET according to claim 1, characterized in that: In the step S5, during the source electrode deposition process, the gate G1 and the gate G0 need to be covered with photoresist. After the photoresist is photolithographically processed, the N substrate layer needs to be exposed to the outside so that metal can be deposited to form the source electrode.

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