A Gradient-Doped Isolated Trench Gate Silicon Carbide VDMOS and Its Manufacturing Method

Abstract

The present invention provides a gradient-doped separated trench gate silicon carbide VDMOS and a manufacturing method thereof. The method includes: epitaxially growing on the side surface of a silicon carbide substrate with a drain metal layer to sequentially form a drift layer, a first N-type region and a second N-type region; forming a blocking layer, etching, ion implanting to form a P-type well region and an N-type source region; reforming the blocking layer, etching, depositing to form a first insulating region; reforming the blocking layer, etching, depositing metal to form a second gate metal layer; reforming the blocking layer, etching, depositing to form a second insulating region, and the insulating dielectric layer includes the first insulating region and the second insulating region; reforming the blocking layer, etching, depositing metal to form a first gate metal layer; reforming the blocking layer, etching, depositing metal to form a source metal layer; improving the breakdown voltage of the device, reducing the gate-drain capacitance of the device, increasing the switching speed of the device, and reducing the switching loss of the device.

Description

Technical Field

[0001] The present invention relates to a separated trench gate silicon carbide VDMOS with gradient doping and a preparation method thereof. Background Art

[0002] Silicon carbide VDMOS is a typical representative of silicon carbide power devices and has wide applications in fields such as electric vehicles, aerospace, and power conversion. For silicon carbide power VDMOS, the requirements for device performance focus on different aspects in different fields. Generally speaking, the overall requirements include lower on-resistance, faster switching speed, higher reliability (including gate reliability, drain voltage impact reliability, etc.), and lower body diode conduction loss. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a separated trench gate silicon carbide VDMOS with gradient doping and a preparation method thereof, which can improve the breakdown voltage of the device without affecting the on-resistance of the device, reduce the gate-drain capacitance of the device, improve the switching speed of the device, and reduce the switching loss of the device.

[0004] In a first aspect, the present invention provides a preparation method of a separated trench gate silicon carbide VDMOS with gradient doping, including the following steps:

[0005] Step 1: Epitaxially grow on the side surface of a silicon carbide substrate with a drain metal layer to form a drift layer;

[0006] Step 2: Epitaxially grow on the drift layer to form a first N-type region;

[0007] Step 3: Epitaxially grow on the first N-type region to form a second N-type region;

[0008] Step 4: Form a blocking layer on the second N-type region, etch the blocking layer to form a through hole, and perform ion implantation to form a P-type well region;

[0009] Step 5: Remove the original blocking layer, form a blocking layer on the second N-type region, etch the blocking layer to form a through hole, and perform ion implantation to form an N-type source region;

[0010] Step 6: Remove the original blocking layer, reform the blocking layer, etch the blocking layer to form a through hole, etch the second N-type region and the first N-type region until the upper side surface of the drift layer, and deposit to form a first insulating region;

[0011] Step 7: Remove the original blocking layer, reform the blocking layer, etch the blocking layer to form a through hole, and etch the first insulating region, and deposit metal to form a second gate metal layer;

[0012] Step 8: Remove the original barrier layer, reform the barrier layer, etch the barrier layer to form a through hole, deposit to form a second insulating region, and the insulating dielectric layer includes a first insulating region and a second insulating region;

[0013] Step 9: Remove the original barrier layer, reform the barrier layer, etch the barrier layer to form a through hole, and etch the second insulating region to form a trench, deposit metal to form a first gate metal layer;

[0014] Step 10: Remove the original barrier layer, reform the barrier layer, etch the barrier layer to form a through hole, and etch the second N-type region to the upper side of the P-type well region, deposit metal to form a source metal layer, remove the barrier layer, and complete the preparation.

[0015] In a second aspect, the present invention provides a gradient-doped separated trench gate silicon carbide VDMOS, and the silicon carbide VDMOS is prepared by using the preparation method of a gradient-doped separated trench gate silicon carbide VDMOS described in the first aspect.

[0016] The advantages of the present invention are as follows:

[0017] First, the present invention constructs a first gate metal layer and a second gate metal layer inside the device, which can effectively reduce the resistivity inside the device and reduce the on-resistance of the device;

[0018] Second, the present invention constructs a first N-type region and a second N-type region on the upper part of the drift layer to achieve gradient doping; when the device is turned off, the voltage from the drain of the device is distributed in the first N-type region and the second N-type region, improving the breakdown voltage of the device; and the doping concentrations of the first N-type region and the second N-type region are higher than that of the drift layer, which can distribute the current to the edge of the device and avoid current concentration inside the device;

[0019] Third, the first gate metal layer and the second gate metal layer of the present invention can partially shield the gate-drain capacitance (i.e., the Miller capacitance), thereby reducing the Miller capacitance of the device and improving the switching speed of the device;

[0020] Fourth, the P-type well region of the present invention forms an ohmic contact with the source metal layer, eliminating the need for an additional P-type source region process and reducing the process cost;

[0021] Fifth, the present invention adopts a multi-epitaxy process, which can reduce the process difficulty, improve the quality of the device gate structure, reduce the defect density, and improve the device reliability. Description of the Drawings

[0022] The following further describes the present invention with reference to the drawings in conjunction with embodiments.

[0023] Figure 1 It is a schematic diagram of a gradient-doped separated trench gate silicon carbide VDMOS of the present invention.

[0024] Figure 2 Process cross-section of a gradient-doped isolated trench-gate silicon carbide VDMOS according to the present invention Figure 1 。

[0025] Figure 3 Process cross-section of a gradient-doped isolated trench-gate silicon carbide VDMOS according to the present invention Figure 2 。

[0026] Figure 4 Process cross-section of a gradient-doped isolated trench-gate silicon carbide VDMOS according to the present invention Figure 3 。

[0027] Figure 5 Process cross-section of a gradient-doped isolated trench-gate silicon carbide VDMOS according to the present invention Figure 4 。

[0028] Figure 6 Process cross-section of a gradient-doped isolated trench-gate silicon carbide VDMOS according to the present invention Figure 5 。

[0029] Figure 7 Process cross-section of a gradient-doped isolated trench-gate silicon carbide VDMOS according to the present invention Figure 6 。

[0030] Figure 8 Process cross-section of a gradient-doped isolated trench-gate silicon carbide VDMOS according to the present invention Figure 7 。

[0031] Figure 9 Process cross-section of a gradient-doped isolated trench-gate silicon carbide VDMOS according to the present invention Figure 8 。

[0032] Figure 10 Process cross-section of a gradient-doped isolated trench-gate silicon carbide VDMOS according to the present invention Figure 9 。

[0033] Figure 11 Process cross-section of a gradient-doped isolated trench-gate silicon carbide VDMOS according to the present invention Figure 10 。

[0034] Figure 12 Process cross-section of a gradient-doped isolated trench-gate silicon carbide VDMOS according to the present invention Figure 10 One.

[0035] Figure 13 Process cross-section of a gradient-doped isolated trench-gate silicon carbide VDMOS according to the present invention Figure 10 Two.

[0036] Figure 14 Process cross-section of a gradient-doped isolated trench gate silicon carbide VDMOS according to the present invention Figure 10 III.

[0037] Figure 15 Process cross-section of a gradient-doped isolated trench gate silicon carbide VDMOS according to the present invention Figure 10 IV. Specific embodiments

[0038] To facilitate an understanding of the present application, the present application will be described more fully hereinafter with reference to the relevant accompanying drawings. Embodiments of the present application are shown in the drawings. However, the present application may be embodied in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided so that the disclosure of the present application will be thorough and complete.

[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terms used in the description of the present application herein are for the purpose of describing particular embodiments only and are not intended to limit the present application.

[0040] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on", "in contact with", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or portions, these elements, components, regions, layers, doping types and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or portion from another element, component, region, layer, doping type or portion. Thus, a first element, component, region, layer, doping type or portion discussed below may be denoted as a second element, component, region, layer or portion without departing from the teachings of the present invention.

[0041] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. can be used herein to describe the relationship of one element or feature described in the figure with other elements or features. It should be understood that, in addition to the orientations described in the figure, spatial relationship terms also include different orientations of the device during use and operation. For example, if the device in the drawing is flipped, an element or feature described as "under other elements" or "beneath them" or "under it" will be oriented "above" other elements or features. Thus, the exemplary terms "under" and "beneath" can include both upper and lower orientations. In addition, the device may also have additional orientations (such as rotating 90 degrees or other orientations), and the spatial descriptors used herein are accordingly interpreted.

[0042] As used herein, the singular forms "a", "an", and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that terms such as "comprises / include" or "has" specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the related listed items.

[0043] As Figures 1 to 15 shown, an embodiment of the present application provides a method for preparing a gradient-doped separated trench gate silicon carbide VDMOS, including the following steps:

[0044] Step 1: Epitaxially grow on the side surface of a silicon carbide substrate 101 having a drain metal layer 109 to form a drift layer 102;

[0045] Step 2: Epitaxially grow on the drift layer 102 to form a first N-type region 103;

[0046] Step 3: Epitaxially grow on the first N-type region 103 to form a second N-type region 104;

[0047] Step 4: Form a blocking layer 110 on the second N-type region 104, etch the blocking layer 110 to form a through hole, perform ion implantation to form a P-type well region 105, and the ion implantation energy is 70 - 230 kev;

[0048] Step 5: Remove the original blocking layer 110, form a blocking layer 110 on the second N-type region 104, etch the blocking layer 110 to form a through hole, perform ion implantation to form an N-type source region 1051, and the ion implantation energy is 70 - 170 kev;

[0049] Step 6: Remove the original blocking layer 110, reform the blocking layer 110, etch the blocking layer 110 to form a through hole, etch the second N-type region 104 and the first N-type region 103 until reaching the upper side of the drift layer 102, and deposit to form the first insulating region 1063;

[0050] Step 7: Remove the original blocking layer 110, reform the blocking layer 110, etch the blocking layer 110 to form a through hole, etch the first insulating region 1063, and deposit metal to form the second gate metal layer 1061;

[0051] Step 8: Remove the original blocking layer 110, reform the blocking layer 110, etch the blocking layer 110 to form a through hole, deposit to form the second insulating region 1064, and the insulating dielectric layer 106 includes the first insulating region 1063 and the second insulating region 1064;

[0052] Step 9: Remove the original blocking layer 110, reform the blocking layer 110, etch the blocking layer 110 to form a through hole, etch the second insulating region 1064 to form a trench 1062, and deposit metal to form the first gate metal layer 107;

[0053] Step 10: Remove the original blocking layer 110, reform the blocking layer 110, etch the blocking layer 110 to form a through hole, etch the second N-type region 104 to the upper side of the P-type well region 105, deposit metal to form the source metal layer 108, and remove the blocking layer 110 to complete the preparation.

[0054] In this embodiment, preferably, the bottom of the trench 1062 and the upper side of the second N-type region 104 are in the same plane.

[0055] In this embodiment, preferably, the thickness of the second gate metal layer 1061 is 2 - 6 μm.

[0056] In this embodiment, preferably, the doping concentration of the first N-type region 103 is greater than that of the drift layer 102; the doping concentration of the second N-type region 104 is greater than that of the first N-type region 103; the doping concentration of the P-type well region 105 is greater than that of the second N-type region 104.

[0057] In this embodiment, preferably, the thickness of the first N-type region 103 is greater than or equal to the thickness of the second N-type region 104.

[0058] In this embodiment, preferably, the distance between the upper side of the second gate metal layer 1061 and the lower side of the first gate metal layer 107 is less than the distance between the lower side of the second gate metal layer 1061 and the upper side of the drift layer 102.

[0059] As Figure 1 shown, the silicon carbide VDMOS obtained by the above manufacturing method includes:

[0060] Silicon carbide substrate 101;

[0061] Drift layer 102, the lower side of the drift layer 102 is connected to the upper side of the silicon carbide substrate 101;

[0062] First N-type region 103, the lower side of the first N-type region 103 is connected to the drift layer 102;

[0063] Second N-type region 104, the lower side of the second N-type region 104 is connected to the upper side of the first N-type region 103;

[0064] P-type well region 105, the lower side of the P-type well region 105 is connected to the upper side of the second N-type region 104; an N-type source region 1051 is provided in the P-type well region 105;

[0065] Insulating dielectric layer 106, the insulating dielectric layer 106 sequentially passes through the N-type source region 1051, the P-type well region 105, the second N-type region 104, and the first N-type region 103, and the lower side of the insulating dielectric layer 106 is connected to the upper side of the drift layer 102; a second gate metal layer 1061 and a trench 1062 are provided in the insulating dielectric layer 106, and the second gate metal layer 1061 is located below the trench 1062;

[0066] First gate metal layer 107, the first gate metal layer 107 is provided in the trench 1062;

[0067] Source metal layer 108, the source metal layer 108 is respectively connected to the P-type well region 105 and the N-type source region 1051;

[0068] And a drain metal layer 109, the drain metal layer 109 is connected to the lower side of the silicon carbide substrate 101.

[0069] In another embodiment of the present invention, the doping concentration of the N-type silicon carbide substrate 101 is 1 - 5e18 cm -3 , the doping concentration of the N-type drift layer 102 is 1 - 5e16 cm -3 , the doping concentration of the first N-type region 103 is 1 - 5e17 cm -3 , the doping concentration of the second N-type region 104 is 1 - 3e18 cm -3 , the doping concentration of the P-type well region 105 is 0.8 - 1.2e19 cm -3 , the doping concentration of the N-type source region 1051 is 1 - 5e18 cm -3 , the material of the insulating dielectric layer 106 can be one or a combination of several of silicon dioxide, aluminum nitride, and hafnium dioxide;

[0070] The doping concentration of the N-type silicon carbide substrate 101 is to ensure a low-resistance ohmic contact with the drain metal layer 109 and reduce the overall on-resistance of the device; the doping concentration of the N-type drift layer 102 is a compromise between the reverse breakdown voltage and on-resistance of the device; the first N-type region 103 and the second N-type region 104 are to form a concentration gradient with the N-type drift layer 102, thereby achieving a trapezoidal distribution of the positive drain voltage in the N-type drift layer 102, the first N-type region 103, and the second N-type region 104 and improving the breakdown voltage capability of the device;

[0071] The doping concentration of the P-type well region 105 has two functions: one is to form a P-type cutoff region from the N-type source region 1051 to the second N-type region 104 to achieve cutoff and breakdown voltage under zero gate voltage conditions; the other is to form a low-resistance ohmic contact with the source metal layer 108 to form the parasitic body diode of the device and complete freewheeling when the device is not conducting. The N-type source region 1051 is to ensure the ohmic contact with the source metal layer 108 and provide electrons when forming a conductive channel during device conduction.

[0072] The thickness of the N-type silicon carbide substrate 101 of the device is 500 - 800 nm, which is to ensure the support for the subsequent structure preparation of the device; the thickness of the N-type drift layer 102 is 10 - 15 μm and is adjusted within the above range according to different requirements for the breakdown voltage characteristics of the device; the thickness of the first N-type region 103 is 3 - 6 μm, and the thickness of the second N-type region 104 is 1 - 3 μm, which is to form a concentration gradient and improve the breakdown voltage capability of the device. The lower side of the device insulating dielectric layer 106 is flush with the lower side of the first N-type region 103, and the distance between the lower side of the second gate metal layer 1061 and the insulating dielectric layer 106 is 2 μm, which is for the anti-drain voltage impact capability of the second gate metal layer 1061. The thickness of the second gate metal layer 1061 is 2 - 6 μm, and the lower side of the second gate metal layer 1061 is 1 μm higher than the upper side of the first N-type region 103, which is to achieve the control of the first gate metal layer 107 over the second gate metal layer 1061; the lower side of the first gate metal layer 107 of the device is flush with the lower side of the P-type well region 105 to ensure the gate control capability of the device. The thickness of the P-type well region 105 is 500 nm, the thickness of the N-type source region 1051 is 300 nm, and the thickness of the source metal layer 108 is 200 nm;

[0073] The first gate metal layer 107 and the second gate metal layer 1061 are constructed inside the device. The first gate metal layer 107 effectively controls the inversion of the P-type well region 105 of the device to form a conductive channel. The second gate metal layer 1061 can increase the electron concentration, thereby reducing the on-resistance of the device. There is an insulating dielectric with a thickness of 2 μm between the second gate metal layer 1061 and the drift layer 102, which can effectively suppress the gate-drain capacitance (Miller capacitance). Reducing the Miller capacitance of the device can effectively improve the switching speed of the device;

[0074] Above the N-type drift layer 102 inside the device, a first N-type region 103 and a second N-type region 104 are constructed to achieve gradient doping, which has two functions: one is to distribute the voltage from the drain of the device in a trapezoidal manner among the N-type drift layer 102, the first N-type region 103 and the second N-type region 104 when the device is turned off, so as to improve the breakdown voltage of the device; the other is that the doping concentrations of the first N-type region 103 and the second N-type region 104 are higher than that of the N-type drift layer 102, which can distribute the current towards the edge of the device and avoid current concentration inside the device.

[0075] The P-type well region 105 constructed in the device can form an ohmic contact with the source metal layer 108, eliminating the need for an additional P-type source region process and reducing the process cost.

[0076] The device structure adopts a multi-epitaxy process, which can reduce the difficulty of thick epitaxy, improve the quality of the device gate structure, reduce the defect density and improve the device reliability.

[0077] Although the specific embodiments of the present invention have been described above, those skilled in the art should understand that the specific embodiments we described are illustrative rather than restrictive of the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should be covered by the scope of the claims of the present invention.

Claims

1. A preparation method of a gradient-doped separated trench gate silicon carbide VDMOS, characterized in that: It includes the following steps: Step 1: Lateral epitaxial growth is carried out on the side of a silicon carbide substrate with a drain metal layer to form a drift layer; Step 2: Epitaxial growth is carried out on the drift layer to form a first N-type region; Step 3: Epitaxial growth is carried out on the first N-type region to form a second N-type region; Step 4: A blocking layer is formed on the second N-type region, the blocking layer is etched to form a through hole, and ion implantation is carried out to form a P-type well region; Step 5: The blocking layer in Step 4 is removed, a blocking layer is formed on the second N-type region, the blocking layer is etched to form a through hole, and ion implantation is carried out to form an N-type source region; Step 6: The blocking layer in Step 5 is removed, a blocking layer is reformed, the blocking layer is etched to form a through hole, the second N-type region and the first N-type region are etched until the upper side of the drift layer, and deposition is carried out to form a first insulating region; Step 7: The blocking layer in Step 6 is removed, a blocking layer is reformed, the blocking layer is etched to form a through hole, and the first insulating region is etched, and metal is deposited to form a second gate metal layer; Step 8: The blocking layer in Step 7 is removed, a blocking layer is reformed, the blocking layer is etched to form a through hole, and deposition is carried out to form a second insulating region. The insulating dielectric layer includes the first insulating region and the second insulating region; Step 9: The blocking layer in Step 8 is removed, a blocking layer is reformed, the blocking layer is etched to form a through hole, and the second insulating region is etched to form a trench, and metal is deposited to form a first gate metal layer; Step 10: The blocking layer in Step 9 is removed, a blocking layer is reformed, the blocking layer is etched to form a through hole, and the second N-type region is etched to the upper side of the P-type well region, and metal is deposited to form a source metal layer, and the blocking layer is removed to complete the preparation; The lower side of the first N-type region is connected to the drift layer; The lower side of the second N-type region is connected to the upper side of the first N-type region; The lower side of the P-type well region is connected to the upper side of the second N-type region; an N-type source region is provided in the P-type well region; The insulating dielectric layer sequentially passes through the N-type source region, the P-type well region, the second N-type region, and the first N-type region. The lower side of the insulating dielectric layer is connected to the upper side of the drift layer; a second gate metal layer and a trench are provided in the insulating dielectric layer, and the second gate metal layer is located below the trench; The first gate metal layer is provided in the trench; the lower side of the first N-type region is flush with the lower side of the insulating dielectric layer; the bottom of the trench and the upper side of the second N-type region are on the same plane.

2. The manufacturing method of a gradient-doped separated trench gate silicon carbide VDMOS according to claim 1, characterized in that: The thickness of the second gate metal layer is 2 - 6 μm.

3. The manufacturing method of a gradient-doped separated trench gate silicon carbide VDMOS as described in claim 1, wherein: The doping concentration of the first N-type region is greater than that of the drift layer; the doping concentration of the second N-type region is greater than that of the first N-type region; the doping concentration of the P-type well region is greater than that of the second N-type region.

4. The preparation method of a gradient-doped separated trench gate silicon carbide VDMOS according to claim 1, characterized in that: The thickness of the first N-type region is greater than or equal to the thickness of the second N-type region.

5. The manufacturing method of a gradient-doped separated trench gate silicon carbide VDMOS according to claim 1, characterized in that: The distance between the upper side of the second gate metal layer and the lower side of the first gate metal layer is less than the distance between the lower side of the second gate metal layer and the upper side of the drift layer.

6. A gradient-doped separated trench gate silicon carbide VDMOS, characterized in that, The silicon carbide VDMOS is prepared by the preparation method described in any one of claims 1 to 5.

Images