Semiconductor structure and forming method thereof

Abstract

The invention provides a semiconductor structure and a forming method thereof. The semiconductor structure comprises a substrate, a buffer layer, a first barrier layer, a channel layer and a second barrier layer. The buffer layer is disposed on the substrate. The first barrier layer is disposed on the buffer layer. The channel layer is disposed on the first barrier layer. The second barrier layer is disposed on the channel layer. Wherein the aluminum content of the first barrier layer increases along the normal direction of the substrate.

Description

Technical Field

[0001] The present invention relates to a semiconductor structure and a method for forming the same, and in particular to a semiconductor structure including a first barrier layer and a second barrier layer and a method for forming the same. Background Art

[0002] Since GaN materials have a wide band-gap and a strong polarization effect, GaN materials are widely used. For example, GaN-based semiconductors are currently widely used in power devices, such as high electron mobility transistors (HEMTs) including heterojunction structures.

[0003] However, in high electron mobility transistors, there may be a problem that the dynamic on-resistance increases with the application of higher voltage, resulting in poor dynamic characteristics. Therefore, although existing semiconductor structures and their formation methods have gradually met their intended uses, they still do not fully meet the requirements in all aspects. Therefore, there are still some problems to be overcome regarding semiconductor structures and their formation methods. Summary of the invention

[0004] The semiconductor structure of the present invention may include a first barrier layer and a second barrier layer, so that the first barrier layer and the second barrier layer serve as a bottom barrier layer and a top barrier layer, respectively. The present invention adjusts the energy level of the first barrier layer by adjusting the aluminum content of the first barrier layer. Thus, a potential well for capturing electrons is formed between the first barrier layer and the channel layer, so that the dynamic on-resistance (dynamic resistance, Ron) of the semiconductor structure of the present invention remains substantially unchanged or decreases when a higher voltage is applied, thereby improving the dynamic characteristics of the semiconductor structure.

[0005] In some embodiments, the present invention provides a semiconductor structure. The semiconductor structure includes a substrate, a buffer layer, a first barrier layer, a channel layer, and a second barrier layer. The buffer layer is disposed on the substrate. The first barrier layer is disposed on the buffer layer. The channel layer is disposed on the first barrier layer. The second barrier layer is disposed on the channel layer. The aluminum (Al) content of the first barrier layer increases along the normal direction of the substrate.

[0006] In some embodiments, the present invention provides a method for forming a semiconductor structure. The method for forming a semiconductor structure includes providing a substrate. Forming a buffer layer on the substrate. Forming a first barrier layer on the buffer layer. Forming a channel layer on the first barrier layer. Forming a second barrier layer on the channel layer. Wherein, the aluminum (Al) content of the first barrier layer increases along the normal direction of the substrate.

[0007] The semiconductor structure and the method for forming the same of the present invention can be applied to various types of electronic devices and the methods for forming the same. To make the components and advantages of the present invention more clearly understood, various embodiments are given below and described in detail with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] When read together with the drawings, the invention can be more fully understood from the following detailed description. It is worth noting that, in accordance with standard practice in the industry, the components are not drawn to scale. In fact, the size of each component can be arbitrarily enlarged or reduced for clarity.

[0009] Figure 1 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the present invention.

[0010] Figure 2 4 is a schematic diagram of the composition of the first barrier layer of the semiconductor structure according to an embodiment of the present invention.

[0011] Figure 3 FIG. 4 is a schematic diagram of an energy band of a semiconductor structure according to an embodiment of the present invention.

[0012] Figures 4 to 6 They are schematic diagrams of cyclic voltammetry analysis of a semiconductor structure according to an embodiment of the present invention.

[0013] 1: Semiconductor structure

[0014] 100:Substrate

[0015] 210: first buffer layer

[0016] 220: Superlattice layer

[0017] 230: Second buffer layer

[0018] 300: first barrier layer

[0019] 400: Channel layer

[0020] 410: Two-dimensional electron gas

[0021] 500: Second barrier layer

[0022] 600: Covering layer

[0023] 700: Protective layer

[0024] AS: Active Layer

[0025] BS: Buffer layer

[0026] BC:Buried Channel

[0027] D1: First direction

[0028] D2: Second direction

[0029] EF: Fermi level

[0030] t300:Thickness

[0031] PW: Potential Well DETAILED DESCRIPTION

[0032] The semiconductor structure of each embodiment of the present invention is described in detail below. It should be understood that the following description provides many different embodiments for implementing different aspects of some embodiments of the present invention. The specific elements and arrangements described below are only for simple and clear description of some embodiments of the present invention. Of course, these are only used as examples and are not limitations of the present invention. In addition, similar and / or corresponding element symbols may be used in different embodiments to indicate similar and / or corresponding elements to clearly describe the present invention. However, the use of these similar and / or corresponding element symbols is only for simple and clear description of some embodiments of the present invention, and does not represent any correlation between the different embodiments and / or structures discussed.

[0033] It should be understood that relative terms may be used in various embodiments, such as "lower" or "bottom" or "upper" or "top" to describe the relative relationship of one element of the diagram to another element. It is understood that if the device of the diagram is turned upside down, the element described on the "lower" side will become the element on the "upper" side. The embodiments of the present invention can be understood in conjunction with the drawings, and the drawings of the present invention are also considered to be part of the disclosure.

[0034] Furthermore, when a first material layer is said to be located on or over a second material layer, it may include a situation where the first material layer is in direct contact with the second material layer, or the first material layer and the second material layer may not be in direct contact, that is, there may be one or more other material layers between the first material layer and the second material layer. However, if the first material layer is directly located on the second material layer, it means that the first material layer and the second material layer are in direct contact.

[0035] In addition, it should be understood that the ordinal numbers used in the specification and claims, such as "first", "second", etc., to modify the elements, are not intended to imply any previous ordinal numbers of the element (or elements), nor do they represent the order of one element and another element, or the order of the manufacturing method. The use of these ordinal numbers is only used to make a component with a certain name clearly distinguishable from another component with the same name. The same words may not be used in the claims and the specification. For example, the first element in the specification may be the second element in the claims.

[0036] In some embodiments of the present invention, terms related to bonding and connection, such as "connect", "interconnect", "bond", etc., unless otherwise defined, may refer to two structures being in direct contact, or may also refer to two structures not being in direct contact, wherein another structure is disposed between the two structures. Such terms related to connection and bonding may also include situations where both structures are movable, or both structures are fixed. In addition, the terms "electrically connected" or "electrically coupled" include any direct and indirect electrical connection means.

[0037] In the text, the terms "approximate", "about", and "substantially" usually mean within 10%, or within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% of a given value or range. The quantity given here is an approximate quantity, that is, in the absence of specific instructions for "about", "approximately", or "substantially", the meaning of "about", "approximately", or "substantially" can still be implied. The term "range is between a first value and a second value" or "first value to second value" means that the range includes the first value, the second value, and other values ​​therebetween. Furthermore, there may be a certain error between any two values ​​or directions used for comparison. If the first value is equal to the second value, it implies that there may be an error of about 10%, or within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% between the first value and the second value.

[0038] Certain words are used throughout the specification and claims of the present invention to refer to specific components. It should be understood by those skilled in the art that electronic equipment manufacturers may refer to the same components by different names. It is not intended to distinguish between components that have the same function but different names. In the following specification and claims, words such as "comprise", "contain", "have" are open-ended words, so they should be interpreted as "including but not limited to...". Therefore, when the terms "comprise", "contain" and / or "have" are used in the description of the present invention, they specify the existence of corresponding parts, areas, steps, operations and / or elements, but do not exclude the existence of one or more corresponding parts, areas, steps, operations and / or elements.

[0039] It should be understood that the following embodiments may replace, reorganize, or combine components in different embodiments to complete other embodiments without departing from the spirit of the present invention. Components between embodiments may be used in any combination as long as they do not violate the spirit of the invention or conflict with each other.

[0040] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meanings as commonly understood by those skilled in the art. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and the present invention, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the embodiments of the present invention.

[0041] In the present invention, each direction is not limited to three axes such as the X-axis, Y-axis and Z-axis of the rectangular coordinate system, and can be interpreted in a broader sense. For example, the X-axis, Y-axis and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other, but are not limited thereto. For ease of explanation, in the following, the X-axis direction is the first direction D1 (width direction), and the Z-axis direction is the second direction D2 (thickness direction). In some embodiments, the cross-sectional schematic diagram described herein is a schematic diagram for observing the XZ plane (the plane formed by the first direction D1 and the second direction D2). In some embodiments, the normal direction of the substrate described herein is the second direction D2.

[0042] Reference Figure 1, which is a schematic cross-sectional view of a semiconductor structure 1 according to an embodiment of the present invention. In some embodiments, the semiconductor structure 1 may include a substrate 100, a buffer layer BS, and an active layer AS. In some embodiments, the buffer layer BS may be disposed on the substrate 100, and the active layer AS may be disposed on the buffer layer BS. Accordingly, the buffer layer BS may improve the compatibility between the substrate 100 and other elements disposed on the substrate 100, such as reducing the difference in thermal expansion coefficient and / or reducing the difference in lattice constant, thereby improving the reliability of the semiconductor structure 1. For example, the buffer layer BS may reduce the lattice dislocation between the substrate 100 and the active layer AS, thereby reducing the defects of the semiconductor structure 1. Furthermore, by adjusting the parameters such as the material and composition of the active layer AS, the electrical performance of the semiconductor structure 1 may be improved.

[0043] In some embodiments, the substrate 100 may include a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or the like. A semiconductor-on-insulator substrate includes a semiconductor layer formed on an insulator. For example, the insulating layer may include silicon oxide, silicon nitride, polysilicon, or a combination thereof, and the semiconductor substrate may include silicon, aluminum nitride (AlN), or the like. The substrate 100 may be an undoped or doped substrate, such as a substrate doped with p-type or n-type dopants. In some embodiments, the substrate 100 may include a multi-layered substrate or a gradient substrate. In some embodiments, the substrate 100 may include a semiconductor substrate or a ceramic substrate, such as a gallium nitride (GaN) substrate, a silicon carbide (SiC) substrate, an aluminum nitride substrate, or a sapphire substrate. In some embodiments, the substrate 100 may be a silicon substrate. In some embodiments, in the second direction D2, the thickness of the substrate 100 may be 500um to 3000um, for example, 500um, 1000um, 1500um, 2000um, 2500um, 3000um or any value therebetween or a numerical range consisting of any values, but the present invention is not limited thereto.

[0044] In some embodiments, a buffer layer BS is formed on the substrate 100 . The buffer layer BS may include a single layer or multiple layers. In some embodiments, the buffer layer BS may include a first buffer layer 210 , a superlattice layer 220 , and a second buffer layer 230 .

[0045] In some embodiments, the first buffer layer 210 may be formed on the substrate 100. In some embodiments, the first buffer layer 210 may be formed by a deposition process. For example, the deposition process may include metalorganic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), similar processes or combinations thereof, but the present invention is not limited thereto.

[0046] In some embodiments, the first buffer layer 210 may include a III-V compound semiconductor material, for example, a III-group nitride. The first buffer layer 210 may include gallium nitride (GaN), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), the like, or a combination thereof, but the present invention is not limited thereto. For example, the first buffer layer 210 may include aluminum nitride. In some embodiments, in the second direction D2, the thickness of the first buffer layer 210 may be 50nm to 500nm, for example, 50nm, 100nm, 150nm, 200nm, 250nm, 400nm, 500nm, or any value between the foregoing values ​​or a numerical range consisting of any value, but the present invention is not limited thereto.

[0047] In some embodiments, a superlattice layer 220 may be formed on the first buffer layer 210. In some embodiments, the superlattice layer 220 may be formed by the aforementioned deposition process. In some embodiments, the superlattice layer 220 may include a first sublayer (not shown) and a second sublayer (not shown) alternately stacked. In some embodiments, the first sublayer may be aluminum nitride and the second sublayer may be gallium nitride. In other embodiments, the first sublayer may be indium gallium arsenide (InGaAs) and the second sublayer may be gallium arsenide (GaAs). In some embodiments, in the second direction D2, the thickness of the superlattice layer 220 may be 1000nm to 3000nm, for example, 1000nm, 1200nm, 1500nm, 1800nm, 2000nm, 2500nm, 3000nm or any value between the aforementioned values ​​or a numerical range consisting of any values, but the present invention is not limited thereto.

[0048] In some embodiments, a second buffer layer 230 may be formed on the superlattice layer 220. In some embodiments, the material and formation method of the second buffer layer 230 may be the same as or different from the material and formation method of the first buffer layer 210. For example, the second buffer layer 230 may be formed by the aforementioned deposition process, and the second buffer layer 230 may include gallium nitride. In some embodiments, in the second direction D2, the thickness of the second buffer layer 230 may be 1500nm to 4000nm, for example, 1500nm, 1800nm, 2000nm, 2500nm, 3000nm, 3500nm, 4000nm or any value between the aforementioned values ​​or a numerical range consisting of any values, but the present invention is not limited thereto.

[0049] In some embodiments, a nucleation layer (not shown) may be further formed between the substrate 100 and the buffer layer BS. In some embodiments, the nucleation layer may be formed by the aforementioned deposition process. In some embodiments, the nucleation layer may include aluminum nitride, aluminum gallium nitride, other suitable materials or combinations thereof, but the present invention is not limited thereto. Accordingly, the nucleation layer may reduce or prevent the lattice constant difference between the substrate 100 and other elements disposed on the substrate 100, thereby improving the crystal quality.

[0050] like Figure 1 As shown, in some embodiments, an active layer AS is formed on the buffer layer BS. The active layer AS may include a multi-layer stack. The active layer AS may include a first barrier layer 300 , a channel layer 400 , and a second barrier layer 500 .

[0051] In some embodiments, the first barrier layer 300 is formed on the buffer layer BS. In some embodiments, the first barrier layer 300 may be formed by the aforementioned deposition process. In some embodiments, the first barrier layer 300 may include a III-V compound semiconductor material, such as a III-nitride. For example, the first barrier layer 300 may include aluminum nitride, aluminum gallium nitride, aluminum indium nitride, indium aluminum gallium nitride (InAlGaN), the like, or a combination thereof, but the present invention is not limited thereto. For example, the first barrier layer 300 may include aluminum gallium nitride.

[0052] In some embodiments, the first barrier layer 300 may be Al x Ga 1-xN, and wherein x is 0.01-0.15. For example, x may be 0.01, 0.02, 0.03, 0.04, 0.05, 0.06, 0.07, 0.08, 0.09, 0.1, 0.11, 0.12, 0.13, 0.14, 0.15, or any value therebetween or a range of values ​​consisting of any values, but the present invention is not limited thereto. In some embodiments, the first barrier layer 300 may include Al (aluminum) and Ga (gallium) in a molar ratio of 0.01-0.15:0.85-0.99, and the first barrier layer 300 may include N (nitrogen) with a valence balance that changes.

[0053] In some embodiments, the first barrier layer 300 may have a thickness t300 along the normal direction of the substrate 100. The thickness t300 of the first barrier layer 300 may be 20 nm to 300 nm. For example, the thickness t300 may be 20 nm, 25 nm, 50 nm, 75 nm, 100 nm, 125 nm, 150 nm, 200 nm, 250 nm, 300 nm, or any value therebetween or a numerical range consisting of any values, but the present invention is not limited thereto.

[0054] In some embodiments, a channel layer 400 may be formed on the first barrier layer 300. In some embodiments, the channel layer 400 may be formed by the aforementioned deposition process. In some embodiments, the channel layer 400 may include a III-V compound semiconductor material, such as a III-V nitride. For example, the channel layer 400 may include gallium nitride, aluminum gallium nitride, aluminum indium nitride, indium gallium nitride (InGaN), the like, or a combination thereof, but the present invention is not limited thereto. For example, the channel layer 400 may include gallium nitride. In some embodiments, in the second direction D2, the thickness of the channel layer 400 may be 50 nm to 500 nm, for example, 50 nm, 100 nm, 200 nm, 300 nm, 350 nm, 400 nm, 500 nm, or any value between the aforementioned values ​​or a numerical range consisting of any value, but the present invention is not limited thereto.

[0055] In some embodiments, a second barrier layer 500 may be formed on the channel layer 400. In some embodiments, the second barrier layer 500 may be formed by the aforementioned deposition process. In some embodiments, the material of the second barrier layer 500 may be the same as or different from the material of the first barrier layer 300. For example, the second barrier layer 500 may include aluminum gallium nitride.

[0056] In some embodiments, the second barrier layer 500 may be Al y Ga 1-yN, and wherein y is 0.2 to 0.25. For example, y may be 0.2, 0.21, 0.22, 0.23, 0.24, 0.25, or any value between the aforementioned values ​​or a numerical range consisting of any values, but the present invention is not limited thereto. In some embodiments, y may be greater than x. Therefore, the Al content in the second barrier layer 500 may be greater than the Al content in the first barrier layer 300. In some embodiments, the second barrier layer 500 may include Al (aluminum) and Ga (gallium) in a molar ratio of 0.2 to 0.25: 0.75 to 0.8, and the second barrier layer 500 may include N (nitrogen) that changes with valence balance.

[0057] In some embodiments, in the second direction D2, the thickness of the second barrier layer 500 may be 5 nm to 50 nm, for example, 5 nm, 10 nm, 15 nm, 20 nm, 27 nm, 30 nm, 35 nm, 40 nm, 50 nm, or any value therebetween or a numerical range consisting of any values, but the present invention is not limited thereto.

[0058] In some embodiments, a capping layer 600 may be formed on the second barrier layer 500. In some embodiments, the capping layer 600 may be formed by a deposition process. For example, the capping layer 600 may include gallium nitride. In other embodiments, the capping layer 600 may be omitted. In some embodiments, in the second direction D2, the thickness of the capping layer 600 may be 1 nm to 15 nm, for example, 1 nm, 2 nm, 5 nm, 7 nm, 10 nm, 12 nm, 15 nm, or any value therebetween or a numerical range consisting of any value, but the present invention is not limited thereto.

[0059] In some embodiments, a protective layer 700 may be formed on the cap layer 600. In some embodiments, the protective layer 700 may be formed by a deposition process. In some embodiments, the protective layer 700 may include an oxide such as silicon oxide, a nitride such as silicon nitride, an oxynitride such as silicon oxynitride, the like, or a combination thereof, but the present invention is not limited thereto. For example, the protective layer 700 may include silicon nitride. Accordingly, the protective layer 700 may protect the components located below the protective layer 700 from damage by the external environment or external force. In other embodiments, the protective layer 700 may be omitted. In some embodiments, in the second direction D2, the thickness of the protective layer 700 may be 1 nm to 15 nm, for example, 1 nm, 2 nm, 5 nm, 7 nm, 10 nm, 12 nm, 15 nm, or any value between the aforementioned values ​​or a numerical range consisting of any values, but the present invention is not limited thereto.

[0060] Hereinafter, the first barrier layer 300 is described in detail.

[0061] Reference Figure 2, which is a schematic diagram of the composition of the first barrier layer 300 of the semiconductor structure 1 according to an embodiment of the present invention.

[0062] In some embodiments, the aluminum (Al) content in the first barrier layer 300 may be increased along the normal direction (second direction D2) of the substrate 100. Accordingly, the energy level of the first barrier layer 300 may be adjusted by adjusting the Al content in the first barrier layer 300. For example, when the first barrier layer 300 is aluminum gallium nitride (AlGaN), increasing the Al content may reduce the lattice constant of the first barrier layer 300. Accordingly, the difference between the lattice constant of the first barrier layer 300 and the lattice constant of gallium nitride as the channel layer 400 increases, thereby forming a potential well between the first barrier layer 300 and the channel layer 400.

[0063] In some embodiments, the Al content in the bottom of the first barrier layer 300 adjacent to the second buffer layer 230 may be lower than the Al content in the top of the first barrier layer 300 adjacent to the channel layer 400. Accordingly, compared with the top of the first barrier layer 300 adjacent to the channel layer 400, the lattice constant difference between the bottom of the first barrier layer 300 adjacent to the second buffer layer 230 and the second buffer layer 230 is smaller, which can improve the compatibility between the second buffer layer 230 and the first barrier layer 300. Furthermore, the energy level of the potential well between the first barrier layer 300 and the channel layer 400 can be adjusted by adjusting the lattice constant difference between the first barrier layer 300 and the channel layer 400.

[0064] Continuing from the above, along the second direction D2, when the first barrier layer 300 may be Al x Ga 1-x N, and when the Al content in the first barrier layer 300 increases from the first content to the second content, x may be a variable value. Wherein, x of the first content may be 0.01-0.03, and x of the second content may be 0.06-0.15. In some embodiments, the Al content in the first barrier layer 300 may be gradually increased to gradually increase the lattice constant of the first barrier layer 300. For example, the Al content in the first barrier layer 300 may be gradually increased, linearly gradually increased, nonlinearly gradually increased, or may include multiple sub-barrier layers. Accordingly, the compatibility between the second buffer layer 230 and the first barrier layer 300 may be improved, and the reliability of the first barrier layer 300 as a whole (throughout) may be improved.

[0065] like Figure 2 As shown, in some embodiments, x of the bottom of the first barrier layer 300 adjacent to the second buffer layer 230 may be represented by a, so that the bottom of the first barrier layer 300 may be represented by Al a Ga 1-aN, and a may be 0.01 to 0.03. For example, a may be 0.01, 0.015, 0.02, 0.025, 0.03, or any value between the aforementioned values ​​or a numerical range consisting of any values, but the present invention is not limited thereto. Figure 2 As shown, in some embodiments, the x of the top of the first barrier layer 300 adjacent to the channel layer 400 may be represented by b, so that the top of the first barrier layer 300 may be represented as Al b Ga 1-b N, and wherein b is greater than a, and b may be 0.06 to 0.15. For example, b may be 0.06, 0.07, 0.08, 0.09, 0.1, 0.11, 0.12, 0.13, 0.14, 0.15, or any value therebetween or a numerical range consisting of any values, but the present invention is not limited thereto.

[0066] In some embodiments, the difference between the second content x and the first content x in the first barrier layer 300 is 0.03 to 0.15. Figure 2 As shown, the difference of b minus a (ba) may be 0.03 to 0.15. For example, the difference of b minus a may be 0.03, 0.04, 0.05, 0.06, 0.07, 0.08, 0.09, 0.1, 0.11, 0.12, 0.13, 0.14, 0.15 or any value therebetween or a numerical range consisting of any value, but the present invention is not limited thereto.

[0067] In some embodiments, the ratio of the second content to the first content in the first barrier layer 300 may be 2 to 15. In other words, Figure 2 As shown, the ratio of b to a (b / a) may be 2 to 15. For example, the ratio of b to a may be 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, or any value therebetween or a range of any values, but the present invention is not limited thereto.

[0068] In some embodiments, when the Al content in the first barrier layer 300 is greater, the thickness t300 of the first barrier layer 300 is smaller, thereby controlling the total Al content in the first barrier layer 300. In some embodiments, when the gradient of the change of the Al content in the first barrier layer 300 is greater, such as the difference of b minus a is greater, the thickness t300 of the first barrier layer 300 is smaller, thereby controlling the total Al content in the first barrier layer 300. For example, when a is 0.02 and b is 0.08, the thickness t300 of the first barrier layer 300 may be 50 nm. For example, when a is 0.02 and b is 0.1, the thickness t300 of the first barrier layer 300 may be 20 nm.

[0069] Reference Figure 3 , which is an energy level diagram of a semiconductor structure 1 according to an embodiment of the present invention. In some embodiments, since the Al content in the second barrier layer 500 is greater than the Al content in the first barrier layer 300, and the Al content in aluminum gallium nitride (AlGaN) affects the lattice constant of aluminum gallium nitride, when the Al content in aluminum gallium nitride (AlGaN) is higher, the lattice constant difference between aluminum gallium nitride and gallium nitride is greater, thereby generating a deeper potential energy well. In some embodiments, when observing the energy level diagram, the potential energy well between the second barrier layer 500 and the channel layer 400 (such as Figure 3 The position of the two-dimensional electron gas 410 as shown may be lower than the potential well PW between the first barrier layer 300 and the channel layer 400. In some embodiments, the energy level of the potential well PW may be higher than the energy level of the two-dimensional electron gas 410.

[0070] like Figure 3 As shown, in some embodiments, the energy level of the potential well PW between the first barrier layer 300 and the channel layer 400 may be higher than the Fermi level E F In some embodiments, a buried channel BC may be present at the interface between the first barrier layer 300 and the channel layer 400, and the energy level of the buried channel BC may be higher than the Fermi level E F Accordingly, the problem that the potential well PW generates an additional current path in the semiconductor structure 1 and causes the semiconductor structure 1 to be unable to maintain a normally off state can be avoided.

[0071] In detail, due to the difference in lattice constants between GaN as the channel layer 400 and AlGaN as the second barrier layer 500, a two-dimensional electron gas (2DEG) 410 is formed near the top surface of the channel layer 400 in the semiconductor structure 1. The two-dimensional electron gas 410 may be formed in the channel layer 400 and adjacent to the second barrier layer 500. Therefore, the two-dimensional electron gas 410 can provide conductive carriers and serve as a current path of the semiconductor structure 1.

[0072] When the Al content in the aluminum gallium nitride is higher, the on-resistance required for the semiconductor structure 1 is lower, thereby improving the conductivity of the semiconductor structure 1, and the semiconductor structure 1 may be in a normally on state. Therefore, when no voltage (0V) is applied, electrons may be trapped in the buffer layer BS. In order to keep the semiconductor structure 1 in a normally off state, a negative voltage may be further applied to the semiconductor structure 1 until the semiconductor structure 1 is turned off. In the off state with a negative voltage applied, electrons may be trapped at the interface between layers or in the middle of the layers, such as the electrons may be trapped at the interface between the cap layer 600 and the second barrier layer 500, or in the buffer layer BS. Furthermore, in a semi-on state, electrons may be trapped at the interface between the cap layer 600 and the second barrier layer 500, at the interface between the second barrier layer 500 and the channel layer 400, or in the buffer layer BS. Therefore, the electrons in the semiconductor structure 1 may be trapped at different positions under different operating conditions. However, these trapped electrons will increase the dynamic resistance (R) of the semiconductor structure 1 when a higher voltage is applied to the semiconductor structure 1. on ), resulting in a decrease in on-state current and a reduction in dynamic characteristics.

[0073] Accordingly, the present invention adjusts the energy level of the first barrier layer 300 by adjusting the Al content of the first barrier layer 300, so that the potential well PW is formed between the first barrier layer 300 and the channel layer 400, and the aforementioned trapped electrons are more likely to be captured by the potential well PW. In other words, the potential well PW can change the position where the electrons are captured, and release (discharge) the electrons captured by the interface (interface) and / or the buffer layer BS.

[0074] Reference Figures 4 to 6 , which are schematic diagrams of cyclic voltammetry analysis of a semiconductor structure 1 according to an embodiment of the present invention. In some embodiments, the presence of a potential well PW or a buried channel BC in the semiconductor structure 1 can be determined by observing a cyclic voltammetry (CV) diagram. Figure 4 As shown, the X-axis is the gate voltage (V g ) (unit: volt (V)), and the Y axis is the gate-source capacitance (C gs ) (unit: picofarad (pF)) analysis diagram (where C gs (F) represents forward scanning, C gs(R) represents reverse scanning), two threshold voltages corresponding to the buried channel BC and the two-dimensional electron gas 410 can be observed, thereby confirming the presence of the buried channel BC in the semiconductor structure 1. Figure 5 As shown, the X-axis is the drain-source voltage (V d , V ds ) (unit: volt (V)), and the Y axis is current (I d )(unit: ampere (A)), it can be observed that at 0 volts (V) there is a current of E-7 to E-10 amperes (A), thereby confirming the presence of a buried channel BC in the semiconductor structure 1.

[0075] In some embodiments, the stress resistance (R s ) and initial resistance (initial resistance, R i ) ratio (R s / R i ) to determine the dynamic characteristics of the semiconductor structure 1. In the present invention, Figure 6 As shown, when the voltage applied to the semiconductor structure 1 increases from 1V to 800V, the ratio (R s / R i ) may be less than 1.2. For example, the ratio (R s / R i ) may be less than 1.2, 1.15, 1.13, 1.1, 1.07, 1.06, 1.05, 1.04, 1.03, 1.02, 1.01, 1, 0.99 or less. For example, when the voltage applied to the semiconductor structure 1 is increased from 300V to 600V, the ratio (R s / R i ) may be substantially less than or equal to 1. Accordingly, when the voltage applied to the semiconductor structure 1 is increased, the on-resistance is reduced and the on-current is increased, thereby improving the dynamic characteristics of the semiconductor structure. In addition, the energy consumption of the semiconductor structure 1 can be reduced.

[0076] In some embodiments, the semiconductor structure 1 of the present invention may be a high electron mobility transistor, or further processes may be performed on the semiconductor structure 1 to form a high electron mobility transistor.

[0077] Accordingly, the present invention forms a potential well for capturing electrons between the first barrier layer and the channel layer by adjusting the aluminum content of the first barrier layer, thereby releasing the electrons captured by the interface and / or the buffer layer, thereby improving the dynamic characteristics of the semiconductor structure of the present invention. For example, the potential well of the present invention forms a buried channel below the channel layer (that is, between the channel layer and the first barrier layer), and the energy level of the potential well is higher than the energy level of the two-dimensional electron gas, and the energy level of the potential well is also higher than the Fermi level. Therefore, as a higher voltage is applied to the semiconductor structure of the present invention, the dynamic on-resistance of the semiconductor structure of the present invention can be substantially unchanged or reduced, thereby improving the dynamic characteristics of the semiconductor structure.

[0078] The scope of protection of the present invention is not limited to the processes, machines, manufactures, material compositions, devices, methods and steps in the specific embodiments described in the specification. Any technician in the relevant technical field can understand the existing or future developed processes, machines, manufactures, material compositions, devices, methods and steps from the disclosure of the present invention. As long as they can implement substantially the same functions or obtain substantially the same results in the embodiments described herein, they can be used according to the present invention. Therefore, the scope of protection of the present invention includes the aforementioned processes, machines, manufactures, material compositions, devices, methods and steps. Any embodiment or claim of the present invention is not required to achieve all the purposes, advantages and / or features described in the present invention.

[0079] Several embodiments are summarized above so that those skilled in the art can better understand the concepts of the embodiments of the present invention. Those skilled in the art should understand that they can design or modify other processes and structures based on the embodiments of the present invention to achieve the same purposes and / or advantages as the embodiments herein. Those skilled in the art should also understand that such equivalent processes and structures do not deviate from the spirit and scope of the present invention, and that they can make various changes, substitutions and replacements without violating the spirit and scope of the present invention.

Claims

1. A semiconductor structure, characterized in that: include: a substrate; a buffer layer disposed on the substrate; a first barrier layer disposed on the buffer layer; a channel layer disposed on the first barrier layer; and a second barrier layer disposed on the channel layer, The aluminum content of the first barrier layer increases along the normal direction of the substrate.

2. The semiconductor structure according to claim 1, wherein: The first barrier layer includes AlxGa1-xN, and x is 0.01-0.

15.

3. The semiconductor structure according to claim 2, wherein: The Al content in the first barrier layer increases from a first content to a second content, and x of the first content is 0.01-0.03, and x of the second content is 0.06-0.

15.

4. The semiconductor structure according to claim 2, characterized in that The Al content in the first barrier layer increases from a first content to a second content, and the difference between the second content and the first content x is 0.03-0.

15.

5. The semiconductor structure according to claim 2, wherein: The Al content in the first barrier layer increases from a first content to a second content, and the ratio of the second content to the first content is 2-15.

6. The semiconductor structure according to claim 1, wherein: Along the normal direction of the substrate, the first blocking layer has a thickness of 20 nm to 300 nm.

7. The semiconductor structure according to claim 1, wherein: A buried channel is provided at the junction of the first barrier layer and the channel layer, and the energy level of the buried channel is higher than the Fermi level.

8. The semiconductor structure according to claim 1, wherein: Also includes: A capping layer is disposed on the second barrier layer.

9. The semiconductor structure according to claim 1, wherein: The buffer layer includes: a first buffer layer disposed on the substrate; a superlattice layer disposed on the first buffer layer; A second buffer layer is disposed on the superlattice layer.

10. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; providing a buffer layer on the substrate; providing a first barrier layer on the buffer layer; providing a channel layer on the first barrier layer; providing a second barrier layer on the channel layer, The aluminum content of the first barrier layer increases along the normal direction of the substrate.

Images