Semiconductor device and forming method thereof

Abstract

Semiconductor devices and methods of forming the same are provided. The semiconductor device includes a substrate, a channel layer, a barrier layer, a gate electrode, a source electrode, a drain electrode, and an adjustment structure. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The gate electrode is disposed on the barrier layer. The source electrode and the drain electrode are respectively disposed on opposite sides of the gate electrode. The adjusting structure is arranged between the gate electrode and the drain electrode. Wherein a width of the adjustment structure decreases in a direction from the gate electrode toward the drain electrode.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for forming the same, and more particularly to a semiconductor device including an adjustment structure and a method for forming the same. Background Art

[0002] Since GaN materials have a wide band-gap and a strong polarization effect, GaN materials are widely used. For example, GaN-based semiconductors are currently widely used in power devices, such as high electron mobility transistors (HEMTs) including heterojunction structures.

[0003] However, in high electron mobility transistors, there may be excessive concentration of electric field distribution, resulting in uneven electric field distribution, insufficient reliability, insufficient breakdown voltage, and other problems. Therefore, although existing semiconductor devices and their formation methods have gradually met their intended uses, they still do not fully meet the requirements in all aspects. Therefore, there are still some problems to be overcome regarding semiconductor devices and their formation methods. Summary of the invention

[0004] The present disclosure adjusts the electric field distribution in the drift region by setting a gradient adjustment structure between the gate electrode and the drain electrode. For example, in a top view, the width of the gradient adjustment structure can decrease along the direction from the gate electrode toward the drain electrode, so that the electric field distribution in the drift region can be gradually adjusted. For example, the adjustment structure can avoid excessive concentration of the electric field at the edge of the gate electrode and / or can avoid insufficient two-dimensional electron gas near the drain electrode. For example, the adjustment structure may include a material (e.g., a material that provides holes) that can be used to balance the charge of carriers (e.g., electrons) in the channel region, or may include a dielectric material. Thus, the gradient adjustment structure can reduce excessive concentration of the electric field distribution and make the electric field distribution more uniform, improve reliability and / or improve breakdown voltage.

[0005] In some embodiments, the present disclosure provides a semiconductor device. The semiconductor device includes a substrate, a channel layer, a barrier layer, a gate electrode, a source electrode, a drain electrode, and an adjustment structure. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The gate electrode is disposed on the barrier layer. The source electrode and the drain electrode are respectively disposed on opposite sides of the gate electrode. The adjustment structure is disposed between the gate electrode and the drain electrode. The width of the adjustment structure decreases along the direction from the gate electrode toward the drain electrode.

[0006] In some embodiments, the present disclosure provides a method for forming a semiconductor device. Provide a substrate. Form a channel layer on the substrate. Form a barrier layer on the channel layer. Form a gate electrode on the barrier layer. Form a source electrode and a drain electrode on opposite sides of the gate electrode. Form an adjustment structure between the gate electrode and the drain electrode. Wherein, the width of the adjustment structure decreases along a direction from the gate electrode toward the drain electrode.

[0007] The semiconductor device and the method for forming the same disclosed herein can be applied to various types of electronic devices and the methods for forming the same. To make the components and advantages of the present disclosure more clearly understandable, various embodiments are given below and described in detail with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] When with Figure 1 The disclosure can be more fully understood from the following detailed description when reading together. It is worth noting that, in accordance with standard practice in the industry, the components are not drawn to scale. In fact, the size of each component can be arbitrarily enlarged or reduced for the sake of clarity.

[0009] Figures 1 to 3 The figures are cross-sectional schematic diagrams of different stages of a method for forming a semiconductor device according to an embodiment of the present disclosure.

[0010] Figure 4 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure.

[0011] Figure 5 is a schematic top view of a semiconductor device according to an embodiment of the present disclosure.

[0012] Figure 6 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure.

[0013] Figure 7 and Figure 8 The figures are cross-sectional schematic diagrams of different stages of a method for forming a semiconductor device according to an embodiment of the present disclosure.

[0014] Fig. 9 and Fig.10The figures are cross-sectional schematic diagrams of different stages of a method for forming a semiconductor device according to an embodiment of the present disclosure.

[0015] Fig.11 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure.

[0016] Fig.12 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure.

[0017] Fig.13 is a schematic top view of a semiconductor device according to an embodiment of the present disclosure.

[0018] Fig.14 is a schematic top view of a semiconductor device according to an embodiment of the present disclosure.

[0019] Fig.15 is a schematic top view of a semiconductor device according to an embodiment of the present disclosure.

[0020] Fig.16 is a schematic top view of a semiconductor device according to an embodiment of the present disclosure.

[0021] Fig.17 is a schematic top view of a semiconductor device according to an embodiment of the present disclosure.

[0022] Description of Figure Numbers:

[0023] 1,2,3,4,5,6,7,8,9,10:Semiconductor devices

[0024] 100:Substrate

[0025] 200: Buffer layer

[0026] 300: Channel layer

[0027] 310: Two-dimensional electron gas

[0028] 400: Barrier layer

[0029] 410: concave part

[0030] 500: Compound semiconductor layer

[0031] 600: Adjust the structure

[0032] 600a,600b,600c,600d,600e: Substructure

[0033] 700: Gate electrode

[0034] 710: Connector

[0035] 710a, 710b, 710c, 710d, 710e: Sub-connectors

[0036] 800: Source electrode

[0037] 900: Drain electrode

[0038] A-A', B-B', C-C': Section

[0039] a1,a2,a3,a4:part

[0040] D1: First direction

[0041] D2: Second direction

[0042] D3: Third direction

[0043] DR: Drift Zone

[0044] Ea: End

[0045] s1,s2,s3: spacing

[0046] t1: first thickness

[0047] t2: second thickness

[0048] w: width

[0049] w1: first width

[0050] w2: second width DETAILED DESCRIPTION

[0051] The following is a detailed description of the semiconductor device of each embodiment of the present disclosure. It should be understood that the following description provides many different embodiments for implementing different aspects of some embodiments of the present disclosure. The specific elements and arrangements described below are only for simple and clear description of some embodiments of the present disclosure. Of course, these are only used as examples and not as limitations on the present disclosure. In addition, similar and / or corresponding element symbols may be used in different embodiments to indicate similar and / or corresponding elements to clearly describe the present disclosure. However, the use of these similar and / or corresponding element symbols is only for the simple and clear description of some embodiments of the present disclosure, and does not represent any correlation between the different embodiments and / or structures discussed.

[0052] It should be understood that relative terms, such as "lower" or "bottom" or "upper" or "top", may be used in various embodiments to describe the relative relationship of one element of the drawings to another element. It is understood that if the device in the drawings is turned upside down, the element described as being on the "lower" side will become the element on the "upper" side. The embodiments of the present disclosure may be used in conjunction with the attached drawings. Figure 1It is also understood that the drawings of the present disclosure are also considered as part of the disclosure.

[0053] Furthermore, when a first material layer is said to be located on or over a second material layer, it may include a situation where the first material layer is in direct contact with the second material layer, or the first material layer and the second material layer may not be in direct contact, that is, there may be one or more other material layers between the first material layer and the second material layer. However, if the first material layer is directly located on the second material layer, it means that the first material layer and the second material layer are in direct contact.

[0054] In addition, it should be understood that the ordinal numbers used in the specification and claims, such as "first", "second", etc., to modify the elements, are not intended to imply any previous ordinal numbers of the element (or elements), nor do they represent the order of one element and another element, or the order of the manufacturing method. The use of these ordinal numbers is only used to make a component with a certain name clearly distinguishable from another component with the same name. The claims and the specification may not use the same words, for example, the first element in the specification may be the second element in the claims.

[0055] In some embodiments of the present disclosure, terms such as "connect", "interconnect", "bond", etc., unless otherwise defined, may refer to two structures being in direct contact, or may refer to two structures not being in direct contact, with other structures disposed between the two structures. Such terms may also include situations where both structures are movable or both structures are fixed. In addition, the terms "electrically connected" or "electrically coupled" include any direct and indirect electrical connection means.

[0056] In the text, the terms "approximate", "about", and "substantially" usually mean within 10%, or within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% of a given value or range. The quantity given here is an approximate quantity, that is, in the absence of specific instructions for "about", "approximately", or "substantially", the meaning of "about", "approximately", or "substantially" can still be implied. The term "range is between a first value and a second value" or "first value to second value" means that the range includes the first value, the second value, and other values ​​therebetween. Furthermore, there may be a certain error between any two values ​​or directions used for comparison. If the first value is equal to the second value, it implies that there may be an error of about 10%, or within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% between the first value and the second value.

[0057] Certain words are used throughout the specification and claims of this disclosure to refer to specific components. It should be understood by those skilled in the art that electronic equipment manufacturers may refer to the same components by different names. This document is not intended to distinguish between components that have the same function but different names. In the following specification and claims, words such as "comprise", "contain", and "have" are open-ended words, so they should be interpreted as "including but not limited to..." Therefore, when the terms "comprise", "contain" and / or "have" are used in the description of this disclosure, they specify the existence of corresponding parts, areas, steps, operations and / or elements, but do not exclude the existence of one or more corresponding parts, areas, steps, operations and / or elements.

[0058] It should be understood that the following embodiments may replace, reorganize, or combine components in different embodiments to implement other embodiments without departing from the spirit of the present disclosure. Components between embodiments may be used in any combination as long as they do not violate the spirit of the invention or conflict with each other.

[0059] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meanings as commonly understood by those skilled in the art. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and the present disclosure, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the embodiments of the present disclosure.

[0060] In the present disclosure, each direction is not limited to three axes of a rectangular coordinate system such as the X-axis, the Y-axis, and the Z-axis, and can be interpreted in a broader sense. For example, the X-axis, the Y-axis, and the Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other, but are not limited thereto. For ease of explanation, in the following, the X-axis direction is the first direction D1 (length direction), the Y-axis direction is the second direction D2 (width direction), and the Z-axis direction is the third direction D3 (thickness direction). In some embodiments, the top view schematic diagram described herein is a schematic diagram for observing the XY plane (the plane formed by the first direction D1 and the second direction D2), and the cross-sectional schematic diagram described herein is a schematic diagram for observing the XZ plane (the plane formed by the first direction D1 and the third direction D3). In some embodiments, the normal direction of the substrate described herein is the third direction D3.

[0061] Reference Figure 1 , which is a cross-sectional schematic diagram of different stages of a method for forming a semiconductor device according to an embodiment of the present disclosure. Figure 1As shown, in some embodiments, a substrate 100 may be provided. In some embodiments, the substrate 100 may include a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or the like. A semiconductor-on-insulator substrate includes a semiconductor layer formed on an insulator. For example, the insulating layer may include silicon oxide, silicon nitride, polysilicon, or a combination thereof, and the semiconductor substrate may include silicon, aluminum nitride (AlN), or the like. The substrate 100 may be an undoped or doped substrate, such as a substrate doped with p-type or n-type dopants. In some embodiments, the substrate 100 may include a multi-layered substrate or a gradient substrate. In some embodiments, the substrate 100 may include a semiconductor substrate or a ceramic substrate, such as a gallium nitride (GaN) substrate, a silicon carbide (SiC) substrate, an aluminum nitride substrate, or a sapphire substrate. In some embodiments, the substrate 100 may be a silicon substrate.

[0062] like Figure 1 As shown, in some embodiments, a buffer layer 200 may be formed on the substrate 100 to enhance the compatibility between the substrate 100 and other elements disposed on the substrate 100, such as reducing the difference in thermal expansion coefficient and / or reducing the difference in lattice constant. In some embodiments, the buffer layer 200 may include a III-V compound semiconductor material, such as a III-V nitride. For example, the buffer layer 200 may include gallium nitride (GaN), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), the like, or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the buffer layer 200 may be formed by a deposition process. For example, the deposition process may be chemical vapor deposition (CVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), the like, or a combination thereof, but the present disclosure is not limited thereto.

[0063] In some embodiments, a nucleation layer may be further disposed between the substrate 100 and the buffer layer 200 to reduce the lattice difference between the substrate 100 and other layers disposed on the substrate 100, thereby improving the quality and reliability of epitaxy. In some embodiments, the nucleation layer may include aluminum nitride (AlN), aluminum gallium nitride (AlGaN), the like, or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the nucleation layer may be formed by a deposition process. In other embodiments, the buffer layer 200 may be omitted.

[0064] like Figure 1 As shown, in some embodiments, a channel layer 300 may be formed on the substrate 100. Specifically, the channel layer 300 may be formed on the buffer layer 200. In some embodiments, the channel layer 300 may include a III-V compound semiconductor material, such as a III-V nitride, but the present disclosure is not limited thereto. For example, the channel layer 300 may include gallium nitride (GaN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), indium aluminum gallium nitride (InAlGaN), the like or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the channel layer 300 may be gallium nitride. In some embodiments, the channel layer 300 may be formed by a deposition process.

[0065] like Figure 1 As shown, in some embodiments, a barrier layer 400 may be formed on the channel layer 300. In some embodiments, the barrier layer 400 may include a III-V compound semiconductor material, such as a III-V nitride, but the present disclosure is not limited thereto. For example, the barrier layer may include aluminum nitride (AlN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium aluminum gallium nitride (InAlGaN), the like, or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the barrier layer 400 may be aluminum gallium nitride. In some embodiments, the barrier layer 400 may be formed by a deposition process. Since there is a heterogeneous interface between the channel layer 300 and the barrier layer 400, and there is a difference in lattice constants between the channel layer 300 and the barrier layer 400, a two-dimensional electron gas (2DEG) may be formed (as described later). Figure 3 The two-dimensional electron gas 310 is shown near the top surface of the channel layer 300 and serves as a current path.

[0066] Reference Figure 2 , which is a cross-sectional schematic diagram of different stages of a method for forming a semiconductor device according to an embodiment of the present disclosure. Figure 2As shown, in some embodiments, a compound semiconductor layer 500 may be formed on the barrier layer 400, so that the compound semiconductor layer 500 may be disposed between the barrier layer 400 and a gate electrode formed subsequently. In some embodiments, the compound semiconductor layer 500 may be formed by a deposition process. In some embodiments, the compound semiconductor layer 500 may be a semiconductor material doped with a p-type dopant. In some embodiments, the compound semiconductor layer 500 may include p-doped gallium nitride (p-GaN). Accordingly, since the compound semiconductor layer 500 may suppress the formation of a two-dimensional electron gas at a position corresponding to the compound semiconductor layer 500 (for example, located below the compound semiconductor layer 500), the two-dimensional electron gas is depleted. Therefore, providing the compound semiconductor layer 500 may make the semiconductor device normally-off.

[0067] like Figure 2 As shown, in some embodiments, an adjustment structure 600 may be formed to make the two-dimensional electron gas discontinuous or to partially reduce the concentration of the two-dimensional electron gas, thereby making the electric field distribution more uniform. Figure 3 The two-dimensional electron gas in the drift region DR) is discontinuous, or the concentration of the two-dimensional electron gas in the drift region is reduced.

[0068] In some embodiments, the adjustment structure 600 may include a material that provides holes. In some embodiments, the adjustment structure 600 may include a p-type doped compound semiconductor material (such as a subsequent Figure 3 The semiconductor device 1 or Figure 6 The semiconductor device 2 shown in FIG. 1 ) or the adjustment structure 600 may include a halogen doped compound semiconductor (as described later) Figure 8 The semiconductor device 3 shown in FIG. 3 ). Accordingly, since the adjustment structure 600 can provide holes, and the carriers in the channel region are electrons (i.e., electrons in the two-dimensional electron gas), the holes provided by the adjustment structure 600 can be used to neutralize the electrons in the channel region, thereby making the carriers in the channel region depleted. Therefore, the electric field distribution can be made more uniform by using the material that provides holes.

[0069] In other embodiments, the adjustment structure 600 may include a dielectric material (such as a Fig.10 The semiconductor device 4 or Fig.11The semiconductor device 5 is shown in the figure, so that the dielectric material destroys the formation of the two-dimensional electron gas or physically interrupts the two-dimensional electron gas. Therefore, the electric field distribution can be made more uniform by the dielectric material.

[0070] In the following, it is described as an example that the adjustment structure 600 may include a p-type doped compound semiconductor.

[0071] like Figure 2 As shown, in some embodiments, the adjustment structure 600 may be formed on the barrier layer 400, and the adjustment structure 600 may be adjacent to the compound semiconductor layer 500. In some embodiments, the adjustment structure 600 and the compound semiconductor layer 500 may be spaced apart by a distance. In some embodiments, the adjustment structure 600 may be formed by a deposition process. In some embodiments, the compound semiconductor layer 500 and the adjustment structure 600 may be formed in the same process, or may be formed separately in different processes. In some embodiments, the adjustment structure 600 may include p-doped gallium nitride (p-GaN).

[0072] Reference Figure 3 , which is a cross-sectional schematic diagram of different stages of a method for forming a semiconductor device 1 according to an embodiment of the present disclosure. Figure 3 As shown, in some embodiments, a gate electrode 700 may be formed on the barrier layer 400. Specifically, the gate electrode 700 may be formed on the compound semiconductor layer 500. In some embodiments, the gate electrode 700 may include a conductive material, for example, the conductive material may include a metal, a metal nitride, a semiconductor material, the like, or a combination thereof, but the disclosure is not limited thereto. In some embodiments, the metal may include gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), titanium nitride (TiN), the like, or a combination thereof, but the disclosure is not limited thereto. The semiconductor material may include polycrystalline silicon or polycrystalline germanium. The conductive material may be formed by chemical vapor deposition, sputtering, resistance heating evaporation, electron beam evaporation, the like, or a combination thereof, but the disclosure is not limited thereto.

[0073] like Figure 3As shown, in some embodiments, a source electrode 800 and a drain electrode 900 may be formed on opposite sides of the gate electrode 700 to obtain a semiconductor device 1. In some embodiments, the source electrode 800 and the drain electrode 900 may be in contact with the channel layer 300, respectively. In some embodiments, the materials and formation methods of the source electrode 800 and the drain electrode 900 may be the same as or different from those of the gate electrode 700. In some embodiments, the source electrode 800 may be formed on one side of the gate electrode 700, and the drain electrode 900 may be formed on the other side of the gate electrode 700. In some embodiments, the source electrode 800 and the drain electrode 900 may penetrate the barrier layer 400 to contact the channel layer 300. Among them, the region between the gate electrode 700 and the drain electrode 900 may be referred to as a drift region DR.

[0074] like Figure 3 As shown (that is, as follows Figure 5 In some embodiments, the adjustment structure 600 may be disposed between the gate electrode 700 and the drain electrode 900. In some embodiments, the adjustment structure 600 may be disposed in the drift region DR. Accordingly, since the holes provided by the adjustment structure 600 can be used to neutralize the electrons in the channel region, the electric field distribution in the drift region DR can be adjusted by the adjustment structure 600. In some embodiments, Figure 3 As shown, the two-dimensional electron gas 310 may be substantially absent below the adjustment structure 600. In other words, the concentration of the two-dimensional electron gas 310 below the adjustment structure 600 may be substantially 0. In other embodiments, the concentration of the two-dimensional electron gas 310 below the adjustment structure 600 may be less than the concentration of the two-dimensional electron gas 310 between the compound semiconductor layer 500 and the adjustment structure 600, and the concentration of the two-dimensional electron gas 310 below the adjustment structure 600 may be greater than 0.

[0075] Reference Figure 4 , which is a cross-sectional view of a semiconductor device 1 according to an embodiment of the present disclosure. In some embodiments, the adjustment structure 600 may not be shown. Therefore, it is possible to ensure that the semiconductor device 1 has sufficient two-dimensional electron gas 310 as a current path that is not affected by the adjustment structure 600.

[0076] Reference Figure 5 , which is a schematic top view of a semiconductor device 1 according to an embodiment of the present disclosure. Figure 5 The section A-A' of Figure 3 In, and Figure 5 The section B-B' of Figure 4 For the sake of explanation, Figure 5The display substrate 100 , the barrier layer 400 , the adjustment structure 600 , the gate electrode 700 , the source electrode 800 and the drain electrode 900 , and other elements are omitted.

[0077] like Figure 5 As shown, in some embodiments, the gate electrode 700, the source electrode 800 and the drain electrode 900 extend along the second direction D2 respectively, so the extension direction of the gate electrode 700, the source electrode 800 and the drain electrode 900 can be the second direction D2. In some embodiments, the gate electrode 700, the source electrode 800 and the drain electrode 900 are arranged in a spaced relationship from each other in the first direction D1.

[0078] In some embodiments, the width w of the adjustment structure 600 decreases along the first direction D1 from the gate electrode 700 toward the drain electrode 900. In some embodiments, the width w of the adjustment structure 600 decreases gradually along the first direction D1. For example, the gradual decrease may include a gradual decrease, a gradient decrease, a linear decrease, or a nonlinear decrease. In some embodiments, the width w of the adjustment structure 600 adjacent to the gate electrode 700 may be greater than the width w of the adjustment structure 600 adjacent to the drain electrode 900. Accordingly, the adjustment structure 600 may reduce the concentration of the two-dimensional electron gas adjacent to the gate electrode 700 more than that adjacent to the drain electrode 900, making the adjacent gate electrode 700 more depleted. Furthermore, since the width w of the adjustment structure 600 decreases gradually, the electric field distribution may be adjusted smoothly.

[0079] In detail, the electric field in the semiconductor device is often concentrated at the edge of the gate electrode 700, especially at the edge of the gate electrode 700 near the drain electrode 900. Therefore, the electric field peak also often appears at the edge of the gate electrode 700 near the drain electrode 900, resulting in the problem of excessive concentration of the electric field distribution in the semiconductor device and poor reliability. In addition, since the breakdown voltage is the integral sum under the electric field distribution curve, there is often a problem of insufficient breakdown voltage. However, since the width w of the adjustment structure 600 of the present disclosure is large near the gate electrode 700, the electric field near the gate electrode 700 can be effectively reduced, thereby making the electric field distribution uniform, improving reliability and / or improving the breakdown voltage. Furthermore, since the width w of the adjustment structure 600 of the present disclosure decreases along the first direction D1 from the gate electrode 700 toward the drain electrode 900, it can provide sufficient two-dimensional electron gas 310 as a current path.

[0080] In some embodiments, when viewed from a top view, the adjustment structure 600 may be a trapezoid, a triangle, a convex shape, a hill shape, a step shape, the above shapes with arc angles, or other suitable shapes, but the present disclosure is not limited thereto.

[0081] In some embodiments, along Figure 5 Observing from the cross section CC' of FIG. 6 , the adjustment structure 600 may include a plurality of substructures 600a-600e. In some embodiments, each of the plurality of substructures 600a-600e is arranged at intervals along the extension direction of the gate electrode 700 (i.e., the second direction D2). Accordingly, since the plurality of substructures 600a-600e are physically separated from each other in the second direction D2, sufficient two-dimensional electron gas 310 can be provided as a current path. In some embodiments, along Figure 5 When observing the cross section CC' of FIG. 1 , the region with electrons and the depletion region appear alternately in the drift region DR along the second direction D2, so that it can be similar to a PN junction.

[0082] Hereinafter, the same or similar element symbols or descriptions are omitted.

[0083] Reference Figure 6 , which is a cross-sectional view of a semiconductor device 2 according to an embodiment of the present disclosure. Figure 6 As shown, in some embodiments, the adjustment structure 600 may include p-type doped gallium nitride (p-GaN), and the adjustment structure 600 may be disposed in the channel layer 300. In some embodiments, the adjustment structure 600 may be disposed on the interface between the buffer layer 200 and the channel layer 300. Accordingly, the adjustment structure 600 may make the two-dimensional electron gas 310 above the adjustment structure 600 discontinuous or partially reduce the concentration of the two-dimensional electron gas 310, so as to make the electric field distribution more uniform.

[0084] Hereinafter, it is described as an example that the adjustment structure 600 may include a halogen-doped compound semiconductor.

[0085] Reference Figure 7 , which is a cross-sectional schematic diagram of different stages of a method for forming a semiconductor device according to an embodiment of the present disclosure. In some embodiments, Figure 7 Can be continued Figure 1 .like Figure 7 As shown, in some embodiments, the adjustment structure 600 may be formed in the barrier layer 400 by performing doping with a halogen element. In some embodiments, the adjustment structure 600 may be located at the top surface of the barrier layer 400. Therefore, the adjustment structure 600 may include a halogen-doped compound semiconductor. For example, the halogen element may include fluorine (F), chlorine (Cl), bromine (Br), iodine (I), or a combination thereof. In some embodiments, the adjustment structure 600 may be a fluorine-doped compound semiconductor.

[0086] Reference Figure 8 , which is a cross-sectional schematic diagram of different stages of a method for forming a semiconductor device 3 according to an embodiment of the present disclosure. Figure 8As shown, the execution Figure 2 and Figure 3 The process shown in the figure is used to obtain the semiconductor device 3. In some embodiments, the barrier layer 400 may include AlGaN, and thus the adjustment structure 600 may include F-doped AlGaN. Accordingly, the two-dimensional electron gas 310 located below the adjustment structure 600 is discontinuous or the concentration of the two-dimensional electron gas 310 is partially reduced, so that the electric field distribution is more uniform.

[0087] In the following, it is described as an example that the adjustment structure 600 may include a dielectric material.

[0088] Reference Fig. 9 , which is a cross-sectional schematic diagram of different stages of a method for forming a semiconductor device according to an embodiment of the present disclosure. In some embodiments, Fig. 9 Can be continued Figure 1 .like Fig. 9 As shown, in some embodiments, a recess 410 may be formed in the barrier layer 400. In some embodiments, the recess 410 may be located on the top surface of the barrier layer 400. In some embodiments, the recess 410 may be formed by an etching process.

[0089] Reference Fig.10 , which is a cross-sectional schematic diagram of different stages of a method for forming a semiconductor device 4 according to an embodiment of the present disclosure. Continuing from the above, in some embodiments, an adjustment structure 600 may be formed in the recess 410. In some embodiments, the adjustment structure 600 may include a dielectric material. For example, the dielectric material may include an oxide such as silicon oxide, a nitride such as silicon nitride, an oxynitride such as silicon oxynitride, the like, or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, in the normal direction (third direction D3) of the substrate 100, the barrier layer 400 may have a first thickness t1, the adjustment structure 600 may have a second thickness t2, and the first thickness t1 may be greater than the second thickness t2. Then, the following steps may be performed. Figure 2 and Figure 3 The process shown is used to obtain the semiconductor device 4. Accordingly, since the dielectric material of the adjustment structure 600 can destroy the formation of the two-dimensional electron gas 310, the two-dimensional electron gas 310 below the adjustment structure 600 is discontinuous or the concentration of the two-dimensional electron gas 310 is partially reduced, so that the electric field distribution is more uniform.

[0090] Reference Fig.11 , which is a cross-sectional view of a semiconductor device 5 according to an embodiment of the present disclosure. Fig.11As shown, in some embodiments, the aforementioned recess (not shown) may penetrate the barrier layer 400 and expose a portion of the channel layer 300. In some embodiments, the adjustment structure 600 may be disposed in the barrier layer 400, and the adjustment structure 600 may penetrate the barrier layer 400. In some embodiments, the adjustment structure 600 may contact the barrier layer 400 and the channel layer 300. In some embodiments, the first thickness t1 of the barrier layer 400 may be less than the second thickness t2 of the adjustment structure 600. Accordingly, the adjustment structure 600 may physically interrupt the two-dimensional electron gas 310, so that the two-dimensional electron gas 310 at the adjustment structure 600 is discontinuous or the concentration of the two-dimensional electron gas 310 is locally reduced, so that the electric field distribution is more uniform.

[0091] Reference Fig.12 and Fig.13 , which is a cross-sectional schematic diagram and a top view schematic diagram of a semiconductor device 6 according to an embodiment of the present disclosure. Fig.13 The section A-A' is shown in Fig.12 In. Fig.12 and Fig.13 As shown, in some embodiments, the semiconductor device 6 may further include a connector 710. In some embodiments, the connector 710 may be disposed on the adjustment structure 600. In some embodiments, the connector 710 may include a plurality of sub-connectors 710a-710e, each of which may be disposed on each of the plurality of sub-structures 600a-600e in the adjustment structure 600, so that the plurality of sub-structures 600a-600e may be electrically connected to each other. In some embodiments, a bias may be applied to the connector 710 to control the concentration of the two-dimensional electron gas 310 located below the adjustment structure 600. For example, when the bias applied to the connector 710 increases, the concentration of the two-dimensional electron gas 310 located below the adjustment structure 600 decreases, and the electric field distribution can be adjusted based on electrical requirements. In some embodiments, the connector 710 may be electrically connected to the gate electrode 700 to simultaneously control the voltage applied to the connector 710 and the gate electrode 700. In other embodiments, the connector 710 may be electrically isolated from the gate electrode 700 to independently control the voltages applied to the connector 710 and the gate electrode 700 .

[0092] Reference Fig.14 , which is a schematic top view of a semiconductor device 7 according to an embodiment of the present disclosure. Fig.14As shown, in some embodiments, the adjustment structure 600 adjacent to the gate electrode 700 may have a first width w1, and the adjustment structure 600 adjacent to the drain electrode 900 may have a second width w2, and the first width w1 may be greater than the second width w2. In some embodiments, the second width w2 may be greater than or equal to 0. In some embodiments, the adjustment structure 600 may be a trapezoid when viewed from a top view. In some embodiments, the ratio of the second width w2 to the first width w1 (second width w2 / first width w1) may be 0.75 to 0.01. For example, the ratio of the second width w2 to the first width w1 may be 0.75, 0.6, 0.5, 0.4, 0.3, 0.2, 0.1, 0.05, 0.04, 0.03, 0.02, 0.01, or any value between the aforementioned values ​​or a numerical range consisting of any values, but the present disclosure is not limited thereto. Accordingly, the adjustment structure 600 can prevent the electric field from being excessively concentrated at the edge of the gate electrode 700 and / or can prevent the two-dimensional electron gas from being insufficient near the drain electrode 900 , thereby making the electric field distribution more uniform.

[0093] Reference Fig.15 , which is a schematic top view of a semiconductor device 8 according to an embodiment of the present disclosure. Fig.15 As shown, in some embodiments, at least one of the plurality of substructures 600a-600e of the adjustment structure 600 may include a plurality of portions a1-a4, and each of the plurality of portions a1-a4 may be arranged in a first direction D1 from the gate electrode 700 toward the drain electrode 900. In some embodiments, each of the plurality of portions a1-a4 has a plurality of intervals s1-s3, and the plurality of intervals s1-s3 may be the same or different.

[0094] In some embodiments, in the first direction D1, there is a spacing s1 between part a1 and part a2, there is a spacing s2 between part a2 and part a3, there is a spacing s3 between part a3 and part a4, and the spacing s1, spacing s2 and spacing s3 are the same. In some embodiments, each of the plurality of substructures 600a-600e may include a plurality of parts a1-a4. In some embodiments, the area of ​​each of the plurality of parts a1-a4 may decrease along the first direction D1 from the gate electrode 700 toward the drain electrode 900. For example, the area of ​​part a1 may be greater than the area of ​​part a2, the area of ​​part a2 may be greater than the area of ​​part a3, and the area of ​​part a3 may be greater than the area of ​​part a4. Accordingly, the adjustment structure 600 may avoid excessive concentration of the electric field at the edge of the gate electrode 700 and / or may avoid insufficient two-dimensional electron gas near the drain electrode 900, so that the electric field distribution is more uniform.

[0095] Reference Fig.16, which is a schematic top view of a semiconductor device 9 according to an embodiment of the present disclosure. In some embodiments, the spacings s1-s3 decrease along the first direction D1 from the gate electrode 700 toward the drain electrode 900. For example, the spacing s1 may be greater than the spacing s2, and the spacing s2 may be greater than the spacing s3. Accordingly, since the area of ​​each of the plurality of portions a1-a4 may decrease along the first direction D1, and the spacings s1-s3 may decrease along the first direction D1, the adjustment structure 600 may avoid excessive concentration of the electric field at the edge of the gate electrode 700 and / or may avoid insufficient two-dimensional electron gas near the drain electrode 900, thereby making the electric field distribution more uniform.

[0096] Reference Fig.17 , which is a schematic top view of a semiconductor device 10 according to an embodiment of the present disclosure. Fig.17 As shown, in some embodiments, the adjustment structure 600 may include an arc-shaped end Ea near the drain electrode 900, but the present disclosure is not limited thereto. For example, the adjustment structure 600 may include a semicircular end, a semi-elliptical end, a curved end, an end with other shapes having rounded corners, or an end with other suitable shapes. Accordingly, the arc-shaped end Ea can avoid excessive concentration of the electric field, such as concentration at the tip, and make the electric field distribution more uniform.

[0097] In some embodiments, the semiconductor devices 1 to 10 disclosed herein can be used in any combination and can be used as high electron mobility transistors. In some embodiments, the cross-sectional view of the semiconductor device can be combined with the top view of the semiconductor device in any combination. For example, Figure 5 The top view of the semiconductor device 1 shown can be compared with Figure 3 The cross-sectional view of the semiconductor device 1 shown in FIG. Figure 6 The cross-sectional view of the semiconductor device 2 shown in FIG. Figure 8 The cross-sectional view of the semiconductor device 3 shown in FIG. Fig.10 A cross-sectional view of the semiconductor device 4 shown, or Fig.11 The cross-sectional view of the semiconductor device 5 is shown in combination. In other embodiments, any of the semiconductor devices 1 to 10 may be further processed to form a high electron mobility transistor. In some embodiments, the gradient adjustment structure disclosed herein may be applied to an enhancement mode (E-mode) or depletion mode (D-mode) high electron mobility transistor.

[0098] Accordingly, the present disclosure adjusts the electric field distribution in the drift region by setting a gradual adjustment structure between the gate electrode and the drain electrode. Thereby, it is possible to reduce excessive concentration of the electric field distribution, improve reliability and / or increase breakdown voltage. Among them, the gradual adjustment structure can have different parameters according to electrical requirements. For example, the gradual adjustment structure can have a gradual width, multiple substructures, multiple parts, a gradual spacing and / or ends of different shapes, and the gradual adjustment structure can be set on the barrier layer, in the channel layer, in the barrier layer or through the barrier layer.

[0099] The scope of protection of the present disclosure is not limited to the processes, machines, manufactures, material compositions, devices, methods and steps in the specific embodiments described in the specification. Any technician in the relevant technical field can understand the current or future developed processes, machines, manufactures, material compositions, devices, methods and steps from the disclosure of the present disclosure. As long as they can implement substantially the same functions or obtain substantially the same results in the embodiments described herein, they can be used according to the present disclosure. Therefore, the scope of protection of the present disclosure includes the aforementioned processes, machines, manufactures, material compositions, devices, methods and steps. Any embodiment or claim of the present disclosure does not need to achieve all the purposes, advantages and / or features described in the present disclosure.

[0100] Several embodiments are summarized above so that those skilled in the art can better understand the concepts of the embodiments of the present disclosure. Those skilled in the art should understand that they can design or modify other processes and structures based on the embodiments of the present disclosure to achieve the same purposes and / or advantages as the embodiments herein. Those skilled in the art should also understand that such equivalent processes and structures do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and replacements without violating the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: include: a substrate; a channel layer, disposed on the substrate; a barrier layer disposed on the channel layer; a gate electrode disposed on the barrier layer; A source electrode and a drain electrode are respectively disposed on opposite sides of the gate electrode; as well as an adjustment structure disposed between the gate electrode and the drain electrode, Wherein, a width of the adjustment structure decreases along a direction from the gate electrode toward the drain electrode.

2. The semiconductor device according to claim 1, wherein The adjustment structure includes a plurality of substructures, and each of the plurality of substructures is arranged at intervals along an extension direction of the gate electrode.

3. The semiconductor device according to claim 2, wherein: At least one of the plurality of substructures includes a plurality of parts, and each of the plurality of parts is arranged at intervals along the direction from the gate electrode toward the drain electrode.

4. The semiconductor device according to claim 3, wherein: An area of ​​each of the plurality of portions decreases along the direction from the gate electrode toward the drain electrode.

5. The semiconductor device according to claim 3, wherein: A spacing between each of the plurality of portions decreases along the direction from the gate electrode toward the drain electrode.

6. The semiconductor device according to claim 1, wherein: The adjustment structure includes an arc-shaped end portion.

7. The semiconductor device according to claim 1, wherein The adjustment structure is arranged on the barrier layer or in the channel layer and comprises a P-type doped compound semiconductor.

8. The semiconductor device according to claim 1, wherein The adjustment structure is disposed in the barrier layer and includes a halogen-doped compound semiconductor.

9. The semiconductor device according to claim 1, wherein: The adjustment structure is disposed in the barrier layer and includes a dielectric material.

10. A method for forming a semiconductor device, characterized in that: include: providing a substrate; forming a channel layer on the substrate; forming a barrier layer on the channel layer; forming a gate electrode on the barrier layer; forming a source electrode and a drain electrode on opposite sides of the gate electrode; and forming an adjustment structure between the gate electrode and the drain electrode, Wherein, a width of the adjustment structure decreases along a direction from the gate electrode toward the drain electrode.

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