A polycrystal face structure resurf gan-based hemt and a preparation method thereof

Abstract

The application discloses a RESURF GaN-based HEMT with a polycrystal face structure and a preparation method thereof, and belongs to the technical field of semiconductor power devices. + The device comprises, from bottom to top, a substrate layer (101), a GaN buffer layer (102), a mask layer (103), a composite channel structure (104), a source electrode (105), a drain electrode (106), a p-NiO layer (107), a p + -NiO layer (108) and a gate electrode (109). By controlling the crystal face orientation of GaN and the epitaxial growth conditions, a three-dimensional GaN mesa with a specific structure is formed, so that etching damage is effectively avoided. Meanwhile, the p-NiO layer (107) and the 2DEG in the composite channel structure (104) are mutually depleted, the electric field distribution is significantly optimized, the breakdown voltage is improved, and the on-resistance is effectively reduced through the multi-channel design of the composite channel structure (104).

Description

Technical Field

[0001] This invention relates to a polycrystalline structure RESURF GaN-based HEMT and its fabrication method, belonging to the field of semiconductor power device technology. Background Technology

[0002] With the development of modern power electronics technology, the demand for high-efficiency and high-reliability semiconductor power devices is increasing. Gallium nitride (GaN) material, due to its excellent wide bandgap characteristics, high electron mobility, and high thermal conductivity, has become an important material in the field of power devices, especially showing great potential in high-frequency, high-power, and high-temperature applications. Gallium nitride-based high electron mobility transistors (HEMTs) are an important structure widely used in power electronic devices, and their performance is particularly outstanding in high-voltage, high-current, and high-temperature environments. GaN-based HEMT devices have broad application prospects, especially in high-power applications such as power electronics, communication systems, and radar. However, with the continuous shrinking of device size and the increase in operating frequency, GaN-based HEMTs still face some challenges in practical applications, particularly in terms of breakdown voltage, on-resistance, reliability, and fabrication processes.

[0003] Currently, the performance of GaN-based HEMT devices is limited by several factors: Firstly, most existing device structures require etching during fabrication, which easily introduces defects into the GaN material surface and increases surface roughness, leading to a decrease in device performance, specifically manifested as increased on-resistance, more surface defects, and reduced thermal stability. Secondly, under high-voltage operating conditions, excessively large local electric fields may occur on the surface or edge regions of the device, causing premature breakdown and excessively high on-resistance, resulting in low dynamic performance of the HEMT device. High breakdown voltage and low on-resistance are typically achieved using field-plate structures, optimized device area, and p-GaN RESURF (Reduced Surface Field) structures. However, field-plate structures introduce large parasitic capacitances, while optimizing the device area increases resistance. Filling p-GaN requires etching, which introduces etching damage and increases the complexity of device fabrication. Therefore, designing a GaN-based HEMT device that avoids etching damage, optimizes electric field distribution, improves breakdown voltage, reduces on-resistance, enhances dynamic performance, and achieves excellent switching efficiency is of great significance. Summary of the Invention

[0004] This invention discloses a RESURF GaN-based HEMT with a polycrystalline facet structure and its fabrication method. The device forms specific three-dimensional GaN mesa by growing the {20-21} and {10-11} facets, or the {1-102} and {11-23} facets of GaN, thus avoiding surface damage caused by traditional etching processes. A p-NiO layer (107) with a gradient doping concentration is disposed on the composite channel structure (104), wherein the high doping concentration of NiO can reduce the barrier width, making it easier for holes in p-NiO to be injected into GaN. The p-type doped NiO and the 2DEG in multiple channels can mutually deplete each other, and the rationally distributed carriers will expand the depletion region, thereby making the electric field distribution in the drift region more uniform and improving the breakdown voltage of the device. The high doping concentration of p-NiO... + The NiO layer (108) further enhances hole injection capability, optimizes current collapse, and combines with the gate (109) to form an ohmic contact. Through structural design and fabrication process optimization, this invention provides a new structure and method for realizing GaN-based HEMT devices with no etch damage, high breakdown voltage, low on-resistance, and high dynamic performance.

[0005] To achieve the above objectives, the present invention adopts the following technical solution:

[0006] On one hand, the present invention provides a RESURF GaN-based HEMT with a polycrystalline structure, characterized in that: it includes, from bottom to top, a substrate layer (101), a GaN buffer layer (102) with an upward crystal plane of (0002), a mask layer (103) containing a specific array of holes, a composite channel structure (104) in the holes of the mask layer (103) and in contact with the GaN buffer layer (102), a source (105) and a drain (106) located at both ends of the composite channel structure (104), a p-NiO layer (107) covering the composite channel structure (104) in a three-dimensional form, and a p-NiO layer (107) covering the p-NiO layer (107). + -NiO layer (108), covering p + - Gate (109) above NiO layer (108); wherein, the hole of mask layer (103) is a hexagonal elongated hole symmetrical along both direction 1 and direction 2, the included angle between any two adjacent sides is 120°, the two sides parallel to direction 1 are the long sides with a length of a, and at each end of direction 1 there are two sides with an included angle of 60° with direction 1, which are the short sides with a length of b; direction 1 is the lateral direction, and direction 2 is the third-dimensional direction that is perpendicular to both the lateral and vertical directions; the composite channel structure (104) is a mesa structure extending upward from the elongated hole of mask layer (103), and from bottom to top includes 2 to 5 pairs of GaN channel layers (1041) and In arranged sequentially. x Al y Ga 1-x-yThe N-type barrier layer (1042) has a bottom surface with a (000-2) crystal plane that is in contact with the GaN buffer layer (102), and a top surface with a (0002) crystal plane. The bottom and top surfaces are formed by P. m crystal planes m and P n A crystal plane n is connected, and both crystal plane m and crystal plane n are inclined planes that are not perpendicular to the top surface; the source (105) covers the inclined plane and top surface of the composite channel structure (104) along direction 1 in the form of an ohmic contact, and the drain (106) covers the inclined plane and top surface of the composite channel structure (104) on the other side of direction 1 in the form of an ohmic contact; the p-NiO layer (107) covers the surface of the composite channel structure (104) and does not contact the edge of the source (105) and the edge of the drain (106), p + A -NiO layer (108) covers the surface of the p-NiO layer (107) and is close to the source (105) side, and a gate (109) covers the p-NiO layer (107). + - The surface of the NiO layer (108).

[0007] Preferably, the substrate layer (101) is made of one of Si, SiC, GaN or Al2O3.

[0008] Preferably, the mask layer (103) is made of SiO2 or SiN. x The GaN buffer layer (102) is selected from one of hBN or Al2O3, with a thickness of 10–100 nm. These materials have excellent corrosion resistance, insulation, and chemical stability, effectively preventing direct contact between the GaN buffer layer (102) and the p-NiO layer (107). The hexagonal hole array pattern in the mask layer (103) is arranged along direction 1. The hexagonal hole array pattern is etched out by the process technology to expose the underlying GaN buffer layer (102). The included angle between any two adjacent sides of the hexagonal hole is 120°. The two sides parallel to direction 1 are the long sides with a length of 'a'. At each end of direction 1, there are two sides with an included angle of 60° with direction 1, which are the short sides with a length of 'b'. The range of 'a' is 10–25 μm, and the numerical relationship between 'a' and 'b' satisfies 'a = 20 × 1.73 × b'. The long side of length 'a' ensures the drift region length of the via array in the device structure, which can improve the breakdown voltage of the device. However, if it is too long, it will increase the on-resistance, so it needs to be limited. The short side of length 'b' optimizes the channel width of the 2DEG and improves the current carrying capacity. However, if the area is too large, the p-NiO layer (107) will not be able to deplete the 2DEG and will occupy too much effective area, thus affecting the overall area utilization of the device. This numerical relationship is the optimal solution obtained after experimental optimization, which improves the breakdown voltage and reduces the on-resistance. The main purpose is to achieve a balance among the various performance aspects of the power device. A certain angle is formed between the different sides to meet the shape of the GaN crystal plane distribution.

[0009] Preferably, the composite channel structure (104) comprises, from bottom to top, 2 to 5 pairs of GaN channel layers (1041) and In layers arranged sequentially. x Al y Ga 1-x-y The N-type barrier layer (1042) and multiple channels form multiple current paths, which can increase the current density and reduce the on-resistance of the entire device. The composite channel structure (104) has a (000-2) crystal plane on the bottom surface and contacts the GaN buffer layer (102), and a (0002) crystal plane on the top surface. The bottom and top surfaces are made of P m crystal planes m and P n Each crystal plane n is connected, and both crystal plane m and crystal plane n are inclined planes that are not perpendicular to the top surface. A structure with inclined planes is formed by combining crystal plane m and crystal plane n, where crystal plane m is a {20-21} plane or a {1-102} plane, and crystal plane n is a {10-11} plane or a {11-23} plane. These inclined planes connect the bottom (000-2) crystal plane and the top (0002) crystal plane of the composite channel structure (104), exhibiting specific growth directions and surface characteristics during fabrication, effectively avoiding etching damage. In the composite channel structure (104), the thickness of each GaN channel layer (1041) ranges from 30 to 100 nm. x Al y Ga 1-x-y The thickness of the N-barrier layer (1042) ranges from 20 to 30 nm, and the In... x Al y Ga 1-x-y The In component x of N is 0–0.15, and the Al component y is 0.15–0.35. x Al y Ga 1-x-y The N-barrier layer (1042) can be modified by adjusting the ratio of In and Al to change the band gap and electronic structure, thereby affecting the carrier mobility and electron density.

[0010] Preferably, the source electrode (105) and drain electrode (106) are made of one or more combinations of Ti, Al, Ni, and Au. The width of the source electrode (105) along direction 1 is 1–3 μm, the width of the drain electrode (106) along direction 1 is 1–3 μm, and the thickness is 30–100 nm. When the source electrode (105) and drain electrode (106) are a Ti / Al / Ni / Au combination, the thicknesses are set to 10 nm, 20 nm, 10 nm, and 30 nm, respectively. Ti, as the first layer, can improve adhesion to reduce contact resistance; Al improves overall conductivity; Ni provides mechanical and thermal stability; and Au provides antioxidant protection and excellent conductivity. Furthermore, when the source (105) and drain (106) cover multiple composite channel structures (104), they contact the composite channel structures (104) with a beveled shape, rather than in the traditional vertical contact. This significantly increases the actual contact area between the source (105) and drain (106) and the channel, improves current injection and extraction efficiency, reduces contact resistance, and thus effectively enhances the conductivity of the device. This beveled design also increases the area and effectively dissipates heat.

[0011] Preferably, the p-NiO layer (107) covers the top and slope surfaces of the composite channel structure (104), with a distance of 2-4 μm from the boundary of the source (105) and 2-8 μm from the boundary of the drain (106), and a thickness ranging from 100 to 300 nm. By controlling the distance between the p-NiO layer (107) and the source (105) and drain (106), current leakage or poor current conduction paths can be avoided. The p-NiO layer (107) is graded doped, with a higher doping concentration closer to the composite channel structure (104). Between the highly doped NiO and GaN, a heterojunction of p-NiO and n-GaN is formed, thereby forming a potential barrier. The higher doping concentration of NiO can reduce the barrier width at the interface, thereby improving the hole injection efficiency and allowing the hole to cross the barrier and enter GaN through the tunneling effect. The doping concentration is b×x1×x2, where b is in μm and x1 is 1×10⁻⁶. 17 cm -3 The range of x2 is 5–20 μm. -1 The width 'b' directly affects the matching relationship between holes and electrons. A larger width requires a higher p-type doping concentration to deplete the 2DEG. The parameter x2 controls the variation in doping concentration to optimize the device's breakdown voltage, on-resistance, and reliability. x2 represents the optimized optimal range, providing a reliable doping concentration range.

[0012] Preferably, the p + -NiO layer (108) covers the surface of p-NiO layer (107) near the source electrode (105), with a width of 2-6 μm and a thickness of 30-100 nm along direction 1.+ - The doping concentration of the NiO layer (108) is 1×10⁻⁶. 19 cm -3 ~1×10 20 cm -3 p with high doping concentration + - The NiO layer (108) can improve hole injection capability, which helps to improve the switching performance of GaN HEMT devices, especially to optimize current collapse phenomenon.

[0013] Preferably, the gate (109) covers p + The NiO layer (108) surface can enhance gate control capability, with a thickness of 30–100 nm. The gate (109) material can be selected from high work function metals such as Pt, Au, and Pd, which helps to interact with p + - The NiO layer (108) forms a good ohmic contact. A good ohmic contact can improve the conductivity, switching speed and reliability of the device.

[0014] On the other hand, the present invention provides a structural feature and fabrication method of a polycrystalline surface structure RESURF GaN-based HEMT. The structural features of this device, from bottom to top, are: a substrate layer (101), a GaN buffer layer (102) with an upward crystal plane of (0002), a mask layer (103) containing a specific array of holes, a composite channel structure (104) in the holes of the mask layer (103) and in contact with the GaN buffer layer (102), a source (105) and a drain (106) located at both ends of the composite channel structure (104), a p-NiO layer (107) covering the composite channel structure (104) in a three-dimensional form, and a p-NiO layer (107) covering the p-NiO layer (107). + -NiO layer (108), covering p + - Gate (109) above NiO layer (108); wherein, the hole of mask layer (103) is a hexagonal elongated hole symmetrical along both direction 1 and direction 2, the included angle between any two adjacent sides is 120°, the two sides parallel to direction 1 are the long sides with a length of a, and at each end of direction 1 there are two sides with an included angle of 60° with direction 1, which are the short sides with a length of b; direction 1 is the lateral direction, and direction 2 is the third-dimensional direction that is perpendicular to both the lateral and vertical directions; the composite channel structure (104) is a mesa structure extending upward from the elongated hole of mask layer (103), and from bottom to top includes 2 to 5 pairs of GaN channel layers (1041) and In arranged sequentially. x Al y Ga 1-x-y The N-type barrier layer (1042) has a bottom surface with a (000-2) crystal plane that is in contact with the GaN buffer layer (102), and a top surface with a (0002) crystal plane. The bottom and top surfaces are formed by P. m crystal planes m and Pn A crystal plane n is connected, and both crystal plane m and crystal plane n are inclined planes that are not perpendicular to the top surface; the source (105) covers the inclined plane and top surface of the composite channel structure (104) along direction 1 in the form of an ohmic contact, and the drain (106) covers the inclined plane and top surface of the composite channel structure (104) on the other side of direction 1 in the form of an ohmic contact; the p-NiO layer (107) covers the surface of the composite channel structure (104) and does not contact the edge of the source (105) and the edge of the drain (106), p + A -NiO layer (108) covers the surface of the p-NiO layer (107) and is close to the source (105) side, and a gate (109) covers the p-NiO layer (107). + - The surface of the NiO layer (108); when P m and P n When the crystal planes are 4 and 2 respectively, the crystal plane m is a {20-21} plane, named m1 to m4, and the crystal plane n is a {10-11} plane, named n1 to n2; among them, the two {10-11} planes, n1 and n2, extend along direction 1 and their bottoms are in contact with the long side of the elongated hole of the mask layer (103), and the p-NiO layer (107) covers these n1 and n2; one side of the source electrode (105) contains two {20-21} planes, m1 and m2, which are in contact with each other and with n1 and n2; one side of the drain electrode (106) contains two {20-21} planes, m3 and m4, which are in contact with each other and with n1 and n2; the fabrication method of this device includes the following steps:

[0015] a) Select one of Si, SiC, GaN or Al2O3, which are commercially available materials that can be directly epitaxially grown into GaN films, as the substrate layer (101), and use one of MOCVD, MBE or HVPE technology to epitaxially grow a GaN buffer layer (102).

[0016] b) Deposit SiO2 or SiN on the GaN buffer layer (102) using PECVD technology. x As a mask layer (103); using standard ultraviolet lithography technology, pattern transfer is achieved on the mask layer (103) to obtain a specially designed hexagonal array pattern. Further, using RIE technology, the hexagonal region is etched away to expose the hexagonal hole array of the GaN buffer layer (102) on the mask layer (103), thus completing the fabrication of the mask layer (103) containing the specific hole array.

[0017] c) Selective epitaxy was performed using an MOCVD system and a hexagonal array of holes in the mask layer to grow the bottommost GaN channel layer (1041). The growth conditions were as follows: growth temperature 1050–1080 °C, V / III ratio (N source to Al,

[0018] The molar flow rate ratio of the Ga source is 800–1500, the growth pressure is 600–760 Torr, and the total flow rate v of the carrier gas introduced into the reaction chamber (in sccm) satisfies 50 PA < 760 v < 80 PA, where P is the growth pressure (in Torr) and A is the area of ​​the graphite disk in the reaction chamber of the MOCVD system (in square centimeters). The upward crystal plane of the composite channel structure (104) is the 0002 plane. By controlling a higher growth temperature and a higher V / III ratio, a three-dimensional growth mode can be triggered to achieve selective epitaxy in the hexagonal hole. At the same time, the edge of the three-dimensional structure is achieved with a higher potential. The {10-11} and {20-21} planes at the end of the crystal plane form a specific three-dimensional GaN mesa; controlling a low carrier gas flow rate ensures that the reactant source is normally transported to the surface of the GaN buffer layer (102) in the hole to achieve growth; after the growth of the bottommost GaN channel layer (1041) is completed, the growth temperature, V / III ratio and pressure are kept constant, and the total flow rate v of the carrier gas introduced into the reaction chamber is increased to 1.1 to 1.3 times to complete the growth of the remaining part of the composite channel structure (104); appropriately increasing the flow rate can control the lateral epitaxial growth rate and ensure that the growth is mainly vertical upward to form a neat edge bevel;

[0019] d) Using standard ultraviolet lithography, a region requiring p-NiO layer (107) deposition is formed on the composite channel structure (104); NiO is deposited using magnetron sputtering with high-purity nickel as the target material. The sputtering conditions are as follows: the introduced gases are O2 and Ar, the sputtering power is 100-200W, and the gas pressure is 3-5mTorr; during the deposition process, the ratio of introduced O2 to Ar is gradually adjusted from the initial 7:3 to 5:5; for the doping concentration control of p-NiO, p-type doping in NiO mainly manifests as Ni vacancies and O interstitials, so the carrier concentration can be controlled by adjusting the O2 flow rate, gradually reducing the O2 flow rate to achieve a gradual distribution of doping concentration; then the p-NiO layer (107) is prepared; similarly, using ultraviolet lithography, a region requiring p-NiO layer (107) to be sputtered is formed above the p-NiO layer (107). + - NiO layer (108) region, deposited p + -NiO layer (108);

[0020] e) in p + - Photoresist is coated on the surface of the NiO layer (108), and then exposed and developed. Subsequently, the gate (109) is deposited, and the corresponding source (105) and drain (106) are prepared on the surface of the composite channel structure (104). Then, a rapid annealing process is performed to complete the fabrication of this device structure.

[0021] This invention also provides a structural feature and fabrication method of a polycrystalline GaN-based HEMT. The structural features of this device, from bottom to top, are: a substrate layer (101), a GaN buffer layer (102) with an upward-facing (0002) facet, a mask layer (103) containing a specific array of holes, a composite channel structure (104) within the holes of the mask layer (103) and in contact with the GaN buffer layer (102), a source (105) and a drain (106) located at both ends of the composite channel structure (104), a p-NiO layer (107) covering the composite channel structure (104) in a three-dimensional form, and a p-NiO layer (107) covering the p-NiO layer (107). + -NiO layer (108), covering p + - Gate (109) above NiO layer (108); wherein, the hole of mask layer (103) is a hexagonal elongated hole symmetrical along both direction 1 and direction 2, the included angle between any two adjacent sides is 120°, the two sides parallel to direction 1 are the long sides with a length of a, and at each end of direction 1 there are two sides with an included angle of 60° with direction 1, which are the short sides with a length of b; direction 1 is the lateral direction, and direction 2 is the third-dimensional direction that is perpendicular to both the lateral and vertical directions; the composite channel structure (104) is a mesa structure extending upward from the elongated hole of mask layer (103), and from bottom to top includes 2 to 5 pairs of GaN channel layers (1041) and In arranged sequentially. x Al y Ga 1-x-y The N-type barrier layer (1042) has a bottom surface with a (000-2) crystal plane that is in contact with the GaN buffer layer (102), and a top surface with a (0002) crystal plane. The bottom and top surfaces are formed by P. m crystal planes m and P n A crystal plane n is connected, and both crystal plane m and crystal plane n are inclined planes that are not perpendicular to the top surface; the source (105) covers the inclined plane and top surface of the composite channel structure (104) along direction 1 in the form of an ohmic contact, and the drain (106) covers the inclined plane and top surface of the composite channel structure (104) on the other side of direction 1 in the form of an ohmic contact; the p-NiO layer (107) covers the surface of the composite channel structure (104) and does not contact the edge of the source (105) and the edge of the drain (106), p + A -NiO layer (108) covers the surface of the p-NiO layer (107) and is close to the source (105) side, and a gate (109) covers the p-NiO layer (107). + - The surface of the NiO layer (108); when P m and P nWhen the crystal planes are 3 and 6 respectively, the crystal plane m is a {1-102} plane, named m1 to m3, and the crystal plane n is a {11-23} plane, named n1 to n6; among them, the two {11-23} planes, n1 and n2, extend along direction 1 and their bottoms are in contact with the long side of the elongated hole of the mask layer (103), and the p-NiO layer (107) covers these n1 and n2; one side of the source electrode (105) contains two {11 and m2} planes. The device comprises a {1-102} surface and two {11-23} surfaces, n3 and n4. m1 and m2 are in contact with n1 and n2, and n3 and n4 are in contact with each other and with m1 and m2 respectively. One side of the drain (106) includes a {1-102} surface (m3) and two {11-23} surfaces (n5 and n6), with n5 and n6 in contact with n1 and n2, and m3 in contact with n5 and n6. The fabrication method of this device includes the following steps:

[0022] a) Select one of Si, SiC, GaN or Al2O3, which are commercially available materials that can be directly epitaxially grown into GaN films, as the substrate layer (101), and use one of MOCVD, MBE or HVPE technology to epitaxially grow a GaN buffer layer (102).

[0023] b) Deposit SiO2 or SiN on the GaN buffer layer (102) using PECVD technology. x As a mask layer (103); using standard ultraviolet lithography technology, pattern transfer is achieved on the mask layer (103) to obtain a specially designed hexagonal array pattern. Further, using RIE technology, the hexagonal region is etched away to expose the hexagonal hole array of the GaN buffer layer (102) on the mask layer (103), thus completing the fabrication of the mask layer (103) containing the specific hole array.

[0024] c) Using an MOCVD system and a hexagonal aperture array of a mask layer (103), selective epitaxy is achieved to grow the bottom GaN channel layer (102). The growth conditions are as follows: growth temperature is 1050–1080 °C, V / III ratio (molar flow ratio of N source to Al and Ga sources) is 500–700, growth pressure is 600–760 Torr, and the total flow rate v (in sccm) of the carrier gas entering the reaction chamber satisfies 50 PA < 760 v < 80 PA, and the flow rate Nv (in sccm) of NH3 satisfies 50 A < Nv < 100 A; where P is the growth pressure (in Torr) and A is the area of ​​the graphite disk in the reaction chamber of the MOCVD system (in square centimeters); composite channel structure (104).

[0025] The upward-facing crystal plane is the 0002 plane. By controlling a higher growth temperature and a higher V / III ratio, a three-dimensional growth mode can be triggered to achieve selective epitaxy within hexagonal holes. Because {11-23} and {1-102} are stable high-potential-energy crystal planes, reducing the flow rate of the reactant sources (NH3 and MO sources) during growth can decrease the growth rate. In this case, the edges of the three-dimensional structure can be controlled to end with the {11-23} and {1-102} planes, forming specific three-dimensional GaN mesa. Controlling the carrier gas... The flow rate ensures that the reactant source is transported normally to the surface of the GaN buffer layer (102) in the hole to achieve growth; after the growth of the bottom GaN channel layer (1041) is completed, the growth temperature, V / III ratio and pressure are kept constant, and the total flow rate v of the carrier gas introduced into the reaction chamber is increased to 1.1 to 1.3 times to complete the growth of the remaining part of the composite channel structure (104); appropriately increasing the flow rate can control the lateral epitaxial growth rate and ensure that the growth is mainly vertical upward to form a neat edge slope.

[0026] d) Using standard ultraviolet lithography techniques, a p-NiO layer is deposited on the composite channel structure (104).

[0027] (107) region; NiO was deposited using magnetron sputtering with high-purity nickel as the target material. The sputtering conditions were as follows: the introduced gases were O2 and Ar, the sputtering power was 100-200 W, and the gas pressure was 3-5 mTorr; during the deposition process, the ratio of introduced O2 to Ar was gradually adjusted from the initial 7:3 to 5:5; for the doping concentration control of p-NiO, p-type doping in NiO mainly manifests as Ni vacancies and O interstitials, so the carrier concentration can be controlled by adjusting the O2 flow rate, gradually reducing the O2 flow rate to achieve a gradual distribution of doping concentration; then the p-NiO layer was completed.

[0028] (107) preparation; similarly, ultraviolet lithography is used to form the required sputtered p-NiO layer (107) above the p-NiO layer. + - NiO layer (108) region, deposited p + -NiO layer (108);

[0029] e) in p + - Photoresist is coated on the surface of the NiO layer (108), and then exposed and developed. Subsequently, the gate (109) is deposited, and the corresponding source (105) and drain (106) are prepared on the surface of the composite channel structure (104). Then, a rapid annealing process is performed to complete the fabrication of this device structure.

[0030] Beneficial effects:

[0031] This invention grows specific three-dimensional GaN mesa surfaces by combining the {20-21} and {10-11} planes, or the {1-102} and {11-23} planes of GaN, thereby avoiding surface damage caused by traditional etching processes. This design not only improves the material quality and crystal growth stability of GaN-based HEMTs, but also optimizes the contact interface between the source (105) and drain (106) and the composite channel structure (104), changing it from a traditional single vertical surface to a sloping structure, increasing the contact area, reducing contact resistance, and improving current injection and extraction efficiency. Simultaneously, this sloping contact method also facilitates heat dissipation, reduces local overheating, and thus improves device reliability.

[0032] Furthermore, the addition of multiple 2DEG channels can increase current density and reduce the overall on-resistance of the device. During the transition from the on to the off state in GaN-based HEMT devices, the resistance increases and the current decreases. Introducing a p-NiO layer (107) with a gradually increasing doping concentration can form a thinner depletion region at the NiO-GaN interface, reducing the barrier width. This design enhances the hole injection capability of NiO, improves the interface tunneling efficiency, and helps optimize the device's conductivity and dynamic response characteristics. The p-NiO layer (107) can also mutually deplete with multiple 2DEG channels, expanding the depletion region and forming a better electric field distribution, maximizing the breakdown voltage. High-doped p + The NiO layer (108) can significantly improve hole injection capability, fill trapped states, and reduce barrier height, thereby mitigating the current drop caused by the trap effect. This can significantly reduce current collapse and improve the dynamic performance and stability of the device. The gate (109) and p + - The NiO layer (108) forms an excellent ohmic contact, and the entire gate (109) covers the p in a three-dimensional morphology. + The NiO layer (108) surface can enhance gate control capability and improve switching efficiency. This invention provides a new structure and method for designing high-performance GaN-based HEMT devices. Attached Figure Description

[0033] exist Figures 1 to 7 In the diagram, 101 is the substrate layer; 102 is the GaN buffer layer; 103 is the mask layer; 104 is the composite channel structure; 1041 is the GaN channel layer; and 1042 is the In... x Al y Ga 1-x-y N-type barrier layer; 105 is the source; 106 is the drain; 107 is the p-NiO layer; 108 is the p-NiO layer. + -NiO layer; 109 is the gate;

[0034] Figure 1A cross-sectional view along direction 1 at the symmetry center position in direction 2 of a RESURF GaN-based HEMT device with a polycrystalline structure provided by the present invention;

[0035] Figure 2 A cross-sectional view along direction 2 on the gate (109) of a RESURF GaN-based HEMT device with a polycrystalline structure provided by the present invention;

[0036] Figure 3 This is a schematic diagram of the hexagonal hole array pattern obtained by etching the mask layer (103) in the fabrication process of a RESURF GaN-based HEMT device with a polycrystalline surface structure provided by the present invention; wherein, the GaN buffer layer (102) is exposed in the etched hexagonal pattern, and the holes in the mask layer (103) are hexagonal elongated holes that are symmetrical along both directions 1 and 2. The included angle between any two adjacent sides is 120°, the two sides parallel to direction 1 are the long sides with a length of a, and at each end of direction 1 there are two sides with an included angle of 60° with direction 1, which are the short sides with a length of b;

[0037] Figure 4 The top view of a RESURF GaN-based HEMT device with a polycrystalline structure provided by the present invention after growing a composite channel structure (104) in the fabrication process; wherein, the overall structure consists of a mask layer (103) and three pairs of GaN channel layers (1041) stacked sequentially upwards and In x Al y Ga 1-x-y The N-type barrier layer (1042) has a bottom surface with a (000-2) crystal plane that is in contact with the GaN buffer layer (102), and a top surface with a (0002) crystal plane. The bottom and top surfaces are formed by P. m crystal planes m and P n There are n crystal planes connected, and both crystal plane m and crystal plane n are inclined planes that are not perpendicular to the top surface; currently P m and P n The crystal planes are 4 and 2 respectively. The crystal plane m is a {20-21} plane, named m1 to m4, and the crystal plane n is a {10-11} plane, named n1 to n2. Among them, the two {10-11} planes n1 and n2 extend along direction 1 and their bottoms are in contact with the long side of the elongated hole of the mask layer (103). The side of the source electrode (105) contains two {20-21} planes m1 and m2, which are in contact with each other and with n1 and n2. The side of the drain electrode (106) contains two {20-21} planes m3 and m4, which are in contact with each other and with n1 and n2.

[0038] Figure 5The top view of a RESURF GaN-based HEMT device with a polycrystalline surface structure provided by the present invention after growing another composite channel structure (104) in the fabrication process; wherein, the overall structure consists of a mask layer (103) and three pairs of GaN channel layers (1041) stacked sequentially upwards and In x Al y Ga 1-x-y The N-type barrier layer (1042) has a bottom surface with a (000-2) crystal plane that is in contact with the GaN buffer layer (102), and a top surface with a (0002) crystal plane. The bottom and top surfaces are formed by P. m crystal planes m and P n There are n crystal planes connected, and both crystal plane m and crystal plane n are inclined planes that are not perpendicular to the top surface; currently P m and P n The crystal planes are 3 and 6 respectively. The crystal plane m is a {1-102} plane, named m1 to m3, and the crystal plane n is a {11-23} plane, named n1 to n6. Among them, the two {11-23} planes, n1 and n2, extend along direction 1 and their bottoms are in contact with the long side of the elongated hole of the mask layer (103). The side of the source electrode (105) includes two {1-102} planes, m1 and m2, and two {11-23} planes, n3 and n4. m1 and m2 are in contact with n1 and n2, and n3 and n4 are in contact with each other and respectively in contact with m1 and m2. The side of the drain electrode (106) includes one {1-102} plane, m3, and two {11-23} planes, n5 and n6. n5 and n6 are in contact with n1 and n2, and m3 is in contact with n5 and n6.

[0039] Figure 6 The present invention provides a RESURF GaN-based HEMT device with a polycrystalline structure. Figure 4 The final device top view after fabrication is shown; in order to facilitate observation of the situation below the source (105), the overlapping part of the source (105) and the composite channel structure (104) is marked as a dashed line, and the drain (106) can be referenced to the source (105) below;

[0040] Figure 7 The present invention provides a RESURF GaN-based HEMT device with a polycrystalline structure. Figure 5 The final device top view after fabrication is shown; in order to facilitate observation of the situation below the source (105), the overlapping part of the source (105) and the composite channel structure (104) is marked as a dashed line, and the drain (106) can be referenced to the source (105). Detailed Implementation

[0041] The present invention will be further described below with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and should not be used to limit the scope of protection of the present invention.

[0042] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are used only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0043] Example 1:

[0044] A top view of a RESURF GaN-based HEMT device with a polycrystalline structure provided in Embodiment 1 of the present invention is shown below. Figure 6 As shown, the cross-sectional view along direction 1 at the center of symmetry in direction 2 is as follows. Figure 1 As shown, a cross-sectional view of the gate (109) along direction 2 is as follows. Figure 2 As shown. The structural features of this device, from bottom to top, are: a substrate layer (101), a GaN buffer layer (102) with an upward crystal plane of (0002), a mask layer (103) containing a specific array of holes, a composite channel structure (104) within the holes of the mask layer (103) and in contact with the GaN buffer layer (102), a source (105) and a drain (106) located at both ends of the composite channel structure (104), a p-NiO layer (107) covering the composite channel structure (104) in a three-dimensional form, and a p-NiO layer (107) covering the p-NiO layer (107). + -NiO layer (108), covering p + - Gate (109) above NiO layer (108); wherein, the hole of mask layer (103) is a hexagonal elongated hole symmetrical along both direction 1 and direction 2, the included angle between any two adjacent sides is 120°, the two sides parallel to direction 1 are the long sides with a length of a, and at each end of direction 1 there are two sides with an included angle of 60° with direction 1, which are the short sides with a length of b; direction 1 is the lateral direction, and direction 2 is the third-dimensional direction that is perpendicular to both the lateral and vertical directions; the composite channel structure (104) is a mesa structure extending upward from the elongated hole of mask layer (103), and from bottom to top includes 2 to 5 pairs of GaN channel layers (1041) and In arranged sequentially. x Al y Ga 1-x-yThe N-type barrier layer (1042) has a bottom surface with a (000-2) crystal plane that is in contact with the GaN buffer layer (102), and a top surface with a (0002) crystal plane. The bottom and top surfaces are formed by P. m crystal planes m and P n A crystal plane n is connected, and both crystal plane m and crystal plane n are inclined planes that are not perpendicular to the top surface; the source (105) covers the inclined plane and top surface of the composite channel structure (104) along direction 1 in the form of an ohmic contact, and the drain (106) covers the inclined plane and top surface of the composite channel structure (104) on the other side of direction 1 in the form of an ohmic contact; the p-NiO layer (107) covers the surface of the composite channel structure (104) and does not contact the edge of the source (105) and the edge of the drain (106), p + A -NiO layer (108) covers the surface of the p-NiO layer (107) and is close to the source (105) side, and a gate (109) covers the p-NiO layer (107). + - The surface of the NiO layer (108).

[0045] P m and P n The crystal planes are 4 and 2 respectively. The crystal plane m is a {20-21} plane, named m1 to m4, and the crystal plane n is a {10-11} plane, named n1 to n2. Among them, the two {10-11} planes n1 and n2 extend along direction 1 and their bottoms are in contact with the long side of the long hole of the mask layer (103). The p-NiO layer (107) covers n1 and n2. One side of the source electrode (105) contains two {20-21} planes m1 and m2, which are in contact with each other and n1 and n2. One side of the drain electrode (106) contains two {20-21} planes m3 and m4, which are in contact with each other and n1 and n2.

[0046] A 5 μm GaN buffer layer (102) is grown on the substrate layer (101). A 30 nm SiO2 thin film is deposited on the GaN buffer layer (102) as a mask layer (103). A hexagonal hole array pattern is etched out. The holes are hexagonal elongated holes that are symmetrical along both directions 1 and 2. The included angle between any two adjacent sides is 120°, exposing the underlying GaN buffer layer (102). The length a of the long side of the hole is 15 μm. Since the numerical relationship between a and b satisfies a = 20 × 1.73 × b, then b is 0.43 μm.

[0047] The composite channel structure (104) includes three pairs of GaN channel layers (1041) and In arranged sequentially. x Al y Ga 1-x-y The N-barrier layer (1042) has a GaN channel layer (1041) with a thickness of 75 nm, and the In... x Al y Ga1-x-y The thickness of the N-barrier layer (1042) is 25 nm. x Al y Ga 1-x-y The In component x of N is 0.1, and the Al component y is 0.25.

[0048] The source electrode (105) has a width of 1 μm along direction 1. The material used for the source electrode (105) is a combination of Ti / Al / Ni / Au, and the thickness of each material is 10 nm, 20 nm, 10 nm, and 30 nm, respectively. The drain electrode (106) has a width of 1 μm along direction 1. The material used for the drain electrode (106) is a combination of Ti / Al / Ni / Au, and the thickness of each material is 10 nm, 20 nm, 10 nm, and 30 nm, respectively.

[0049] The p-NiO layer (107) is 3 μm away from the boundary of the source (105) and 3 μm away from the boundary of the drain (106), with a thickness of 200 nm. The gradient p-type doping concentration ranges from 2.2 × 10⁻⁶. 17 cm -3 ~8.6×10 17 cm -3 .

[0050] p + The NiO layer (108) has a width of 3 μm and a thickness of 50 nm along direction 1, with a p-type doping concentration of 5 × 10⁻⁶. 19 cm -3 .

[0051] The gate (109) is made of Pt, a metal with a high work function, and has a thickness of 50 nm.

[0052] Embodiment 1 of the present invention provides a method for fabricating a RESURF GaN-based HEMT device with a polycrystalline structure, comprising the following steps:

[0053] a) SiC, a commercially available material that can be directly epitaxially grown into GaN thin films, is selected as the substrate layer (101), and a GaN buffer layer (102) is grown by MOCVD epitaxy.

[0054] b) SiO2 is deposited on the GaN buffer layer (102) as a mask layer (103) using PECVD technology; using standard ultraviolet lithography, pattern transfer is performed on the mask layer (103) to obtain a specially designed hexagonal array pattern; further, RIE technology is used to etch away the hexagonal regions, exposing the hexagonal hole array of the GaN buffer layer (102) on the mask layer (103), thus completing the fabrication of the mask layer (103) containing the specific hole array, such as... Figure 3 As shown;

[0055] c) Using an MOCVD system, selective epitaxy was achieved using a hexagonal array of holes in the mask layer (103) to grow the bottom GaN channel layer (1041). The growth conditions were as follows: growth temperature of 1060℃, V / III ratio of 1000, growth pressure of 700 Torr, and the total flow rate v (in sccm) of the carrier gas entering the reaction chamber satisfied 760v = 70pa, where P is the growth pressure (in Torr) and A is the area of ​​the graphite disk in the reaction chamber of the MOCVD system (in square centimeters). After the growth of the bottom GaN channel layer (1041) was completed, the growth temperature was maintained.

[0056] With the V / III ratio and pressure unchanged, the total flow rate v of the carrier gas introduced into the reaction chamber is increased to 1.2 times to complete the growth of the remaining part of the composite channel structure (104), such as Figure 4 As shown;

[0057] d) Using standard ultraviolet lithography, the region requiring p-NiO layer (107) deposition is formed on the composite channel structure (104); NiO is deposited using magnetron sputtering with high-purity nickel as the target material. The sputtering conditions are as follows: the introduced gases are O2 and Ar, the sputtering power is 150W, and the gas pressure is 4mTorr; during the deposition process, the ratio of introduced O2 to Ar is adjusted from the initial 7:3 to 5:5, and the oxygen flow rate is gradually reduced, thus completing the preparation of the p-NiO layer (107). Similarly, using ultraviolet lithography, the region requiring p-NiO layer (107) to be sputtered is formed above the p-NiO layer (107). + - NiO layer (108) region, deposited p + -NiO layer (108);

[0058] e) in p + - Photoresist is coated on the surface of the NiO layer (108), and then exposed and developed. Subsequently, the gate (109) is deposited, and the corresponding source (105) and drain (106) are prepared on the surface of the composite channel structure (104). Then, a rapid annealing process is performed to complete the fabrication of this device structure, such as Figure 6 As shown.

[0059] Example 2:

[0060] A top view of a RESURF GaN-based HEMT device with a polycrystalline structure provided in Embodiment 2 of the present invention is shown below. Figure 7 As shown, the cross-sectional view along direction 1 at the center of symmetry in direction 2 is as follows. Figure 1 As shown, a cross-sectional view of the gate (109) along direction 2 is as follows. Figure 2As shown. The structural features of this device, from bottom to top, are: a substrate layer (101), a GaN buffer layer (102) with an upward crystal plane of (0002), a mask layer (103) containing a specific array of holes, a composite channel structure (104) within the holes of the mask layer (103) and in contact with the GaN buffer layer (102), a source (105) and a drain (106) located at both ends of the composite channel structure (104), a p-NiO layer (107) covering the composite channel structure (104) in a three-dimensional form, and a p-NiO layer (107) covering the p-NiO layer (107). + -NiO layer (108), covering p + - Gate (109) above NiO layer (108); wherein, the hole of mask layer (103) is a hexagonal elongated hole symmetrical along both direction 1 and direction 2, the included angle between any two adjacent sides is 120°, the two sides parallel to direction 1 are the long sides with a length of a, and at each end of direction 1 there are two sides with an included angle of 60° with direction 1, which are the short sides with a length of b; direction 1 is the lateral direction, and direction 2 is the third-dimensional direction that is perpendicular to both the lateral and vertical directions; the composite channel structure (104) is a mesa structure extending upward from the elongated hole of mask layer (103), and from bottom to top includes 2 to 5 pairs of GaN channel layers (1041) and In arranged sequentially. x Al y Ga 1-x-y The N-type barrier layer (1042) has a bottom surface with a (000-2) crystal plane that is in contact with the GaN buffer layer (102), and a top surface with a (0002) crystal plane. The bottom and top surfaces are formed by P. m crystal planes m and P n A crystal plane n is connected, and both crystal plane m and crystal plane n are inclined planes that are not perpendicular to the top surface; the source (105) covers the inclined plane and top surface of the composite channel structure (104) along direction 1 in the form of an ohmic contact, and the drain (106) covers the inclined plane and top surface of the composite channel structure (104) on the other side of direction 1 in the form of an ohmic contact; the p-NiO layer (107) covers the surface of the composite channel structure (104) and does not contact the edge of the source (105) and the edge of the drain (106), p + A -NiO layer (108) covers the surface of the p-NiO layer (107) and is close to the source (105) side, and a gate (109) covers the p-NiO layer (107). + - The surface of the NiO layer (108).

[0061] P m and P nThe crystal planes are 3 and 6 respectively. The crystal plane m is a {1-102} plane, named m1 to m3, and the crystal plane n is a {11-23} plane, named n1 to n6. Among them, the two {11-23} planes n1 and n2 extend along direction 1 and their bottoms are in contact with the long side of the long hole of the mask layer (103). The p-NiO layer (107) covers n1 and n2. The side of the source electrode (105) includes two {1-102} planes m1 and m2 and two {11-23} planes n3 and n4. m1 and m2 are in contact with n1 and n2, and n3 and n4 are in contact with each other and respectively in contact with m1 and m2. The side of the drain electrode (106) includes one {1-102} plane m3 and two {11-23} planes n5 and n6. n5 and n6 are in contact with n1 and n2, and m3 is in contact with n5 and n6.

[0062] A 6 μm GaN buffer layer (102) is grown on the substrate layer (101). A 40 nm SiO2 thin film is deposited on the GaN buffer layer (102) as a mask layer (103). A hexagonal hole array pattern is etched out. The holes are hexagonal elongated holes that are symmetrical along both directions 1 and 2. The included angle between any two adjacent sides is 120°, exposing the underlying GaN buffer layer (102). The length a of the long side of the hole is 20 μm. Since the numerical relationship between a and b satisfies a = 20 × 1.73 × b, then b is 0.58 μm.

[0063] The composite channel structure (104) includes three pairs of GaN channel layers (1041) and In arranged sequentially. x Al y Ga 1-x-y The N-barrier layer (1042) has a thickness of 85 nm, where the GaN channel layer (1041) is 85 nm thick. x Al y Ga 1-x-y The thickness of the N-barrier layer (1042) is 25 nm. x Al y Ga 1-x-y The In component x of N is 0, and the Al component y is 0.25.

[0064] The source electrode (105) has a width of 2 μm along direction 1. The material used for the source electrode (105) is a combination of Ti / Al / Ni / Au, and the thickness of each material is 10 nm, 20 nm, 10 nm, and 30 nm, respectively. The drain electrode (106) has a width of 2 μm along direction 1. The material used for the drain electrode (106) is a combination of Ti / Al / Ni / Au, and the thickness of each material is 10 nm, 20 nm, 10 nm, and 30 nm, respectively.

[0065] The p-NiO layer (107) is 4 μm from one boundary of the source (105) and 4 μm from one boundary of the drain (106), with a thickness of 250 nm. The gradient p-type doping concentration ranges from 2.9 × 10⁻⁶. 17 cm -3 ~1.2×10 18 cm -3 .

[0066] p + The NiO layer (108) has a width of 4 μm and a thickness of 50 nm along direction 1, with a p-type doping concentration of 6 × 10⁻⁶. 19 cm -3 .

[0067] The gate (109) is made of Pt, a metal with a high work function, and has a thickness of 50 nm.

[0068] Embodiment 2 of the present invention provides a method for fabricating a RESURF GaN-based HEMT device with a polycrystalline structure, comprising the following steps:

[0069] a) Select Si, a commercially available material that can be directly epitaxially grown into GaN thin films, as the substrate layer (101), and use MOCVD to epitaxially grow a GaN buffer layer (102).

[0070] b) SiO2 is deposited on the GaN buffer layer (102) as a mask layer (103) using PECVD technology; using standard ultraviolet lithography, pattern transfer is performed on the mask layer (103) to obtain a specially designed hexagonal array pattern; further, RIE technology is used to etch away the hexagonal regions, exposing the hexagonal hole array of the GaN buffer layer (102) on the mask layer (103), thus completing the fabrication of the mask layer (103) containing the specific hole array, such as... Figure 3 As shown;

[0071] c) Using an MOCVD system and a hexagonal aperture array of a mask layer (103), selective epitaxy is achieved to grow the bottom GaN channel layer (1041). The growth conditions are as follows: growth temperature is 1070℃, V / III ratio is 600, growth pressure is 750 Torr, and the total flow rate v of the carrier gas entering the reaction chamber (in sccm) satisfies 760v = 70 Pa, and the flow rate Nv of NH3 (in sccm) satisfies Nv = 80 A. Where P is the growth pressure (in Torr) and A is the area of ​​the graphite disk in the reaction chamber of the MOCVD system (in square centimeters). After the growth of the bottom GaN channel layer (1041) is completed, the growth temperature, V / III ratio and pressure are kept constant, and the total flow rate v of the carrier gas entering the reaction chamber is increased to 1.2 times to complete the growth of the remaining part of the composite channel structure (104), such as Figure 5 As shown;

[0072] d) Using standard ultraviolet lithography, the region requiring p-NiO layer (107) deposition is formed on the composite channel structure (104); NiO is deposited using magnetron sputtering with high-purity nickel as the target material. The sputtering conditions are as follows: the introduced gases are O2 and Ar, the sputtering power is 150W, and the gas pressure is 4mTorr; during the deposition process, the ratio of introduced O2 to Ar is adjusted from the initial 7:3 to 5:5, and the oxygen flow rate is gradually reduced, thus completing the preparation of the p-NiO layer (107). Similarly, using ultraviolet lithography, the region requiring p-NiO layer (107) to be sputtered is formed above the p-NiO layer (107). + - NiO layer (108) region, deposited p + -NiO layer (108);

[0073] e) in p + - Photoresist is coated on the surface of the NiO layer (108), and then exposed and developed. Subsequently, the gate (109) is deposited, and the corresponding source (105) and drain (106) are prepared on the surface of the composite channel structure (104). Then, a rapid annealing process is performed to complete the fabrication of this device structure, such as Figure 7 As shown.

[0074] Working principle of this invention:

[0075] The composite channel structure (104) adopts a beveled design, forming specific three-dimensional GaN mesa by growing the {20-21} and {10-11} or {1-102} and {11-23} planes of GaN, thus avoiding damage during the etching process. Furthermore, the composite channel structure (104) consists of alternating GaN channel layers (1041) and In... x Al y Ga 1-x-y The device consists of an N-barrier layer (1042), and the multi-channel structure forms multiple current paths, reducing the on-resistance of the device. A p-NiO layer (107) is deposited on the surface and slope of the composite channel structure (104), and the doping concentration is adjusted using gradient doping technology, with higher doping concentration closer to the composite channel structure (104). The higher concentration of the p-NiO layer (107) effectively reduces the barrier width between NiO and GaN, enhances hole injection capability, improves current transport characteristics, and optimizes the electric field distribution through interaction with 2DEG, thereby improving the device's breakdown voltage and dynamic performance. + The high concentration of NiO in the NiO layer (108) optimizes current collapse and forms an ohmic contact with the gate (109). The gate (109) covers the p in a three-dimensional morphology. +- The NiO layer (108) surface enhances gate control capability. In summary, the polycrystalline structure RESURF GaN-based HEMT device of the present invention achieves high breakdown voltage, low on-resistance, and excellent dynamic performance through optimized structural design and gradient doping process without etching damage, making it suitable for high-power electronic devices.

Claims

1. A RESURF GaN-based HEMT with a polycrystalline structure, characterized in that: The structure includes, from bottom to top, a substrate layer (101), a GaN buffer layer (102) with an upward crystal plane (0002), a mask layer (103) containing a specific array of holes, a composite channel structure (104) within the holes of the mask layer (103) and in contact with the GaN buffer layer (102), a source electrode (105) and a drain electrode (106) located at both ends of the composite channel structure (104), a p-NiO layer (107) covering the composite channel structure (104) in a three-dimensional form, and a p-NiO layer (107) covering the p-NiO layer (107). + -NiO layer (108), covering p + - Gate (109) above NiO layer (108); wherein, the hole of mask layer (103) is a hexagonal elongated hole symmetrical along both direction 1 and direction 2, the included angle between any two adjacent sides is 120°, the two sides parallel to direction 1 are the long sides with a length of a, and at each end of direction 1 there are two sides with an included angle of 60° with direction 1, which are the short sides with a length of b; the direction 1 is the lateral direction, and the direction 2 is the third-dimensional direction that is perpendicular to both the lateral and vertical directions; the composite channel structure (104) is a mesa structure extending upward from the elongated hole of mask layer (103), and from bottom to top includes 2 to 5 pairs of GaN channel layers (1041) and In x Al y Ga 1-x-y The N-type barrier layer (1042) has a bottom surface with a (000-2) crystal plane and is in contact with the GaN buffer layer (102). The top surface has a (0002) crystal plane. The bottom and top surfaces are formed by P. m crystal planes m and P n The crystal planes n are connected, and both crystal planes m and n are inclined planes that are not perpendicular to the top surface; the source (105) covers the inclined plane and top surface of the composite channel structure (104) along direction 1 in the form of an ohmic contact, and the drain (106) covers the inclined plane and top surface of the composite channel structure (104) on the other side of direction 1 in the form of an ohmic contact; the p-NiO layer (107) covers the surface of the composite channel structure (104) and does not contact the edge of the source (105) and the edge of the drain (106), p + A -NiO layer (108) covers the surface of the p-NiO layer (107) and is close to the source (105) side, and a gate (109) covers the p-NiO layer. + -Surface of NiO layer (108); P m and P n When the values ​​are 4 and 2 respectively, the crystal plane m is a {20-21} plane, named m1~m4, and the crystal plane n is a {10-11} plane, named n1~n2; among them, the two {10-11} planes n1 and n2 extend along direction 1 and their bottoms are in contact with the long side of the elongated hole of the mask layer (103), and the p-NiO layer (107) covers these n1 and n2; one side of the source electrode (105) contains two {20-21} planes m1 and m2, which are in contact with each other and with n1 and n2; one side of the drain electrode (106) contains two {20-21} planes m3 and m4, which are in contact with each other and with n1 and n2; or, P m and P n When the crystal planes are 3 and 6 respectively, the crystal plane m is a {1-102} plane, named m1~m3, and the crystal plane n is a {11-23} plane, named n1~n6; among them, the two {11-23} planes n1 and n2 extend along direction 1 and their bottoms are in contact with the long side of the long hole of the mask layer (103), and the p-NiO layer (107) covers n1 and n2; one side of the source electrode (105) includes two {1-102} planes m1 and m2 and two {11-23} planes n3 and n4, m1 and m2 are in contact with n1 and n2, n3 and n4 are in contact with each other and are in contact with m1 and m2 respectively; one side of the drain electrode (106) includes one {1-102} plane m3 and two {11-23} planes n5 and n6, n5 and n6 are in contact with n1 and n2, and m3 is in contact with n5 and n6.

2. The RESURF GaN-based HEMT with a polycrystalline structure according to claim 1, characterized in that: The mask layer (103) is made of SiO2 or SiN. x The material is one of hBN or Al2O3, with a thickness of 10~100 nm; in the hexagonal elongated hole in the mask layer (103), the numerical relationship between the length of the long side a and the length of the short side b satisfies a=20×1.73×b, where the length of a ranges from 10 to 25 μm.

3. A RESURF GaN-based HEMT with a polycrystalline structure according to claim 1, characterized in that: The thickness of the GaN channel layer (1041) in the composite channel structure (104) ranges from 30 to 100 nm, and the In... x Al y Ga 1-x-y The thickness of the N-barrier layer (1042) ranges from 20 to 30 nm; among which, In x Al y Ga 1-x-y The In component x in N is 0~0.15, and the Al component y is 0.15~0.

35.

4. A RESURF GaN-based HEMT with a polycrystalline structure according to claim 1, characterized in that: The source (105) has a width of 1~3 μm along direction 1, and the drain (106) has a width of 1~3 μm along direction 1. The source (105) and drain (106) can be made of any one of Ti, Al, Ni, and Au, and their thickness is 30~100 nm. Alternatively, the source (105) and drain (106) can be made of a multilayer structure composed of Ti / Al / Ni / Au, and the thickness of each material is 10 nm, 20 nm, 10 nm, and 30 nm, respectively.

5. A RESURF GaN-based HEMT with a polycrystalline structure according to claim 1, characterized in that: The p-NiO layer (107) covers the top and slope surfaces of the composite channel structure (104), with a distance of 2~4 μm from one side boundary of the source (105) and 2~8 μm from one side boundary of the drain (106), and a thickness of 100~300 nm. The p-NiO layer (107) is a graded p-type doped layer, with a higher doping concentration near the composite channel structure (104), and the doping concentration is b×x1×x2, where b is in μm and x1 is 1×10. 17 cm -3 The range of x2 is 5~20 μm -1 .

6. A RESURF GaN-based HEMT with a polycrystalline structure according to claim 1, characterized in that: The p + The -NiO layer (108) covers the surface of the p-NiO layer (107) near the source (105), with a width of 2~6 μm and a thickness of 30~100 nm along direction 1, and a doping concentration ranging from 1×10⁻⁶. 19 cm -3 ~1×10 20 cm -3 .

7. A RESURF GaN-based HEMT with a polycrystalline structure according to claim 1, characterized in that: The gate (109) covers p + - The surface of the NiO layer (108) is made of one or more of the high work function metals Pt, Au, and Pd, with a thickness of 30~100 nm.

8. The method for preparing a polycrystalline GaN-based HEMT according to claim 1, wherein when P m and P n When the crystal planes are 4 and 2 respectively, the crystal plane m is a {20-21} plane, named m1~m4, and the crystal plane n is a {10-11} plane, named n1~n2; among them, the two {10-11} planes n1 and n2 extend along direction 1 and their bottoms are in contact with the long side of the long hole of the mask layer (103), and the p-NiO layer (107) covers these n1 and n2; one side of the source electrode (105) contains two {20-21} planes m1 and m2, which are in contact with each other and with n1 and n2; one side of the drain electrode (106) contains two {20-21} planes m3 and m4, which are in contact with each other and with n1 and n2; the fabrication method of this device includes the following steps: a) Select one of Si, SiC, GaN or Al2O3 that can be used to directly grow GaN thin films as a substrate layer (101), and grow a GaN buffer layer using one of MOCVD, MBE or HVPE technology (102). b) Deposit SiO2 or SiN on the GaN buffer layer (102) using PECVD technology. x As a mask layer (103), a pattern transfer is performed on the mask layer (103) using standard ultraviolet lithography technology to obtain a specially designed hexagonal array pattern. Then, the hexagonal area is etched away using RIE technology to expose the hexagonal hole array of the GaN buffer layer (102) on the mask layer (103), thus completing the fabrication of the mask layer (103) containing the specific hole array. c) Using an MOCVD system, selective epitaxy is achieved using the hexagonal aperture array of the mask layer (103) to grow the bottom GaN channel layer (1041). The growth conditions are as follows: growth temperature is 1050~1080℃, V / III ratio is 800~1500, growth pressure is 600~760 Torr, and the total flow rate v of the carrier gas introduced into the reaction chamber satisfies 50PA<760v<80PA, where P is the growth pressure, A is the area of ​​the graphite disk in the reaction chamber of the MOCVD system, v is in sccm, P is in Torr, and A is in square centimeters. After the growth of the bottom GaN channel layer (1041) is completed, the growth temperature, V / III ratio and pressure are kept constant, and the total flow rate v of the carrier gas introduced into the reaction chamber is increased to 1.1~1.3 times to complete the growth of the remaining part of the composite channel structure (104). d) Using standard ultraviolet lithography, the region where the p-NiO layer (107) needs to be deposited is formed on the composite channel structure (104); NiO is deposited using magnetron sputtering with high-purity metallic nickel as the target material. The sputtering conditions are as follows: the introduced gases are O2 and Ar, the sputtering power is 100~200 W, and the gas pressure is 3~5 mTorr; during the deposition process, the ratio of introduced O2 to Ar is adjusted from the initial 7:3 to 5:5, and the oxygen flow rate is gradually reduced, and then the p-NiO layer (107) is prepared; similarly, the region where the p-NiO layer (107) needs to be sputtered is formed on top of the p-NiO layer (107) using ultraviolet lithography. + - NiO layer (108) region, deposited p + -NiO layer (108); e) In p + - Photoresist is coated on the surface of the NiO layer (108), and then exposed and developed. Subsequently, the gate (109) is deposited, and the corresponding source (105) and drain (106) are prepared on the surface of the composite channel structure (104). Then, a rapid annealing process is performed to complete the fabrication of this device structure.

9. The method for preparing a polycrystalline GaN-based HEMT according to claim 1, wherein when P m and P n When the crystal planes are 3 and 6 respectively, the crystal plane m is a {1-102} plane, named m1~m3, and the crystal plane n is a {11-23} plane, named n1~n6; among them, the two {11-23} planes, n1 and n2, extend along direction 1 and their bottoms are in contact with the long side of the elongated hole of the mask layer (103), and the p-NiO layer (107) covers these n1 and n2; one side of the source electrode (105) contains two {m1 and m2} planes. The device comprises a {1-102} surface and two {11-23} surfaces, n3 and n4. m1 and m2 are in contact with n1 and n2, and n3 and n4 are in contact with each other and respectively with m1 and m2. One side of the drain (106) includes a {1-102} surface, m3, and two {11-23} surfaces, n5 and n6. n5 and n6 are in contact with n1 and n2, and m3 is in contact with n5 and n6. The fabrication method of this device includes the following steps: a) Select one of Si, SiC, GaN or Al2O3 that can be used to directly grow GaN thin films as a substrate layer (101), and grow a GaN buffer layer using one of MOCVD, MBE or HVPE technology (102). b) Deposit SiO2 or SiN on the GaN buffer layer (102) using PECVD technology. x As a mask layer (103), a pattern transfer is performed on the mask layer (103) using standard ultraviolet lithography technology to obtain a specially designed hexagonal array pattern. Then, the hexagonal area is etched away using RIE technology to expose the hexagonal hole array of the GaN buffer layer (102) on the mask layer (103), thus completing the fabrication of the mask layer (103) containing the specific hole array. c) Using an MOCVD system, selective epitaxy is achieved using a hexagonal aperture array of a mask layer (103) to grow the bottom GaN channel layer (1041). The growth conditions are as follows: the growth temperature is 1050~1080℃, the V / III ratio is 500~700, the growth pressure is 600~760 Torr, and the total flow rate v of the carrier gas introduced into the reaction chamber satisfies 50PA<760v<80PA, and the flow rate Nv of NH3 satisfies 50A<Nv<100A; where P is the growth pressure, A is the area of ​​the graphite disk in the reaction chamber of the MOCVD system, v and Nv are in sccm, P is in Torr, and A is in square centimeters; after the growth of the bottom GaN channel layer (1041) is completed, the growth temperature, V / III ratio and pressure are kept constant, and the total flow rate v of the carrier gas introduced into the reaction chamber is increased to 1.1~1.3 times to complete the growth of the remaining part of the composite channel structure (104); d) Using standard ultraviolet lithography, the region where the p-NiO layer (107) needs to be deposited is formed on the composite channel structure (104); NiO is deposited using magnetron sputtering with high-purity metallic nickel as the target material. The sputtering conditions are as follows: the introduced gases are O2 and Ar, the sputtering power is 100~200 W, and the gas pressure is 3~5 mTorr; during the deposition process, the ratio of introduced O2 to Ar is adjusted from the initial 7:3 to 5:5, and the oxygen flow rate is gradually reduced, and then the p-NiO layer (107) is prepared; similarly, the region where the p-NiO layer (107) needs to be sputtered is formed on top of the p-NiO layer (107) using ultraviolet lithography. + - NiO layer (108) region, deposited p + -NiO layer (108); e) In p + - Photoresist is coated on the surface of the NiO layer (108), and then exposed and developed. Subsequently, the gate (109) is deposited, and the corresponding source (105) and drain (106) are prepared on the surface of the composite channel structure (104). Then, a rapid annealing process is performed to complete the fabrication of this device structure.

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