Switching element

Abstract

The switching element is configured with a plurality of rows in which the connection regions are linearly arranged at intervals in a second direction intersecting the trenches extending in the first direction. An intersection portion between the inter-trench semiconductor layer and the column has a connection intersection portion in which the connection region is provided and a non-connection intersection portion in which the connection region is not provided. In each of the columns, portions in which the connecting intersection sections are continuous and portions in which the non-connecting intersection sections are continuous are alternately arranged. Between adjacent columns, the phases of the patterns are shifted in the second direction. The Chebyshev distance to the connection intersection portion in each of the non-connection intersection portions is 1. In each connection intersection, the Chebyshev distance to the non-connection intersection is 1.

Description

Technical Field

[0001] The technology disclosed in this specification relates to a switching element. Background Art

[0002] Patent document 1 discloses a trench gate type switching element. In this switching element, a plurality of deep layers of p type are provided inside an n type drift layer. In the thickness direction of the semiconductor substrate, each deep layer is arranged on the lower side than the lower end of the trench. In addition, in the thickness direction of the semiconductor substrate, each deep layer can also be arranged in a range including the lower end of the trench. In addition, the switching element of patent document 1 has a plurality of p type connection regions. Each connection region connects each deep layer to a p type body layer. By providing the deep layer and the connection region in this way, it is possible to suppress the electric field applied to the gate insulating film covering the lower end of the trench.

[0003] In Patent Document 1, when the semiconductor substrate is viewed from above, the connection regions are dispersedly arranged with predetermined intervals in the x-direction and the y-direction. That is, when the semiconductor substrate is viewed from above, the connection regions are dispersedly arranged. By distributing the connection regions, a wider channel is ensured.

[0004] Inside the switch element, a diode (so-called body diode) is formed by the interface between the p-type body layer and the n-type drift layer. When the voltage applied to the body diode is switched from forward to reverse, a recovery current flows through the switch element, generating a recovery surge. If the density of the connection area is low as in Patent Document 1, the recovery surge can be suppressed.

[0005] Prior art literature

[0006] Patent Literature

[0007] Patent Document 1: Japanese Patent Application Publication No. 2022-083790 Summary of the invention

[0008] During the operation of the switching element, a recovery current or an avalanche current may flow from the drift region to each connection region. According to the switching element of Patent Document 1, when a recovery current or an avalanche current flows in the drift region, the current is likely to concentrate near each connection region.

[0009] In addition, according to Patent Document 1, a connection region is independently provided for each semiconductor layer sandwiched by the trench (hereinafter referred to as an inter-trench semiconductor layer). However, when the trenches are highly densed, the width of the inter-trench semiconductor layer becomes narrower, making it difficult to independently form a connection region for each inter-trench semiconductor layer.

[0010] In this specification, a technique is proposed for ensuring a wide channel and suppressing current concentration near each connection region when it is difficult to independently form a connection region for each inter-trench semiconductor layer.

[0011] The switch element disclosed in this specification comprises a semiconductor substrate, a gate insulating film, a gate electrode and a source electrode. A plurality of grooves are provided on the upper surface of the semiconductor substrate, each of the grooves extending linearly in a first direction on the upper surface of the semiconductor substrate, and each of the grooves is arranged at intervals in a second direction intersecting the first direction on the upper surface of the semiconductor substrate. The gate insulating film covers the inner surface of each of the grooves. The gate electrode is arranged in each of the grooves and insulated from the semiconductor substrate by the gate insulating film. The source electrode is in contact with the upper surface of the semiconductor substrate. The semiconductor substrate comprises a plurality of inter-groove semiconductor layers sandwiched by the plurality of grooves. Each inter-groove semiconductor layer comprises: an n-type source region in contact with the gate insulating film and the source electrode; and a p-type body region in contact with the gate insulating film on the lower side of the source region. The semiconductor substrate comprises a drift region, a plurality of deep regions and a plurality of connection regions. The drift region is an n-type region, distributed across the lower part of the plurality of inter-trench semiconductor layers, and in contact with the gate insulating film at the lower side of the body region in each inter-trench semiconductor layer. The plurality of deep regions are p-type regions, arranged in the range surrounded by the drift region, and arranged at a distance from the body region and below the body region, and arranged in the range including the lower end of the trench or below the lower end of the trench in the thickness direction of the semiconductor substrate. The plurality of connection regions are p-type regions connecting the body region and the deep region. When the semiconductor substrate is observed from above, the connection regions constitute a plurality of columns that are spaced apart and arranged in a straight line along the second direction, and the plurality of columns are spaced apart in the first direction. When the semiconductor substrate is observed from above, the intersections of the plurality of inter-trench semiconductor layers and the plurality of columns have connection intersections in which the connection regions are provided and non-connection intersections in which the connection regions are not provided. The connection intersections and the non-connection intersections satisfy the following conditions (i) to (iv), namely:

[0012] (i) in each of the columns, the connected intersections and the non-connected intersections are arranged in a pattern in which a portion of the connected intersections having a first reference number of two or more and a portion of the non-connected intersections having a second reference number of two or more are arranged alternately in the second direction;

[0013] (ii) between adjacent columns, the phase of the pattern is shifted in the second direction;

[0014] (iii) when the Chebyshev distance is counted in units of the above-mentioned intersections, in each non-connected intersection, the Chebyshev distance to the above-mentioned connected intersection is 1;

[0015] (iv) When the Chebyshev distance is counted in units of the intersections, in each connected intersection, the Chebyshev distance to the non-connected intersection is 1.

[0016] In this switch element, the first reference number (ie, 2 or more) of connection intersections are continuous in the second direction. That is, the connection intersections are provided across a plurality of inter-trench semiconductor layers. Therefore, even when the width of the inter-trench semiconductor layer is narrow, the connection intersections can be appropriately formed.

[0017] In addition, if the connection intersections are dense, the connection area located at the center of the dense area hardly contributes to the stability of the potential in the deep layer. If such a useless connection area exists, the channel is reduced corresponding to its connection area. In contrast, in the above-mentioned switching element disclosed in this specification, when the Chebyshev distance is counted in units of the above-mentioned intersections, in each connection intersection, the Chebyshev distance to the above-mentioned non-connection intersection is 1. That is, the density of the connection intersections is suppressed. Therefore, in this switching element, the channel can be ensured to be wider.

[0018] In addition, if there is a non-connected intersection that is very far from the connected intersection, it is difficult for the recovery current and the avalanche current to flow near the non-connected intersection that is very far from the connected intersection. In this case, the density of the recovery current and the avalanche current becomes high near the connection area. In contrast, in the above-mentioned switching element disclosed in this specification, when the Chebyshev distance is counted in units of intersections, in each non-connected intersection, the Chebyshev distance to the connected intersection is 1. That is, there is no non-connected intersection that is very far from the connected intersection. Therefore, in this switching element, the concentration of current near each connection area is suppressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a perspective view including a longitudinal cross section along the x direction and the y direction of the switching element according to the first embodiment.

[0020] Figure 2 is a diagram showing the position including the deep region of the switch element according to the first embodiment ( Figure 6 A cross-sectional view of the longitudinal section along the y direction at the position of the II-II line).

[0021] Figure 3 is a diagram showing a position of the switch element according to the first embodiment excluding the deep region ( Figure 6A cross-sectional view of the longitudinal section along the y direction at the position of the III-III line).

[0022] Figure 4 is a diagram showing a position of the switching element according to the first embodiment excluding the groove ( Figure 6 A cross-sectional view of the longitudinal section along the x direction at the position of the IV-IV line.

[0023] Figure 5 1 shows the position of the switching element including the groove ( Figure 6 A cross-sectional view of the longitudinal section along the x direction at the position of the V-V line.

[0024] Figure 6 It is a plan view showing the arrangement of the connection intersection portions of the switching element according to the first embodiment.

[0025] Figure 7 This is a layout diagram of the connection intersection portion according to the first embodiment.

[0026] Figure 8 It is a layout diagram of the connection intersection part of the first comparative example.

[0027] Fig. 9 It is a layout diagram of the connection intersection portion of the second comparative example.

[0028] Fig.10 It is a perspective view including a longitudinal cross section along the x direction and the y direction of the switching element according to the second embodiment.

[0029] Fig.11 It is a plan view showing the arrangement of connection intersection portions of a switching element according to the second embodiment.

[0030] Fig.12 It is a perspective view including a longitudinal cross section along the x direction and the y direction of the switching element according to the third embodiment.

[0031] Fig.13 It is a plan view showing the arrangement of connection intersection portions of a switching element according to a third embodiment.

[0032] Fig.14 It is a perspective view including a longitudinal cross section along the x direction and the y direction of the switching element according to the fourth embodiment.

[0033] Fig.15 It is a plan view showing the arrangement of connection intersection portions of a switching element according to a fourth embodiment.

[0034] Fig.16 This is a perspective view including a longitudinal cross section along the x-direction and the y-direction of a switching element according to another embodiment.

[0035] Fig.17It is a configuration diagram showing a variation in the configuration of the connection crossing portion that satisfies conditions (i) to (iv) when A = B.

[0036] Fig.18 It is a configuration diagram showing a variation in the configuration of the connection crossing portion that satisfies conditions (i) to (iv) when A < B.

[0037] Fig.19 It is a configuration diagram showing the configuration of the connection crossing portion that satisfies conditions (i) to (iv) when A > B.

[0038] Fig. 20 It is a configuration diagram showing the configuration of the connection crossing portion when the amount of stagger changes. Detailed implementation

[0039] In the switching element of an example disclosed in this specification, it is possible that the above second reference number is equal to or greater than the above first reference number.

[0040] According to this structure, a small number of connection crossing portions can be efficiently and dispersedly arranged.

[0041] In the switching element of an example disclosed in this specification, it is possible that in each of the above trench-interposed semiconductor layers, when observed in units of the above crossing portion, the above connection crossing portion is not continuous in the above first direction.

[0042] According to this structure, the connection crossing portions can be arranged more dispersedly.

[0043] In the switching element of an example disclosed in this specification, it is possible that in each of the above trench-interposed semiconductor layers, when observed in units of the above crossing portion, the number of consecutive portions of the above connection crossing portion that are continuous in the above first direction is 3 or less.

[0044] According to this structure, the connection crossing portions can be arranged more dispersedly.

[0045] In the switching element of an example disclosed in this specification, it is possible that when the above first reference number is represented by an arbitrary integer A, the above second reference number is 3A. It is possible that in a plurality of the above columns, the phase of the above pattern periodically changes every 4 of the above columns. It is possible that when 4 of the above columns are sequentially set as the first column, the second column, the third column, and the fourth column and the amount of stagger of the phase of the above pattern is counted in units of the above crossing portion, the amount of stagger of the above second column with respect to the above first column is A, the amount of stagger of the above third column with respect to the above first column is 3A, and the amount of stagger of the above fourth column with respect to the above first column is 2A.

[0046] According to this structure, the connection crossing portions can be arranged dispersedly.

[0047] In a switching element of an example disclosed in the present specification, when the semiconductor substrate is viewed from above, the plurality of deep regions may extend linearly along the second direction and be spaced apart in the first direction in such a manner that each of the deep regions extends along the corresponding column.

[0048] In the switching element of one example disclosed in the present specification, a p-type contact region connecting the body region and the source electrode may be provided on an upper portion of each of the connection regions.

[0049] [First embodiment]

[0050] Figure 1 The switch element 10 of the first embodiment shown has a semiconductor substrate 12. The semiconductor substrate 12 is made of SiC. However, the semiconductor substrate 12 may also be made of other semiconductors such as Si and GaN. Hereinafter, a direction parallel to the upper surface 12a of the semiconductor substrate 12 is referred to as the x direction, a direction parallel to the upper surface 12a and orthogonal to the x direction is referred to as the y direction, and a thickness direction of the semiconductor substrate 12 is referred to as the z direction. A plurality of grooves 14 are provided on the upper surface 12a of the semiconductor substrate 12. Each groove 14 extends linearly in the x direction on the upper surface 12a. Each groove 14 is arranged at intervals in the y direction on the upper surface 12a. The inner surface of each groove 14 is covered by a gate insulating film 16. A gate electrode 18 is arranged in each groove 14. Each gate electrode 18 is insulated from the semiconductor substrate 12 by the gate insulating film 16. An interlayer insulating film 20 is arranged in each groove 14. Each interlayer insulating film 20 covers the upper surface of the gate electrode 18.

[0051] like Figure 2 to Figure 5 As shown in FIG. 1 , a source electrode 22 is provided on the upper portion of the semiconductor substrate 12. Figure 1 The source electrode 22 is omitted from the illustration. The source electrode 22 covers the upper surface of the interlayer insulating film 20 and the upper surface 12a of the semiconductor substrate 12. The source electrode 22 is insulated from the gate electrode 18 by the interlayer insulating film 20. A drain electrode 24 is provided at the lower part of the semiconductor substrate 12. The drain electrode 24 covers the lower surface 12b of the semiconductor substrate 12.

[0052] Figure 6 1 shows the upper surface 12a of the semiconductor substrate 12. As described above, on the upper surface 12a, a plurality of grooves 14 extending linearly in the x direction are arranged at intervals in the y direction. Figure 6The inter-trench semiconductor layer 30 shown is a semiconductor layer sandwiched by two trenches 14 (i.e., a semiconductor layer arranged between the two trenches 14). Each inter-trench semiconductor layer 30 extends linearly in the x direction on the upper surface 12a. Each inter-trench semiconductor layer 30 is arranged at intervals in the y direction on the upper surface 12a.

[0053] like Figure 1 As shown, the semiconductor substrate 12 has a source region 40 , a body region 42 , a drift region 44 , and a drain region 46 .

[0054] The source region 40 is an n-type region having a high n-type impurity concentration. The source region 40 is disposed in the inter-trench semiconductor layer 30. Figure 2 , Figure 3 As shown, the source region 40 is in contact with the source electrode 22 in the inter-trench semiconductor layer 30. The source region 40 is in contact with the gate insulating film 16 at the side surfaces of the trench 14 provided on both sides of the inter-trench semiconductor layer 30.

[0055] The body region 42 is a p-type region having a low p-type impurity concentration. The body region 42 is disposed in the inter-trench semiconductor layer 30. Figure 2 , Figure 3 As shown, the body region 42 is arranged in the inter-trench semiconductor layer 30 and arranged on the lower side of the source region 40. The body region 42 is in contact with the gate insulating film 16 on the lower side of the source region 40. That is, the body region 42 is in contact with the gate insulating film 16 at the side surfaces of the trenches 14 provided on both sides of the inter-trench semiconductor layer 30.

[0056] The drift region 44 is an n-type region having a low n-type impurity concentration. Figure 2 , Figure 3 As shown, the drift region 44 is distributed across the lower portion of the semiconductor layer 30 between the plurality of trenches. Figure 3 As shown, the upper end of the drift region 44 extends into each of the trench semiconductor layers 30. In each of the trench semiconductor layers 30, the drift region 44 is in contact with the body region 42 from the lower side. The drift region 44 is in contact with the gate insulating film 16 on the lower side of the body region 42. That is, the drift region 44 is in contact with the gate insulating film 16 at the side surfaces of the trenches 14 provided on both sides of each of the trench semiconductor layers 30.

[0057] The drain region 46 is an n-type region having a high n-type impurity concentration. The n-type impurity concentration of the drain region 46 is higher than the n-type impurity concentration of the drift region 44. Figure 2 to Figure 5 As shown, the drain region 46 is adjacent to the drift region 44 from the lower side. The drain region 46 is adjacent to the drain electrode 24 in the lower surface 12 b of the semiconductor substrate 12 .

[0058] The semiconductor substrate 12 has a plurality of p-type deep regions 50. Figure 2 , Figure 4 As shown, each deep region 50 is arranged in a range surrounded by the drift region 44. Each deep region 50 is arranged below the body region 42 at a distance from the body region 42. The drift region 44 is divided in the space between each deep region 50 and the body region 42. Figure 6 The area with dotted shadows in FIG. 5 represents the distribution range of the deep area 50. Figure 6 As shown in FIG. 1 , when the semiconductor substrate 12 is viewed from above, each deep region 50 extends in a straight line in the y direction. When the semiconductor substrate 12 is viewed from above, each deep region 50 is arranged at intervals in the x direction. Figure 1 , Figure 2 , Figure 5 As shown, each deep region 50 is arranged in a range including the lower end of the trench 14 in the z direction. Therefore, each deep region 50 is in contact with the gate insulating film 16 at the lower end of each trench 14.

[0059] like Figure 1 As shown, the semiconductor substrate 12 has a plurality of connection regions 52 and a plurality of contact regions 54. Figure 1 , Figure 2 , Figure 4 As shown, the connection region 52 is a p-type region connecting the body region 42 and the deep region 50. A plurality of connection regions 52 are provided in each of the trench-inter-semiconductor layers 30. The contact region 54 is a p-type region connecting the body region 42 and the source electrode 22. That is, the contact region 54 extends upward from the body region 42 and is in contact with the source electrode 22 at its upper end. A plurality of contact regions 54 are provided in each of the trench-inter-semiconductor layers 30. In the present embodiment, the contact region 54 and the connection region 52 extend continuously in the z direction. That is, the contact region 54 is arranged on the upper part of the connection region 52. The semiconductor substrate 12 has a group of a plurality of contact regions 54 and deep regions 50. Each deep region 50 is connected to the source electrode 22 via the connection region 52 and the contact region 54.

[0060] exist Figure 6 The area shaded with oblique lines in FIG. 5 represents a group of the connection area 52 and the contact area 54. The group of the connection area 52 and the contact area 54 is partially provided in the upper part of the deep area 50. Figure 6 As shown in FIG. 1 , when the semiconductor substrate 12 is viewed from above, the plurality of connection regions 52 are arranged in a plurality of rows 53 extending linearly in the y direction. Figure 6 In the diagram, the row 53 extending in the y direction overlaps with the deep region 50. The plurality of rows 53 are arranged at intervals in the x direction.

[0061] Figure 6The intersection 60 shown is a portion where the trench semiconductor layer 30 and the column 53 intersect when the semiconductor substrate 12 is viewed from above. In the first embodiment, the intersection 60 coincides with a portion where the trench semiconductor layer 30 and the deep region 50 intersect when the semiconductor substrate 12 is viewed from above. As described above, each trench semiconductor layer 30 extends in a straight line in the x-direction, and each column 53 extends in a straight line in the y-direction. Therefore, when the semiconductor substrate 12 is viewed from above, a plurality of intersections 60 are arranged in a matrix along the x-direction and the y-direction. Figure 6 As shown, the connection area 52 and the contact area 54 are arranged in a part of the plurality of intersections 60. Figure 1 , Figure 2 , Figure 6 As shown, each connection region 52 is connected to the gate insulating film 16 at the side of the groove 14 located on both sides of the intersection 60. In addition, the contact region 54 is connected to the gate insulating film 16 at the side of the groove 14 located on both sides of the intersection 60. Hereinafter, the intersection 60 provided with the connection region 52 is referred to as the connection intersection 60a, and the intersection 60 without the connection region 52 is referred to as the non-connection intersection 60b.

[0062] Figure 7 A diagram showing the arrangement of the connection intersection portion 60a and the non-connection intersection portion 60b. Figure 7 Each cell shown shows an intersection 60 . Figure 7 The cells shaded with diagonal lines in FIG. 6 show the connection intersection 60a. Figure 7 The blank cells in the figure show the non-connected intersection 60b. Figure 7 In FIG. 5 , the columns 53 are sequentially represented as columns 53a, 53b, 53c, 53d, 53e, 53f, 53g, and 53h from the left. The connection intersections 60a and the non-connection intersections 60b are arranged to satisfy the following conditions (i) to (vi).

[0063] (i) In each column 53, connected intersections 60a and non-connected intersections 60b are arranged in a repeated pattern in which parts P1 and parts P2 are alternately arranged in the y direction, wherein part P1 is a part continuous with connected intersections 60a of a first reference number A that is greater than or equal to 2, and part P2 is a part continuous with non-connected intersections 60b of a second reference number B that is greater than or equal to 2.

[0064] (ii) Between adjacent columns 53 , the phase of the repetitive pattern is shifted in the y direction.

[0065] (iii) When the Chebyshev distance is counted in units of the intersection 60 , the Chebyshev distance from each non-connected intersection 60 b to the connected intersection 60 a is 1.

[0066] (vi) When the Chebyshev distance is counted in units of the intersection portion 60 , the Chebyshev distance from each connected intersection portion 60 a to the non-connected intersection portion 60 b is 1.

[0067] In addition, Figure 7 In FIG. 1 , the first reference number A is 2 and the second reference number B is 2. In addition, Figure 7 The configuration is such that the phase of the repetitive pattern shifts downward by a certain amount as it shifts from column 53a to the right. Hereinafter, the amount of phase shift when the phase of the repetitive pattern shifts downward by a certain amount as it shifts to the right is referred to as the shift amount C. The shift amount C is counted in units (i.e., the intersection 60 units). Figure 7 , the case where the shift amount C is 2 is shown. That is, in column 53b, the phase of the repeated pattern is shifted downward by 2 units relative to column 53a, and in column 53c, the phase of the repeated pattern is shifted downward by 2 units relative to column 53b. Figure 7 In the embodiment, each non-connected intersection 60b is adjacent to the connected intersection 60a. Therefore, in all the non-connected intersections 60b, the Chebyshev distance from the non-connected intersection 60b to the connected intersection 60a is 1. Figure 7 In the embodiment, each connection intersection portion 60a is adjacent to the non-connection intersection portion 60b. Therefore, in all the connection intersection portions 60a, the Chebyshev distance from each connection intersection portion 60a to the non-connection intersection portion 60b is 1.

[0068] The switching element 10 of the first embodiment is a so-called MOSFET (metal-oxide-semiconductor field effect transistor). Normally, a higher potential than the source electrode 22 is applied to the drain electrode 24. If a potential higher than the gate threshold is applied to the gate electrode 18, an inversion layer is formed in the body region 42. In the non-connected intersection 60b, the source region 40 and the drift region 44 are connected by the inversion layer formed in the body region 42. As a result, the switching element 10 is turned on, and current flows from the drain electrode 24 to the source electrode 22. In this way, the inversion layer formed in the non-connected intersection 60b functions as a channel. On the other hand, in the connected intersection 60a, a contact region 54 and a connection region 52 are provided above and below the body region 42. Therefore, in the connected intersection 60a, almost no current flows in the inversion layer formed in the body region 42. That is, the inversion layer formed in the connected intersection 60a does not function as a channel. As described above, when a high potential is applied to the gate electrode 18 , the inversion layer formed in the non-connected intersection portion 60 b functions as a channel, whereby the switching element 10 turns on.

[0069] If the potential of the gate electrode 18 is lowered to a potential lower than the gate threshold, the inversion layer disappears and the switch element 10 is turned off. When the switch element 10 is turned off, a reverse voltage is applied to the pn junction at the interface between the body region 42 and the drift region 44, and the depletion layer expands from the body region 42 to the drift region 44. In addition, the connection region 52 is provided to stabilize the potential of the deep region 50 at the potential of the body region 42. In other words, since the deep region 50 is connected to the body region 42 by the connection region 52, the potential of the deep region 50 is substantially equal to the potential of the body region 42. Therefore, a reverse voltage is applied to the pn junction at the interface between the deep region 50 and the drift region 44, and the depletion layer expands from the deep region 50 to the drift region 44. The depletion layer extending from the deep region 50 prevents a high electric field from being applied to the gate insulating film 16 at the lower end of each trench 14.

[0070] There is a case where a higher potential than that of the drain electrode 24 is applied to the source electrode 22. In this case, the diode (so-called body diode) formed by the pn junction at the interface between the body region 42 and the drift region 44 is turned on, and current flows from the source electrode 22 to the drain electrode 24. When the body diode is turned on, holes flow from the body region 42 into the drift region 44, so there are many holes in the drift region 44. Then, when the potential of the drain electrode 24 becomes higher than that of the source electrode 22, the body diode is turned off. As a result, the holes existing in the drift region 44 are Figure 2 As shown by the arrow 100, the holes flowing from the drift region 44 into the deep region 50 flow toward the source electrode 22 via the connection region 52 and the contact region 54. The current generated when the body diode is disconnected in this way is called recovery current. Figure 2 As shown, in the connection intersection 60 a where the connection region 52 is provided, the recovery current is more likely to flow in the drift region 44 than in the non-connection intersection 60 b where the connection region 52 is not provided.

[0071] In addition, there is a case where an overvoltage is applied to the switching element 10 in a direction in which the drain electrode 24 has a higher potential than the source electrode 22. In this case, an avalanche current is generated in the drift region 44. The avalanche current is as follows: Figure 2 As shown by arrow 100, the avalanche current flows into the deep region 50 from the drift region 44. The avalanche current flowing into the deep region 50 flows to the source electrode 22 via the connection region 52 and the contact region 54. Figure 2 As shown, in the connection intersection 60 a where the connection region 52 is provided, an avalanche current is more likely to flow in the drift region 44 than in the non-connection intersection 60 b where the connection region 52 is not provided.

[0072] As described above, the recovery current and the avalanche current are more likely to flow in the drift region 44 at the connection intersection 60a than at the non-connection intersection 60b. At the non-connection intersection 60b, the longer the distance to the connection intersection 60a, the more difficult it is for the recovery current and the avalanche current to flow. If there is a non-connection intersection 60b where the recovery current and the avalanche current are less likely to flow, the recovery current and the avalanche current are more likely to be concentrated at the connection intersection 60a.

[0073] Figure 8 FIG. 4 shows the arrangement of the connection intersection portion 60a and the non-connection intersection portion 60b of the switch element of the first comparative example. Figure 8 In the configuration shown, A=2, B=6, and C=1. Figure 8 In the configuration of , the Chebyshev distance from the non-connected intersection 60b-1 to the connected intersection 60a is 2. That is, Figure 8 The configuration does not satisfy the above condition (iii). In the non-connected intersection 60b-1 where the Chebyshev distance to the connected intersection 60a is long, it is extremely difficult for the recovery current and the avalanche current to flow. Figure 8 In the configuration of the first embodiment, the recovery current and the avalanche current are easily concentrated at the connection intersection 60a. Therefore, the recovery resistance and the avalanche resistance of the switch element of the first comparative example are low. In contrast, according to the switch element 10 of the first embodiment, Figure 7 As shown, in all the non-connected intersections 60b, the Chebyshev distance to the connected intersection 60a is 1. Therefore, according to the switch element 10 of the first embodiment, it is difficult for the recovery current and the avalanche current to be concentrated in the connected intersection 60a. Therefore, the switch element 10 of the first embodiment has a high recovery tolerance and avalanche tolerance. Therefore, according to the structure of the switch element 10 of the first embodiment, higher reliability can be achieved.

[0074] Fig. 9 FIG. 4 shows the arrangement of the connection intersection portion 60a and the non-connection intersection portion 60b of the switch element of the second comparative example. Fig. 9 In the configuration shown, A=5, B=4, and C=1. Fig. 9 In the configuration of , the Chebyshev distance from the connected intersection 60a-1 to the non-connected intersection 60b is 2. That is, Fig. 9In the embodiment, the connection intersections 60a are densely packed, and the connection intersections 60a-1 exist in the center of the densely packed part. As described above, the connection region 52 (i.e., the connection intersections 60a) is provided to stabilize the potential of the deep region 50 at the potential of the body region 42. In the densely packed part of the connection intersections 60a, the deep region 50 and the body region 42 are connected by many connection intersections 60a, so the connection intersections 60a-1 existing in the center of the densely packed part hardly contribute to the stabilization of the potential of the deep region 50. If there are useless connection intersections 60a-1 in this way, the density of the channel decreases, and the on-resistance of the switching element increases. In contrast, according to the switching element 10 of the first embodiment, as Figure 7 As shown, in all the connection intersections 60a, the Chebyshev distance to the non-connection intersection 60b is 1. Therefore, according to the switch element 10 of the first embodiment, all the connection intersections 60a contribute to the stabilization of the potential of the deep region 50, and there are no useless connection intersections 60a. Therefore, the channel can be arranged at a high density. Therefore, according to the structure of the switch element 10 of the first embodiment, a lower on-resistance can be achieved.

[0075] In addition, in recent years, in order to further increase the current density (i.e., channel density) of the switching element, the interval of the groove 14 has been narrowed. That is, the width of the inter-groove semiconductor layer 30 has been narrowed. Therefore, it is difficult to form the connection region 52 and the contact region 54 for each inter-groove semiconductor layer 30. In contrast, in the first embodiment, the connection intersection 60a is continuously arranged in the y direction with a first reference number A (i.e., 2 or more), so that the connection region 52 and the contact region 54 can be formed across a plurality of inter-groove semiconductor layers 30. Therefore, the connection region 52 and the contact region 54 can be easily formed even when the width of the inter-groove semiconductor layer 30 is narrow. For example, since the ion implantation region (i.e., the region where ions are implanted to form the connection region 52 and the contact region 54) can be provided across a plurality of inter-groove semiconductor layers 30 even when the width of the inter-groove semiconductor layer 30 is narrow, the width of the ion implantation region can be ensured relatively wide. Therefore, the width of the opening of the ion implantation mask does not become extremely narrow, and the connection region 52 and the contact region 54 can be easily formed.

[0076] As described above, according to the switch element of the first embodiment, the concentration of the recovery current and the avalanche current at the connection intersection 60a can be suppressed. In addition, according to the switch element of the first embodiment, the channel density can be increased, and a lower on-resistance can be achieved. In addition, according to the structure of the switch element of the first embodiment, the connection region 52 and the contact region 54 can be easily formed even when the interval between the grooves 14 is narrow.

[0077] [Second embodiment]

[0078] Fig.10 , Fig.11 2 shows a switch element 200 according to the second embodiment. In the second embodiment, each deep region 50 extends linearly in the x direction. A plurality of deep regions 50 are arranged at intervals in the y direction. Each deep region 50 is arranged below the center of the inter-trench semiconductor layer 30 in the y direction.

[0079] Each deep region 50 is connected to the source electrode 22 via the connection region 52 and the contact region 54. Fig.11 As shown in FIG. 1 , the plurality of connection regions 52 are arranged in a plurality of rows 53 extending linearly in the y direction. The plurality of rows 53 are arranged at intervals in the x direction.

[0080] like Fig.11 As shown, the connection region 52 and the contact region 54 are arranged in a part of the plurality of intersections 60. The arrangement of the connection intersection 60a and the non-connection intersection 60b of the second embodiment (i.e., the arrangement observed in unit units) is different from that of the first embodiment (i.e., Figure 7 ) are equal. That is, the connection intersection 60a and the non-connection intersection 60b are configured in a manner that satisfies the above-mentioned conditions (i) to (iv). Therefore, in the second embodiment, it is possible to suppress the concentration of recovery current and avalanche current while ensuring a wider channel. In addition, in the second embodiment, it is also possible to easily form the connection region 52 and the contact region 54 when the interval between the grooves 14 is narrow.

[0081] [Third Embodiment]

[0082] Fig.12 , Fig.13 1 shows a switching element 300 according to a third embodiment. In the third embodiment, each deep region 50 extends linearly in the x direction. A plurality of deep regions 50 are arranged at intervals in the y direction. Each deep region 50 is arranged at the bottom of the groove 14 .

[0083] Each deep region 50 is connected to the source electrode 22 via the connection region 52 and the contact region 54. Fig.13 As shown in FIG. 1 , the plurality of connection regions 52 are arranged in a plurality of rows 53 extending linearly in the y direction. The plurality of rows 53 are arranged at intervals in the x direction.

[0084] like Fig.13 As shown, the connection region 52 and the contact region 54 are arranged in a part of the plurality of intersections 60. The arrangement of the connection intersection 60a and the non-connection intersection 60b of the third embodiment (i.e., the arrangement observed in unit units) is different from that of the first embodiment (i.e., Figure 7) are equal. That is, the connection intersection 60a and the non-connection intersection 60b are configured in a manner that satisfies the above-mentioned conditions (i) to (iv). Therefore, in the third embodiment, it is also possible to suppress the concentration of recovery current and avalanche current while ensuring a wider channel. In addition, in the third embodiment, it is also possible to easily form the connection region 52 and the contact region 54 when the interval between the grooves 14 is narrow.

[0085] [Fourth embodiment]

[0086] Fig.14 , Fig.15 4. The switch element 400 of the fourth embodiment is shown. The switch element 400 of the fourth embodiment has two deep regions 50x and 50y. Each deep region 50y extends in a straight line in the y direction. A plurality of deep regions 50y are arranged at intervals in the x direction. Each deep region 50y is arranged at a depth including the lower end of the groove 14. Each deep region 50x is arranged on the lower side than each deep region 50y. Each deep region 50x extends in a straight line in the x direction. A plurality of deep regions 50x are arranged at intervals in the y direction. The upper end of each deep region 50x is arranged at a depth that overlaps with the lower end of each deep region 50y. Each deep region 50x and each deep region 50y are connected to each other at the portion where they intersect.

[0087] Each deep region 50y is connected to the source electrode 22 via the connection region 52 and the contact region 54. Fig.15 As shown in FIG. 1 , the plurality of connection regions 52 are arranged in a plurality of rows 53 extending linearly in the y direction. Fig.15 In the embodiment, the row 53 extending in the y direction overlaps with the deep region 50y. The plurality of rows 53 are arranged at intervals in the x direction.

[0088] like Fig.15 As shown, the connection region 52 and the contact region 54 are arranged in a part of the plurality of intersections 60. The arrangement of the connection intersection 60a and the non-connection intersection 60b of the fourth embodiment (i.e., the arrangement observed in unit units) is different from that of the first embodiment (i.e., Figure 7 ) are equal. That is, the connection intersection 60a and the non-connection intersection 60b are configured in a manner that satisfies the above-mentioned conditions (i) to (iv). Therefore, in the fourth embodiment, it is also possible to suppress the concentration of recovery current and avalanche current while ensuring a wider channel. In addition, in the fourth embodiment, it is also possible to easily form the connection region 52 and the contact region 54 when the interval between the grooves 14 is narrowed.

[0089] In the fourth embodiment, the deep regions 50x and 50y extend in the x direction and the y direction. Therefore, the deep regions 50x and 50y in each non-connected intersection 60b are connected to the connection region 52 via a shorter current path. Therefore, the potential of the deep regions 50x and 50y can be further stabilized.

[0090] In the fourth embodiment described above, the deep region 50y is disposed above the deep region 50x. However, the deep region 50x may be disposed above the deep region 50y. Furthermore, the deep region 50x and the deep region 50y may be disposed at the same depth.

[0091] In the first to fourth embodiments described above, each deep region 50 is disposed at a depth including the lower end of the groove 14. However, each deep region 50 may be disposed below the lower end of the groove 14. For example, in the first embodiment, Fig.16 As shown, each deep region 50 is arranged below the lower end of the groove 14 .

[0092] In the first to fourth embodiments described above, the contact region 54 is provided above the connection region 52. However, the connection region 52 and the contact region 54 may be positioned offset in the x direction. In addition, the number of the connection regions 52 and the number of the contact regions 54 may be different.

[0093] In addition, in the above-mentioned first to fourth embodiments, if Figure 7 The connection intersection portion 60a and the non-connection intersection portion 60b are arranged as shown. However, the connection intersection portion 60a and the non-connection intersection portion 60b may be arranged in any manner as long as the above-mentioned conditions (i) to (iv) are satisfied. Fig.17 An example of arrangement that satisfies conditions (i) to (iv) when the first reference number A and the second reference number B are equal is shown. Fig.18 An example of a configuration that satisfies conditions (i) to (iv) is shown when the first reference number A is smaller than the second reference number B. Fig.17 , Fig.18 In FIG. 6 , the horizontal direction is the X direction, the vertical direction is the Y direction, the cells shaded with diagonal lines are the connected intersections 60a, and the blank cells are the non-connected intersections 60b. Fig.19 An example of arrangement that satisfies conditions (i) to (iv) is shown when the first reference number A is larger than the second reference number B.

[0094] In addition, in Fig.17 , Fig.18When the second reference number B is equal to or larger than the first reference number A as exemplified, the non-connected intersection portion 60 b (ie, the channel) can be ensured to be wide, and the on-resistance of the switching element can be effectively reduced.

[0095] In addition, in Fig.17 , Fig.18 (Except Fig.17 When the number of consecutive connection intersections 60a in the x direction is 3 or less as exemplified in the example of A=4, B=4, C=1, the density of the connection intersections 60a can be more effectively suppressed. Therefore, each connection intersection 60a contributes to the stabilization of the potential of the deep region 50, and the number of useless connection intersections 60a can be reduced. Therefore, the non-connection intersection 60b (i.e., the channel) can be ensured to be wider, and the on-resistance of the switch element can be effectively reduced.

[0096] In addition, Fig.17 , Fig.18 In the configurations where (A, B, C) are (2, 2, 2), (3, 3, 3), (4, 4, 4), (2, 4, 2), (3, 6, 3), (3, 6, 4), (4, 8, 4), and (4, 8, 5), there is no portion where the connection intersection portion 60a is continuous in the x direction. According to the configurations where there is no portion where the connection intersection portion 60a is continuous in the x direction as exemplified in these examples, the connection intersection portion 60a can be arranged more dispersedly, and the concentration of current on the connection intersection portion 60a can be more effectively suppressed.

[0097] In addition, Fig.17 , Fig.18 , Fig.19 In the configuration, as the column shifts to the right, the phase of the repeated pattern shifts downward by a certain amount (i.e., the shift amount C), but the shift amount of the phase of the repeated pattern may not be constant. Fig. 20 As shown, the amount of phase shift can also vary depending on the position. Fig. 20 , the first reference number A is 2, and the second reference number B is 6 (i.e., 3A). In addition, the offset amount of column 53b relative to column 53a is 2, the offset amount of column 53c relative to column 53b is 4, and the offset amount of column 53d relative to column 53c is -2. In other words, the offset amount of column 53b relative to column 53a is 2 (i.e., A), the offset amount of column 53c relative to column 53a is 6 (i.e., 3A), and the offset amount of column 53d relative to column 53a is 4 (i.e., 2A). Fig. 20 In the embodiment, the phase shift amount changes in a cycle of 4 columns. By changing the phase shift amount in this way, the connected intersection 60a and the non-connected intersection 60b can be more evenly distributed. Fig. 20In different cases, the second reference number B and each shift amount can be set at the above-mentioned ratio.

[0098] The x direction in the above-mentioned embodiment is an example of the first direction. The y direction in the above-mentioned embodiment is an example of the second direction.

[0099] The above detailed description of the implementation methods is provided, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various forms of deformation and modification of the specific examples illustrated above. The technical elements described in this specification or the drawings exert technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of application. In addition, the technology illustrated in this specification or the drawings achieves multiple purposes at the same time, and achieving one of the purposes itself has technical usefulness.

Claims

1. A switching element, characterized in that: have: A semiconductor substrate, wherein a plurality of grooves are provided on an upper surface of the semiconductor substrate, each of the grooves extending linearly in a first direction on the upper surface of the semiconductor substrate, and each of the grooves is arranged at intervals in a second direction intersecting the first direction on the upper surface of the semiconductor substrate; A gate insulating film covers the inner surface of each of the trenches; A gate electrode is disposed in each of the trenches and is insulated from the semiconductor substrate by the gate insulating film; as well as A source electrode connected to the upper surface of the semiconductor substrate; The semiconductor substrate has a plurality of inter-trench semiconductor layers sandwiched by the plurality of trenches; The semiconductor layer between each trench has: An n-type source region in contact with the gate insulating film and the source electrode; and A p-type body region in contact with the gate insulating film at a lower side of the source region; The semiconductor substrate has: An n-type drift region is distributed across the lower portions of the plurality of inter-trench semiconductor layers and is in contact with the gate insulating film at the lower side of the body region in each inter-trench semiconductor layer; A plurality of p-type deep regions are arranged in a range surrounded by the drift region, are arranged at intervals from the body region and are arranged below the body region, and are arranged in a range including a lower end of the trench or below the lower end of the trench in a thickness direction of the semiconductor substrate; as well as A plurality of p-type connection regions connecting the body region and the deep region; When the semiconductor substrate is viewed from above, the connection region forms a plurality of rows that are spaced apart and arranged linearly along the second direction, and the plurality of rows are spaced apart and arranged in the first direction; When the semiconductor substrate is observed from above, the intersections of the plurality of trench semiconductor layers and the plurality of columns include connection intersections provided with the connection regions and non-connection intersections without the connection regions. The above-mentioned connection intersection portion and the above-mentioned non-connection intersection portion satisfy the following conditions (i) to (iv), namely: (i) in each of the columns, the connected intersections and the non-connected intersections are arranged in a pattern in which a portion of the connected intersections having a first reference number of two or more and a portion of the non-connected intersections having a second reference number of two or more are arranged alternately in the second direction; (ii) between adjacent columns, the phase of the pattern is shifted in the second direction; (iii) when the Chebyshev distance is counted in units of the above-mentioned intersections, in each non-connected intersection, the Chebyshev distance to the above-mentioned connected intersection is 1; (iv) When the Chebyshev distance is counted in units of the intersections, in each connected intersection, the Chebyshev distance to the non-connected intersection is 1.

2. The switching element according to claim 1, wherein: The second reference number is greater than or equal to the first reference number.

3. The switching element according to claim 1 or 2, characterized in that: In each of the inter-trench semiconductor layers, the connection intersection portion is discontinuous in the first direction when viewed in units of the intersection portion.

4. The switching element according to claim 1 or 2, characterized in that: In each of the inter-trench semiconductor layers, when viewed in units of the intersections, the number of consecutive connection intersections in the first direction is 3 or less.

5. The switching element according to claim 1 or 2, characterized in that: When the first reference number is represented by an arbitrary integer A, the second reference number is 3A; In the plurality of the columns, the phase of the pattern changes periodically every four of the columns; When the four columns are sequentially designated as the first column, the second column, the third column, and the fourth column and the amount of phase shift of the pattern is counted in units of the intersections, The offset amount of the second column relative to the first column is A; The offset amount of the third column relative to the first column is 3A; The offset amount of the fourth row relative to the first row is 2A.

6. The switching element according to claim 1 or 2, characterized in that: When the semiconductor substrate is viewed from above, the plurality of deep regions extend linearly along the second direction and are arranged at intervals in the first direction so that each of the deep regions extends along the corresponding column.

7. The switching element according to claim 1 or 2, characterized in that: A p-type contact region for connecting the body region and the source electrode is provided on the upper portion of each of the connection regions.

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