Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, the structure comprises a substrate, the substrate comprises a first semiconductor layer, an insulating layer located on the surface of the first semiconductor layer and a second semiconductor layer located on the insulating layer, and the substrate comprises a first region and a second region which are arranged along a first direction parallel to the surface of the substrate and are adjacent to each other; the source-drain through holes are located in the first region on the two sides of the channel region, and the source-drain through holes are exposed out of the surface of the insulating layer; the source-drain structure is positioned in the source-drain through hole; the gate through hole is positioned in the second region, is adjacent to the channel region and is exposed out of the surface of the insulating layer; and the gate structure is positioned in the gate through hole. The size of the source-drain through hole is equal to that of the gate through hole in the direction perpendicular to the surface of the substrate, so that the gate structure and the source-drain structure are located on the same layer, the longitudinal size of the device is reduced, the uniformity and stability of the manufacturing process are improved, and the performance stability of the device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] Fully depleted silicon-on-insulator (FD-SOI) devices are a process technology that continues to be based on a planar transistor structure. Specifically, an ultra-thin buried oxide (box) layer is introduced into the bulk silicon as an insulating layer, and an ultra-thin top silicon layer is used to manufacture a fully depleted transistor channel. The biggest feature of FDSOI is that it can achieve chip area miniaturization, energy saving, performance improvement and function expansion under Moore's Law without completely transforming the device structure and production process.

[0003] However, the gate, source and drain of the existing FD-SOI device are not in the same plane, which increases the longitudinal size of the FD-SOI device and affects the uniformity and stability of the manufacturing process. In addition, the back bias control end of the existing FD-SOI device is led out from the top of the wafer, so it is necessary to remove part of the single crystal silicon (SOI) layer and prepare the bias connection and pure planar process devices in the area where the single crystal silicon layer is removed. Since an additional protection process is required when removing the single crystal silicon layer in the process, the existing FD-SOI preparation process is both complex and costly. Summary of the invention

[0004] The technical problem solved by the invention is to reduce the volume of the device and improve the uniformity and stability of the manufacturing process.

[0005] To solve the above technical problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate, the substrate including: a first semiconductor layer, an insulating layer located on the surface of the first semiconductor layer, and a second semiconductor layer located on the insulating layer, the substrate including: adjacent first and second regions arranged along a first direction parallel to the substrate surface, the first region having a channel region; source-drain through holes located in the first region on both sides of the channel region, the source-drain through holes exposing the surface of the insulating layer, the source-drain through holes and the channel region arranged along a second direction, the second direction being parallel to the substrate surface and perpendicular to the first direction; a source-drain structure located in the source-drain through hole; a gate through hole located in the second region, the gate through hole being adjacent to the channel region, and the gate through hole exposing the surface of the insulating layer; a gate structure located in the gate through hole.

[0006] Optionally, the substrate includes a plurality of first regions that are separated from each other, the plurality of first regions are arranged along a first direction, and the second region is located between adjacent first regions.

[0007] Optionally, the first region includes a plurality of channel regions, the plurality of channel regions are arranged along a first direction, and a source-drain through hole is provided between adjacent channel regions.

[0008] Optionally, the source-drain structure includes: a source-drain diffusion layer located in the source-drain through hole and a source-drain doping layer located on the surface of the source-drain diffusion layer.

[0009] Optionally, the gate structure includes: a gate oxide layer located on the surface of the gate through hole, a gate dielectric layer located on the surface of the gate oxide layer, and a gate material layer located on the surface of the gate dielectric layer.

[0010] Optionally, the substrate further includes a bias well region located in the second semiconductor layer.

[0011] Optionally, the semiconductor structure further includes: an isolation structure located in the second region on both sides of the gate structure and between the bias well region and the first region.

[0012] Optionally, the semiconductor structure further includes: an interlayer dielectric layer located on the surface of the first region, the surface of the second region, the surface of the bias well region, the surface of the isolation structure and the surface of the second semiconductor layer.

[0013] Optionally, the semiconductor structure also includes: a connection structure located in the interlayer dielectric layer on the surface of the gate structure, the surface of the source and drain structure, and the surface of the bias well region, and the connection structure is electrically connected to one or more of the gate structure, the source and drain structure, and the bias well region.

[0014] Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, including: providing a substrate, the substrate including: a first semiconductor layer, an insulating layer located on the surface of the first semiconductor layer, and a second semiconductor layer located on the insulating layer, the substrate also including: adjacent first regions and second regions arranged along a first direction parallel to the surface of the substrate, the first region having a channel region; forming a source-drain structure in the first region; and forming a gate structure in the second region.

[0015] Optionally, the substrate includes a plurality of first regions that are separated from each other, the plurality of first regions are arranged along a first direction, and the second region is located between adjacent first regions.

[0016] Optionally, the first region includes a plurality of channel regions, the plurality of channel regions are arranged along a first direction, and a source-drain through hole is provided between adjacent channel regions.

[0017] Optionally, the method for forming the source-drain structure includes: etching the second semiconductor layer in the first region on both sides of the channel region until the surface of the insulating layer is exposed to form source-drain through holes; performing a thermal diffusion process on the source-drain through holes to form an initial source-drain diffusion layer; forming an initial source-drain doped layer on the surface of the initial source-drain diffusion layer; and planarizing the initial source-drain diffusion layer and the initial source-drain doped layer to form a source-drain diffusion layer and a source-drain doped layer.

[0018] Optionally, the method for forming the gate structure includes: etching the second semiconductor layer in the second region on both sides of the channel region until the surface of the insulating layer is exposed to form a gate through hole; depositing an initial gate oxide layer on the surface of the gate through hole; depositing an initial gate dielectric layer on the surface of the initial gate oxide layer; depositing an initial gate material layer on the surface of the initial gate dielectric layer; and planarizing the initial gate oxide layer, the initial gate dielectric layer and the initial gate material layer until the surface of the second semiconductor layer is exposed to form a gate oxide layer, a gate dielectric layer and a gate material layer.

[0019] Optionally, before forming the gate structure and the source-drain structure, an initial second semiconductor layer is formed on the surface of the insulating layer; and ion implantation is performed on the initial second semiconductor layer to form the second semiconductor layer.

[0020] Optionally, the substrate further includes a bias well region located in the second semiconductor layer, and an isolation structure is provided between the bias well region and the first region.

[0021] Optionally, the channel region and the bias well region are formed simultaneously.

[0022] Optionally, the method for forming the semiconductor structure also includes: the method for forming the isolation structure includes: after forming the gate structure, etching the second semiconductor layer in the second region on both sides of the gate structure, the second semiconductor layer in the first region on both sides of the source and drain structure, and the second semiconductor layer on both sides of the bias well region until the insulating layer is exposed to form a shallow trench; depositing an initial isolation structure in the shallow trench; and flattening the initial isolation structure until the surface of the second semiconductor layer is exposed to form an isolation structure.

[0023] Optionally, the method for forming the semiconductor structure also includes: forming an initial interlayer dielectric layer on the surface of the first region, the surface of the second region, the surface of the bias well region, the surface of the isolation structure, and the surface of the second semiconductor layer; etching the initial interlayer dielectric layer on the surface of the gate structure, the surface of the source and drain structure, and the surface of the bias well region to form a plurality of first openings and an interlayer dielectric layer; and forming a connection structure in the first opening, wherein the connection structure is electrically connected to one or more of the gate structure, the source and drain structure, and the bias well region.

[0024] Optionally, the ions doped in the second semiconductor layer include P-type or N-type ions.

[0025] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0026] In the semiconductor structure provided by the technical solution of the present invention, the source-drain structure is located in the source-drain through hole, the gate structure is located in the gate through hole, and the bottoms of the source-drain through hole and the gate through hole both expose the surface of the insulating layer. Therefore, the source-drain through hole and the gate through hole have the same size in a direction perpendicular to the substrate surface, so that the gate structure and the source-drain structure are located in the same layer, which reduces the longitudinal size of the device, improves the uniformity and stability of the manufacturing process, and thereby improves the stability of device performance.

[0027] Furthermore, the technical solution of the present invention includes several first regions, and several source-drain structures located on both sides of the channel region in the several first regions. Two source-drain structures located in the same region form a MOS device with a gate structure, so that the source-drain structures in adjacent regions share a gate structure, further reducing the area of ​​the device, reducing the preparation cost and the power consumption of the device.

[0028] Furthermore, the tops of the bias well region, source-drain structure and gate structure in the technical solution of the present invention are flush in a direction parallel to the substrate surface, avoiding height differences between devices when different functional devices are connected, thereby improving the consistency of the lithography process.

[0029] In the method for forming a semiconductor structure provided by the technical solution of the present invention, the source-drain structure and the gate structure are formed in the substrate, so that the size of the gate structure and the source-drain structure in the direction perpendicular to the surface of the substrate is reduced, thereby reducing the longitudinal size of the device, improving the uniformity and stability of the manufacturing process, and thereby improving the performance stability of the device.

[0030] Furthermore, in the technical solution of the present invention, several first regions are formed on the substrate, and several source-drain structures are formed on both sides of the channel region in the several first regions. Two source-drain structures located in the same region form a MOS device with a gate structure, so that the source-drain structures in adjacent regions share a gate structure, further reducing the area of ​​the device, reducing the preparation cost and the power consumption of the device.

[0031] Furthermore, in the technical solution of the present invention, a bias well region, a source-drain structure, and a gate structure are formed in the second semiconductor layer, so that the tops of the bias well region, the source-drain structure, and the gate structure are flush in a direction parallel to the substrate surface, thereby avoiding height differences within the device or between devices with different functions and improving the consistency of the lithography process. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1It is a schematic diagram of the structure of a semiconductor structure;

[0033] Figure 2 It is a schematic diagram of the structure of another semiconductor structure;

[0034] Figures 3 to 22 is a structural schematic diagram of a formation process of a semiconductor structure in an embodiment of the present invention;

[0035] Fig.23 FIG. 4 is a schematic diagram of a circuit structure of a semiconductor structure in an embodiment of the present invention. DETAILED DESCRIPTION

[0036] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to direct contact.

[0037] As described in the background art, it is necessary to reduce the size of the device and improve the uniformity and stability of the manufacturing process. Now, an analysis and description will be given in conjunction with a specific embodiment.

[0038] Figure 1 It is a structural diagram of a semiconductor structure.

[0039] Please refer to Figure 1 The semiconductor structure includes: a first substrate, the first substrate includes: a first semiconductor layer 100, an insulating layer 104 located on the surface of the first semiconductor layer 100, and a second semiconductor layer 103 located on the insulating layer 104, the first substrate includes: adjacent first regions I and second regions II arranged along a first direction X parallel to the surface of the first substrate; a first source-drain structure 101 located in the first region I; and a first gate structure 102 located in the second region II.

[0040] In this embodiment, the first substrate further includes a bias well region III located in the second semiconductor layer 103 , the bias well region III includes a bias connection structure 105 ; and an isolation structure 106 is provided between the bias well region III and the first region I.

[0041] In this embodiment, the method for forming the bias connection structure 105 includes: forming an initial insulating layer (not shown in the figure) and an initial second semiconductor layer (not shown in the figure) on a first substrate, etching the initial insulating layer (not shown in the figure) and the initial second semiconductor layer (not shown in the figure) in the bias well region III until the surface of the first substrate is exposed to form a bias opening, an insulating layer 104 and a second semiconductor layer 103; forming a bias connection structure 105 in the bias opening, and the bias connection structure 105 is electrically connected to the first semiconductor layer 100.

[0042] This embodiment is a connection structure of two devices with the same function.

[0043] In the above scheme, on the one hand, since the first gate structure 102 is higher than the first source-drain structure 101 in the direction perpendicular to the substrate surface, an undulating structure is formed between the first gate structure 102 and the first source-drain structure 101, which increases the longitudinal size of the device, and the height of the first gate structure 102 and the height of the first source-drain structure 101 need to be taken into account during the photolithography process, which increases the difficulty of the manufacturing process. On the other hand, since the insulating layer 104 and the second semiconductor layer 103 need to be etched to form a bias opening, and a bias connection structure 105 is formed in the bias opening, a height difference exists between the bias well region III and the first region I and the second region II, which further increases the difficulty of the manufacturing process, and the removal of the insulating layer 104 requires an additional protection process, which increases the cost of the manufacturing process.

[0044] Figure 2 It is a structural diagram of another semiconductor structure.

[0045] exist Figure 1 Based on Figure 2 The semiconductor also includes: a second substrate 200, the second substrate 200 includes a plurality of mutually discrete fourth regions IV arranged along the first direction X, and a fifth region V located between adjacent fourth regions IV; a second source-drain structure 201 located in the fourth region IV; a second gate structure 202 located in the fifth region V, and an isolation structure 106 located between the bias well region III and the fifth region V.

[0046] In this embodiment, when the semiconductor structure includes an insulating layer 104, the semiconductor structure is a core device; when the semiconductor structure does not include an insulating layer 104, the semiconductor structure is an I / O device; the core device and the I / O device have different functions.

[0047] In the above scheme, since the insulating layer 104 and the second semiconductor layer 103 in the core device need to be etched to form a bias opening and a bias connection structure 105 is formed in the bias opening, a height difference exists between the core device and the I / O device, which further increases the difficulty of the manufacturing process. In addition, removing the insulating layer 104 requires an additional protection process, which increases the cost of the process.

[0048] In addition, the above two schemes are connection structures of two devices with the same function or two devices with different functions, including two gate structures and four source-drain structures, that is, each gate structure and two source-drain structures form a MOS device. The increase in the number of gate structures increases the area of ​​the device, and the above-mentioned semiconductor structure has a small current generation capacity and cannot cope with the generation of large current, which increases the power consumption of the device and thus affects the device performance.

[0049] In order to solve the problems of increased device volume and increased difficulty of the manufacturing process in the above-mentioned semiconductor structure formation method, the present invention provides a semiconductor structure and a method for forming the same, wherein the source-drain structure and the gate structure are located in the same layer, thereby reducing the longitudinal size of the device, improving the uniformity and stability of the manufacturing process, and thereby improving the stability of device performance.

[0050] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0051] Figures 3 to 22 It is a structural schematic diagram of the formation process of the semiconductor structure in an embodiment of the present invention.

[0052] Please refer to Figure 3 as well as Figure 4 , Figure 4 This is a top view of the structure. Figure 3 yes Figure 4 In the cross-sectional schematic diagram along line AA1, a substrate 303 is provided, wherein the substrate 303 comprises: a first semiconductor layer 300, an insulating layer 301 located on the surface of the first semiconductor layer 300, and a second semiconductor layer 302 located on the insulating layer 301, and the substrate 303 further comprises: adjacent first regions I and second regions II arranged along a first direction X parallel to the surface of the substrate 303.

[0053] In this embodiment, the material of the substrate 303 includes silicon, and the doping type of the substrate 303 includes P-type doping or N-type doping.

[0054] In other embodiments, the material of the substrate 303 includes silicon carbide, silicon germanium, and a multi-component semiconductor material composed of group III-V elements. The multi-component semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0055] In this embodiment, the second semiconductor layer 302 is used to provide a receiving space for a source-drain structure and a gate structure to be formed subsequently.

[0056] In this embodiment, the substrate 303 includes a plurality of first regions I that are separated from each other. The plurality of first regions I are arranged along a first direction X, and the second region II is located between adjacent first regions I.

[0057] In this embodiment, the method for forming the second semiconductor layer 302 includes: forming an initial second semiconductor layer (not shown in the figure) on the surface of the insulating layer 301; performing ion implantation treatment on the initial second semiconductor layer (not shown in the figure) to form the second semiconductor layer 302.

[0058] In this embodiment, the ions doped into the second semiconductor layer 302 include P-type or N-type ions.

[0059] Please refer to Figure 5 , Figure 6 as well as Figure 7 , Figure 7 This is a top view of the structure. Figure 5 yes Figure 7 Schematic diagram of the cross section along line BB1, Figure 6 yes Figure 7 In the cross-sectional diagram along line AA1, the second semiconductor layer 302 in the first region I on both sides of the channel region 305 is etched until the surface of the insulating layer 301 is exposed to form source-drain through holes 304.

[0060] In this embodiment, the source-drain through holes 304 are used to accommodate the source-drain structures formed subsequently.

[0061] In this embodiment, the process of etching the source-drain through hole 304 includes wet etching or dry etching. Wet etching is a technique of etching by immersing the etching material in an etching solution. It is a pure chemical etching with excellent selectivity. Wet etching is isotropic. Dry etching includes isotropic radial etching, reactive ion etching, sputtering etching, ion milling, ion beam assisted etching, reactive ion beam etching, etc. Dry etching is anisotropic.

[0062] In this embodiment, the depth of the source-drain through hole 304 is the same as the thickness of the second semiconductor layer 302 .

[0063] In this embodiment, a channel region 305 is defined in the first region I, and the channel region 305 is located between adjacent source-drain through holes 304 .

[0064] In other embodiments not shown in the figure, the first region includes a plurality of channel regions, the plurality of channel regions are arranged along a first direction, and a source-drain through hole is provided between adjacent channel regions.

[0065] In this embodiment, the substrate further includes a bias well region 314 located in the second semiconductor layer 302 .

[0066] In this embodiment, the channel region 305 and the bias well region 314 are formed simultaneously.

[0067] In this embodiment, the method for forming the channel region 305 and the bias well region 314 includes: performing ion implantation on a portion of the second semiconductor layer 302 to form the channel region 305 and the bias well region 314 .

[0068] In this embodiment, the ions in the ion implantation process include P-type or N-type ions.

[0069] Please refer to Figure 8 as well as Fig. 9 , Fig. 9 This is a top view of the structure. Figure 8 yes Fig. 9 In the cross-sectional schematic diagram along line BB1, the source-drain through hole 304 is subjected to a thermal diffusion process to form an initial source-drain diffusion layer (not shown in the figure); an initial source-drain doping layer (not shown in the figure) is formed on the surface of the initial source-drain diffusion layer (not shown in the figure); the initial source-drain diffusion layer (not shown in the figure) and the initial source-drain doping layer (not shown in the figure) are planarized to form a source-drain diffusion layer 306 and a source-drain doping layer 307.

[0070] In this embodiment, the method for forming the initial source and drain doping layer (not shown in the figure) includes: one or more of chemical vapor deposition, physical deposition, atomic layer deposition, and jet vapor deposition, the deposition gas includes: hydrogen and monosilane, and the reaction temperature ranges from 400 degrees Celsius to 800 degrees Celsius.

[0071] In this embodiment, the planarization treatment method includes: mechanical polishing, chemical polishing, fluid polishing, and chemical mechanical polishing. Specifically, in this embodiment, the planarization treatment method is chemical mechanical polishing. Different from the traditional pure mechanical or pure chemical polishing method, the chemical mechanical polishing method avoids the surface damage caused by pure mechanical polishing and the shortcomings of slow polishing speed, poor surface flatness and polishing consistency caused by pure chemical polishing through the combined action of chemistry and mechanics. Chemical mechanical polishing is widely used for high planarization polishing of various materials at the nano level.

[0072] In this embodiment, the material of the source / drain doping layer 307 includes polysilicon doped with N-type ions or P-type ions.

[0073] Please refer to Fig.10 as well as Fig.11 , Fig.11 This is a top view of the structure. Fig.10 yes Fig.11In the cross-sectional view along line AA1, the second semiconductor layer 302 in the second region II on both sides of the channel region 305 is etched until the surface of the insulating layer 301 is exposed, thereby forming a gate through hole 308.

[0074] In this embodiment, the gate through hole 308 is used to accommodate a gate structure to be formed subsequently.

[0075] In this embodiment, the process of etching the gate through hole 308 includes wet etching or dry etching. Wet etching is a technique of etching by immersing the etching material in an etching solution. It is a pure chemical etching with excellent selectivity. Wet etching is isotropic. Dry etching includes isotropic radial etching, reactive ion etching, sputtering etching, ion milling, ion beam assisted etching, reactive ion beam etching, etc. Dry etching is anisotropic.

[0076] In this embodiment, the depth of the gate through hole 308 is the same as the thickness of the second semiconductor layer 302 .

[0077] In the above scheme, the source-drain through hole 304 and the gate through hole 308 are equal in size in the direction perpendicular to the surface of the substrate 303, so that the gate structure and the source-drain structure are located in the same layer, reducing the longitudinal size of the device, improving the uniformity and stability of the manufacturing process, and thus improving the stability of device performance.

[0078] Please refer to Fig.12 as well as Fig.13 , Fig.13 This is a top view of the structure. Fig.12 yes Fig.13 In the cross-sectional schematic diagram along line AA1, an initial gate oxide layer (not shown in the figure) is deposited on the surface of the gate through hole 308; an initial gate dielectric layer (not shown in the figure) is deposited on the surface of the initial gate oxide layer (not shown in the figure); an initial gate material layer (not shown in the figure) is deposited on the surface of the initial gate dielectric layer (not shown in the figure); the initial gate oxide layer (not shown in the figure), the initial gate dielectric layer (not shown in the figure) and the initial gate material layer (not shown in the figure) are planarized until the surface of the second semiconductor layer 302 is exposed, thereby forming a gate oxide layer 309, a gate dielectric layer 310 and a gate material layer 311.

[0079] In this embodiment, the method for forming the initial gate dielectric layer (not shown in the figure), the initial gate material layer (not shown in the figure) and the initial gate oxide layer (not shown in the figure) includes: one or more of chemical vapor deposition, physical deposition, atomic layer deposition, and jet vapor deposition, the deposition gas includes: hydrogen and monosilane, and the reaction temperature ranges from 400 degrees Celsius to 800 degrees Celsius.

[0080] In this embodiment, the planarization processing method includes: mechanical polishing method, chemical polishing method, fluid polishing method, chemical mechanical polishing method, etc.

[0081] In this embodiment, the material of the gate dielectric layer 310 includes a high-K dielectric.

[0082] In this embodiment, the material of the gate oxide layer 309 includes silicon oxide.

[0083] In this embodiment, the material of the gate material layer 311 includes: polysilicon doped with N-type ions or P-type ions.

[0084] In the above scheme, the substrate 303 includes two first regions I and one second region II. The gate structure in the second region II and the source-drain structure in the first region I respectively constitute a MOS tube, that is, the two source-drain structures share a gate structure to form two MOS tubes, which reduces the area of ​​the device, improves the integration of the device, and thus improves the device performance and reduces the power consumption of the device.

[0085] Please refer to Fig.14 , Fig.15 as well as Fig.16 , Fig.16 This is a top view of the structure. Fig.14 yes Fig.16 Schematic diagram of the cross section along line BB1, Fig.15 yes Fig.16 In the cross-sectional schematic diagram along line AA1, after the gate structure is formed, the second semiconductor layer 302 in the second region II on both sides of the gate structure, the second semiconductor layer 302 in the first region I on both sides of the source-drain structure, and the second semiconductor layer 302 on both sides of the bias well region 314 are etched until the insulating layer 301 is exposed to form a shallow trench 312.

[0086] In this embodiment, the method for forming the shallow groove 312 includes wet etching or dry etching. Wet etching is a technique of etching by immersing the etching material in an etching solution. It is a pure chemical etching with excellent selectivity. Wet etching is isotropic. Dry etching includes isotropic radial etching, reactive ion etching, sputtering etching, ion milling, ion beam assisted etching, reactive ion beam etching, etc. Dry etching is anisotropic.

[0087] In this embodiment, the shallow trench 312 is used to accommodate an isolation structure 313 that is formed subsequently.

[0088] In this embodiment, the depth of the shallow trench 312 is the same as the thickness of the second semiconductor layer 302 .

[0089] Please refer to Fig.17 , Fig.18 as well as Fig.19 , Fig.19 This is a top view of the structure. Fig.17 yes Fig.19 Schematic diagram of the cross section along line BB1, Fig.18 yes Fig.19 In the cross-sectional diagram along line AA1, an initial isolation structure (not shown) is deposited in the shallow trench 312; the initial isolation structure (not shown) is planarized until the surface of the second semiconductor layer 302 is exposed to form an isolation structure 313.

[0090] In this embodiment, the isolation structure 313 is used to avoid electrical crosstalk between adjacent gate structures.

[0091] In this embodiment, the method for forming the isolation structure 313 includes one or more of chemical vapor deposition, physical deposition, atomic layer deposition, and jet vapor deposition. The reaction gas includes hydrogen and monosilane. The reaction temperature ranges from 400 degrees Celsius to 800 degrees Celsius.

[0092] In this embodiment, the planarization processing method includes: mechanical polishing method, chemical polishing method, fluid polishing method, chemical mechanical polishing method, etc.

[0093] In this embodiment, the material of the isolation structure 313 includes silicon oxide.

[0094] In the above scheme, through flattening treatment, the bias well region 314, the source-drain structure and the top of the gate structure are flush in a direction parallel to the surface of the substrate 303, avoiding height differences between devices when different functional devices are connected, thereby improving the consistency of the lithography process.

[0095] Please refer to Fig. 20 , Fig.21 as well as Fig. 22 , Fig. 22 This is a top view of the structure. Fig.21 yes Fig. 22 Schematic diagram of the cross section along line AA1, Fig.21 yes Fig. 22 In the cross-sectional view along line BB1 ​​, a connection structure 315 is formed on the surface of the gate structure, the surface of the source-drain structure, and the surface of the bias well region 314 .

[0096] In this embodiment, the method for forming the connection structure 315 includes: forming an initial interlayer dielectric layer (not shown in the figure) on the surface of the first region I, the surface of the second region II, the surface of the bias well region 314, the surface of the isolation structure 313, and the surface of the second semiconductor layer 302; etching the initial interlayer dielectric layer (not shown in the figure) on the surface of the gate structure, the surface of the source and drain structure, and the surface of the bias well region 314 to form a plurality of first openings (not shown in the figure) and an interlayer dielectric layer (not shown in the figure); and forming a connection structure 315 in the first opening (not shown in the figure).

[0097] In this embodiment, the connection structure 315 is used to electrically connect to one or more of the gate structure, the source-drain structure, and the bias well region 314 .

[0098] In this embodiment, the material of the connection structure 315 includes a metal conductive material. Specifically, the connection structure 315 is aluminum.

[0099] In this embodiment, the depth of the first opening (not shown in the figure) ranges from 0 μm to 10 μm.

[0100] In this embodiment, the material of the interlayer dielectric layer (not shown in the figure) includes silicon dioxide.

[0101] Please continue to refer to Fig. 20 , Fig.21 as well as Fig. 22 The technical solution of the present invention also provides a semiconductor structure, including: a substrate 303, the substrate 303 includes: a first semiconductor layer 300, an insulating layer 301 located on the surface of the first semiconductor layer 300, and a second semiconductor layer 302 located on the insulating layer 301, the substrate 303 includes: adjacent first regions I and second regions II arranged along a first direction X parallel to the surface of the substrate 303, the first region I having a channel region 305; source-drain through holes in the first region I on both sides of the channel region 305 304, the source-drain through hole 304 exposes the surface of the insulating layer 301, the source-drain through hole 304 and the channel region 305 are arranged along a second direction Y, the second direction Y is parallel to the surface of the substrate 303 and perpendicular to the first direction X; a source-drain structure located in the source-drain through hole 304; a gate through hole 308 located in the second region II, the gate through hole 308 is adjacent to the channel region 305, and the gate through hole 308 exposes the surface of the insulating layer 301; a gate structure located in the gate through hole 308.

[0102] In this embodiment, the material of the substrate 303 includes silicon, and the doping type of the substrate 303 is P-type doping.

[0103] In this embodiment, the substrate 303 includes a plurality of first regions I that are separated from each other. The plurality of first regions I are arranged along a first direction X, and the second region II is located between adjacent first regions I.

[0104] In this embodiment, the first region I includes a plurality of channel regions 305 , the plurality of channel regions 305 are arranged along a first direction X, and a source-drain through hole 304 is provided between adjacent channel regions 305 .

[0105] In this embodiment, the depth of the source-drain through hole 304 is the same as the thickness of the second semiconductor layer 302 .

[0106] In this embodiment, the source-drain structure includes: a source-drain diffusion layer 306 located in the source-drain through hole 304 and a source-drain doping layer 307 located on the surface of the source-drain diffusion layer 306 .

[0107] In this embodiment, the material of the source / drain doping layer 307 includes: polysilicon doped with N-type ions or P-type ions.

[0108] In this embodiment, the gate structure includes: a gate oxide layer 309 located on the surface of the gate through hole 308 , a gate dielectric layer 310 located on the surface of the gate oxide layer, and a gate material layer 311 located on the surface of the gate dielectric layer 310 .

[0109] In this embodiment, the material of the gate dielectric layer 310 includes a high-K dielectric.

[0110] In this embodiment, the material of the gate oxide layer 309 includes silicon oxide.

[0111] In this embodiment, the material of the gate material layer 311 includes: polysilicon doped with N-type ions or P-type ions.

[0112] In this embodiment, the substrate 303 further includes a bias well region 314 located in the second semiconductor layer 302. In this embodiment, the semiconductor structure further includes an isolation structure 313 located in the second region II on both sides of the gate structure and between the bias well region 314 and the first region I.

[0113] In this embodiment, the material of the isolation structure 313 includes silicon oxide.

[0114] In this embodiment, the semiconductor structure further includes: an interlayer dielectric layer located on the surface of the first region I, the surface of the second region II, the surface of the bias well region 314 , the surface of the isolation structure 313 , and the surface of the second semiconductor layer 302 .

[0115] In this embodiment, the material of the interlayer dielectric layer includes silicon dioxide.

[0116] In this embodiment, the semiconductor structure also includes: a connection structure 315 located in the interlayer dielectric layer on the surface of the gate structure, the surface of the source and drain structure, and the surface of the bias well region 314, and the connection structure 315 is electrically connected to one or more of the gate structure, the source and drain structure, and the bias well region 314.

[0117] In this embodiment, the material of the connection structure 315 includes a metal conductive material. Specifically, the connection structure 315 is aluminum.

[0118] Please refer to Fig.23 , Fig.23 for Fig. 22 The circuit structure schematic diagram of the semiconductor structure shown in the figure includes: a first MOS tube M1 and a second MOS tube M2, wherein the source S of the first MOS tube M1 and the second MOS tube M2 are connected, the drain D of the first MOS tube M1 and the second MOS tube M2 are connected, and the gate G of the first MOS tube M1 and the second MOS tube M2 are connected.

[0119] Please Fig. 22 Based on reference Fig.23 The first MOS tube M1 is formed by the gate structure and the left source-drain structure, and the second MOS tube M2 is formed by the gate structure and the right source-drain structure, that is, the two source-drain structures share one gate structure to form two MOS tubes, which reduces the area of ​​the device, improves the integration of the device, and thus improves the device performance and reduces the power consumption of the device.

[0120] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: A substrate, the substrate comprising: a first semiconductor layer, an insulating layer located on a surface of the first semiconductor layer, and a second semiconductor layer located on the insulating layer, the substrate comprising: adjacent first and second regions arranged along a first direction parallel to a surface of the substrate, the first region having a channel region; source-drain through holes located in the first region on both sides of the channel region, the source-drain through holes exposing a surface of the insulating layer, the source-drain through holes and the channel region arranged along a second direction, the second direction being parallel to the surface of the substrate and perpendicular to the first direction; A source-drain structure located in the source-drain through hole; a gate through hole located in the second region, the gate through hole being adjacent to the channel region, and the gate through hole exposing a surface of the insulating layer; A gate structure is positioned within the gate through hole.

2. The semiconductor structure according to claim 1, wherein: The substrate includes a plurality of first regions separated from each other, the plurality of first regions are arranged along a first direction, and the second region is located between adjacent first regions.

3. The semiconductor structure according to claim 2, wherein: The first region includes a plurality of channel regions, the plurality of channel regions are arranged along a first direction, and a source-drain through hole is provided between adjacent channel regions.

4. The semiconductor structure according to claim 1, wherein: The source-drain structure includes: a source-drain diffusion layer located in the source-drain through hole and a source-drain doping layer located on the surface of the source-drain diffusion layer.

5. The semiconductor structure according to claim 1, wherein: The gate structure comprises: a gate oxide layer located on the surface of the gate through hole, a gate dielectric layer located on the surface of the gate oxide layer, and a gate material layer located on the surface of the gate dielectric layer.

6. The semiconductor structure according to claim 1, wherein: The substrate also includes a bias well region located within the second semiconductor layer.

7. The semiconductor structure according to claim 6, wherein: Also includes: An isolation structure is located in the second region on both sides of the gate structure and between the bias well region and the first region.

8. The semiconductor structure according to claim 7, wherein: Also includes: An interlayer dielectric layer is located on the surface of the first region, the surface of the second region, the surface of the bias well region, the surface of the isolation structure and the surface of the second semiconductor layer.

9. The semiconductor structure according to claim 8, characterized in that Also includes: A connection structure is located in the interlayer dielectric layer on the surface of the gate structure, the surface of the source-drain structure and the surface of the bias well region, and the connection structure is electrically connected to one or more of the gate structure, the source-drain structure and the bias well region.

10. A method for forming a semiconductor structure, characterized in that: Providing a substrate, the substrate comprising: a first semiconductor layer, an insulating layer located on a surface of the first semiconductor layer, and a second semiconductor layer located on the insulating layer, the substrate further comprising: a first region and a second region adjacent to each other arranged along a first direction parallel to a surface of the substrate, wherein the first region has a channel region; forming a source-drain structure in the first region; A gate structure is formed in the second region.

11. The method for forming a semiconductor structure according to claim 10, wherein: The substrate includes a plurality of first regions separated from each other, the plurality of first regions are arranged along a first direction, and the second region is located between adjacent first regions.

12. The method for forming a semiconductor structure according to claim 11, wherein: The first region includes a plurality of channel regions, the plurality of channel regions are arranged along a first direction, and a source-drain through hole is provided between adjacent channel regions.

13. The method for forming a semiconductor structure according to claim 10, wherein: The method for forming the source-drain structure includes: etching the second semiconductor layer in the first region on both sides of the channel region until the surface of the insulating layer is exposed to form a source-drain through hole; performing a thermal diffusion process on the source-drain through hole to form an initial source-drain diffusion layer; forming an initial source-drain doped layer on the surface of the initial source-drain diffusion layer; and flattening the initial source-drain diffusion layer and the initial source-drain doped layer to form a source-drain diffusion layer and a source-drain doped layer.

14. The method for forming a semiconductor structure according to claim 10, wherein: The method for forming the gate structure includes: etching the second semiconductor layer in the second region on both sides of the channel region until the surface of the insulating layer is exposed to form a gate through hole; depositing an initial gate oxide layer on the surface of the gate through hole; depositing an initial gate dielectric layer on the surface of the initial gate oxide layer; depositing an initial gate material layer on the surface of the initial gate dielectric layer; and planarizing the initial gate oxide layer, the initial gate dielectric layer and the initial gate material layer until the surface of the second semiconductor layer is exposed to form a gate oxide layer, a gate dielectric layer and a gate material layer.

15. The method for forming a semiconductor structure according to claim 14, wherein: Also includes: Before forming the gate structure and the source-drain structure, forming an initial second semiconductor layer on the surface of the insulating layer; The initial second semiconductor layer is subjected to ion implantation to form a second semiconductor layer.

16. The method for forming a semiconductor structure according to claim 10, wherein: The substrate further includes a bias well region located in the second semiconductor layer, and an isolation structure is provided between the bias well region and the first region.

17. The method for forming a semiconductor structure according to claim 16, wherein: The channel region and the bias well region are formed simultaneously.

18. The method for forming a semiconductor structure according to claim 17, wherein: The method for forming the isolation structure includes: after forming the gate structure, etching the second semiconductor layer in the second region on both sides of the gate structure, the second semiconductor layer in the first region on both sides of the source and drain structure, and the second semiconductor layer on both sides of the bias well region until the insulating layer is exposed to form a shallow trench; depositing an initial isolation structure in the shallow trench; and flattening the initial isolation structure until the surface of the second semiconductor layer is exposed to form an isolation structure.

19. The method for forming a semiconductor structure according to claim 18, wherein: Also includes: Forming an initial interlayer dielectric layer on the surface of the first region, the surface of the second region, the surface of the bias well region, the surface of the isolation structure, and the surface of the second semiconductor layer; The initial interlayer dielectric layer on the surface of the gate structure, the surface of the source-drain structure and the surface of the bias well region is etched to form a plurality of first openings and an interlayer dielectric layer; a connection structure is formed in the first opening, and the connection structure is electrically connected to one or more of the gate structure, the source-drain structure and the bias well region.

20. The method for forming a semiconductor structure according to claim 15, wherein: The ions doped in the second semiconductor layer include P-type or N-type ions.

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