Shield gate power semiconductor device and preparation method thereof

Abstract

The invention relates to the technical field of semiconductors, particularly provides a preparation method of a shield gate power semiconductor device and the shield gate power semiconductor device, and aims to solve the problem of insufficient flatness of the top of a shield gate in the existing preparation method of the shield gate power semiconductor device. In order to achieve the purpose, according to the preparation method of the shield gate power semiconductor device, in the process of forming a shield gate, a protection layer is formed on the side wall of the top of a middle structure, namely a shield gate material structure, and in the subsequent process of etching the shield gate material structure, under the blocking and protection effects of the protection layer, the shield gate material structure is prevented from being damaged. By means of the method, common V-shaped Recess in an existing shield gate can be effectively removed, so that the top of the shield gate has a flat surface, it is guaranteed that an isolation layer and a control gate formed subsequently have ideal shapes, and it is guaranteed that a shield gate power semiconductor device has good performance.

Description

Technical Field

[0001] The present disclosure relates to the technical field of power semiconductor devices, and specifically provides a method for preparing a shielded gate power semiconductor device and a shielded gate power semiconductor device. Background Art

[0002] SGT (Shielded Gate Trench) MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is based on the charge balance theory. It introduces a shielded gate connected to the source electrode vertically in the traditional trench MOSFET (U-MOSFET) for electric field modulation, which reduces switching losses while retaining the low conduction losses of the traditional trench MOSFET. At present, SGT MOSFET is mainly used as a switching device in the core power control components of new energy electric vehicles, new photovoltaic power generation, energy-saving home appliances and other fields.

[0003] Research shows that the morphology of the shield gate, control gate, and isolation layer between the two in SGT MOSFET will affect the performance of the device. Among them, since the shield gate is located in the bottom area of ​​the trench and is formed first, its morphology will affect the morphology of the isolation layer and control gate formed subsequently. The shield gate in the existing SGT MOSFET has insufficient flatness on the top during the preparation process, which reduces the insulation performance of the isolation layer formed on the shield gate, resulting in easy leakage between the control gate and the shield gate. Summary of the invention

[0004] The present disclosure aims to solve the above technical problem, that is, to solve the problem of insufficient flatness of the top of the shielding gate in the existing method for preparing the shielding gate power semiconductor device.

[0005] In a first aspect, the present disclosure provides a method for preparing a shielded gate power semiconductor device, comprising: forming a groove in a semiconductor substrate, and forming a first dielectric layer covering the side walls and bottom wall of the groove; forming a shielded gate material structure in the groove, wherein the highest point of the top surface of the shielded gate material structure does not exceed the opening of the groove; partially removing the first dielectric layer on the upper part of the side wall of the groove to form a gap between the top area of ​​the shielded gate material structure and the remaining first dielectric layer to expose the side wall of the top area; forming a protective layer on the side wall of the top area; and etching the top area of ​​the shielded gate material structure to form a shielded gate.

[0006] In some embodiments, a reactive ion etching process is used to etch the top region of the shielding gate material structure to form the shielding gate, wherein a reaction rate in the reactive ion etching process is greater than a bombardment rate.

[0007] In some embodiments, the process of forming the protective layer includes: forming a protective material layer to at least cover the side walls and the top surface of the top area; patterning the protective material layer to remove the protective material layer on the top surface of the top area and retain the protective material layer on the side walls of the top area to form the aforementioned protective layer.

[0008] In some embodiments, the protective material layer is patterned, including: using a dry etching process to remove the protective material layer on the top surface of the top area, and retaining the protective material layer on the side wall of the top area, and during the dry etching process, controlling the etching rate of the protective material layer on the top surface of the top area to be greater than the etching rate of the protective material layer on the side wall.

[0009] In some embodiments, there is a gap between the protection layer on the sidewall of the top region and the remaining first dielectric layer.

[0010] In some embodiments, forming a shielding gate material structure in a trench includes: filling the trench with a shielding gate material; removing a portion of the shielding gate material so that the highest point of the top surface of the remaining shielding gate material in the trench does not exceed the opening of the trench.

[0011] In some embodiments, the protection layer is removed using a wet etching process.

[0012] In some other embodiments, the protection layer is removed simultaneously during the etching of the top region of the shielding gate material structure.

[0013] In some embodiments, the preparation method also includes: removing the first dielectric layer located on the upper portion of the sidewall of the trench to expose the upper portion of the sidewall of the trench; forming a second dielectric layer, the second dielectric layer at least covering the shielding gate and the exposed sidewall of the trench; forming a control gate in the trench, wherein the control gate is electrically insulated from the shielding gate by the second dielectric layer.

[0014] In a second aspect, the present disclosure provides a shielded gate power semiconductor device, which is manufactured using the above-mentioned manufacturing method.

[0015] Compared with the prior art, the present invention has the following beneficial effects:

[0016] The preparation method of the shielded gate power semiconductor device provided by the present invention forms a protective layer on the top side wall of the intermediate structure, that is, the shielding gate material structure, during the process of forming the shielding gate. In the subsequent process of etching the shielding gate material structure, the common recessed structure (V-shaped recess) in the existing shielding gate can be effectively removed under the blocking and protective effect of the protective layer, so that the top of the shielding gate has a relatively flat surface, which is beneficial to ensure that the isolation layer and the control gate formed subsequently have ideal morphology, and ensure that the shielded gate power semiconductor device has good performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figures 1A to 1D It is a cross-sectional schematic diagram of the process of manufacturing a shielded gate using an existing SGT MOSFET manufacturing process;

[0018] Figure 2A and Figure 2C They are schematic cross-sectional views of a process of forming a shielding gate and a schematic cross-sectional view of a process of forming a shielding gate using another existing SGT MOSFET manufacturing process;

[0019] Figure 2B and Figure 2D The scanning electron microscope photos are respectively taken during the process of forming the shield gate by using another existing SGT MOSFET preparation process and after the shield gate is formed;

[0020] Figure 3 A flow chart of forming a shielding gate using the SGT MOSFET preparation process provided by the present disclosure;

[0021] FIG. 4A to FIG. 4C and Figure 4E A cross-sectional view of a shielding gate formed by the SGT MOSFET manufacturing process provided by the present disclosure;

[0022] Figure 4D This is a scanning electron microscope photograph of a shielding gate formed by the SGT MOSFET preparation process provided by the present disclosure.

[0023] Description of reference numerals:

[0024] 1. Semiconductor substrate; 11. Groove; 2. First dielectric layer; 3a. Shielding gate material; 3b. Shielding gate material structure; 30. Top area; 3. Shielding gate; 4a. Protective material layer; 4b. First protective material layer; 4c. Second protective material layer; 4. Protective layer. DETAILED DESCRIPTION

[0025] The preferred embodiments of the present disclosure are described below with reference to the accompanying drawings. It should be understood by those skilled in the art that these embodiments are only used to explain the technical principles of the present disclosure and are not intended to limit the scope of protection of the present disclosure. It should also be noted that in the description of the present disclosure, "first", "second" and similar expressions are only used for distinction and do not represent priority or quantity.

[0026] like Figures 1A to 1D As shown, a typical SGT MOSFET manufacturing process currently includes the following steps:

[0027] S10, forming a trench 11 in the semiconductor substrate 1, and forming a first dielectric layer 2 on the inner wall (including the side wall and the bottom wall) of the trench 11, such as Figure 1A shown.

[0028] S20, forming a shielding gate 3 in the trench 11, which specifically includes:

[0029] S21, filling the shielding gate material 3a in the trench 11, such as Figure 1B As shown, the shielding gate material 3a fills the entire trench 11 and is generally not lower than the opening of the trench 11, that is, the lowest point of the top surface of the shielding gate material 3a corresponding to the trench 11 is higher than the opening of the trench 11, or the lowest point of the top surface of the shielding gate material 3a is flush with the opening of the trench 11, thereby ensuring that the entire trench 11 is filled. The material of the shielding gate material 3a is doped polysilicon, etc., which can be used as a shielding gate material in SGT MOSFET.

[0030] S22, using a planarization process such as CMP (Chemical Mechanical Polishing) to remove the shielding gate material 3a that is higher than the opening of the trench 11, and using the first dielectric layer 2 on the semiconductor substrate 1 as a stop layer, such as Figure 1C shown.

[0031] S23, continue to etch back the shielding gate material 3a to form a shielding gate material structure 3b whose height is lower than the opening of the groove 11, as a shielding gate 3, as shown in Figure 1d, the highest point of the top surface of the shielding gate 3 does not exceed the opening of the groove 11, or in other words, the highest point of the top surface of the shielding gate 3 does not exceed the top surface of the semiconductor substrate 1.

[0032] S30 , etching the first dielectric layer 2 located on the sidewalls of the trench 11 , removing the exposed first dielectric layer 2 , and retaining the first dielectric layer 2 located on the side and bottom of the shielding gate 3 .

[0033] S40, forming a second dielectric layer on the exposed sidewalls of the trench 11 and on the top of the shielding gate 3. The material of the second dielectric layer can be the same as or different from that of the first dielectric layer 2. The second dielectric layer on the top of the shielding gate 3 is an isolation layer.

[0034] S50 , forming a control gate in the trench 11 .

[0035] Among them, in step S21, taking the filling of doped polysilicon into the groove 11 as an example, in the process of filling the groove 11, the doped polysilicon gradually closes from the edge of the groove 11 to the middle, and when the groove 11 is filled, the doped polysilicon will form a conical recessed structure (V-shaped recess) at the closed position. Although the planarization process in step S22 can help improve the above-mentioned recessed structure, it is difficult to completely remove it. In addition, based on the groove filling principle, the material of the top center area of ​​the shielding grid 3 (i.e., the closed part) is relatively loose, so in the process of back etching in step S23, the etching rate of the center area is relatively fast, so not only the recessed structure at the top of the shielding grid 3 is retained, but also if the ordinary dry etching process is adopted, the depth of the recessed structure may be increased. The morphology of the shielding grid 3 will inevitably affect the morphology of the isolation layer and the control grid formed subsequently, resulting in a decrease in the insulation performance of the isolation layer, and easy leakage between the control grid and the shielding grid 3, which ultimately leads to a decrease in product performance or even failure.

[0036] In order to improve the morphology of the shielding gate, a more common solution in the industry is to deposit a sufficiently thick shielding gate material 3a such as doped polysilicon in step S21, so that the lowest point of the top surface of the shielding gate material 3a is higher than the top surface of the first dielectric layer 2, and then in step S22, the V-shaped Recess is fully removed by the CMP process. However, this solution will significantly increase the process time and production cost, and it is also necessary to strictly control the process conditions of the back etching in step S23. In addition, another solution proposed by the applicant is to trim the top of the shielding gate 3. Specifically, on the basis of step S23, the process of forming the shielding gate 3 in the groove 11 also includes:

[0037] S24, partially removing the first dielectric layer 2 on the sidewall of the trench 11, so that a gap is formed between the top region 30 of the shielding gate material structure 3b and the remaining first dielectric layer 2 to expose the top region 30 of the shielding gate material structure 3b, such as Figure 2A As shown; this step can adopt an isotropic etching process such as wet etching to reduce the thickness of the first dielectric layer 2 located on the upper side wall of the groove 11, thereby forming a gap between the top area 30 of the shielding gate material structure 3b. Of course, the thickness of the first dielectric layer 2 located on the lower side wall of the groove 11 remains unchanged.

[0038] S25, etching the shielding grid material structure 3b by using etching processes such as reactive ion etching, so as to obtain a shielding grid with a relatively flat top surface.

[0039] S30 ′, etching the remaining first dielectric layer 2 to retain the first dielectric layer 2 at the side and bottom of the shielding gate, exposing the upper sidewall of the trench 11 .

[0040] S40 ′, continue to form a second dielectric layer on the exposed sidewalls of the trench 11 and the top of the shielding gate.

[0041] S50 ′, forming a control gate in the trench 11 .

[0042] With this solution, during the execution of step S25, by strictly controlling the bombardment rate and reaction rate during the reactive ion etching process, the recessed structure can be theoretically reduced or fully eliminated. However, practice has proved that the etching conditions of this step are relatively harsh and the process window is narrow. Once the etching process is unstable or even the process is unstable during the deposition process of filling the groove 11, the top of the recently obtained shielding gate 3 may not have a relatively flat surface. Instead, the edge of the top of the shielding gate is lower than the central part, that is, a sharp corner appears in the central part of the top of the shielding gate 3, such as Figure 2C As shown. It is speculated that the top edge of the shielding grid may be the first to contact the etching material, and the contact area between the edge and the etching material is larger (including the area of ​​the top edge and the exposed side wall area), resulting in a higher etching rate at the edge than at the center. In addition, the center is more prone to the accumulation of etching products, which is not conducive to the continuation of the etching reaction. Even if the material at the closed center is relatively sparse, the combined effect of the above factors ultimately results in the center of the top of the shielding grid 3 being higher than the edge, which will also affect the morphology of the isolation layer and the control gate.

[0043] Figure 2B and Figure 2D They are scanning electron microscope photos obtained during the process of adopting this solution. After measurement, the flatness of the top of the shielding grid 3 formed by this preparation process is slightly improved, that is, the height difference between the edge part and the center part of the top of the shielding grid 3 is reduced but not obvious, so there is still a possibility of leakage between the control grid and the shielding grid.

[0044] Based on this, Figure 3 As shown, the present disclosure provides a method for preparing a shielded gate power semiconductor device, including: forming a groove in a semiconductor substrate, and forming a first dielectric layer covering the sidewalls and bottom wall of the groove; forming a shielded gate material structure in the groove, wherein the highest point of the top surface of the shielded gate material structure does not exceed the opening of the groove; partially removing the first dielectric layer on the upper part of the sidewall of the groove to form a gap between the top area of ​​the shielded gate material structure and the remaining first dielectric layer to expose the sidewall of the top area; forming a protective layer on the sidewall of the top area; and etching the top area of ​​the shielded gate material structure to form a shielded gate.

[0045] S100, such as Figure 1A As shown, a trench 11 is formed in a semiconductor substrate 1 .

[0046] The semiconductor substrate 1 may be a substrate commonly used in processing power semiconductor devices, such as a silicon substrate, a gallium nitride substrate, a silicon carbide substrate, an SOI substrate, etc. The semiconductor substrate 1 may include a substrate and an epitaxial layer formed on the substrate. The bottom of the trench 11 may be located in the epitaxial layer, or may extend to the junction between the substrate and the epitaxial layer.

[0047] S200, continue to refer to Figure 1A A first dielectric layer 2 is formed on the inner wall of the trench 11. Of course, in addition to covering the bottom wall and sidewall of the trench 11, the first dielectric layer 2 may also extend to cover the surface of the semiconductor substrate 1. The material of the first dielectric layer 2 may be a single-layer structure of silicon oxide, hafnium oxide, silicon oxynitride, etc., or a stacked structure, such as a stack of silicon oxide and silicon nitride layers.

[0048] S300, forming a shielding gate material structure 3b in the trench 11, specifically comprising the following steps:

[0049] S310, such as Figure 1B As shown, the shielding gate material 3a is filled in the groove 11, and the shielding gate material 3a can be higher than the groove 11, and can also cover the dielectric layer 2 located on the semiconductor substrate 1. Among them, the lowest point of the top surface of the shielding gate material 3a can be higher than the opening of the groove 11, and can also be flush with the opening of the groove 11, that is, the lowest point of the top surface of the shielding gate material 3a is flush with the top surface of the semiconductor substrate 1 or exceeds the top surface of the semiconductor substrate 1. Of course, the present disclosure is not limited to this, as long as it can be closed from the edge of the groove 11 to the middle during the deposition of the shielding gate material, and generally the deposition thickness is controlled to be not less than 1 / 2 of the maximum width of the groove 11.

[0050] S320, such as Figure 1C As shown, the shielding gate material 3a that is higher than the top opening of the trench 11 is removed through a planarization process such as CMP.

[0051] S330, such as Figure 1D As shown, the planarized shielding gate material 3a is etched back to form a shielding gate material structure 3b, wherein the shielding gate material structure 3b is located in the groove 11 and does not exceed the opening of the groove 11, that is, the highest point of the top surface of the shielding gate material structure 3b located in the groove 11 does not exceed the top surface of the semiconductor substrate 1.

[0052] Of course, it should be noted that in this embodiment, a portion of the shielding gate material 3a is removed by a planarization process plus an etching process to obtain a shielding gate material structure 3b, and the top of the shielding gate material structure 3b still retains a morphology similar to the concave structure, that is, the edge of the top of the shielding gate material structure 3b is higher than the center. However, the present disclosure is not limited to this, and a planarization process such as CMP can also be omitted, and only a conventional etching process, such as anisotropic etching, can be used to obtain the shielding gate material structure 3b.

[0053] S400, processing the shielding grid material structure 3b into the shielding grid 3, specifically comprising the following steps:

[0054] S410, partially removing the first dielectric layer 2 on the side wall of the groove 11, such as Figure 2A As shown, the thickness of the first dielectric layer 2 on the sidewalls of the trench 11 corresponding to the upper and oblique sides of the shielding gate material structure 3b and the side of the top region 30 of the shielding gate material structure 3b is reduced, so that a gap is formed between the top region 30 of the shielding gate material structure 3b and the remaining first dielectric layer 2 to expose the top region 30 of the shielding gate material structure 3b, that is, the top surface and sidewalls of the top region 30 are exposed.

[0055] Specifically, an isotropic etching process such as a wet etching process may be used to partially remove the first dielectric layer 2 on the upper sidewall of the trench 11 to form a gap between the top region 30 of the shielding gate material structure 3 b and the corresponding first dielectric layer 2 .

[0056] S420, such as Figure 4A and Figure 4B As shown, a protective layer 4 is formed to cover the sidewalls of the top region 30 of the shielding gate material structure 3b and expose the top surface of the top region 30. Specifically, the steps include:

[0057] S421, forming a protective material layer 4a to at least cover the sidewalls and top surface of the top region 30 of the shielding gate material structure 3b. In the following, for the convenience of distinction and description, the protective material layer 4a covering the sidewalls of the top region 30 is referred to as the first protective material layer 4b, and the protective material layer covering the top surface of the top region 30 is referred to as the second protective material layer 4c. Figure 4A shown.

[0058] S422, patterning the protective material layer 4a, removing the second protective material layer 4c and retaining the first protective material layer 4b, thereby forming a protective layer 4, such as Figure 4B shown.

[0059] In one implementation, patterning the protective material layer 4a includes: first forming a mask to expose the second protective material layer 4c; then using a dry etching process to remove the second protective material layer 4c and retain the first protective material layer 4b; and finally removing the mask.

[0060] In another preferred implementation, the protective material layer 4a can also be etched without the protection of a mask, and the etching rate of the second protective material layer 4c is greater than the etching rate of the first protective material layer 4b by reasonably controlling the process conditions during the etching process. Specifically, anisotropic etching, especially dry etching, can be used, and the etching depth depends on the thickness of the second protective material layer 4c, so that the second protective material layer 4c is completely removed, and the height of the first protective material layer 4b (i.e., the dimension along the depth direction of the groove 11) is only reduced, thereby obtaining the protective layer 4.

[0061] In some examples, the thickness of the first protective material layer 4b does not exceed the gap between the shielding grid material structure 3b and the first dielectric layer 2, that is, the first protective material layer 4b does not completely fill the gap between the shielding grid material structure 3b and the first dielectric layer 2, so that there is also a gap between the top area 30 of the shielding grid material structure 3b and the first dielectric layer 2. At this time, the thickness of the first protective material layer 4b is relatively thin, and there is a gap between the first protective material layer 4b and the first dielectric layer 2, which is convenient for the subsequent removal of the first protective material layer 4b constituting the protective layer 4, saving process time. Of course, the thickness of the protective material layer 4a cannot be too thin, otherwise the formed protective layer 4 is difficult to play a protective role. Practice shows that the thickness of the protective material layer 4a can be set in the range of 250 angstroms to 350 angstroms, which can not only play a protective role, but also facilitate subsequent removal. The material of the protective material layer 4a can be inorganic insulating materials such as silicon oxide and silicon nitride.

[0062] S423, etching the shielding gate material structure 3b to form the shielding gate 3, as shown in FIG4c. Specifically, a reactive ion etching process can be used to etch the exposed shielding gate material structure 3b, and the reaction rate in the reactive ion etching process is controlled to be greater than the bombardment rate. Of course, the etching gas used in the reactive ion etching process has a high selective etching ratio for the shielding gate material structure 3b and the protective layer 4, so as to minimize the consumption of the protective layer 4 in the process of etching the shielding gate material structure 3b. For example, the material of the shielding gate material structure 3b is doped polysilicon, the material of the protective layer 4 is silicon dioxide, and the etching gas used in the reactive ion etching process is SF6.

[0063] In the process of etching the exposed shielding grid material structure 3b by reactive ion etching, the edge area of ​​the top of the shielding grid material structure 3b is more easily exposed during the etching process. In addition, the protective layer 4 protects the top sidewall of the shielding grid material structure 3b, and the reaction product is deposited in the central area. Therefore, although the material in the central area is relatively sparse, the above factors work together to make the etching rate of the edge area slightly greater than the etching rate of the central area, but the difference between the two is controllable. As the etching proceeds, the height difference between the edge area and the central area will gradually decrease. In addition, as the height of the shielding grid material structure 3b gradually decreases, the protective layer 4 is inevitably etched away, and it also decreases accordingly. The specific degree of reduction depends on the etching selectivity ratio of the protective layer to the shielding grid material structure 3b. Therefore, under the blocking and protective effect of the protective layer 4, it is not easy to have the situation that the edge area of ​​the top of the etched shielding grid 3 is significantly lower than the central area, so the height difference between the edge area and the central area of ​​the finally formed shielding grid 3 can be reduced to improve the flatness of the top of the shielding grid 3, and the window of this etching process is large and the controllability is good.

[0064] like Figure 4D As shown, the average height difference between the top center and the edge of the shielding grid 3 is only about 55nm, which is Figure 2B Compared with the shielding grid manufactured by the prior art process, the depth of the recessed structure is reduced by about 47.1%.

[0065] S500, removing the protective layer 4. Specifically, a wet etching process is used to remove the protective layer 4. Since the protective layer 4 is inevitably damaged during the process of etching to form the shielding gate 3, the remaining protective layer 4 can be removed by rinsing.

[0066] In other examples, during the process of etching the shielding gate material structure 3b to form the shielding gate 3 in step S423, the selective etching ratio of the shielding gate material structure 3b and the protective layer 4 can be adjusted so that the protective layer 4 and the shielding gate material structure 3b are etched synchronously. It is only necessary to ensure that the protective layer 4 protects the side wall of the shielding gate material structure 3b. This can save the step of removing the protective layer 4 separately.

[0067] S600, remove the first dielectric layer 2 covering the upper sidewall of the trench 11 to expose the upper sidewall of the trench 11, and then form a second dielectric layer (not shown), the second dielectric layer at least covers the shielding gate 3 and the exposed sidewall of the trench 11, and then continue to form a control gate in the trench 11, wherein the second dielectric layer between the control gate and the shielding gate 3 is an isolation layer. Of course, the subsequent steps also include forming a metallization layer to realize electrode extraction, etc., which can adopt existing processes and will not be repeated.

[0068] In summary, the method for preparing the shielded gate power semiconductor device provided by the present disclosure has at least the following advantages:

[0069] (1) In the process of forming the shielding gate 3, a protective layer 4 is formed on the side wall of the shielding gate material structure 3b. In this way, in the process of etching the shielding gate material structure 3b, due to the blocking and protection of the protective layer 4, the etching rate of the edge area of ​​the top of the shielding gate material structure 3b can be slightly greater than the etching rate of the central area. It is less likely that the edge part of the top of the shielding gate 3 after etching is significantly lower than the central part. The height difference between the edge area and the central area of ​​the top of the shielding gate 3 finally formed can be reduced, so as to improve the flatness of the top of the shielding gate 3. In addition, the process window of the above-mentioned etching process is larger and the controllability is better.

[0070] (2) In the process of forming the shielding gate 3, the etching selectivity between the shielding gate material structure 3b and the protective layer 4 can be controlled to ensure the protective effect of the protective layer 4 and to control whether the protective layer 4 is removed synchronously, making the entire process route more flexible.

[0071] The present disclosure also provides a shielded gate power semiconductor device, which is manufactured by the above-mentioned manufacturing method. There are also the following points that need to be explained: (1) The drawings of the embodiments of the present disclosure only show the structures involved in the embodiments of the present disclosure, and other structures can refer to conventional designs; (2) For the sake of clarity, in the drawings used to assist in describing the embodiments of the present disclosure, the thickness of the layer or region is enlarged or reduced, that is, these drawings are not drawn according to the actual scale; (3) In the absence of conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0072] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A method for preparing a shielded gate power semiconductor device, characterized in that: include: Forming a trench in a semiconductor substrate, and forming a first dielectric layer covering the sidewalls and bottom wall of the trench; forming a shielding grid material structure in the groove, wherein the highest point of the top surface of the shielding grid material structure does not exceed the opening of the groove; Partially removing the first dielectric layer from a portion of the sidewall of the trench to form a gap between the top region of the shielding gate material structure and the remaining first dielectric layer to expose the sidewall of the top region; forming a protective layer on the sidewalls of the top region; The top area of ​​the shielding grid material structure is etched to form a shielding grid.

2. The preparation method according to claim 1, characterized in that: A reactive ion etching process is used to etch the top area of ​​the shielding grid material structure to form the shielding grid, wherein the reaction rate in the reactive ion etching process is greater than the bombardment rate.

3. The preparation method according to claim 1, characterized in that: The process of forming the protective layer includes: forming a protective material layer to cover at least the sidewalls and the top surface of the top region; The protective material layer is patterned to remove the protective material layer on the top surface of the top region and retain the protective material layer on the side wall of the top region to form the protective layer.

4. The preparation method according to claim 3, characterized in that: The protective material layer is subjected to patterning, comprising: A dry etching process is used to remove the protective material layer on the top surface of the top area, and the protective material layer on the side wall of the top area is retained. During the dry etching process, the etching rate of the protective material layer on the top surface of the top area is controlled to be greater than the etching rate of the protective material layer on the side wall.

5. The preparation method according to any one of claims 1 to 4, characterized in that: There is a gap between the protection layer and the remaining first dielectric layer.

6. The preparation method according to claim 1, characterized in that: A shielding gate material structure is formed in the trench, comprising: Filling the trench with a shielding grid material; Part of the shielding grid material is removed so that the highest point of the top surface of the remaining shielding grid material in the groove does not exceed the opening of the groove.

7. The preparation method according to claim 1, characterized in that: Also includes: The protection layer is removed by a wet etching process.

8. The preparation method according to claim 1, characterized in that: During the etching process of the top area of ​​the shielding gate material structure, the protection layer is removed simultaneously.

9. The preparation method according to any one of claims 1-4 and 6-8, characterized in that: Also includes: removing the first dielectric layer located on the upper portion of the sidewall of the trench to expose the upper portion of the sidewall of the trench; forming a second dielectric layer, wherein the second dielectric layer at least covers the shielding grid and the exposed sidewalls of the trench; A control gate is formed in the trench, wherein the control gate is electrically insulated from the shielding gate by the second dielectric layer.

10. A shielded gate power semiconductor device, characterized in that: The method is prepared according to any one of claims 1 to 9.

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