Preparation method of stacked transistor, stacked transistor and semiconductor device

Abstract

The invention provides a preparation method of a stacked transistor, the stacked transistor and a semiconductor device. The method comprises the steps that a fin-shaped structure is formed on a semiconductor substrate through one-time etching, the fin-shaped structure comprises a first part and a second part which are stacked in the first direction, and the first part is far away from the semiconductor substrate compared with the second part; forming a first transistor based on the first part, the first transistor comprising: a first gate structure formed by a first gate preparation process; reversing and removing the semiconductor substrate; based on the second part, forming a second transistor stacked with the first transistor along the first direction, the second transistor comprising: a second gate structure formed by a second gate preparation process; the second gate preparation process and the first gate preparation process are at least different in preparation step; the heat resistance of the first gate structure is greater than that of the second gate structure.

Description

Technical Field

[0001] The present application relates to the field of semiconductor chip manufacturing, and in particular to a method for preparing a stacked transistor, a stacked transistor and a semiconductor device. Background Art

[0002] As Moore's Law continues to deepen, continuing to promote the miniaturization of transistor size is a hot issue in the current industry research and development. Stacked transistors integrate two or more layers of transistors in a vertical space to further increase the integration density of transistors, becoming one of the important technologies to continue the miniaturization of integrated circuit size.

[0003] In some schemes for preparing stacked transistors, active regions of upper and lower layers of transistors of the same source are formed by etching, and stacked transistors are made on the front and back sides of the wafer by flipping the wafer. This can also be called a "self-aligned flip transistor" scheme. However, in the "self-aligned flip transistor" scheme, some preparation processes have the problem of not being able to withstand high temperatures. Therefore, there is still a lot of room for improvement in the "self-aligned flip transistor" scheme. Summary of the invention

[0004] The present application provides a method for preparing a stacked transistor, a stacked transistor and a semiconductor device to form a gate structure that is more resistant to high temperatures on the front side of a wafer, so that on the one hand, the thermal budget of the back side transistor can be improved and the flexibility of the back side transistor can be enhanced, and on the other hand, the failure rate of the front side transistor can be reduced to ensure the success rate of preparing the stacked transistor.

[0005] In a first aspect, an embodiment of the present application provides a method for preparing a stacked transistor, comprising: etching on a semiconductor substrate once to form a fin structure, wherein the fin structure comprises a first portion and a second portion stacked along a first direction, the first portion being farther away from the semiconductor substrate than the second portion; based on the first portion, forming a first transistor, wherein the first transistor comprises: a first gate structure, the first gate structure being formed by a first gate preparation process; flipping and removing the semiconductor substrate; based on the second portion, forming a second transistor stacked along the first direction with the first transistor, wherein the second transistor comprises: a second gate structure, the second gate structure being formed by a second gate preparation process; the second gate preparation process and the first gate preparation process having at least different preparation steps; the heat resistance of the first gate structure is greater than the heat resistance of the second gate structure.

[0006] In some embodiments, a first transistor is formed based on the first part, including: depositing a first gate dielectric material in the gate region of the stacked transistor to form a first gate dielectric layer covering the first part; depositing a metal oxide material on the first gate dielectric layer to form a covering layer; depositing a first gate material on the covering layer to form a first gate electrode layer, wherein the first gate dielectric layer, the covering layer and the first gate electrode layer together constitute a first gate structure; the preparation steps for forming the first gate structure are included in the first gate preparation process; in the source and drain region of the stacked transistor, based on the first part, a first source and drain structure is formed, wherein the first source and drain structure and the first gate structure together constitute a first transistor.

[0007] In some embodiments, when the first transistor is an N-type field effect transistor, the metal oxide material is lanthanum oxide; when the first transistor is a P-type field effect transistor, the metal oxide material is aluminum oxide.

[0008] In some embodiments, a second transistor is formed based on the second part, including: depositing a dummy gate material in the gate region of the stacked transistor to form a dummy gate structure; forming a second source-drain structure in the source-drain region of the stacked transistor based on the second part; removing the dummy gate structure, and depositing a second gate dielectric material at the position where the dummy gate structure is removed to form a second gate dielectric layer; depositing a second gate material on the second gate dielectric layer to form a second gate electrode layer; wherein the second gate dielectric layer and the second gate electrode layer together constitute a second gate structure; the preparation steps for forming the second gate structure are included in the second gate preparation process; the second source-drain structure and the second gate structure together constitute a second transistor.

[0009] In some embodiments, when the first transistor is an N-type field effect transistor, after forming a second transistor based on the second part, the method further includes: bonding the second transistor to a carrier wafer; and flipping the bonded second transistor.

[0010] In some embodiments, when the first transistor is a P-type field effect transistor, the first portion is formed of silicon germanium material.

[0011] In some embodiments, the fin structure also includes a third portion located between the first portion and the second portion; after forming the pseudo gate structure, the preparation method also includes: removing the third portion, and depositing an insulating material at the position where the third portion is removed to form an isolation layer, wherein the isolation layer is used to electrically isolate the first portion and the second portion.

[0012] In a second aspect, an embodiment of the present application provides a stacked transistor, which includes: a first transistor; a second transistor, the first transistor and the second transistor are stacked along a first direction, and the first active area of ​​the first transistor is self-aligned with the second active area of ​​the second transistor; the first transistor includes a first gate structure, and the second transistor includes a second gate structure, and the first gate structure and the second gate structure are arranged back to back; the first gate structure is formed by a first gate preparation process; the first active area is formed based on the first part of the fin structure, and the second active area is formed based on the second part of the fin structure; the second gate structure is formed by a second gate preparation process; the second gate preparation process and the first gate preparation process have at least different preparation steps; the heat resistance of the first gate structure is greater than the heat resistance of the second gate structure.

[0013] In some embodiments, when the first transistor is a P-type field effect transistor, the first active region of the first transistor is formed of silicon germanium material.

[0014] In a third aspect, an embodiment of the present application provides a semiconductor device, which includes: a stacked transistor as described in the above embodiment.

[0015] In the disclosed embodiment, by etching a fin structure on a semiconductor substrate once, and preparing a first transistor and a second transistor on the front and back sides of the semiconductor substrate based on the first part and the second part of the fin structure, respectively, it is possible to achieve self-alignment of the active structures of the upper and lower layers of transistors in the stacked transistor. At the same time, the first gate structure of the first transistor is prepared by the first preparation process, and the second gate structure of the second transistor is prepared by the second preparation process, so that the heat resistance of the first gate structure is greater than the heat resistance of the second gate structure. In this way, on the one hand, the thermal budget of the reverse transistor can be improved, and the flexibility of the reverse transistor can be enhanced. On the other hand, the failure rate of the front transistor can be reduced, and the success rate of preparing the stacked transistor can be ensured.

[0016] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0018] Figure 1 A schematic diagram of an implementation process of a method for preparing a stacked transistor according to an embodiment of the present application;

[0019] Figure 2 is a top view of a first stacked transistor according to an embodiment of the present application;

[0020] Figures 3 to 34 is a schematic diagram of a preparation process of a first stacked transistor according to an embodiment of the present application;

[0021] Figure 35 to Figure 37 It is a schematic diagram of a preparation process of a second stacked transistor according to an embodiment of the present application.

[0022] Figures 10, stacked transistor; 11, first transistor; 12, second transistor; 111, first sidewall spacer; 112, first source-drain structure; 113, first interlayer dielectric layer; 114, first gate structure; 115, first source-drain metal; 116, first metal interconnect layer; 121, second pseudo-gate sidewall spacer; 122, second source-drain structure; 123, second interlayer dielectric layer; 124, second gate structure; 125, second source-drain metal; 126, second metal interconnect layer;

[0023] 20. Semiconductor substrate; 21. Third material layer; 22. First material layer; 23. Second material layer; 24. First part; 25. Second part; 26. Third part; 27. Shallow trench isolation structure; 28. Front oxide layer; 29. ​​First gate dielectric layer; 30. Covering layer; 31. First gate electrode layer; 32. First source-drain groove; 33. Insulating layer; 34. Carrier wafer; 35. Back oxide layer; 36. Initial dummy gate structure; 37. Dummy gate structure; 38. Second sidewall; 39. Isolation layer; 40. Source-drain isolation structure; 41. Second source-drain groove; 42. Second gate dielectric layer; 43. Second gate electrode layer; 44. Gate isolation structure. DETAILED DESCRIPTION

[0024] Here, exemplary embodiments are described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application.

[0025] As Moore's Law continues to deepen, continuing to promote the miniaturization of transistor size is a hot topic in the current industry research and development. Stacked transistors can achieve the integration of two or more layers of transistors in a vertical space through three-dimensional transistor stacking, which helps to further improve the integration density of transistors and improve circuit performance. It is considered to be one of the important technologies for continuing the miniaturization of integrated circuit size.

[0026] In one embodiment, there are two schemes for manufacturing the stacked transistors, the first is a monolithic scheme, and the second is a sequential scheme.

[0027] The first solution is to make N-channel field effect transistors (NFET) and P-channel field effect transistors (PFET) on the same substrate without using wafer bonding technology. This determines that the transistors on the same layer must be of the same type, namely NFET or PFET. In addition, the upper and lower layer transistors must be strictly in the same plane space without alignment deviation. The advantage of this solution is that it has a better integration density. This solution currently has the following technical challenges: (1) The process is complex and requires a lot of process technology development and optimization; (2) The polarity of each layer of transistors is fixed, and two layers of transistors must be relied on to form a basic complementary metal-oxide-semiconductor (CMOS) circuit, which has poor design flexibility.

[0028] The second solution is to bond a wafer on top of the fabricated lower transistor and use the bonded wafer to prepare the upper transistor, thereby stacking the two transistors vertically. However, this solution requires strict temperature control during the processing of the upper transistor to avoid affecting the lower transistor and the interconnection lines between the upper and lower transistors. The advantage of this solution is that thanks to wafer bonding, the device structure, channel crystal orientation and even channel material used by the upper and lower transistors can be different to obtain better and more matched device performance. However, this solution currently has the following technical challenges: (1) Preparation of high-quality top transistor active layer; (2) Thinning and defect control of the top transistor bonded wafer; (3) There is an alignment error between the upper and lower transistors, which requires extremely high lithography accuracy.

[0029] The common technical difficulties faced by the above two solutions include: (1) the thermal stability of the bottom layer device when making the top layer device; (2) the performance of the top layer device under a low thermal budget; and (3) the metal interconnection between the transistors on the top and bottom layers.

[0030] In order to solve the above technical problems, the embodiments of the present disclosure propose a flip-chip scheme for realizing self-aligned stacked transistors. The flip-chip scheme forms active areas of upper and lower layers of homologous transistors by etching, and realizes the production of stacked transistors on the front and back sides of the wafer by flipping the wafer to overcome the shortcomings of the above two schemes. This can also be called a "self-aligned flip transistor" scheme. However, in the "self-aligned flip transistor" scheme, some preparation processes have the problem of not being resistant to high temperatures. Therefore, there is still a lot of room for improvement in the "self-aligned flip transistor" scheme.

[0031] In order to solve the above technical problems, the embodiments of the present application provide a method for preparing a stacked transistor, a stacked transistor and a semiconductor device to form a gate structure that is more resistant to high temperatures on the front side of the wafer, so that on the one hand, the thermal budget of the back side transistor can be improved and the flexibility of the back side transistor can be enhanced, and on the other hand, the failure rate of the front side transistor can be reduced to ensure the success rate of preparing the stacked transistor.

[0032] At the same time, when the first transistor in the stacked transistor is an NFET, a lanthanum oxide capping layer is deposited on the channel corresponding to the NFET, and the lanthanum oxide capping layer can increase negatively charged atoms, thereby effectively reducing the threshold voltage of the NFET. When the first transistor in the stacked transistor is a PFET, a channel is prepared using silicon germanium material to increase carrier mobility, reduce the threshold voltage of the PFET, and further improve the electrical performance of the PFET.

[0033] Furthermore, in order to compensate for the temperature effect, the back-end interconnect structure in the stacked transistor can use high-temperature resistant metal materials such as ruthenium (Ru) or tungsten (W), so that the front-side transistor prepared first in the stacked transistor can withstand higher temperatures.

[0034] In a first aspect, an embodiment of the present application provides a method for preparing a stacked transistor. Figure 1 FIG. 1 is a schematic diagram of an implementation process of a method for preparing a stacked transistor according to an embodiment of the present application, see Figure 1 As shown, the method for preparing a stacked transistor may include:

[0035] Step S101: etching once to form a fin structure on a semiconductor substrate, wherein the fin structure includes a first portion and a second portion stacked along a first direction, and the first portion is farther away from the semiconductor substrate than the second portion;

[0036] Step S102: forming a first transistor based on the first part, wherein the first transistor comprises: a first gate structure, the first gate structure being formed by a first gate preparation process;

[0037] Step S103: flipping the wafer and removing the semiconductor substrate;

[0038] Step S104: Based on the second part, a second transistor is formed which is stacked with the first transistor along the first direction, wherein the second transistor includes: a second gate structure, which is formed by a second gate preparation process; the second gate preparation process and the first gate preparation process are different in at least the preparation steps; and the heat resistance of the first gate structure is greater than the heat resistance of the second gate structure.

[0039] It is understandable that the first gate preparation process and the second gate preparation process both include preparation steps, preparation processes, structural materials, etc. In the embodiment of the present application, the first gate preparation process and the second gate preparation process differ at least in the preparation steps, so that gate structures with different heat resistance can be obtained.

[0040] In some embodiments, the first gate preparation process and the second gate preparation process have at least different preparation steps, which may include different numbers of preparation steps. In one embodiment, the first gate preparation process may have additional steps compared to the second gate preparation process, thereby realizing more material layers in the first gate structure and improving the heat resistance of the first gate structure.

[0041] In some embodiments, in addition to the different preparation steps, the first gate preparation process and the second gate preparation process may also differ in the execution order of the preparation steps (ie, preparation flow) and / or the materials used to execute the preparation steps (ie, structural materials).

[0042] It is understandable that different execution orders of the preparation steps or different materials used in the execution steps can result in different gate structures, thereby obtaining gate structures with different heat resistances. In the embodiment of the present application, the heat resistance of the first gate structure is controlled to be relatively large, and after the semiconductor substrate is flipped, a higher temperature can be used to prepare the reverse transistor. On the one hand, the thermal budget of the reverse transistor can be increased, and the flexibility of the reverse transistor can be improved. On the other hand, the failure rate of the front transistor can be reduced, and the success rate of preparing the stacked transistor can be ensured.

[0043] It should be noted that the first direction in the embodiment of the present application may be a direction perpendicular to the semiconductor substrate, and may also be understood as the height direction of the fin structure. The second direction may be perpendicular to the first direction. The second direction may be understood as the length direction of the fin structure. The second direction may be, for example, the length direction of the gate structure. The third direction may be perpendicular to the first direction and the second direction. The third direction may be understood as the extension direction of the fin structure. The third direction may be, for example, the width direction of the gate structure.

[0044] The following will be combined Figure 1 The preparation method is exemplarily described.

[0045] In step S101 , a fin structure is formed by etching a semiconductor substrate.

[0046] The fin structure includes a first portion and a second portion stacked along a first direction, wherein the first portion is further away from the semiconductor substrate than the second portion. The first portion of the fin structure can be used to form an active region of a front transistor (i.e., a first transistor) in a stacked transistor; and the second portion stacked with the first portion along the first direction is used to form an active region of a back transistor (i.e., a second transistor) in the stacked transistor.

[0047] In some embodiments, step S101 may include: performing material layer deposition, epitaxial growth, photolithography and other processes on a semiconductor substrate to form a fin structure on the semiconductor substrate at one time. The fin structure includes a first portion and a second portion, wherein the second portion is closer to the semiconductor substrate than the first portion.

[0048] In some embodiments, a fin field effect transistor may be formed according to the fin structure.

[0049] In some embodiments, when a fin-shaped structure (including a first portion and a second portion) is formed by etching once, a larger etching depth may be used. For example, the height of the fin-shaped structure obtained by etching may be greater than 100 nm. It should be noted that the height of the fin-shaped structure may be set according to actual conditions, and the embodiments of the present application do not limit this.

[0050] In some embodiments, the etching process mentioned in the embodiments of the present application may include any of the following: dry etching, wet etching, reactive ion etching and chemical oxide removal process, which is not limited in the embodiments of the present application. In one embodiment, etching to form a fin structure may adopt a photolithography process. In one embodiment, the steps of the photolithography process may include: depositing a photoresist material, exposing and developing the photoresist material, removing a portion of the photoresist material, etching to remove a material layer corresponding to a portion of the photoresist material, etc.

[0051] In some embodiments, the first transistor and the second transistor are both fin field effect transistors.

[0052] In some embodiments, step S101 may include: forming a first material layer and a second material layer stacked along a first direction on a semiconductor substrate, and then etching the first material layer and the second material layer sequentially from top to bottom to obtain a first portion and a second portion, respectively. Here, the etched first material layer may form the first portion; and the etched second material layer may form the second portion.

[0053] In some embodiments, step S101 may include: electrically isolating the first portion and the second portion. It is understandable that the electrically isolating the first portion and the second portion may be achieved by forming an isolation layer, forming an insulating layer, ion implantation, etc. This embodiment of the application does not limit this.

[0054] In some embodiments, step S101 may include: providing a wafer; etching the wafer to a preset depth to form an initial fin structure; using a fin cutting process to remove the initial fin structure in the region located on both sides of the stacked transistor in the third direction to form a fin structure. Ion implantation is performed in the middle of the fin structure to electrically isolate the first part and the second part. Here, the region located on both sides of the stacked transistor in the third direction refers to the region located on both sides of the stacked transistor in the cross-sectional view in the CC' direction.

[0055] It is understandable that the initial fin structure located in the two side regions of the stacked transistor can be removed by the fin cutting process, so that the fin structures of multiple standard transistor units are disconnected from each other, completing the isolation between adjacent transistor units. Exemplarily, the ions implanted include P-type ions, N-type ions or oxygen ions. Among them, P-type ions include one or more of boron ions, gallium ions and indium ions; N-type ions include one or more of phosphorus ions, arsenic ions and antimony ions.

[0056] In some embodiments, step S101 may include: forming a first material layer, a third material layer, and a second material layer stacked along a first direction on a semiconductor substrate, and then etching the first material layer, the third material layer, and the second material layer in sequence from top to bottom to obtain a first portion, a third portion, and a second portion, respectively. The third portion is located between the first portion and the second portion. The etched first material layer may form a first portion; the etched second material layer may form a second portion; and the etched third material layer may form a third portion.

[0057] In one embodiment, the third portion is used to electrically isolate the first portion from the second portion. In one embodiment, the third portion may be formed of an oxide material. In one embodiment, the third portion may be formed of a dielectric material.

[0058] In some embodiments, the material of the material layers forming the first portion, the second portion and the third portion can be selected according to actual needs. In one embodiment, when the first transistor is a P-type field effect transistor, the material forming the first portion can be silicon germanium material.

[0059] In some embodiments, after the fin structure is obtained, an insulating material may be deposited on the semiconductor substrate to obtain a shallow trench isolation structure. Here, the shallow trench isolation structure may wrap the second portion, and the first portion may be exposed outside the shallow trench isolation structure.

[0060] The oxide used to form the shallow trench isolation structure 24 may be silicon-based oxide (SiOx, where x is the number of oxygen atoms), such as silicon dioxide (SiO2).

[0061] In step S102 , a first transistor of a stacked transistor is formed based on the first portion.

[0062] It is understandable that, based on the exposed first portion, a semiconductor manufacturing process can be used to form a first transistor in the stacked transistor. The first transistor includes: a first pseudo-gate sidewall, a first source-drain structure, a first interlayer dielectric layer, a first gate structure, and a first source-drain metal. The first gate structure can be formed using a first gate manufacturing process.

[0063] In some embodiments, step S102 may include: depositing a first gate dielectric material in the gate region of the stacked transistor to form a first gate dielectric layer covering the first part; depositing a metal oxide material on the first gate dielectric layer to form a covering layer; depositing a first gate material on the covering layer to form a first gate electrode layer, wherein the first gate dielectric layer, the covering layer and the first gate electrode layer together constitute a first gate structure; the preparation step of forming the first gate structure is included in the first gate preparation process; and forming a first source-drain structure in the source-drain region of the stacked transistor based on the first part.

[0064] It is understandable that the first gate preparation process may include the steps of forming a first gate dielectric layer, forming a capping layer, and forming a first gate electrode layer. Through the above steps, a first gate structure with greater heat resistance can be obtained. It is understandable that the first gate structure can be directly formed in the first gate preparation process without forming a dummy gate structure, and then the dummy gate structure can be replaced by a metal gate, which can reduce the process complexity.

[0065] It can be understood that the capping layer is located between the first gate dielectric layer and the first gate electrode layer, and the capping layer can solve the Fermi level pinning phenomenon and adjust the threshold voltage of the transistor.

[0066] In some embodiments, the metal oxide material forming the covering layer can be selected according to actual needs, such as hafnium oxide, aluminum oxide, titanium oxide, etc., which is not limited in the embodiments of the present application. In one embodiment, when the first transistor is an N-type field effect transistor, the metal oxide forming the covering layer may be lanthanum oxide. The lanthanum oxide material contains more negatively charged atoms, thereby reducing the threshold voltage (Vt) of the N-type field effect transistor. In one embodiment, when the first transistor is a P-type field effect transistor, the metal oxide forming the covering layer may be aluminum oxide. The aluminum oxide material contains more positively charged atoms, thereby reducing the threshold voltage (Vt) of the P-type field effect transistor.

[0067] In some embodiments, the first gate dielectric material may be a high dielectric constant (K) material. In some embodiments, the first gate material may be polysilicon or a metal material. Here, for an N-type field effect transistor, the metal material may be tantalum nitride, tantalum, etc.; for a P-type field effect transistor, the metal material may be titanium nitride, tungsten, cobalt, etc.

[0068] In some embodiments, step 102 may include: forming a first gate isolation structure in the gate isolation region. It is understandable that after forming the first gate structure, a gate removal process may be used to remove the first gate structures located on both sides of the stacked transistor in the second direction, and an insulating material may be deposited at the position where the first gate structure is removed to form a first gate isolation structure. The first gate isolation structure is used to electrically isolate the gate structures of two adjacent first transistors.

[0069] In some embodiments, step S104 may include: based on the exposed first portion; forming a first gate dielectric layer across the first portion, and sequentially depositing a capping layer and a first gate electrode layer on the first gate dielectric layer to form a first gate structure. After forming the first gate structure, a spacer material may also be deposited to form a first spacer. Here, the spacer material may be silicon oxide, silicon nitride, or the like. The first spacer is used to protect the covered structure.

[0070] In some embodiments, after forming the first gate structure, a standard semiconductor manufacturing process can be used to form a first source-drain structure. Then, step S102 may include: forming a first source-drain structure of a first transistor based on the first part. In some embodiments, a first part in the source-drain region of the stacked transistor can be etched to form a first source-drain groove; and a first source-drain structure is epitaxially grown in the first source-drain groove. After forming the first source-drain structure, an insulating material can be deposited on the first source-drain structure to form a first interlayer dielectric layer. In one embodiment, a first source-drain groove can be formed on the first part using a fin structure deep etching process. In one embodiment, a strained material such as silicon germanium or silicon carbide can be formed in the first source-drain groove by selective epitaxial growth to fill the first source-drain groove, and then a first source-drain structure is formed on the above-mentioned strained material by a heavy doping process.

[0071] In some embodiments, after forming the first gate structure, the first interlayer dielectric layer may be etched to expose the first source-drain structure, and a metal material may be deposited on the first source-drain structure to form a first source-drain metal.

[0072] In one embodiment, after forming the first gate structure and the first source-drain metal, a first metal interconnection layer can be formed on the first gate structure and the first source-drain metal using a standard back-end process for semiconductor manufacturing (such as deposition of dielectric between interconnect lines, formation of metal lines, formation of lead pads, etc.).

[0073] In one embodiment, the metal wires in the first metal interconnect layer may be made of high temperature resistant metal materials such as ruthenium (Ru) or tungsten (W), thereby improving the tolerance of the first transistor to high temperatures.

[0074] It should be noted that, for ease of explanation, the first source-drain structure mentioned in the embodiments of the present application is an abbreviation, specifically referring to the first source electrode structure and / or the first drain electrode structure. In addition, the second source-drain structure, the first source-drain metal, the second source-drain metal, etc. are similar to the first source-drain groove, where "source-drain" is an abbreviation for "source electrode and / or drain electrode".

[0075] In step S103, the semiconductor substrate is flipped and removed.

[0076] It is understandable that after obtaining the first transistor, the first transistor can be flipped so that the completed first transistor is located at the bottom and the second part for preparing the second transistor can be located at the top, which is convenient for subsequent preparation of the second transistor.

[0077] In some embodiments, after the back-end process of the first transistor is completed, the first transistor may be bonded to the carrier wafer. For example, an insulating material (such as silicon oxide) may be deposited on the first metal interconnect layer to form an insulating layer, and the insulating layer may be bonded to the carrier wafer and flipped so that the first transistor is located at the lower layer of the stacked transistor after flipping.

[0078] In the disclosed embodiment, the bonded carrier wafer can provide physical support for the flipped first transistor after inversion, thereby effectively preventing the first transistor from being broken by external force during the preparation of the second transistor.

[0079] In one embodiment, after flipping, the semiconductor substrate may be removed by polishing or chemical mechanical planarization to expose the second portion.

[0080] In step S104 , a second transistor of the stacked transistor is formed based on the second portion.

[0081] It is understandable that after the first transistor is prepared, a second transistor in the stacked transistor can be formed based on the exposed second portion using a semiconductor preparation process. The second transistor includes: a second pseudo-gate sidewall, a second source-drain structure, a second interlayer dielectric layer, a second gate structure, and a second source-drain metal. The second gate structure can be formed using a second gate preparation process. The second gate preparation process is different from the first gate preparation process.

[0082] In some embodiments, step S104 may include: depositing a dummy gate material in the gate region of the stacked transistor to form a dummy gate structure; forming a second source-drain structure in the source-drain region of the stacked transistor based on the second part; removing the dummy gate structure, and depositing a second gate dielectric material at the position where the dummy gate structure is removed to form a second gate dielectric layer; depositing a second gate material on the second gate dielectric layer to form a second gate electrode layer; wherein the second gate dielectric layer and the second gate electrode layer together constitute a second gate structure; and the preparation step of forming the second gate structure is included in the second gate preparation process.

[0083] It is understandable that the second gate preparation process may include the steps of forming a dummy gate structure, removing the dummy gate structure, forming a second gate dielectric layer, and forming a second gate electrode layer. Through the above steps, a second gate structure can be obtained. The heat resistance of the second gate structure is lower than that of the first gate structure, but the second gate structure has the characteristics of reducing power consumption and leakage, improving carrier mobility, etc. that are superior to the first gate structure. It is understandable that to prepare the second gate structure by the second gate preparation process, it is necessary to first form a dummy gate structure and then form the second gate structure.

[0084] In some embodiments, the second gate dielectric material may be a high dielectric constant (K) material. In some embodiments, the material forming the second gate dielectric layer may be the same as or different from the material forming the first gate dielectric layer. In some embodiments, the second gate material may be a metal oxide material. In one example, the second gate dielectric layer may be composed of a silicon oxide layer plus a hafnium oxide layer with a high K value, and the thickness of the silicon oxide layer and the hafnium oxide layer may be determined according to the polarity and performance of the second transistor. The second gate electrode layer may be composed of a multilayer electrode material, and the electrode material of each layer includes but is not limited to hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide). In one example, the second gate dielectric layer may include: a 0.6nm silicon oxide layer and a 1.7nm hafnium oxide layer.

[0085] In some embodiments, step S104 may include: thinning the shallow trench isolation structure to expose the second portion wrapped by the shallow trench isolation structure; forming a dummy gate structure across the second portion and a second dummy gate sidewall covering the sidewall of the dummy gate structure; after preparing and forming the first source and drain structure, removing the dummy gate structure by a gate replacement process, and depositing a second gate structure at the position where the dummy gate structure is removed. Here, the second dummy gate sidewall may be formed based on the sidewall material.

[0086] In some embodiments, step 104 may include: forming a second gate isolation structure in the gate isolation region. It is understandable that after forming the second gate structure, a gate removal process may be used to remove the second gate structures located on both sides of the stacked transistor in the second direction, and an insulating material may be deposited at the position where the second gate structure is removed to form a second gate isolation structure. The first gate isolation structure and the second gate isolation structure are stacked along the first direction. The second gate isolation structure is used to electrically isolate the gate structures of two adjacent second transistors.

[0087] In some embodiments, when the first gate isolation structure is not formed in the stacked transistor, step 104 may include: forming a third gate isolation structure in the gate isolation region. It is understandable that after forming the second gate structure, a gate removal process may be used to remove the second gate structure and the first gate structure located on both sides of the stacked transistor in the second direction, and an insulating material may be deposited at the position where the second gate structure and the first gate structure are removed to form a third gate isolation structure. The third gate isolation structure is used to electrically isolate the gate structures of two adjacent stacked transistors.

[0088] In some embodiments, when the fin structure further includes a third portion located between the first portion and the second portion, before forming the dummy gate structure, step S104 may include: removing the third portion, and depositing an insulating material at the position where the third portion is removed to form an isolation layer. It can be understood that the isolation layer is used to electrically isolate the first portion from the second portion.

[0089] In some embodiments, after forming the second gate structure, a standard semiconductor manufacturing process can be used to form a second source-drain structure. Then, step S104 may include: forming a second source-drain structure of the second transistor based on the second part. In some embodiments, the second part in the source-drain region of the stacked transistor can be etched to form a second source-drain groove; and the second source-drain structure is epitaxially grown in the second source-drain groove. After forming the second source-drain structure, an insulating material can be deposited on the second source-drain structure to form a second interlayer dielectric layer. In one embodiment, a second source-drain groove can be formed on the second part using a fin structure deep etching process. In one embodiment, a strained material such as silicon germanium or silicon carbide can be formed in the second source-drain groove by selective epitaxial growth to fill the second source-drain groove, and then a second source-drain structure is formed on the above-mentioned strained material by a heavy doping process.

[0090] In some embodiments, after forming the second gate structure, the second interlayer dielectric layer may be etched to expose the second source-drain structure, and a metal material may be deposited on the second source-drain structure to form a second source-drain metal.

[0091] In one embodiment, after forming the second gate structure and the second source-drain metal, a second metal interconnection layer can be formed on the second gate structure and the second source-drain metal using standard semiconductor manufacturing back-end processes (such as interconnect line dielectric deposition, metal line formation, lead pad formation, etc.).

[0092] In some embodiments, when the first transistor is an N-type field effect transistor, the first metal interconnection layer may not be prepared in step S102, so that after step S104, the following steps are further included: flipping the second transistor; and forming a first metal interconnection layer on the first source-drain structure and the first gate structure.

[0093] It is understandable that when the first transistor is an N-type field effect transistor and the second transistor is a P-type field effect transistor, considering the stress effect in the stacked transistor, the first transistor can be placed in the upper layer and the second transistor can be placed in the lower layer, thereby improving the performance of the stacked transistor during use. Accordingly, in some embodiments, the first transistor is an N-type field effect transistor, a first metal interconnect layer is prepared in step S102, the second transistor is a P-type field effect transistor, and a second metal interconnect layer is prepared in step S104. At this time, the first transistor and the second transistor can also be flipped so that the first transistor is located in the upper layer and the second transistor is located in the lower layer.

[0094] In some embodiments, when the first transistor is an N-type field effect transistor, a first metal interconnection layer can be prepared in step S102, and a second metal interconnection layer can be prepared in step S104, thereby after step S104 also including: bonding the second transistor to the carrier wafer; and flipping the bonded second transistor.

[0095] It can be understood that in order to improve the performance of the stacked transistor during use, the N-type field effect transistor can be placed on the upper layer of the stacked transistor and the second transistor can be placed on the lower layer of the stacked transistor by bonding the carrier wafer and flipping the wafer.

[0096] At this point, the preparation process of the first type of stacked transistor is completed.

[0097] In the disclosed embodiment, by etching a fin structure on a semiconductor substrate once, and preparing a first transistor and a second transistor on the front and back sides of the semiconductor substrate based on the first part and the second part of the fin structure, respectively, it is possible to achieve self-alignment of the active structures of the upper and lower layers of transistors in the stacked transistor. At the same time, the first gate structure of the first transistor is prepared by the first preparation process, and the second gate structure of the second transistor is prepared by the second preparation process, so that the heat resistance of the first gate structure is greater than the heat resistance of the second gate structure. In this way, on the one hand, the thermal budget of the reverse transistor can be improved, and the flexibility of the reverse transistor can be enhanced. On the other hand, the failure rate of the front transistor can be reduced, and the success rate of preparing the stacked transistor can be ensured.

[0098] Below, a specific example is used to introduce the method for preparing the stacked transistor in the embodiment of the present application.

[0099] Figure 2 FIG. 1 is a top view of a first stacked transistor according to an embodiment of the present application. Figure 2 As shown, the top view only shows the fin structure, gate structure and source-drain structure of the stacked transistor. Figures 3 to 34 FIG. 1 is a schematic diagram of a preparation process of a first stacked transistor according to an embodiment of the present application. For ease of understanding, Figures 3 to 34 (a) shows the Figure 2 The cross-sectional view along the dashed line AA'. Figures 3 to 34 (b) shows the Figure 2 The cross-sectional view along the dotted line BB', Figures 3 to 34 (c) shows the Figure 2 Cross-sectional view along the dashed line CC'.

[0100] In this embodiment, it is assumed that the first transistor is a P-type field effect transistor and the second transistor is an N-type field effect transistor. Figures 1 to 34A possible implementation of the stacked transistor provided in this embodiment is described.

[0101] First step, see Figure 3 As shown, a third material layer 21 and a first material layer 22 are epitaxially formed on a semiconductor substrate 20 (formed of silicon material). The first material layer 22 is formed of silicon germanium material, and the third material layer 21 is formed of silicon germanium material. The percentage of germanium atoms in the silicon germanium in the first material layer 22 and the silicon germanium in the third material layer 21 is different. The first material layer 22 can be prepared to form a channel (PFET channel) of the first transistor 11, and the third material layer 21 can be prepared to form an isolation layer between the first transistor 11 and the second transistor 12. At the same time, a portion of the semiconductor substrate 20 close to the third material layer 21 can be understood as a second material layer 23, and the second material layer 23 can be prepared to form a channel (NFET channel) of the second transistor 12.

[0102] Step 2, see Figure 4 As shown, the first material layer 22, the third material layer 21 and the second material layer 23 are sequentially etched to form an initial fin structure. The initial fin structure located on both sides of the semiconductor substrate 20 in the third direction is removed to obtain a fin structure.

[0103] It can be understood that the positions located on both sides of the semiconductor substrate 20 in the third direction refer to the positions located on both sides in the CC' direction. The fin structure includes a first portion 24, a second portion 25 and a third portion 26, and the third portion 26 is located between the first portion 24 and the second portion 25. The first portion 24 is formed by the first material layer 22, the second portion 25 is formed by the second material layer 23, and the third portion 26 is formed by the third material layer 21.

[0104] Step 3, see Figure 5 As shown, an insulating material is deposited on the semiconductor substrate 20 to form a shallow trench isolation structure 27 covering the fin structure, and a chemical-mechanical planarization (CMP) process is performed on the shallow trench isolation structure 27 to ensure that the shallow trench isolation structure 27 in any region has the same height. It can be understood that the height of the shallow trench isolation structure 27 after the chemical-mechanical planarization process in the first direction is slightly higher than the fin structure.

[0105] Step 4, see Figure 6 As shown, the shallow trench isolation structure 27 is etched by an etching process until the first portion of the fin structure is exposed. Here, the etched shallow trench isolation structure 27 can expose the first portion 24 and wrap the third portion 26 and the second portion 25.

[0106] Step 5, see Figure 7As shown, an isotropic deposition process is used to deposit an oxide material on the shallow trench isolation structure 27 to form a front oxide layer 28. Here, the front oxide layer 28 is used to protect the fin structure and improve the reliability and performance of the device. It can be understood that the front oxide layer 28 can cover the upper surface of the shallow trench isolation structure 27, the upper surface of the fin structure, and the sidewalls of the fin structure.

[0107] Step 6, see Figure 8 As shown, an isotropic deposition process is used to deposit a first gate dielectric material on the front oxide layer 28 to form a first gate dielectric layer 29. It can be understood that when the first transistor 11 is a P-type field effect transistor, the first gate dielectric material can be hafnium dioxide, zirconium dioxide, silicon nitride, lanthanum trioxide, titanium nitride and the like.

[0108] Step 7, see Fig. 9 As shown, an isotropic deposition process is used to deposit a metal oxide material on the first gate dielectric layer 29 to form a capping layer 30 of the P-type field effect transistor. Here, the metal oxide material may be aluminum oxide.

[0109] Step 8, see Fig.10 As shown, an isotropic deposition process is used to deposit a first gate material on the cover layer 30 to form a first gate electrode layer 31, and a chemical mechanical planarization process is performed on the first gate electrode layer 31. It can be understood that when the first transistor 11 is a P-type field effect transistor, the first gate material can be polysilicon, titanium nitride, tantalum nitride and the like.

[0110] Step 9, see Fig.11 As shown, the first gate dielectric layer 29, the capping layer 30 and the first gate electrode layer 31 in the front source and drain region are removed by photolithography to form a first gate structure 114 in the front gate region. Here, the first gate dielectric layer 29, the capping layer 30 and the first gate electrode layer 31 after photolithography together constitute the first gate structure 114. The height of the first gate structure 114 in the first direction is greater than the height of the fin structure in the first direction. Fig.11 In the CC' cross-sectional view, the first gate structures 114 are arranged at intervals along the third direction.

[0111] Step 10, see Fig.12 As shown, an isotropic deposition process is used to deposit a spacer material (such as silicon nitride) in the gate region and the source / drain region of the front transistor to form an initial dummy gate spacer that completely covers the first gate structure 114 and the first portion 24, and then an anisotropic etching process is used to etch the initial dummy gate spacer to form a first spacer 111. Here, the first spacer 111 can cover the sidewalls of the first gate structure 114 and the sidewalls of the first portion 24.

[0112] Step 11, see Fig.13 As shown, a portion of the first portion 24 of the partial fin-shaped structure and the first spacer 111 corresponding to the portion are removed by a fin-shaped structure deep etching process to form a first source-drain groove 32 .

[0113] Step 12, see Fig.14 As shown, when the first transistor 11 is a P-type field effect transistor, a germanium silicon epitaxial layer can be formed by epitaxial growth in the first source-drain groove 32, and then a first source-drain structure 112 is formed based on the germanium silicon epitaxial layer through a heavy doping process.

[0114] Step 13, see Fig.15 As shown, after forming the first source-drain structure 112, an insulating material is deposited on the first source-drain structure 112 to form a first interlayer dielectric layer 113, and the first interlayer dielectric layer 113 is processed by a chemical mechanical planarization process to make the height of the first transistor 11 uniform. Here, the insulating material can be silicon nitride, silicon oxide, and the like.

[0115] Step 14, see Fig.16 As shown, the first interlayer dielectric layer 113 is etched to expose the first source-drain structure 112 , and a metal material is deposited on the first source-drain structure 112 to form a first source-drain metal 115 .

[0116] Step 15, see Fig.17 As shown, a first metal interconnection layer 116 is formed on the first gate structure 114 and the first source-drain metal 115 by using a standard back-end process of semiconductor manufacturing (such as dielectric deposition between interconnection lines, formation of metal lines, formation of lead pads, etc.). In one embodiment, the metal lines in the first metal interconnection layer 116 can be made of high-temperature resistant metal materials such as ruthenium (Ru) or tungsten (W), thereby improving the tolerance of the first transistor to high temperatures.

[0117] Step 16, see Fig.18 As shown, the semiconductor substrate 20 is flipped so that the first transistor 11 is located at the lower layer. An insulating material is deposited on top of the first metal interconnect layer 116 to form an insulating layer 33, and the insulating layer 33 is bonded to the carrier wafer 34. The bonded first transistor 11 is flipped so that the first transistor 11 is located at the lower layer.

[0118] Step 17, see Fig.19 As shown, an etching process is adopted to remove the semiconductor substrate 20 until the shallow trench isolation structure 27 is exposed, and at the same time, the upper surface of the second portion 25 may also be exposed.

[0119] Step 18, see Fig. 20As shown, the shallow trench isolation structure 27 is thinned by an etching process so that the second portion 25 is exposed outside the thinned shallow trench isolation structure 27. The thinned shallow trench isolation structure 27 can wrap the third portion 26. The thinned shallow trench isolation structure 27 has a certain thickness in the first direction and can be used to electrically isolate the first transistor 11 from the second transistor 12.

[0120] Step 19, see Fig.21 As shown, an isotropic deposition process is used to deposit an oxide material on the shallow trench isolation structure 27 to form a reverse oxide layer 35. The function of the reverse oxide layer 35 can refer to the front oxide layer 28, which will not be repeated here. The oxide material forming the front oxide layer 28 can be the same as or different from the oxide material forming the reverse oxide layer 35.

[0121] Step 20, see Fig. 22 As shown, an isotropic deposition process is adopted to deposit a dummy gate material (polysilicon) on the reverse oxide layer 35 to form an initial dummy gate structure 36 , and the initial dummy gate structure 36 is subjected to a chemical mechanical planarization process.

[0122] Step 21, see Fig.23 As shown, the initial dummy gate structure 36 in the reverse source and drain region is removed by photolithography to form a dummy gate structure 37 in the reverse gate region. The height of the dummy gate structure 37 in the first direction is greater than the height of the fin structure in the first direction. Fig.11 In the CC' cross-sectional view in FIG. 3 , the dummy gate structures 37 are arranged at intervals along the third direction. In one embodiment, a portion of the dummy gate structure 37 can be removed by using a fin cutting process, and the portion is located at the edge portion in the third direction.

[0123] Step 22, see Fig.24 As shown, an etching process is used to remove the reverse oxide layer 35 and the shallow trench isolation structure 27 in the reverse source and drain region. Here, after the shallow trench isolation structure 27 is removed, the third portion 26 can be exposed.

[0124] Step 23, see Fig.25 As shown, an isotropic etching process is used to remove the third portion 26 located between the first portion 24 and the second portion 25 in the reverse source / drain region and the gate region. Fig.25 In the AA' cross-sectional view, the third portion 26 between the dummy gate structure and the first gate structure 114 is removed; in the BB' cross-sectional view, the third portion 26 above the first source-drain structure 112 is removed; in the CC' cross-sectional view, the third portion 26 between the first portion 24 and the second portion 25 is removed.

[0125] Step 24, see Fig.26As shown, an isotropic deposition process is used to deposit the spacer material to simultaneously form the second dummy gate spacer 121 of the second dummy gate structure 37, the second spacer 38 of the second portion 25, and the isolation layer 39 between the first portion 24 and the second portion 25. Here, the isolation layer 39 is used to electrically isolate the first portion 24 from the second portion 25. The spacer material can be an insulating material. The second dummy gate spacer 121 covers the sidewall of the dummy gate structure 37. The second spacer 38 covers the sidewall of the second portion 25.

[0126] Step 25, see Fig. 27 As shown, an insulating material is deposited in the reverse source and drain region and etched back to form a source-drain isolation structure 40 between the first transistor 11 and the second transistor 12. Here, the source-drain isolation structure 40 is used to electrically isolate the first transistor 11 from the second transistor 12.

[0127] Step 26, see Fig.28 As shown, a portion of the second portion 25 of the partial fin-shaped structure and the second sidewall 38 corresponding to the portion are removed by a fin-shaped structure deep etching process to form a second source-drain groove 41 .

[0128] Step 27, see Fig.29 As shown, when the second transistor 12 is an N-type field effect transistor, a strained material such as silicon germanium or silicon carbide can be formed in the second source and drain grooves 41 by selective epitaxial growth to fill the second source and drain grooves 41, and then a second source and drain structure 122 is formed on the above-mentioned strained material by a heavy doping process.

[0129] Step 28, see Fig.30 As shown, after forming the second source-drain structure 122 , an insulating material is deposited on the second source-drain structure 122 to form a second interlayer dielectric layer 123 , and the second interlayer dielectric layer 123 is processed by a chemical mechanical planarization process to make the height of the second transistor 12 uniform.

[0130] Step 29, see Fig.31 As shown, the dummy gate structure 37 is removed by an etching process, and a second gate dielectric material is deposited at the position where the dummy gate structure 37 is removed to form a second gate dielectric layer 42; a second gate material is deposited on the second gate dielectric layer 42 to form a second gate electrode layer 43. The second gate dielectric layer 42 and the second gate electrode layer 43 together constitute a second gate structure 124. Here, the second gate dielectric layer 42 can cover the upper surface of the second portion 25, the upper surface of the shallow trench isolation structure 27, the sidewall of the second portion 25, and the sidewall of the second dummy gate spacer 121. The second gate dielectric layer 42 can completely isolate the second gate electrode layer 43 from other structures.

[0131] Step 30, see Fig.32As shown, a gate removal process is used to remove the second gate structure 124, the first gate structure 114, and the structure between the second gate structure 124 and the first gate structure 114 on both sides of the stacked transistor in the second direction to form a gate isolation trench, and an insulating material is deposited in the gate isolation trench to form a gate isolation structure 44.

[0132] Step 31, see Fig.33 As shown, the second interlayer dielectric layer 123 is etched to expose the second source-drain structure 122 , and a metal material is deposited on the second source-drain structure 122 to form a second source-drain metal 125 .

[0133] Step 32, see Fig.34 As shown, a second metal interconnection layer 126 is formed on the second gate structure 124 and the second source-drain metal 125 by using standard back-end semiconductor manufacturing processes (such as dielectric deposition between interconnects, metal line formation, lead pad formation, etc.).

[0134] In an embodiment of the present application, the first transistor is a P-type field effect transistor. The first transistor can use a silicon germanium channel to increase the carrier mobility in the P-type fin field effect transistor, reduce the threshold voltage, and improve the electrical performance of the P-type fin field effect transistor. At the same time, the first transistor has a high temperature resistant first gate structure 114, which helps to ensure that the first transistor is not damaged during the preparation of the second transistor.

[0135] Figure 35 to Figure 37 FIG. 1 is a schematic diagram of a preparation process of a second stacked transistor according to an embodiment of the present application. For ease of understanding, Figure 35 to Figure 37 (a) shows the Figure 2 The cross-sectional view along the dashed line AA'. Figure 35 to Figure 37 (b) shows the Figure 2 The cross-sectional view along the dotted line BB', Figure 35 to Figure 37 (c) shows the Figure 2 Cross-sectional view along the dashed line CC'.

[0136] In this embodiment, it is assumed that the first transistor is an N-type field effect transistor and the second transistor is a P-type field effect transistor. Figure 1 to Figure 2 , Figure 35 to Figure 37 A possible implementation of the stacked transistor provided in this embodiment is described.

[0137] First step, see Fig.35As shown, a third material layer 21 and a first material layer 22 are epitaxially formed on a semiconductor substrate 20 (formed of silicon material). Among them, the first material layer 22 is formed of silicon material, and the third material layer 21 is formed of silicon germanium material. The first material layer 22 can be prepared to form a channel (NFET channel) of the first transistor 11, and the third material layer 21 can be prepared to form an isolation layer between the first transistor 11 and the second transistor 12. At the same time, a portion of the semiconductor substrate 20 close to the third material layer 21 can be understood as a second material layer 23, and the second material layer 23 can be prepared to form a channel (PFET channel) of the second transistor 12.

[0138] For steps 2 to 32, see Fig.36 As shown, the stacked transistor 10 is obtained by adopting the same preparation process from the second step to the thirty-second step in the embodiment corresponding to the first transistor 11 being a P-type field effect transistor and the second transistor being an N-type field effect transistor.

[0139] It should be noted that the first transistor is an N-type field effect transistor, the second transistor is a P-type field effect transistor, and the channels of the first transistor and the second transistor are both made of silicon material. The covering layer 30 corresponding to the first transistor is the covering layer 30 of the N-type field effect transistor, and here, the metal oxide material forming the covering layer 30 of the N-type field effect transistor can be lanthanum oxide. The covering layer 30 formed by lanthanum oxide can reduce the threshold voltage of the NFET.

[0140] Step 33, see Fig.37 As shown, an insulating material is deposited on the top of the first metal interconnect layer 116 to form an insulating layer 33, and the insulating layer 33 is bonded to the carrier wafer 34. The bonded second transistor 12 is flipped over so that the second transistor 12 is located at the lower layer.

[0141] In an embodiment of the present application, the first transistor is an N-type field effect transistor, and the capping layer in the first transistor can be prepared by lanthanum oxide material, which can increase negatively charged atoms, thereby effectively reducing the threshold voltage of the NFET. At the same time, the first transistor has a high temperature resistant first gate structure 114, which helps to ensure that the first transistor is not damaged during the preparation of the second transistor. Finally, after the second transistor is prepared, the first transistor, which is an N-type field effect transistor, is flipped to the upper layer of the stacked transistor, thereby helping to improve the performance of the stacked transistor.

[0142] In a second aspect, a stacked transistor is provided in an embodiment of the present disclosure. The stacked transistor can be used Figures 1 to 34 The method of one or more corresponding embodiments is prepared. Fig.34 As shown, the stacked transistor includes:

[0143] A first transistor 11; a second transistor 12, the first transistor and the second transistor 12 are stacked along a first direction, and a first active region of the first transistor 11 is self-aligned with a second active region of the second transistor 12; the first transistor 11 includes a first gate structure 114, the second transistor 12 includes a second gate structure 124, and the first gate structure 114 and the second gate structure 124 are arranged opposite to each other;

[0144] The first gate structure 114 is formed by a first gate preparation process; the second gate structure 124 is formed by a second gate preparation process; the second gate preparation process and the first gate preparation process are at least different in preparation steps; the heat resistance of the first gate structure 114 is greater than the heat resistance of the second gate structure 124.

[0145] It can be understood that the preparation process of the first transistor 11 and the second transistor 12 can refer to the description in one or more of the above embodiments, and for the sake of brevity of the description, it will not be repeated here.

[0146] It can be understood that the first transistor 11 and the second transistor 12 are self-aligned, and the self-aligned arrangement may refer to that the first channel in the first transistor 11 and the second channel in the second transistor 12 are aligned vertically, the first source-drain structure 112 in the first transistor 11 and the second source-drain structure 122 in the second transistor 12 are aligned vertically, and the first gate structure 114 in the first transistor 11 and the second gate structure 124 in the second transistor 12 are aligned vertically. Here, the first channel, the first source-drain structure 112, and the first gate structure 114 are all prepared and formed based on the first portion 24 of the fin structure.

[0147] In this embodiment, the preparation processes of the first gate structure 114 and the second gate structure 124 may be different, so that the heat resistance of the first gate structure 114 is greater than that of the second gate structure. In this way, the tolerance of the first gate structure 114 to a large number of high-temperature processes in subsequent processes is improved, and the failure rate of the front device is reduced.

[0148] In some embodiments, when the first transistor 11 is a P-type field effect transistor, the first active region of the first transistor 11 is formed of a silicon germanium material. It is understandable that when the first transistor 11 is a P-type field effect transistor, the first portion 24 of the fin structure can be formed of a silicon germanium material, so that the first active region of the first transistor 11 is formed of a silicon germanium material. For a P-type field effect transistor, the channel formed by using a silicon germanium material can reduce the threshold voltage of the P-type field effect transistor and further improve the electrical performance of the upper and lower layers of the stacked transistor.

[0149] It can be understood that in the embodiment of the present application, a stacked transistor implementation scheme with high thermal budget tolerance is achieved by using a first gate preparation process for the first transistor 11 and a second gate preparation process for the second transistor 12.

[0150] In some embodiments, the stacked transistors can be inspected by means of transmission electron microscope (TEM) slices, and the following can be obtained: Fig.34 The structure shown. Fig.34 It can be seen that the morphology of the gate dielectric layer inside the gate structure in the front and back transistors (i.e., the first transistor 11 and the second transistor 12) is different: the first gate structure 114 in the first transistor 11 is prepared before the first source and drain structure 112, and the corresponding gate dielectric layer only exists at the bottom of the gate electrode layer material; the second gate structure 124 in the second transistor 12 is prepared after the second source and drain structure 122, and the corresponding gate dielectric layer wraps the side wall and bottom of the gate electrode layer, thereby improving the overall performance of the stacked transistors and the overall circuit energy efficiency.

[0151] It should be noted that stacked transistors are self-aligned, which, on the one hand, solves the long-standing problems of complex processes and difficult alignment in the existing mainstream technical solutions for stacked transistors, and promotes the industrialization of transistor stacking technology. On the other hand, through the self-aligned "back-to-back" fin structure and gate structure, the upper and lower transistors can have independent signal and power supply networks, and are interconnected through stacked transistors, which greatly releases metal wiring resources.

[0152] Finally, the solution of realizing upper and lower transistors by flipping the wafer is compatible with the existing mainstream device architecture, and can realize the front and back stacking of planar transistors, FinFET, GAA Nanosheet and even vertical transistors (VTFET), without the need for special process development for specific device architectures. It is highly flexible and has strong extensibility from the perspective of semiconductor process node iteration. The flip-chip transistor is very advanced in concept, has important industrial value, is highly practical, and has broad prospects for development.

[0153] In a third aspect, an embodiment of the present application provides a semiconductor device, including: a stacked transistor as in the above embodiment. The specific definition of the stacked transistor can be found in the above Fig.34 The stacked transistors shown are not described in detail here.

[0154] In a fourth aspect, an embodiment of the present application provides an electronic device, comprising: a circuit board and a semiconductor device as in the above embodiment, wherein the semiconductor device is disposed on the circuit board. The semiconductor device comprises the above stacked transistor. The specific definition of the stacked transistor can be found in the above Fig.34 The structure shown will not be described in detail here.

[0155] In the description of the present application, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the embodiments of the present application. In the present application, the schematic representation of the above terms is not necessarily for the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine different embodiments or examples described in the present application and the features of different embodiments or examples without contradiction.

[0156] The above are only preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for preparing a stacked transistor, characterized in that: The method comprises: Etching once to form a fin-shaped structure on a semiconductor substrate, wherein the fin-shaped structure comprises a first portion and a second portion stacked along a first direction, and the first portion is farther away from the semiconductor substrate than the second portion; Based on the first part, a first transistor is formed, wherein the first transistor includes: a first gate structure, the first gate structure is formed by a first gate preparation process; Flipping and removing the semiconductor substrate; Based on the second part, a second transistor is formed and stacked along the first direction with the first transistor, wherein the second transistor includes: a second gate structure, the second gate structure is formed by a second gate preparation process; the second gate preparation process and the first gate preparation process are different in at least the preparation steps; the heat resistance of the first gate structure is greater than the heat resistance of the second gate structure.

2. The preparation method according to claim 1, characterized in that: The step of forming a first transistor based on the first portion includes: Depositing a first gate dielectric material in the gate region of the stacked transistor to form a first gate dielectric layer covering the first portion; Depositing a metal oxide material on the first gate dielectric layer to form a capping layer; Depositing a first gate material on the cover layer to form a first gate electrode layer, wherein the first gate dielectric layer, the cover layer and the first gate electrode layer together constitute the first gate structure; and the preparation step of forming the first gate structure is included in the first gate preparation process; In the source-drain region of the stacked transistor, a first source-drain structure is formed based on the first portion, wherein the first source-drain structure and the first gate structure together constitute the first transistor.

3. The preparation method according to claim 2, characterized in that: When the first transistor is an N-type field effect transistor, the metal oxide material is lanthanum oxide; When the first transistor is a P-type field effect transistor, the metal oxide material is aluminum oxide.

4. The preparation method according to claim 2, characterized in that: The forming of a second transistor based on the second portion comprises: Depositing a dummy gate material in a gate region of the stacked transistor to form a dummy gate structure; In the source-drain region of the stacked transistor, forming a second source-drain structure based on the second portion; removing the dummy gate structure, and depositing a second gate dielectric material at the position where the dummy gate structure is removed to form a second gate dielectric layer; Depositing a second gate material on the second gate dielectric layer to form a second gate electrode layer; The second gate dielectric layer and the second gate electrode layer together constitute the second gate structure; the preparation step of forming the second gate structure is included in the second gate preparation process; and the second source-drain structure and the second gate structure together constitute the second transistor.

5. The preparation method according to claim 4, characterized in that: When the first transistor is an N-type field effect transistor, after forming the second transistor based on the second portion, the method further includes: Bonding the second transistor to the carrier wafer; The bonded second transistor is flipped.

6. The preparation method according to claim 4, characterized in that: When the first transistor is a P-type field effect transistor, the first portion is formed of silicon germanium material.

7. The preparation method according to claim 4, characterized in that: The fin-shaped structure further includes a third portion located between the first portion and the second portion; After forming the dummy gate structure, the preparation method further includes: The third portion is removed, and an insulating material is deposited at a position where the third portion is removed to form an isolation layer, wherein the isolation layer is used to electrically isolate the first portion from the second portion.

8. A stacked transistor, prepared by the method according to any one of claims 1 to 7, characterized in that: include: a first transistor; a second transistor, wherein the first transistor and the second transistor are stacked along a first direction, a first active region of the first transistor and a second active region of the second transistor are self-aligned; the first transistor includes a first gate structure, the second transistor includes a second gate structure, the first gate structure and the second gate structure are arranged opposite to each other; the first active region is formed based on a first portion of a fin structure, and the second active region is formed based on a second portion of the fin structure; The first gate structure is formed by a first gate preparation process; the second gate structure is formed by a second gate preparation process; the second gate preparation process and the first gate preparation process have at least different preparation steps; the heat resistance of the first gate structure is greater than that of the second gate structure.

9. The stacked transistor according to claim 8, characterized in that: When the first transistor is a P-type field effect transistor, the first active region of the first transistor is formed of silicon germanium material.

10. A semiconductor device, characterized in that: include: A stacked transistor as claimed in claim 8 or 9.

Images