Preparation method of semiconductor structure and semiconductor structure
By forming doped regions in the substrate of the semiconductor device and forming a multi-layer oxidation structure, the problem that the oxide thickness in the traditional process does not meet the needs of different devices is solved, and the effect of simplifying the process and reducing costs is achieved.
Patent Information
- Application Number
- CN202510026282.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-07
- Publication Date
- 2025-04-22
AI Technical Summary
In traditional semiconductor devices, the preparation process of oxides of different thicknesses is cumbersome, the cost is high, and the process is complicated, making it difficult to meet the performance requirements of different devices at the same time.
The preparation of oxide layers of different thicknesses is achieved by forming a first doped region and a second doped region in the substrate, and forming a first oxide layer and an initial oxide layer on the top surface thereof, and then removing part of the initial oxide layer to form a second oxide layer.
This method can meet the device performance requirements of oxide layers with different thicknesses, save the growth time of oxide layers, simplify the process flow, and reduce costs.
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Figure CN119866056A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for preparing a semiconductor structure and a semiconductor structure. Background Art
[0002] In semiconductor devices, Local Oxidation of Silicon (LOCOS) is a layer of oxide grown by a high-temperature furnace tube. Its main function is to isolate transistors during chip manufacturing and reduce the electrical interaction between transistors. Another main function is to serve as a field oxide structure in the drift region of the transistor to improve the surface electric field and reduce the on-resistance. Due to its simple process and strong practicality, LOCOS is widely used in various semiconductor devices.
[0003] Different semiconductor devices usually have different drift region conditions, and therefore require oxides of different thicknesses. However, in traditional preparation processes, the preparation process of oxides of different thicknesses is cumbersome and costly. Summary of the invention
[0004] Based on this, an embodiment of the present application provides a method for preparing a semiconductor structure and a semiconductor structure.
[0005] According to some embodiments, the present application provides a method for preparing a semiconductor structure, which, in some embodiments, includes:
[0006] Providing a substrate, wherein the substrate has an isolation structure;
[0007] A first doping region and a second doping region are formed in the substrate, the first doping region and the second doping region are located at two opposite sides of the isolation structure, and the second doping region includes a first sub-doping region and a second sub-doping region stacked in a direction parallel to the substrate;
[0008] forming a first oxide layer and an initial oxide layer, wherein the first oxide layer is located on a top surface of the first doping region, and the initial oxide layer is located on a top surface of the first sub-doping region;
[0009] A portion of the initial oxide layer is removed to form a second oxide layer, wherein the thickness of the second oxide layer is less than the thickness of the first oxide layer.
[0010] In the method for preparing the semiconductor structure of the above embodiment, the first oxide layer and the initial oxide layer are formed at the same time, and then the second oxide layer is formed by removing part of the initial oxide layer, the formed first oxide layer is located on the top surface of the first doping region, and the formed second oxide layer is located on the top surface of the first sub-doping region. Since the thickness of the second oxide layer is less than the thickness of the first oxide layer, the device performance requirements of oxide layers of different thicknesses can be met. On this basis, the above method can save the time of growing oxide layers multiple times, and does not need to add additional masks, can effectively simplify the process flow, and is conducive to reducing costs.
[0011] In some embodiments, forming a first doping region and a second doping region in a substrate includes: forming a first doping region and an initial doping region in the substrate; forming a first sub-doping region based on the initial doping region, and the remaining initial doping region constitutes a second sub-doping region.
[0012] In some embodiments, after forming a first doping region and an initial doping region in a substrate, forming a first sub-doping region based on the initial doping region includes: using a target mask to form a first mask layer on a top surface of the substrate; based on the first mask layer, replacing a portion of the initial doping region to form the first sub-doping region; removing the first mask layer;
[0013] Removing part of the initial oxide layer to form a second oxide layer includes: using the same target mask to form a second mask layer, the second mask layer is located on the top surface of the first oxide layer and the exposed top surface of the substrate; based on the second mask layer, removing part of the initial oxide layer to form a second oxide layer; removing the second mask layer.
[0014] In some embodiments, forming the first oxide layer and the initial oxide layer includes: forming the first oxide layer and the initial oxide layer simultaneously based on a one-time deposition process.
[0015] In some embodiments, a first oxide layer and an initial oxide layer are simultaneously formed based on a one-time deposition process, including: forming an oxide material layer on the top surface of the substrate; removing part of the oxide material layer; treating the oxide material layer with an oxidation process to form a first oxide layer and an initial oxide layer; wherein the oxide material layer located on the top surface of the first doped region constitutes the first oxide layer, and the oxide material layer located on the top surface of the first sub-doped region constitutes the initial oxide layer.
[0016] In some embodiments, the first oxide layer has a thickness ranging from 1700 angstroms to 1900 angstroms; and / or the second oxide layer has a thickness ranging from 1300 angstroms to 1500 angstroms.
[0017] In some embodiments, the method also includes: forming a first drain and a second drain in the substrate; the first drain is located on the top surface of the first doped region and between the first oxide layer and the isolation structure; the second drain is located on the top surface of the second sub-doped region and between the second oxide layer and the isolation structure; a third doped region and a fourth doped region are also formed in the substrate, the third doped region is located on a side of the first doped region away from the second doped region, and the fourth doped region is located on a side of the second doped region close to the first doped region; a first source and a second source are formed, the first source is located on the top surface of the third doped region, and the second source is located on the top surface of the fourth doped region.
[0018] In some embodiments, the method further includes: forming a first contact structure, the first contact structure is located on the top surface of the third doped region and between the first source and the isolation structure; forming a second contact structure, the second contact structure is located on the top surface of the fourth doped region and between the second source and the isolation structure.
[0019] In some embodiments, after removing a portion of the initial oxide layer to form a second oxide layer, the method also includes: forming a first gate structure on the top surface of the substrate, the first gate structure is located between the first doping region and the third doping region, and at least covers a portion of the first oxide layer; forming a second gate structure on the top surface of the substrate, the second gate structure is located between the second doping region and the fourth doping region, and at least covers a portion of the second oxide layer.
[0020] According to some embodiments, the present application further provides a semiconductor structure, which is prepared using the method for preparing the semiconductor structure in any of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] Figure 1 A schematic diagram of a process for preparing a semiconductor structure provided in one embodiment of the present application;
[0022] Figure 2 A schematic cross-sectional view of a structure obtained in step S10 and step S30 in a method for preparing a semiconductor structure provided in one embodiment of the present application;
[0023] Figure 3 A schematic cross-sectional view of a structure obtained in step S50 in a method for preparing a semiconductor structure provided in an embodiment of the present application;
[0024] Figure 4 A schematic cross-sectional view of a structure obtained in step S71 of a method for preparing a semiconductor structure provided in an embodiment of the present application;
[0025] Figure 5 A schematic cross-sectional view of a structure obtained in step S72 of a method for preparing a semiconductor structure provided in an embodiment of the present application;
[0026] Figure 6 A schematic cross-sectional view of a structure obtained in step S73 in a method for preparing a semiconductor structure provided in an embodiment of the present application;
[0027] Figure 7 A schematic cross-sectional view of a structure obtained in step S81 and step S82 in a method for preparing a semiconductor structure provided in one embodiment of the present application is shown.
[0028] Explanation of the accompanying drawings: 10, substrate; 11, isolation structure; 12, first doping region; 13, second doping region; 131, first sub-doping region; 132, second sub-doping region; 14, third doping region; 15, fourth doping region; 21, first drain; 22, second drain; 23, first source; 24, second source; 31, first oxide layer; 32, second oxide layer; 33, initial oxide layer; 40, target mask; 51, first contact structure; 52, second contact structure; 61, first gate structure; 62, second gate structure. DETAILED DESCRIPTION
[0029] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. Preferred embodiments of the present invention are provided in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present invention more thorough and comprehensive.
[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.
[0031] In the case of using “including”, “having”, and “comprising” described herein, another component may be added unless a clear limiting term such as “only”, “consisting of”, etc. is used. Unless mentioned otherwise, a term in the singular form may include a plural form and should not be understood as being one in number.
[0032] In addition, in order to clearly indicate the multiple layers and regions in the drawings, the thickness of each layer and each region in the drawings are enlarged to clearly illustrate the relative positions between the layers and the distribution of each region. When a layer, film, region, plate, etc. is expressed as being located on the "side" of another part, the expression includes not only the case where it is "directly" above the other part, but also the case where there are other layers in between. And, it is understood that when a layer, film, region, plate, etc. is expressed as being located on the "side" of another part, it generally refers to the side located directly above the other part.
[0033] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.
[0034] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.
[0035] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic representations of idealized embodiments (and intermediate structures) of the present disclosure, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the present disclosure should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. Thus, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shapes of the regions of the device, and do not limit the scope of the present disclosure.
[0036] In semiconductor devices, Local Oxidation of Silicon (LOCOS) is a layer of oxide grown by a high-temperature furnace tube, mainly used to form a local oxide layer on a silicon wafer. LOCOS technology allows the creation of an insulating layer on a silicon substrate by selective oxidation, thereby guiding and defining the structure of semiconductor devices, especially in the CMOS (Complementary Metal Oxide Semiconductor) process. Its main function is to isolate transistors during chip manufacturing and reduce the electrical interaction between transistors. Another main function is to serve as a field oxygen structure in the drift region of the transistor to improve the surface electric field and reduce the on-resistance. Due to the simplicity of the LOCOS process and its strong practicality, it is widely used in various semiconductor devices.
[0037] In a specific semiconductor device application, two different process design requirements are usually involved: one is to achieve a higher breakdown voltage (BV), and the other is to reduce the on-resistance (Ron). However, due to the different drift region conditions required and the same LOCOS thickness used, the final device performance is not ideal. Different semiconductor devices usually have different drift region conditions, so different thicknesses of oxides are required. However, when meeting the performance requirements of both devices at the same time, the traditional process is more complicated, and the preparation process of oxides of different thicknesses is cumbersome. Not only does it require additional masks, but the furnace tubes grow slowly, which means that the process is more complicated and takes longer, thereby increasing the process cost.
[0038] Based on this, an embodiment of the present application provides a method for preparing a semiconductor structure and a semiconductor structure.
[0039] See also Figure 1 The present application provides a method for preparing a semiconductor structure, which includes the following steps.
[0040] Step S10, providing a substrate, wherein the substrate has an isolation structure;
[0041] Step S30, forming a first doping region and a second doping region in the substrate, the first doping region and the second doping region are located at opposite sides of the isolation structure, and the second doping region includes a first sub-doping region and a second sub-doping region stacked in a direction parallel to the substrate;
[0042] Step S50, forming a first oxide layer and an initial oxide layer, wherein the first oxide layer is located on a top surface of the first doping region, and the initial oxide layer is located on a top surface of the first sub-doping region;
[0043] Step S70: removing part of the initial oxide layer to form a second oxide layer, wherein the thickness of the second oxide layer is less than the thickness of the first oxide layer.
[0044] In the method for preparing the semiconductor structure of the above embodiment, the first oxide layer and the initial oxide layer are formed at the same time, and then the second oxide layer is formed by removing part of the initial oxide layer, the formed first oxide layer is located on the top surface of the first doping region, and the formed second oxide layer is located on the top surface of the first sub-doping region. Since the thickness of the second oxide layer is less than the thickness of the first oxide layer, the device performance requirements of oxide layers of different thicknesses can be met. On this basis, the above method can save the time of growing oxide layers multiple times, and does not need to add additional masks, can effectively simplify the process flow, and is conducive to reducing costs.
[0045] In some embodiments, step S30, forming a first doped region and a second doped region in the substrate, includes:
[0046] Step S31, forming a first doping region and an initial doping region in the substrate;
[0047] Step S32: forming a first sub-doping region based on the initial doping region, and the remaining initial doping region constitutes a second sub-doping region.
[0048] In some embodiments, after step S31, forming a first doping region and an initial doping region in the substrate, step S32, forming a first sub-doping region based on the initial doping region, includes:
[0049] Step S321, using a target photomask to form a first mask layer on the top surface of the substrate;
[0050] Step S322, based on the first mask layer, replacing part of the initial doping region to form a first sub-doping region;
[0051] Step S323, removing the first mask layer.
[0052] In some embodiments, step S50, forming a first oxide layer and an initial oxide layer, comprises:
[0053] Step S51 : forming a first oxide layer and an initial oxide layer simultaneously based on a one-time deposition process.
[0054] In some embodiments, step S51, forming the first oxide layer and the initial oxide layer simultaneously based on a one-time deposition process, includes:
[0055] Step S511, forming an oxide material layer on the top surface of the substrate;
[0056] Step S512, removing part of the oxidized material layer; treating the oxidized material layer with an oxidation process to form a first oxidized layer and an initial oxidized layer; wherein the oxidized material layer located on the top surface of the first doped region constitutes the first oxidized layer, and the oxidized material layer located on the top surface of the first sub-doped region constitutes the initial oxidized layer.
[0057] In some embodiments, the first oxide layer has a thickness ranging from 1700 angstroms to 1900 angstroms; and / or the second oxide layer has a thickness ranging from 1300 angstroms to 1500 angstroms.
[0058] In some embodiments, step S70, removing a portion of the initial oxide layer to form a second oxide layer, includes:
[0059] Step S71, using the same target mask as in step S321 to form a second mask layer, the second mask layer being located on the top surface of the first oxide layer and the exposed top surface of the substrate;
[0060] Step S72, based on the second mask layer, removing part of the initial oxide layer to form a second oxide layer;
[0061] Step S73, removing the second mask layer.
[0062] In the above embodiments of the present disclosure, unless otherwise specified herein, the execution of each step in the method is not strictly limited in order, and these steps may not necessarily be executed in the order described, and may be executed in other ways. Moreover, at least a part of any step may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but may be executed at different times, and the execution order of these sub-steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least a part of the sub-steps or stages of other steps.
[0063] In order to more clearly illustrate the method for preparing the semiconductor structure provided by the above embodiment, Figures 2 to 7 The method is described in detail.
[0064] like Figure 2 As shown, in step S10, a substrate 10 is provided, and an isolation structure 11 is provided in the substrate 10. For example, the substrate 10 has a plurality of isolation structures 11 arranged at intervals along a first direction, and the first direction is a direction parallel to the substrate 10.
[0065] As an example, in the embodiment of the present disclosure, the substrate 10 can be made of semiconductor material, insulating material, conductor material or any combination of their material types. The substrate 10 can be a single-layer structure or a multi-layer structure. For example, the substrate 10 can be a silicon (Si) substrate 10, a silicon germanium (SiGe) substrate 10, a silicon germanium carbon (SiGeC) substrate 10, a silicon carbide (SiC) substrate 10, a gallium arsenide (GaAs) substrate 10, an indium arsenide (InAs) substrate 10, an indium phosphide (InP) substrate 10 or other III / V semiconductor substrates 10 or II / VI semiconductor substrates 10. Alternatively, for example, the substrate 10 can be a layered substrate 10 including a stack of Si and SiGe, a stack of Si and SiC, a silicon on insulator (SOI) or a silicon germanium on an insulator. Those skilled in the art can select the type of substrate 10 according to the type of transistor formed on the substrate 10, so the type of substrate 10 should not limit the scope of protection of the present disclosure.
[0066] like Figure 2 As shown, in step S30, a first doping region 12 and a second doping region 13 are formed in the substrate 10, the first doping region 12 and the second doping region 13 are located on opposite sides of the isolation structure 11, the second doping region 13 includes a first sub-doping region 131 and a second sub-doping region 132 stacked in a direction parallel to the substrate 10, and the first sub-doping region 131 is located between the first doping region 12 and the second sub-doping region 132. For example, the top surfaces of the first doping region 12 and the second doping region 13 are flush with the top surface of the substrate 10.
[0067] It can be understood that those skilled in the art can determine the doping type and doping concentration of the first sub-doping region 131 and the second sub-doping region 132 according to the required device type. For example, the first doping region 12 and the second doping region 13 have the same doping type. In a specific embodiment, the first doping region 12 and the second doping region 13 are both N-type doping layers, and the first sub-doping region 131 and the second doping region 13 have the same doping concentration. For example, the first sub-doping region 131 and the second sub-doping region 132 have different doping concentrations. In a specific embodiment, the doping concentration of the first sub-doping region 131 is greater than the doping concentration of the second sub-doping region 132.
[0068] In some embodiments, step S30 of forming the first doping region 12 and the second doping region 13 in the substrate 10 includes the following steps S31 and S32 .
[0069] Step S31, forming a first doping region 12 and an initial doping region (not shown) in the substrate 10;
[0070] Step S32 : forming a first sub-doping region 131 based on the initial doping region, and the remaining initial doping region constitutes a second sub-doping region 132 .
[0071] For example, in step S31, the first doping region 12 and the initial doping region may be formed by doping a designated region in the substrate 10, so that the first doping region 12 and the initial doping region have a preset doping type. In step S31, the first sub-doping region 131 may be formed by doping a designated region in the initial doping region, so that the first sub-doping region 131 has a preset doping concentration.
[0072] In some embodiments, after step S31 , forming the first doping region 12 and the initial doping region in the substrate 10 , step S32 , forming the first sub-doping region 131 based on the initial doping region, includes the following steps S321 to S323 .
[0073] Step S321 : using the target photomask 40 to form a first mask layer on the top surface of the substrate 10 .
[0074] In some embodiments, step S321 also includes the step of forming a photoresist material layer on the top surface of the substrate 10. The photoresist material layer undergoes a series of steps such as exposure and development under the action of the target mask 40 to form a patterned first mask layer. The first mask layer has an opening pattern with the position and shape of the first sub-doped region 131. The photoresist can be a positive photoresist or a negative photoresist, and the development method can be a positive development or a negative development.
[0075] Step S322 : Based on the first mask layer, replace part of the initial doping region to form a first sub-doping region 131 .
[0076] For example, in step S322 , based on the patterned first mask layer, the portion where the first sub-doping region 131 is to be formed is doped again to form the first sub-doping region 131 .
[0077] Step S323, removing the first mask layer.
[0078] For example, in step S323 , the first mask layer may be removed by a process such as ashing.
[0079] like Figure 2 As shown, in some embodiments, the method further includes the following steps S41 to S45.
[0080] Step S41, forming a first drain 21 and a second drain 22 in the substrate 10; the first drain 21 is located on the top surface of the first doped region 12 and between the first oxide layer 31 and the isolation structure 11; the second drain 22 is located on the top surface of the second sub-doped region 132 and between the second oxide layer 32 and the isolation structure 11.
[0081] For example, the first drain 21 and the second drain 22 have the same doping type. In a specific embodiment, the doping type of the first drain 21 and the second drain 22 are both N-type.
[0082] Step S42 , forming a third doping region 14 and a fourth doping region 15 in the substrate 10 , wherein the third doping region 14 is located on a side of the first doping region 12 away from the second doping region 13 , and the fourth doping region 15 is located on a side of the second doping region 13 close to the first doping region 12 .
[0083] For example, the third doping region 14 and the fourth doping region 15 have the same doping type. In a specific embodiment, the third doping region 14 and the fourth doping region 15 are both P-type doping types.
[0084] Step S43 , forming a first source 23 and a second source 24 , wherein the first source 23 is located on the top surface of the third doping region 14 , and the second source 24 is located on the top surface of the fourth doping region 15 .
[0085] For example, the first source 23 and the second source 24 have the same doping type. In a specific embodiment, the doping type of the first source 23 and the second source 24 are both N-type.
[0086] Step S44 , forming a first contact structure 51 . The first contact structure 51 is located on the top surface of the third doping region 14 and between the first source 23 and the isolation structure 11 .
[0087] Step S45 , forming a second contact structure 52 , where the second contact structure 52 is located on the top surface of the fourth doping region 15 and between the second source 24 and the isolation structure 11 .
[0088] For example, the first contact structure 51 and the second contact structure 52 have the same doping type. In a specific embodiment, the doping types of the first contact structure 51 and the second contact structure 52 are both P-type. The first contact structure 51 located on the side wall of the first source 23 and the second contact structure 52 located on the side wall of the second source 24 can reduce the contact resistance between the source and the semiconductor material and improve the current conduction efficiency, thereby improving the switching characteristics of the device due to the high doping concentration. In addition, the abundant holes in the first contact structure 51 and the second contact structure 52 provide better carrier injection capability, helping to improve the breakdown voltage and working performance of the device.
[0089] For example, the first contact structure 51 and the first source 23 have different doping types, and the second contact structure 52 and the second source 24 have different doping types. In this way, the formed PN junction helps to establish a suitable potential barrier, control the current flow between the source and the base, and is conducive to adjusting the working state (on / off) of the device.
[0090] In step S44 and step S45, the electric field formed by the first contact structure 51 and the second contact structure 52 can effectively control the flow of holes and electrons in the insulator, which is helpful for the stability and reliability of the device. In the power supply circuit, the first contact structure 51 and the second contact structure 52 help to maintain the stability of the threshold voltage and reduce fluctuations caused by temperature changes or other external factors. In addition, the first contact structure 51 and the second contact structure 52 can reduce the leakage current of the device under reverse bias, thereby improving the overall performance of the device.
[0091] like Figure 3 As shown, in some embodiments, in step S50 , a first oxide layer 31 and an initial oxide layer 33 are formed, the first oxide layer 31 is located on the top surface of the first doping region 12 , and the initial oxide layer 33 is located on the top surface of the first sub-doping region 131 .
[0092] For example, the first oxide layer 31 and the initial oxide layer 33 may be formed by chemical vapor deposition or physical vapor deposition (PVD) and other processes. The chemical vapor deposition process may include one or more of atmospheric pressure chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD). For example, the first oxide layer 31 and the initial oxide layer 33 may be formed by plasma enhanced chemical vapor deposition, which is formed by ionizing the film layer by glow discharge in a deposition chamber and then chemically reacting on the film layer to deposit and form the first oxide layer 31 and the initial oxide layer 33. The plasma enhanced chemical vapor deposition method can enhance the activity of chemical vapor reaction substances through plasma activation, increase the surface reaction rate, and significantly reduce the deposition temperature through high energy ions.
[0093] In some embodiments, the first oxide layer 31 and the initial oxide layer 33 may be made of the same material. For example, the material of the first oxide layer 31 and the initial oxide layer 33 may be selected from silicon oxide, silicon nitride, silicon oxynitride or a combination thereof.
[0094] In some embodiments, step S50, forming the first oxide layer 31 and the initial oxide layer 33, comprises:-
[0095] Step S51 : forming the first oxide layer 31 and the initial oxide layer 33 simultaneously based on a one-time deposition process.
[0096] It should be added that the “one-time deposition process” mentioned in some embodiments of the present disclosure can be understood as a deposition process based on the same deposition material; and is not limited to a specific deposition method.
[0097] In some embodiments, step S51, forming the first oxide layer 31 and the initial oxide layer 33 simultaneously based on a one-time deposition process, includes:
[0098] Step S511, forming an oxide material layer on the top surface of the substrate 10;
[0099] Step S512, remove part of the oxide material layer; use an oxidation process to treat the oxide material layer to form a first oxide layer 31 and an initial oxide layer 33; wherein the oxide material layer located on the top surface of the first doping region 12 constitutes the first oxide layer 31, and the oxide material layer located on the top surface of the first sub-doping region 131 constitutes the initial oxide layer 33.
[0100] In some embodiments, the thickness of the first oxide layer 31 ranges from 1700 angstroms to 1900 angstroms. For example, the thickness of the first oxide layer 31 is 1700 angstroms, 1800 angstroms, or 1900 angstroms.
[0101] In some embodiments, the thickness of the second oxide layer 32 ranges from 1300 angstroms to 1500 angstroms. For example, the thickness of the second oxide layer 32 is 1300 angstroms, 1400 angstroms, or 1500 angstroms.
[0102] like Figure 6 As shown, in some embodiments, in step S70 , a portion of the initial oxide layer 33 is removed to form a second oxide layer 32 , and the thickness of the second oxide layer 32 is less than the thickness of the first oxide layer 31 .
[0103] For example, in step S70 , an etching process or a planarization process (chemical mechanical polishing, CMP) may be used to remove a portion of the initial oxide layer 33 .
[0104] In some embodiments, step S70, removing a portion of the initial oxide layer 33 to form the second oxide layer 32, includes the following steps S71 to S73.
[0105] Step S71 , using the same target mask 40 as in step S321 to form a second mask layer, the second mask layer being located on the top surface of the first oxide layer 31 and the exposed top surface of the substrate 10 .
[0106] like Figure 4As shown, since the position of the first sub-doping region 131 is the same as the position of the initial oxide layer 33, in step S71, the same target mask 40 in step S321 can be directly used to form a graphic second mask layer, and the second mask layer has the position and shape of the second oxide layer 32, thereby saving masks, reducing process steps, and simplifying the process flow.
[0107] Step S72 : based on the second mask layer, remove a portion of the initial oxide layer 33 to form a second oxide layer 32 .
[0108] like Figure 5 As shown, in step S72 , the initial oxide layer 33 may be etched in a direction perpendicular to the substrate 10 to reduce its thickness, thereby forming a second oxide layer 32 having a thickness less than that of the first oxide layer 31 .
[0109] Step S73: Figure 6 As shown, the second mask layer is removed.
[0110] like Figure 7 As shown, in some embodiments, after step S70, removing a portion of the initial oxide layer 33 to form the second oxide layer 32, the method further includes:
[0111] Step S81, forming a first gate structure 61 on the top surface of the substrate 10, wherein the first gate structure 61 is located between the first doping region 12 and the third doping region 14 and covers at least a portion of the first oxide layer 31;
[0112] Step S82 , forming a second gate structure 62 on the top surface of the substrate 10 , wherein the second gate structure 62 is located between the second doping region 13 and the fourth doping region 15 and covers at least a portion of the second oxide layer 32 .
[0113] In some embodiments, the first gate structure 61 and the second gate structure 62 both include a gate dielectric layer and a gate conductive layer sequentially stacked in a direction perpendicular to the substrate 10. For example, the material of the gate conductive layer is selected from titanium, tungsten, tantalum, molybdenum, cobalt, platinum, titanium tungsten, tungsten nitride, titanium nitride, titanium nitride, or a combination thereof.
[0114] See also Figure 5 According to some embodiments, the present application further provides a semiconductor structure, which is prepared by the method for preparing the semiconductor structure in any of the above embodiments. Since a better preparation method is used to prepare the semiconductor structure, the beneficial effects of the preparation method of the above semiconductor structure are also possessed by the semiconductor structure in the embodiments of the present application, which will not be described in detail here.
[0115] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0116] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.
Claims
1. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate, wherein the substrate has an isolation structure; forming a first doping region and a second doping region in the substrate, wherein the first doping region and the second doping region are located at opposite sides of the isolation structure, and the second doping region includes a first sub-doping region and a second sub-doping region stacked in a direction parallel to the substrate; forming a first oxide layer and an initial oxide layer, wherein the first oxide layer is located on a top surface of the first doping region, and the initial oxide layer is located on a top surface of the first sub-doping region; A portion of the initial oxide layer is removed to form a second oxide layer, wherein the thickness of the second oxide layer is less than the thickness of the first oxide layer.
2. The method for preparing a semiconductor structure according to claim 1, characterized in that: The forming of the first doping region and the second doping region in the substrate includes: forming the first doped region and the initial doped region in the substrate; A first sub-doping region is formed based on the initial doping region, and the remaining initial doping region constitutes a second sub-doping region.
3. The method for preparing a semiconductor structure according to claim 2, characterized in that: After forming the first doping region and the initial doping region in the substrate, forming a first sub-doping region based on the initial doping region includes: forming a first mask layer on the top surface of the substrate using a target photomask; Based on the first mask layer, replacing a portion of the initial doping region to form the first sub-doping region; removing the first mask layer; The removing part of the initial oxide layer to form a second oxide layer comprises: Using the same target photomask to form a second mask layer, the second mask layer is located on the top surface of the first oxide layer and the exposed top surface of the substrate; Based on the second mask layer, removing a portion of the initial oxide layer to form a second oxide layer; The second mask layer is removed.
4. The method for preparing a semiconductor structure according to claim 1, characterized in that: The forming of the first oxide layer and the initial oxide layer comprises: The first oxide layer and the initial oxide layer are formed simultaneously based on a one-time deposition process.
5. The method for preparing a semiconductor structure according to claim 4, characterized in that: The method of simultaneously forming the first oxide layer and the initial oxide layer based on a one-time deposition process includes: forming an oxide material layer on the top surface of the substrate; removing a portion of the oxidized material layer; The oxide material layer is treated by an oxidation process to form the first oxide layer and the initial oxide layer; wherein the oxide material layer located on the top surface of the first doping region constitutes the first oxide layer, and the oxide material layer located on the top surface of the first sub-doping region constitutes the initial oxide layer.
6. The method for preparing a semiconductor structure according to any one of claims 1 to 5, characterized in that: The thickness of the first oxide layer ranges from 1700 angstroms to 1900 angstroms; and / or The thickness of the second oxide layer ranges from 1300 angstroms to 1500 angstroms.
7. The method for preparing a semiconductor structure according to claim 1, characterized in that: The method further comprises: A first drain and a second drain are formed in the substrate; the first drain is located on the top surface of the first doped region and between the first oxide layer and the isolation structure; the second drain is located on the top surface of the second sub-doped region and between the second oxide layer and the isolation structure; A third doping region and a fourth doping region are also formed in the substrate, wherein the third doping region is located on a side of the first doping region away from the second doping region, and the fourth doping region is located on a side of the second doping region close to the first doping region; A first source and a second source are formed, wherein the first source is located on a top surface of the third doping region, and the second source is located on a top surface of the fourth doping region.
8. The method for preparing a semiconductor structure according to claim 7, characterized in that: The method further comprises: forming a first contact structure, wherein the first contact structure is located on the top surface of the third doping region and between the first source and the isolation structure; A second contact structure is formed, where the second contact structure is located on the top surface of the fourth doping region and between the second source and the isolation structure.
9. The method for preparing a semiconductor structure according to claim 7, characterized in that: After removing part of the initial oxide layer to form a second oxide layer, the method further comprises: forming a first gate structure on the top surface of the substrate, wherein the first gate structure is located between the first doping region and the third doping region and covers at least a portion of the first oxide layer; A second gate structure is formed on the top surface of the substrate, wherein the second gate structure is located between the second doping region and the fourth doping region and covers at least a portion of the second oxide layer.
10. A semiconductor structure, characterized in that: The semiconductor structure is prepared by the method for preparing the semiconductor structure according to any one of claims 1 to 9.