A back contact battery with a specific passivation structure and its manufacturing method and application

Abstract

The present invention belongs to the technical field of back contact batteries, and specifically relates to a back contact battery with a specific passivation structure, and its manufacturing method and application. The second semiconductor layer in the back contact battery includes an amorphous silicon layer and a second doped crystalline silicon layer arranged in sequence from the back of the silicon wafer to the outside, and the second doped crystalline silicon layer includes a second doped microcrystalline region and a second doped amorphous region located on both sides of the second doped microcrystalline region. The second doped microcrystalline region is located at a position corresponding to the second semiconductor opening region and in contact with the conductive film layer, and the second doped amorphous region is laid outside the side end of the first doped polycrystalline silicon layer and the back of its adjacent part; wherein the crystallization rate of the second doped microcrystalline region is 5%-80%. The present invention can significantly reduce the bulk resistivity of the second doped crystalline silicon layer, and also reduce the contact resistivity between the second doped crystalline silicon layer and the conductive film layer, thereby significantly reducing the series resistance of the battery, while effectively avoiding leakage current and improving battery efficiency.

Description

Technical Field

[0001] The present invention belongs to the technical field of back contact batteries, and in particular relates to a back contact battery with a specific passivation structure and a manufacturing method and application thereof. Background Art

[0002] At present, the back contact battery includes two semiconductor regions of different polarities alternately arranged on the back of the silicon wafer, and there are two semiconductor superimposed spacer regions between the two semiconductor regions. The process flow is generally as follows: S1, provide a silicon wafer; S2, form a first semiconductor layer and a mask layer on the back of the silicon wafer in sequence, the first semiconductor layer includes a first tunneling oxide layer and an N-type doped polysilicon layer; S3, perform a first etching on the back obtained in S2 to form a second semiconductor opening area; S4, perform texturing and cleaning, and form a texturing surface on the front of the silicon wafer and the second semiconductor opening area at the same time; then remove part or all of the mask layer outside the second semiconductor opening area on the back of the silicon wafer; S5, form a passivation layer and an anti-reflection layer on the front of the silicon wafer; S6, clean it with a conventional RCA standard solution so that the interface cleanliness of the second semiconductor opening area on the back of the silicon wafer meets the requirements. The requirements for depositing the second semiconductor layer are met; S7, a second semiconductor layer is deposited on the back side obtained in S6, the second semiconductor layer comprises an intrinsic silicon layer and a P-type doped amorphous silicon layer; S8, a second etching is performed on a portion of the second semiconductor layer on the back side of the silicon wafer to form a first semiconductor opening region arranged at intervals with the second semiconductor opening region; S9, a conductive film layer is deposited on the back side; S10, a third etching is performed on a portion of the conductive film layer located between the first semiconductor opening region and the second semiconductor opening region to form an isolation groove; S11, metal electrodes are respectively formed on the outer surfaces of the corresponding conductive film layers in the areas where the first semiconductor opening region and the second semiconductor opening region are located.

[0003] However, the above-mentioned back-contact battery structure has the following deficiencies: ① The conductivity of the P-type doped amorphous silicon layer is very small, and the contact resistivity with the back conductive film layer is relatively large, thereby increasing the series resistance of the battery and reducing the battery efficiency. ② Although the conductivity of P-type doped microcrystalline silicon is higher than that of P-type doped amorphous silicon, if the prior art uses a P-type doped microcrystalline silicon layer to replace the P-type doped amorphous silicon layer, there will be serious leakage problems in the longitudinal overlap and side boundary areas between the P-type doped crystalline silicon layer (i.e., the P-type doped microcrystalline silicon layer) and the N-type doped polycrystalline silicon layer, thereby greatly reducing the battery efficiency.

[0004] It should be noted that this part of the present invention only provides background technology related to the present invention and does not necessarily constitute prior art or known technology. Summary of the invention

[0005] The purpose of the present invention is to overcome the defect in the prior art that the back-contact battery with two semiconductor overlapping spacer regions cannot take into account both the series resistance and the leakage current, resulting in low battery efficiency, and to provide a back-contact battery with a specific passivation structure and a manufacturing method and application thereof. The present invention can greatly reduce the bulk resistivity of the second doped crystalline silicon layer, and also reduce the contact resistivity between the second doped crystalline silicon layer and the conductive film layer, thereby greatly reducing the series resistance of the battery, while effectively avoiding leakage current and improving battery efficiency.

[0006] In order to achieve the above-mentioned purpose, in a first aspect, the present invention provides a back-contact battery with a specific passivation structure, comprising a silicon wafer, a first semiconductor layer and a second semiconductor layer alternately arranged on the back side of the silicon wafer, and a conductive film layer arranged outside the first semiconductor layer and the second semiconductor layer, wherein a second semiconductor opening area is formed between adjacent first semiconductor layers, two ends of the second semiconductor layer respectively extend outward to cover the outside of the partial back side of the adjacent first semiconductor layer, and a first semiconductor opening area not covering the second semiconductor layer is opened on the back side of the first semiconductor layer, the first semiconductor layer comprises a first doped polycrystalline silicon layer; the second semiconductor layer comprises an amorphous silicon layer and a second doped crystalline silicon layer arranged in sequence from the back side of the silicon wafer to the outside, the second doped crystalline silicon layer comprises a second doped microcrystalline area and a second doped amorphous area located on both sides of the second doped microcrystalline area, the second doped microcrystalline area is located at a position corresponding to the second semiconductor opening area and in contact with the conductive film layer, and the second doped amorphous area is laid outside the side end of the first doped polycrystalline silicon layer and the back side of the adjacent part thereof; wherein the crystallization rate of the second doped microcrystalline area is 5%-80%.

[0007] In some preferred embodiments of the present invention, the ratio of the conductivity of the second doped microcrystalline region to the conductivity of the second doped amorphous region is (1e1-1e6): 1, and / or the conductivity of the second doped microcrystalline region is 1e-1 (Ω·cm) -1 -5e2(Ω·cm) -1 .

[0008] In some preferred embodiments of the present invention, the width of the second doped microcrystalline region is 20%-90% of the width of the second semiconductor opening region, and / or the ratio of the thickness of the second doped microcrystalline region to the conductive film layer is (0.1-1):1.

[0009] In some preferred embodiments of the present invention, the width of the second doped microcrystalline region is 10-500 μm.

[0010] In some preferred embodiments of the present invention, the thickness of the second doped microcrystalline region is 5-36 nm, and the thickness of the second doped amorphous region is 6-36 nm.

[0011] In some preferred embodiments of the present invention, the thickness of the second doped microcrystalline region is the same as the thickness of the second doped amorphous region, and / or the ratio of the thickness of the second doped microcrystalline region to the first doped polysilicon layer and the amorphous silicon layer is 1: (2-20): (0.2-1.5).

[0012] Preferably, in the present invention, the thickness of the amorphous silicon layer is 6-50 nm.

[0013] In some preferred embodiments of the present invention, the area of ​​the second doped microcrystalline region accounts for 10%-80% of the area of ​​the second doped crystalline silicon layer.

[0014] In some preferred embodiments of the present invention, the body resistivity of the second doped crystalline silicon layer is between 1e2Ω·cm and 1e7Ω·cm.

[0015] In some preferred embodiments of the present invention, the back contact cell further has at least one of the following structures:

[0016] Structure 1: The first semiconductor layer further comprises a tunneling oxide layer, and the tunneling oxide layer is located between the silicon wafer and the first doped polysilicon layer;

[0017] Structure 2: The portion of the silicon wafer located at the position of the second semiconductor opening area is a textured surface, a polished surface, or a semi-polished structure in between the textured surface and the polished surface, and the portion of the silicon wafer at the position corresponding to the first semiconductor layer is a polished surface; the front side of the silicon wafer is a textured surface, a polished surface, or a semi-polished structure in between the textured surface and the polished surface;

[0018] Structure 3: The second semiconductor opening region and the first semiconductor opening region are arranged at intervals and the area between them is a spacing region, an isolation groove is provided on the portion of the conductive film layer located in the spacing region, and a mask layer is provided between the first semiconductor layer and the second semiconductor layer in the spacing region or no mask layer is provided;

[0019] Structure 4: The back contact battery further includes a metal electrode, which is arranged on the outer surface of the conductive film layer corresponding to the second semiconductor opening region and the first semiconductor opening region;

[0020] Structure 5. The back contact cell also includes a front passivation layer and an anti-reflection layer sequentially arranged on the front side of the silicon wafer;

[0021] Structure 6: The first doped polysilicon layer is N-type, and the second doped crystalline silicon layer is P-type.

[0022] In a second aspect, the present invention provides a method for manufacturing a back contact battery with a specific passivation structure, comprising the following steps:

[0023] S101, providing silicon wafers;

[0024] S102, forming a first semiconductor layer and a mask layer in sequence on the back side of the silicon wafer, wherein the first semiconductor layer includes a first doped polysilicon layer;

[0025] S103, performing a first etching opening on the back surface obtained in S102 to form a second semiconductor opening region;

[0026] S104, texturing and cleaning, followed by or without a step of removing at least a portion of the mask layer;

[0027] S107, depositing an amorphous silicon layer and a second doped amorphous film layer in sequence on the back side;

[0028] S108, performing a second etching opening on the corresponding portion of the second semiconductor layer superimposed outside the first semiconductor layer on the back side of the silicon wafer to form a first semiconductor opening region spaced apart from the second semiconductor opening region;

[0029] S109, laser scribing is performed on at least a portion of the second doped amorphous film layer corresponding to the second semiconductor opening region, so that a portion of the second doped amorphous film layer in the laser scribing region is crystallized to form a second doped microcrystalline region, and the non-crystallized amorphous silicon region is the second doped amorphous region, thereby forming a second semiconductor layer; during the process, the crystallization rate of the second doped microcrystalline region is controlled to be 5%-80% by laser scribing;

[0030] S110, depositing a conductive film layer on the back side.

[0031] In some preferred embodiments of the present invention, the laser scribing conditions in S109 include: the laser pulse width is less than 100 ps, ​​the laser energy density is 0.2-5 mJ / mm 2 ; and / or, the laser wavelength of the laser scribing is 300-1100nm.

[0032] In some preferred embodiments of the present invention, the manufacturing method further includes performing the following after S104 and before S107: S105, sequentially forming a front passivation layer and an anti-reflection layer on the front side of the silicon wafer; S106, performing cleaning to ensure the interface cleanliness of the second semiconductor opening area on the back side of the silicon wafer.

[0033] In some preferred embodiments of the present invention, the manufacturing method further comprises, after S110, performing:

[0034] S111, performing a third etching opening on a portion of the conductive film layer located between the first semiconductor opening region and the second semiconductor opening region to form an isolation groove;

[0035] S112, forming metal electrodes on the outer surfaces of the corresponding conductive film layers in the areas where the first semiconductor opening region and the second semiconductor opening region are located.

[0036] In a third aspect, the present invention provides a back-contact battery, which includes a back-contact battery manufactured by the method for manufacturing a back-contact battery with a specific passivation structure described in the second aspect.

[0037] In a fourth aspect, the present invention provides a battery assembly, which includes the back-contact battery with a specific passivation structure described in the first aspect, or includes the back-contact battery described in the third aspect.

[0038] Beneficial effects:

[0039] The present invention adopts the above technical scheme, especially in the structure with two semiconductor layers superimposed and covered, adopts the second doped crystalline silicon layer with a specific structure containing a second doped microcrystalline region and a second doped amorphous region to cooperate with the amorphous silicon layer to form the second semiconductor layer, which can greatly reduce the body resistivity of the second doped crystalline silicon layer. At the same time, since the second doped microcrystalline region is in contact with the conductive film layer, the contact resistivity is small, and the contact resistivity between the second doped crystalline silicon layer and the conductive film layer is also reduced, thereby greatly reducing the series resistance of the battery; and in addition to the second doped amorphous region being arranged to be laid on the side end of the first doped polycrystalline silicon layer and the back of its adjacent part, it can also effectively avoid the serious leakage problem in the longitudinal superimposed covering area and the side boundary area of ​​the first semiconductor layer and the second semiconductor layer, thereby synergistically improving the battery efficiency. Among them, the present invention adopts a second doped microcrystalline region with a suitable crystallization rate, and cooperates with the second doped amorphous region to form a second doped crystalline silicon layer with different conductivity gradients, which is conducive to reducing the battery series connection while maintaining the passivation effect, thereby improving the battery efficiency.

[0040] In the manufacturing method of the present invention, a laser scribing process is used to form a second doped microcrystalline region from a local second doped amorphous film layer, so that the width of the microcrystalline region can be accurately controlled to obtain a second semiconductor layer with a specific structure, thereby greatly reducing the body resistivity of the second doped crystalline silicon layer with a specific structure containing the second doped microcrystalline region and the second doped amorphous region and the contact resistivity between the second doped crystalline silicon layer and the conductive film layer, thereby greatly reducing the series resistance of the battery, while effectively avoiding leakage current and improving battery efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0042] Figure 1 A schematic structural diagram of a double-sided polished silicon wafer is provided in one embodiment of the present invention.

[0043] Figure 2It is a structural schematic diagram of sequentially forming a first semiconductor layer and a mask layer on the back side of a silicon wafer in one embodiment of the present invention.

[0044] Figure 3 It is a schematic diagram of a structure for forming a second semiconductor opening region in one embodiment of the present invention.

[0045] Figure 4 It is a schematic diagram of the structure of removing the mask layer after texturing and cleaning in one embodiment of the present invention.

[0046] Figure 5 It is a schematic structural diagram of forming a front passivation layer and an anti-reflection layer on the front side of a silicon wafer in one embodiment of the present invention.

[0047] Figure 6 It is a schematic diagram of the structure in which an intrinsic amorphous silicon layer and a P-type doped amorphous silicon layer are formed on the back side in one embodiment of the present invention.

[0048] Figure 7 It is a schematic structural diagram of forming P-type microcrystalline silicon after forming a first semiconductor opening region in one embodiment of the present invention.

[0049] Figure 8 It is a schematic diagram of the structure of forming a transparent conductive film layer in one embodiment of the present invention.

[0050] Fig. 9 It is a schematic diagram of the structure of forming an isolation trench in one embodiment of the present invention.

[0051] Fig.10 It is a schematic diagram of the structure of forming a metal electrode in one embodiment of the present invention.

[0052] Description of Reference Numerals

[0053] Silicon wafer 1, tunneling oxide layer 2, N-type doped polysilicon layer 3, mask layer 4, front passivation layer 5, anti-reflection layer 6, intrinsic amorphous silicon layer 7, P-type doped amorphous silicon layer 81, P-type microcrystalline silicon 82, transparent conductive film layer 9, metal electrode 10. Second semiconductor opening area W1, first semiconductor opening area W2, isolation trench W3. DETAILED DESCRIPTION

[0054] In the present invention, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0055] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0056] The endpoints and any values ​​of the ranges disclosed herein are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges. For numerical ranges, the endpoint values ​​of each range, the endpoint values ​​of each range and the individual point values, and the individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed in this article. Among them, the terms "optional" and "optional" all mean that they may be included or not included (or may be present or not).

[0057] In the present invention, the area close to the silicon wafer is referred to as the inside, and the area far from the silicon wafer is referred to as the outside.

[0058] In the present invention, the crystallinity ratio is obtained by Raman spectroscopy.

[0059] In the first aspect, the present invention provides a back-contact battery with a specific passivation structure, comprising a silicon wafer, a first semiconductor layer and a second semiconductor layer alternately arranged on the back side of the silicon wafer, and a conductive film layer arranged outside the first semiconductor layer and the second semiconductor layer, wherein a second semiconductor opening area is formed between adjacent first semiconductor layers, two ends of the second semiconductor layer respectively extend outward to cover the outside of the partial back side of the adjacent first semiconductor layer, and a first semiconductor opening area not covering the second semiconductor layer is opened on the back side of the first semiconductor layer, the first semiconductor layer comprises a first doped polycrystalline silicon layer; the second semiconductor layer comprises an amorphous silicon layer and a second doped crystalline silicon layer arranged in sequence from the back side of the silicon wafer outward, the second doped crystalline silicon layer comprises a second doped microcrystalline area and a second doped amorphous area located on both sides of the second doped microcrystalline area, the second doped microcrystalline area is located at a position corresponding to the second semiconductor opening area and in contact with the conductive film layer, and the second doped amorphous area is laid outside the side end of the first doped polycrystalline silicon layer and the back side of the adjacent part thereof; wherein the crystallization rate of the second doped microcrystalline area is 5%-80%.

[0060] The crystallization rate of the second doped microcrystalline zone is 5%-80%, for example, it can be 5%, 8%, 10%, 12%, 15%, 17%, 20%, 23%, 25%, 28%, 30%, 33%, 35%, 38%, 40%, 42%, 45%, 48%, 50%, 53%, 55%, 58%, 60%, 62%, 65%, 68%, 70%, 72%, 75%, 78%, 80%, etc., or it is in the numerical range formed by any two of the above specific values ​​as endpoints. In some preferred embodiments, 5%-60% is preferred.

[0061] In the present invention, the doping types in the first doped polysilicon layer and the second doped crystalline silicon layer are N-type and P-type, respectively. It is understood that the second doped amorphous region is laid outside the amorphous silicon layer and is located outside the side end of the first doped polysilicon layer and the back side of its adjacent portion.

[0062] In some preferred embodiments of the present invention, the conductivity ratio of the second doped microcrystalline region to the second doped amorphous region is (1e1-1e6): 1, preferably (1e1-8e2): 1. This preferred solution is more conducive to reducing the series resistance of the battery.

[0063] In some preferred embodiments of the present invention, the conductivity of the second doped microcrystalline region is between 1e-1 (Ω·cm) and -1 -5e2(Ω·cm) -1 , preferably 1e-1 (Ω·cm) -1 -0.8e1(Ω·cm) -1 .

[0064] In some preferred embodiments of the present invention, the width of the second doped microcrystalline region is 20%-90%, preferably 20%-85% of the width of the second semiconductor opening region. Using a second doped microcrystalline region with a suitable width ratio is more conducive to reducing the series resistance of the battery while controlling the leakage current between the first semiconductor and the second semiconductor.

[0065] In some preferred embodiments of the present invention, the width of the second doped microcrystalline region is 10-500 μm.

[0066] In some preferred embodiments of the present invention, the area of ​​the second doped microcrystalline region accounts for 10%-80% of the area of ​​the second doped crystalline silicon layer, which is more conducive to reducing the series resistance of the battery while controlling the leakage current between the first semiconductor and the second semiconductor.

[0067] In some preferred embodiments of the present invention, the thickness ratio of the second doped microcrystalline region to the conductive film layer is (0.1-1):1, more preferably (0.1-0.8):1, and further preferably (0.2-0.8):1, which is more conducive to reducing the series resistance of the battery.

[0068] In some preferred embodiments of the present invention, the thickness of the second doped microcrystalline region is 5-36 nm, preferably 13-36 nm, and the thickness of the second doped amorphous region is 6-36 nm, preferably 13-36 nm.

[0069] In some preferred embodiments of the present invention, the thickness of the second doped microcrystalline region is the same as the thickness of the second doped amorphous region.

[0070] In some preferred embodiments of the present invention, the thickness ratio of the second doped microcrystalline region to the first doped polysilicon layer and the amorphous silicon layer is 1: (2-20): (0.2-1.5), preferably 1: (5-20): (0.3-1.5), and further preferably 1: (5-20): (1-1.5). The second doped microcrystalline region with a suitable thickness ratio is matched with the first doped polysilicon layer and the amorphous silicon layer, which is more conducive to improving the efficiency of the battery.

[0071] In the present invention, preferably, the thickness of the amorphous silicon layer is 6-50 nm, preferably 10-50 nm.

[0072] Preferably, in the present invention, the thickness of the first doped polysilicon layer is 80-120 nm.

[0073] In some preferred embodiments of the present invention, the body resistivity of the second doped crystalline silicon layer is 1e2Ω·cm-1e7Ω·cm, which is more conducive to controlling the leakage current between the first semiconductor and the second semiconductor.

[0074] Preferably, the effective doping concentration of the second doped crystalline silicon layer is 5e18cm -3 -5e19cm -3 It can be understood that the effective doping concentrations of the second doped microcrystalline region and the second doped amorphous region can be the same or different, as long as they are within the above concentration range.

[0075] In some preferred embodiments of the present invention, the first semiconductor layer further comprises a tunneling oxide layer, and the tunneling oxide layer is located between the silicon wafer and the first doped polysilicon layer. The use of a joint passivation structure in combination with the specific second semiconductor layer of the present invention is more conducive to improving the mass production of the battery.

[0076] In the present invention, the thickness of the tunnel oxide layer and the doping concentration of the first doped polysilicon layer can be selected in a wide range, and can refer to the prior art. For example, the thickness of the tunnel oxide layer can be 1-2nm, and the effective doping concentration of the first doped polysilicon layer is 5e18cm -3 -1e20cm -3 .

[0077] In some preferred embodiments of the present invention, part of the silicon wafer located at the position of the second semiconductor opening area is a textured surface, a polished surface, or a semi-polished structure between the textured surface and the polished surface, and part of the silicon wafer at the position corresponding to the first semiconductor layer is a polished surface. The semi-polished structure between the textured surface and the polished surface means that the surface has a concave-convex structure, and the concave-convex structure can be, for example, a semi-pyramid structure.

[0078] In some preferred embodiments of the present invention, the front side of the silicon wafer is a textured surface, a polished surface, or a semi-polished structure in between the textured surface and the polished surface.

[0079] In some preferred embodiments of the present invention, the second semiconductor opening region is spaced apart from the first semiconductor opening region and the region between them is a spacer region, an isolation groove is provided on the portion of the conductive film layer located in the spacer region, and a mask layer is provided or not provided between the first semiconductor layer and the second semiconductor layer in the spacer region. It is understandable that the first semiconductor layer and the second semiconductor layer in the spacer region are superimposed in the thickness direction.

[0080] In the present invention, the thickness and material of the conductive film layer can be selected in a wide range. Exemplarily, the thickness of the conductive film layer is 40-80nm, and the material of the conductive film layer can be, for example, an indium oxide-based film doped with at least one of tin, tungsten, titanium, and zinc, or a zinc oxide-based film doped with aluminum and / or boron.

[0081] In some preferred embodiments of the present invention, the back contact battery further comprises a metal electrode, and the metal electrode is arranged on the outer surface of the conductive film layer corresponding to each of the second semiconductor opening region and the first semiconductor opening region.

[0082] The widths of the first semiconductor opening region and the second semiconductor opening region in the present invention can be determined according to the range of the prior art and actual needs. For example, the width of the second semiconductor opening region can be 400-800 μm, and the width of the first semiconductor opening region can be 100-250 μm.

[0083] In some preferred embodiments of the present invention, the back contact cell further comprises a front passivation layer and an anti-reflection layer sequentially arranged on the front side of the silicon wafer. The types and thicknesses of the front passivation layer and the anti-reflection layer in the present invention can refer to the prior art and can be used in the present invention. Exemplarily, the front passivation layer can be one or more of silicon oxide, amorphous silicon, and aluminum oxide. Exemplarily, the thickness of the front passivation layer can be 2-30nm. Exemplarily, the anti-reflection layer can be a silicon dielectric film, and the silicon dielectric film can be silicon nitride, silicon oxynitride, silicon oxide, etc. Exemplarily, the thickness of the anti-reflection layer is 50-180nm.

[0084] In some preferred embodiments of the present invention, the first doped polysilicon layer is of N type, and the second doped crystalline silicon layer is of P type.

[0085] In a second aspect, the present invention provides a method for manufacturing a back contact battery with a specific passivation structure, comprising the following steps:

[0086] S101, providing silicon wafers;

[0087] S102, forming a first semiconductor layer and a mask layer in sequence on the back side of the silicon wafer, wherein the first semiconductor layer includes a first doped polysilicon layer;

[0088] S103, performing a first etching opening on the back surface obtained in S102 to form a second semiconductor opening region;

[0089] S104, texturing and cleaning, followed by or without a step of removing at least a portion of the mask layer;

[0090] S107, depositing an amorphous silicon layer and a second doped amorphous film layer in sequence on the back side;

[0091] S108, performing a second etching opening on the corresponding portion of the second semiconductor layer superimposed outside the first semiconductor layer on the back side of the silicon wafer to form a first semiconductor opening region spaced apart from the second semiconductor opening region;

[0092] S109, laser scribing is performed on at least a portion of the second doped amorphous film layer corresponding to the second semiconductor opening region, so that a portion of the second doped amorphous film layer in the laser scribing region is crystallized to form a second doped microcrystalline region, and the non-crystallized amorphous silicon region is the second doped amorphous region, thereby forming a second semiconductor layer; during the process, the crystallization rate of the second doped microcrystalline region is controlled to be 5%-80% by laser scribing;

[0093] S110, depositing a conductive film layer on the back side.

[0094] In some preferred embodiments of the present invention, the laser scribing conditions in S109 include: the laser pulse width is less than 100 ps, ​​the laser energy density is 0.2-5 mJ / mm 2 The adoption of this preferred solution is more conducive to obtaining the target second doped microcrystalline region while reducing the impact on the battery interface passivation.

[0095] In some preferred embodiments of the present invention, the laser wavelength of the laser scribing in S109 is 300-1100 nm, such as 1064 nm, 532 nm, 354 nm, etc.

[0096] In some preferred embodiments of the present invention, the manufacturing method further comprises performing, after S104 and before S107:

[0097] S105, sequentially forming a front passivation layer and an anti-reflection layer on the front side of the silicon wafer;

[0098] S106, cleaning is performed to ensure the cleanliness of the interface of the second semiconductor opening area on the back side of the silicon wafer.

[0099] The cleaning in S106 can use an RCA standard solution, which can be, for example, standard cleaning solution No. 1 (SC1) and standard cleaning solution No. 2 (SC2). Standard cleaning solution No. 1 is a mixture of NH4OH / H2O2 / H2O (ammonia water / hydrogen peroxide / water) in a mass ratio of 1:1:5, and standard cleaning solution No. 2 is a mixture of HCL / H2O2 / H2O (hydrochloric acid / hydrogen peroxide / water) in a mass ratio of 1:1:6.

[0100] In some preferred embodiments of the present invention, the manufacturing method further comprises, after S110, performing:

[0101] S111, performing a third etching opening on a portion of the conductive film layer located between the first semiconductor opening region and the second semiconductor opening region to form an isolation groove;

[0102] S112, forming metal electrodes on the outer surfaces of the corresponding conductive film layers in the areas where the first semiconductor opening region and the second semiconductor opening region are located.

[0103] In a third aspect, the present invention provides a back contact battery, which includes a back contact battery made by the method for making a back contact battery with a specific passivation structure described in the second aspect. The back contact battery in the third aspect has the same structure as the back contact battery in the first aspect, and will not be described in detail here.

[0104] In a fourth aspect, the present invention provides a battery assembly, which includes the back contact battery with a specific passivation structure described in the first aspect, or includes the back contact battery described in the third aspect. The battery assembly may include, for example, any component in any form including a battery module or the like containing the back contact battery of the present invention.

[0105] The embodiments of the present invention are described in detail below, which are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0106] Example 1

[0107] A back contact battery is prepared by the following manufacturing method:

[0108] S101, such as Figure 1 As shown, a double-sided polished silicon wafer 1 is provided;

[0109] S102, such as Figure 2As shown, a first semiconductor layer and a mask layer 4 are sequentially formed on the back of the silicon wafer 1. The first semiconductor layer includes a tunneling oxide layer 2 with a thickness of 1.5 nm and an N-type doped polysilicon layer 3 (i.e., a first doped polysilicon layer); the thickness of the N-type doped polysilicon layer 3 is 120 nm, and the effective doping concentration is 1e20 cm -3 ;

[0110] S103, such as Figure 3 As shown, a first etching opening is performed on the back surface obtained in S102 to form a second semiconductor opening region W1 with a width of 500 μm;

[0111] S104, such as Figure 4 As shown, texturing cleaning is performed to form a texturing surface on the front side of the silicon wafer 1 and the second semiconductor opening area W1 at the same time, and then all mask layers 4 outside the second semiconductor opening area W1 on the back side of the silicon wafer 1 are removed;

[0112] S105, such as Figure 5 As shown, a front passivation layer 5 and an anti-reflection layer 6 are formed on the front side of the silicon wafer 1;

[0113] S106, cleaning with a conventional RCA standard solution (No. 1 standard cleaning solution, composed of NH4OH / H2O2 / H2O mixed in a mass ratio of 1:1:5) so that the interface cleanliness of the second semiconductor opening area W1 on the back side of the silicon wafer 1 meets the requirements for depositing the second semiconductor layer;

[0114] S107, such as Figure 6 As shown, in S106, an intrinsic amorphous silicon layer 7 (i.e., an amorphous silicon layer) with a thickness of 6 nm and a P-type doped amorphous silicon layer 81 (i.e., a second doped amorphous film layer) are deposited on the back side. The P-type doped amorphous silicon layer 81 has a thickness of 20 nm and an effective doping concentration of 1e19 cm -3 ;

[0115] S108, performing a second etching on the intrinsic amorphous silicon layer 7 (amorphous silicon layer) and the P-type doped amorphous silicon layer 81 above the first semiconductor layer vertical stack on the back side of the silicon wafer 1 to form a first semiconductor opening region W2 spaced apart from the second semiconductor opening region W1;

[0116] S109, laser scribing the corresponding portion of the P-type doped amorphous silicon layer 81 in the second semiconductor opening region W1, so that the P-type doped amorphous silicon layer 81 in the laser scribing region is partially crystallized to form P-type microcrystalline silicon 82 (i.e., the second doped microcrystalline region), such as Figure 7 As shown, the uncrystallized amorphous silicon region is a P-type second doped amorphous region, the second doped microcrystalline region and the second doped amorphous region form a second doped crystalline silicon layer, and the amorphous silicon layer forms a second semiconductor layer. The laser scribing conditions include: laser pulse width 50ps, laser power density 0.2mJ / mm 2, the wavelength is 532nm, the crystallization rate of the P-type microcrystalline silicon 82 is 30%, and the conductivity is 1 (Ω·cm) -1 . The conductivity ratio of the second doped microcrystalline region (P-type microcrystalline silicon 82) to the second doped amorphous region is 1e2:1. The width of the second doped microcrystalline region is 60% of the width of the second semiconductor opening region W1. The thickness ratio of the second doped microcrystalline region to the first doped polycrystalline silicon layer and the amorphous silicon layer is 1:6:0.3 after conversion. The area of ​​the second doped microcrystalline region accounts for 40% of the area of ​​the second doped crystalline silicon layer, and the body resistivity of the second doped crystalline silicon layer is 1e3Ω·cm.

[0117] S110, such as Figure 8 As shown, a transparent conductive film layer 9 (ITO) with a thickness of 60 nm is deposited on the back surface obtained in S109, and the ratio of the thickness of the second doped microcrystalline region to the transparent conductive film layer 9 is 0.33:1 after conversion;

[0118] S111, such as Fig. 9 As shown, a third etching opening is performed on a portion of the transparent conductive film layer 9 between the first semiconductor opening region W2 and the second semiconductor opening region W1 to form an isolation groove W3;

[0119] S112, such as Fig.10 As shown, metal electrodes 10 are formed on the outer surfaces of the corresponding transparent conductive film layer 9 in the areas where the first semiconductor opening area W2 and the second semiconductor opening area W1 are located.

[0120] Example 2

[0121] The method is carried out in accordance with Example 1, except that the crystallization rate of the second doped microcrystalline region is adjusted to 70%, and the conductivity of the second doped microcrystalline region is adjusted to 10 (Ω·cm). -1 , so that the conductivity ratio of the second doped microcrystalline region to the second doped amorphous region is 1e3:1. To meet this condition, the corresponding process parameters that need to be modified are: laser capacity density is 0.6mJ / mm 2 .

[0122] Example 3

[0123] The same method is performed with reference to Example 1, except that the width of the second doped microcrystalline region is adjusted to 90% of the width of the second semiconductor opening region, and the width of the second doped microcrystalline region is 450 μm. The corresponding process parameters that need to be modified to meet this condition are: the laser scribing width in the second semiconductor opening region is 450 μm.

[0124] Example 4

[0125] The method is carried out with reference to Example 1, except that the thickness of the second doped microcrystalline region and the second doped amorphous region are both adjusted to 10 nm, and specifically, the thickness of the second doped amorphous film layer is directly controlled to be 10 nm in S107.

[0126] Example 5

[0127] The process is carried out with reference to Example 1, except that the thickness of the first doped polysilicon layer is adjusted to 80 nm, so that the thickness ratio of the second doped microcrystalline region to the first doped polysilicon layer is 1:4.

[0128] Comparative Example 1

[0129] The process is carried out with reference to Example 1, except that no second doped microcrystalline region is formed, that is, the second semiconductor layer is composed of an amorphous silicon layer and a P-type doped amorphous silicon layer arranged in sequence; to satisfy this structure, laser scribing in S109 is not performed accordingly.

[0130] Comparative Example 2

[0131] The process is carried out with reference to Example 1, except that the second doped crystalline silicon layer is a P-type doped microcrystalline silicon layer without P-type doped amorphous silicon, that is, the amorphous silicon layer and the P-type doped microcrystalline silicon layer are directly deposited in S107, and S109 is not performed, but S110 is performed subsequently.

[0132] Comparative Example 3

[0133] The method is carried out in accordance with Example 1, except that the crystallization rate of the second doped microcrystalline region is adjusted to 1%, and the conductivity of the second doped microcrystalline region is adjusted to 80 (Ω·cm). -1 To meet this condition, the corresponding process parameters that need to be modified are: laser capacity density is 0.05mJ / mm 2 .

[0134] Test Case

[0135] The back contact cells obtained in the above examples and comparative examples were subjected to performance tests, and the results are shown in Table 1.

[0136] Table 1

[0137]

[0138] It can be seen from the above results that, compared with the comparative example, the embodiment scheme of the present invention can significantly reduce the bulk resistivity of the second doped crystalline silicon layer and the contact resistivity between the second doped crystalline silicon layer and the conductive film layer, thereby significantly reducing the series resistance of the battery, while effectively avoiding leakage current and improving battery efficiency.

[0139] Furthermore, according to Example 1 and Examples 2-5, it can be seen that the preferred solution of the present invention is more conducive to reducing the series resistance of the battery, while effectively avoiding leakage current and improving battery efficiency.

[0140] The preferred embodiments of the present invention are described in detail above, but the present invention is not limited thereto. Within the technical concept of the present invention, the technical solution of the present invention can be subjected to a variety of simple modifications, including the combination of various technical features in any other suitable manner, and these simple modifications and combinations should also be regarded as the contents disclosed by the present invention and belong to the protection scope of the present invention.

Claims

1. A back contact battery with a specific passivation structure, comprising a silicon wafer, a first semiconductor layer and a second semiconductor layer alternately arranged on the back of the silicon wafer, and a conductive film layer arranged outside the first semiconductor layer and the second semiconductor layer, wherein a second semiconductor opening region is formed between adjacent first semiconductor layers, two ends of the second semiconductor layer respectively extend outward to cover the back of the adjacent first semiconductor layer, and a first semiconductor opening region not covering the second semiconductor layer is opened on the back of the first semiconductor layer, and the first semiconductor layer includes a first doped polysilicon layer; characterized in that The second semiconductor layer comprises an amorphous silicon layer and a second doped crystalline silicon layer arranged in sequence from the back side of the silicon wafer outward, the second doped crystalline silicon layer comprises a second doped microcrystalline region and a second doped amorphous region located on both sides of the second doped microcrystalline region, the second doped microcrystalline region is located at a position corresponding to the second semiconductor opening region and in contact with the conductive film layer, and the second doped amorphous region is laid outside the back side end of the first doped polycrystalline silicon layer and its adjacent part; wherein the crystallization rate of the second doped microcrystalline region is 5%-80%, the ratio of the conductivity of the second doped microcrystalline region to the second doped amorphous region is (1e1-1e6): 1, and the conductivity of the second doped microcrystalline region is 1e-1 (Ω·cm) -1 -5e2(Ω·cm) -1 .

2. The back contact battery with a specific passivation structure according to claim 1, characterized in that: The width of the second doped microcrystalline region is 20%-90% of the width of the second semiconductor opening region.

3. The back contact battery with a specific passivation structure according to claim 1, characterized in that: The thickness ratio of the second doped microcrystalline region to the conductive film layer is (0.1-1):

1.

4. The back contact battery with a specific passivation structure according to claim 1, characterized in that: The width of the second doped microcrystalline region is 10-500 μm, and / or The thickness of the second doped microcrystalline region is 5-36 nm, and the thickness of the second doped amorphous region is 6-36 nm.

5. The back contact battery with a specific passivation structure according to any one of claims 1 to 4, characterized in that: The thickness of the second doped microcrystalline region is the same as the thickness of the second doped amorphous region, and / or the ratio of the thickness of the second doped microcrystalline region to the first doped polysilicon layer and the amorphous silicon layer is 1:(2-20):(0.2-1.5).

6. The back contact battery with a specific passivation structure according to claim 1, characterized in that: The area of ​​the second doped microcrystalline region accounts for 10%-80% of the area of ​​the second doped crystalline silicon layer, and / or the body resistivity of the second doped crystalline silicon layer is 1e2Ω·cm-1e7Ω·cm.

7. The back contact battery with a specific passivation structure according to claim 1, characterized in that: The back contact cell also has at least one of the following structures: Structure 1: The first semiconductor layer further comprises a tunneling oxide layer, and the tunneling oxide layer is located between the silicon wafer and the first doped polysilicon layer; Structure 2: The portion of the silicon wafer located at the position of the second semiconductor opening area is a textured surface, a polished surface, or a semi-polished structure in between the textured surface and the polished surface, and the portion of the silicon wafer at the position corresponding to the first semiconductor layer is a polished surface; the front side of the silicon wafer is a textured surface, a polished surface, or a semi-polished structure in between the textured surface and the polished surface; Structure 3: The second semiconductor opening region and the first semiconductor opening region are arranged at intervals and the area between them is a spacing region, an isolation groove is provided on the portion of the conductive film layer located in the spacing region, and a mask layer is provided between the first semiconductor layer and the second semiconductor layer in the spacing region or no mask layer is provided; Structure 4: The back contact battery further includes a metal electrode, which is arranged on the outer surface of the conductive film layer corresponding to the second semiconductor opening region and the first semiconductor opening region; Structure 5. The back contact cell also includes a front passivation layer and an anti-reflection layer sequentially arranged on the front side of the silicon wafer; Structure 6: The first doped polysilicon layer is N-type, and the second doped crystalline silicon layer is P-type; Structure 7: The thickness of the amorphous silicon layer is 6-50nm.

8. A method for manufacturing a back contact battery with a specific passivation structure, characterized in that: The steps include: S101, providing silicon wafers; S102, forming a first semiconductor layer and a mask layer in sequence on the back side of the silicon wafer, wherein the first semiconductor layer includes a first doped polysilicon layer; S103, performing a first etching opening on the back surface obtained in S102 to form a second semiconductor opening region; S104, texturing and cleaning, followed by or without a step of removing at least a portion of the mask layer; S107, depositing an amorphous silicon layer and a second doped amorphous film layer in sequence on the back side; S108, performing a second etching opening on the corresponding portion of the second semiconductor layer superimposed outside the first semiconductor layer on the back side of the silicon wafer to form a first semiconductor opening region spaced apart from the second semiconductor opening region; S109, laser scribing is performed on at least a portion of the second doped amorphous film layer corresponding to the second semiconductor opening region, and a portion of the second doped amorphous film layer in the laser scribing region is crystallized to form a second doped microcrystalline region, and the non-crystallized amorphous silicon region is the second doped amorphous region, thereby forming a second semiconductor layer; during the process, the crystallization rate of the second doped microcrystalline region is controlled by laser scribing to be 5%-80%; the ratio of the conductivity of the second doped microcrystalline region to the second doped amorphous region is (1e1-1e6): 1, the conductivity of the second doped microcrystalline region is 1e-1 (Ω·cm) -1 -5e2(Ω·cm) -1 ; S110, depositing a conductive film layer on the back side.

9. The method for manufacturing a back contact battery with a specific passivation structure according to claim 8, characterized in that: The conditions for laser scribing in S109 include: laser pulse width less than 100ps, laser energy density of 0.2-5mJ / mm 2 ; and / or, the laser wavelength of the laser scribing is 300-1100nm.

10. The method for manufacturing a back contact battery with a specific passivation structure according to claim 8, characterized in that: The manufacturing method further includes performing the following steps after S104 and before S107: S105, sequentially forming a front passivation layer and an anti-reflection layer on the front side of the silicon wafer; S106, performing cleaning to ensure the cleanliness of the interface of the second semiconductor opening region on the back side of the silicon wafer; And / or, the manufacturing method further includes, after S110, performing: S111, performing a third etching opening on a portion of the conductive film layer located between the first semiconductor opening region and the second semiconductor opening region to form an isolation groove; S112, forming metal electrodes on the outer surfaces of the corresponding conductive film layers in the areas where the first semiconductor opening region and the second semiconductor opening region are located.

11. A back contact battery, characterized in that: It comprises a back contact battery manufactured by the method for manufacturing a back contact battery with a specific passivation structure as described in any one of claims 8 to 10.

12. A battery assembly, characterized in that: It comprises a back contact cell having a specific passivation structure as claimed in any one of claims 1 to 7, or comprises a back contact cell as claimed in claim 11.

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