Chip structure and fabrication method of LED with dual-channel hole injection function

Abstract

This invention relates to a chip structure for an LED with dual-channel hole injection capability and its fabrication method. The structure involves epitaxially growing a sandwich-structure intrinsic layer and an N-type GaN layer on a P-type GaN layer. Specifically, the GaN layer above the P-region completely absorbs photons. After photon absorption, photogenerated electrons and holes are generated. By adjusting the electric field of this portion of the material, the photogenerated holes can be re-injected into the quantum well and emit photons through radiative recombination. This effectively avoids the problem in traditional methods where the top GaN layer absorbs photons but the photogenerated holes are not effectively utilized. This invention significantly improves the photon utilization rate at the top of the device, thereby increasing the light output from the substrate.

Description

Technical Field

[0001] The technical solution of this invention relates to the field of semiconductor light-emitting devices, specifically to a chip structure of an LED with a PIN structure and a method for its fabrication. Background Technology

[0002] In recent years, deep-ultraviolet light-emitting diodes (DUV LEDs) have demonstrated enormous application potential in various fields such as sensors, sterilization and disinfection, air purification, water treatment, and optical communication. Compared with traditional mercury lamps, AlGaN-based DUV LEDs are not only non-toxic and environmentally friendly, but also possess significant advantages such as small size, long lifespan, fast response speed, and strong controllability. These advantages have provided valuable opportunities for the research and development of related technologies, promoting the widespread application of deep-ultraviolet light sources across various industries.

[0003] For DUV LEDs with shorter emission wavelengths, achieving high wall-plug efficiency (WPE) and high external quantum efficiency (EQE) still faces numerous challenges in terms of physical mechanisms and processing technology. As the wavelength decreases further, the EQE of DUV LEDs typically declines, leading to a significant reduction in luminous efficiency. Low light extraction efficiency (LEE) is the primary cause of this problem. In traditional LEDs, due to the difficulty of p-type doping of AlGaN materials, a heavily doped GaN layer is typically used on the top layer to achieve good ohmic contacts. However, the severe absorption of ultraviolet light by GaN materials and electrodes results in low light extraction efficiency. This problem is particularly prominent in short-wavelength DUV LEDs; as the emission wavelength decreases, the absorption effect becomes more significant, further affecting the light output performance of the LED. Therefore, solving the material absorption problem and optimizing light extraction efficiency have become key technical challenges for improving the performance of short-wavelength DUV LEDs.

[0004] To improve the light extraction efficiency of chips, patent CN119069586A proposes a method using a photonic crystal structure, but its fabrication process is complex and requires high-precision manufacturing processes. Another patent, CN118610328A, proposes a surface roughening technique, but it faces significant technical challenges due to its use of dry etching or wet etching processes. Literature DOI: 10.1109 / LED.2024.3351857 proposes thinning the GaN layer to reduce light absorption, but this introduces problems such as current congestion. Therefore, to further improve the luminous efficiency of light-emitting diodes (LEDs), including both internal and external quantum efficiency, optimizing the epitaxial structure of the LED to improve its luminous performance is particularly important. Summary of the Invention

[0005] The purpose of this invention is to address the serious performance degradation problem caused by light absorption in traditional AlGaN-based LEDs. This invention proposes an LED chip structure with a PIN structure and its fabrication method. When photons are absorbed by a material, their energy is transferred to electrons within the material, exciting them to transition from the valence band to the conduction band, forming electron-hole pairs. However, in traditional LED structures, the electric field near the absorption layer is not effectively controlled, resulting in insufficient separation of photogenerated carriers and their inability to effectively participate in the light emission process. The proposed LED structure forms a sandwich structure by growing an intrinsic AlGaN layer and an N-type GaN layer above the P-type GaN capping layer of a traditional LED. By adjusting the thickness and composition of each intrinsic layer in the sandwich structure, as well as the doping concentration of the N-type GaN layer, the internal electric field of the ultraviolet light absorbing material layer can be precisely controlled. Through a rationally designed electric field, electron-hole pairs generated by photon absorption can be effectively separated, allowing photogenerated carriers to be re-injected into the LED's multiple quantum wells under the influence of the electric field, recombine with electrons in the wells, and generate radiative emission. Furthermore, the separation process of photogenerated carriers under the electric field also induces collisional ionization, thereby further improving photoelectric performance. Based on the absorption characteristics of the material and the emission spectrum of the quantum well, this invention can flexibly control the structure of the intrinsic layer and the doping concentration of the N-type GaN layer, making it suitable for ultraviolet LED applications of different wavelengths.

[0006] The technical solution of this invention is as follows:

[0007] A chip structure for an LED with dual-channel hole injection capability, comprising one of the following two structures:

[0008] The first type includes, from bottom to top, a substrate, a buffer layer, and an N-type electron injection layer; the N-type electron injection layer is divided into two parts, with the upper part exposed, the area of ​​which is 5% to 90% of the lower part, and the thickness of which is 10% to 80% of the entire N-type electron injection layer.

[0009] The upper layer of the N-type electron injection layer, from bottom to top, consists of a multi-quantum well layer, a P-type electron blocking layer, a P-type semiconductor transport layer, and a top P-contact layer. Above the top P-contact layer is a sandwich-like structure, consisting of two intrinsic layers and an intrinsic interlayer sandwiched between them. Above the interlayer structure is the top N-contact layer. An ohmic electrode is located in the middle of the top N-contact layer. An ohmic electrode is also located in the middle of the exposed portion of the lower layer of the N-type electron injection layer.

[0010] Alternatively, the second type includes, from bottom to top, a substrate, a buffer layer, and an N-type electron injection layer; wherein, the N-type electron injection layer is divided into two parts, with the upper part exposed, the area of ​​which is 5% to 90% of the lower part, and the thickness of which is 10% to 80% of the entire N-type electron injection layer.

[0011] The upper layer of the N-type electron injection layer consists of, from bottom to top, a multi-quantum well layer, a P-type electron blocking layer, a P-type semiconductor transport layer, and a top P-contact layer. Above the top P-contact layer is an array-distributed "sandwich-like" sandwich structure, consisting of two intrinsic layers and an intrinsic sandwich layer sandwiched between them. The array-distributed sandwich structure occupies 10% to 90% of the surface area of ​​the top P-contact layer, and the top N-contact layer is on top of the sandwich structure, together forming an array-distributed protruding structure. P-type ohmic electrodes cover the surface, sidewalls, and exposed top P-contact layer of the protruding structure.

[0012] An ohmic electrode is provided in the middle of the exposed portion of the lower layer of the N-type electron injection layer;

[0013] The substrate is sapphire, Si, SiC, AlN, quartz glass, or GaN.

[0014] The buffer layer is made of Al. x1 In y1 Ga 1-x1-y1 N, where 0≤x1≤1, 0≤y1≤1, 0≤1-x1-y1≤1, and the thickness is 10~2000nm.

[0015] The N-type electron injection layer is made of Al. x1 In y1 Ga 1-x1-y1 N, where 0≤x1≤1, 0≤y1≤1, 0≤1-x1-y1≤1, and the thickness is 2~8μm.

[0016] The material of the multi-quantum well layer is Al. x1 In y1 Ga 1-x1-y1 N / Al x2 In y2 Ga 1-x2-y2N, where 0≤x1≤1, 0≤y1≤1, 0≤1-x1-y1≤1, 0≤x2≤1, 0≤y2≤1, 0≤1-x2-y2≤1; where, quantum barrier Al x2 In y2 Ga 1-x2-y2 The thickness of N is 5–50 nm, and the quantum well Al x1 In y1 Ga 1-x1-y1 The thickness of N is 1–10 nm.

[0017] The material of the P-type electron blocking layer is Al. x3 In y3 Ga 1-x3-y3 N, where 0≤x3≤1, 0≤y3≤1, 0≤1-x3-y3, and the thickness is 10~500nm.

[0018] The P-type semiconductor transport layer Al x4 In y4 Ga 1-x4-y4 N, where 0≤x4≤1, 0≤y4≤1, 0≤1-x4-y4, and the thickness is 10~500nm.

[0019] The Al of the top P contact layer x5 In y5 Ga 1-x5-y5 N, where 0≤x5≤1, 0≤y5≤1, 0≤1-x5-y5, has a thickness of 1~500nm, and the material is heavily doped with P-type doping.

[0020] The first intrinsic layer is made of Al. x6 In y6 Ga 1-x6-y6 N, where 0≤x6≤1, 0≤y6≤1, 0≤1-x6-y6, has a thickness of 1~100nm and is not intentionally doped.

[0021] The intrinsic interlayer material is Al. x7 In y7 Ga 1-x7-y7 N, where 0≤x7≤x6, y6≤y7≤1, 0≤1-x7-y7, has a thickness of 1~100nm, and is not intentionally doped.

[0022] The top N-contact layer is made of Al. x8 In y8 Ga 1-x8-y8 N, where 0≤x8≤1, 0≤y8≤1, 0≤1-x8-y8, thickness is 10~1000nm, material is N-type heavily doped, and doping concentration is 10. 18 -10 21 cm -3.

[0023] The P-type ohmic electrode is made of Ni / Au, Cr / Au, Pt / Au, or Ni / Al.

[0024] The N-type ohmic electrode is made of N-type ohmic electrode material Al / Au, Cr / Au, or Ti / Al / Ti / Au.

[0025] The method for fabricating the LED chip structure with dual-channel hole injection function is one of the following two methods:

[0026] Method 1 includes the following steps:

[0027] The first step is to bake the substrate at 950°C to 1400°C in an MOCVD (Metal-Organic Chemical Vapor Deposition) or MBE (Molecular Beam Epitaxy) reactor.

[0028] The second step is to epitaxially grow a buffer layer with a thickness of 10 to 2000 nm on the surface of the substrate after the first step in a reactor.

[0029] In the third step, in the reactor, an N-type electron injection layer with a thickness of 2–8 μm and a quantum barrier Al are epitaxially grown sequentially on the buffer layer obtained in the second step. x2 In y2 Ga 1-x2-y2 The thickness of N is 5–50 nm, and the quantum well Al x1 In y1 Ga 1-x1-y1 N consists of a multi-quantum well layer with a thickness of 1–10 nm and a P-type electron blocking layer, a P-type semiconductor transport layer, and a top P-contact layer with a thickness of 100–500 nm.

[0030] In the fourth step, in the reactor, a first intrinsic layer and an intrinsic interlayer with a thickness of 1 to 100 nm and a top N contact layer with a thickness of 10 to 1000 nm are epitaxially grown sequentially on the epitaxial layer obtained in the third step.

[0031] The fifth step involves creating steps using photolithography and dry etching processes to expose the N-type electron injection layer.

[0032] The sixth step is to vapor deposit and photolithography to fabricate the N-type ohmic electrode;

[0033] Thus, a chip structure for an LED with dual-channel hole injection capability was obtained;

[0034] Alternatively, method two, the second method for fabricating an LED chip structure with dual-channel hole injection capability, includes the following steps:

[0035] The first step is to bake the substrate at 950°C to 1400°C in an MOCVD (Metal-Organic Chemical Vapor Deposition) or MBE (Molecular Beam Epitaxy) reactor.

[0036] The second step is to epitaxially grow a buffer layer with a thickness of 10 to 2000 nm on the surface of the substrate after the first step in a reactor.

[0037] In the third step, in the reactor, an N-type electron injection layer with a thickness of 2–8 μm and a quantum barrier Al are epitaxially grown sequentially on the buffer layer obtained in the second step. x2 In y2 Ga 1-x2-y2 The thickness of N is 5–50 nm, and the quantum well Al x1 In y1 Ga 1-x1-y1 N consists of a multi-quantum well layer with a thickness of 1–10 nm and a P-type electron blocking layer, a P-type semiconductor transport layer, and a top P-contact layer with a thickness of 100–500 nm.

[0038] In the fourth step, in the reactor, a first intrinsic layer and an intrinsic interlayer with a thickness of 1 to 100 nm and a top N contact layer with a thickness of 10 to 1000 nm are epitaxially grown sequentially on the epitaxial layer obtained in the third step.

[0039] The fourth step involves creating steps using photolithography and dry etching processes to expose the aforementioned N-type electron injection layer.

[0040] The fifth step involves patterning the first intrinsic layer, the intrinsic interlayer, and the top N contact layer using photolithography and dry etching processes, partially exposing the top P contact layer.

[0041] The sixth step involves vapor deposition and photolithography to fabricate an N-type ohmic electrode made of Ti / Al / Ti / Au and a P-type ohmic electrode made of Ni / Au.

[0042] Thus, a chip structure for an LED with dual-channel hole injection function was successfully fabricated.

[0043] The above-mentioned method for fabricating an LED chip structure involves an epitaxial growth process performed using metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), or plasma-enhanced chemical vapor deposition (PECVD) systems known in the art.

[0044] The above-mentioned method for fabricating an LED chip structure involves obtaining the P-type ohmic electrode and the N-type ohmic electrode using electron beam deposition (E-beam) or magnetron sputtering methods known in the art.

[0045] The above-mentioned method for fabricating an LED chip structure, wherein the photolithography process, dry etching process, and vapor deposition process are known in the art.

[0046] The essential features of this invention are:

[0047] Current technologies primarily focus on preventing materials from absorbing ultraviolet light to improve light extraction efficiency, with common methods including patterning and dielectric cavities. However, these methods typically involve complex process flows.

[0048] This invention proposes an innovative solution: epitaxially growing an intrinsic layer and an N-type GaN layer on a conventional P-type GaN layer, allowing the GaN layer above the P-region to completely absorb photons. After the material absorbs photons, photogenerated electrons and holes are generated. By adjusting the electric field of this portion of the material, the photogenerated holes can be re-injected into the quantum well and emit photons through radiative recombination. This effectively avoids the problem in traditional methods where the top GaN layer absorbs photons but the photogenerated holes are not effectively utilized. Since ultraviolet LEDs emit light from the substrate, this method can significantly improve the photon utilization rate at the top of the device, thereby increasing the light output from the substrate.

[0049] Regarding electric field modulation, this patent proposes a sandwich structure (see Examples 2 and 3), which utilizes the polarization effect of AlGaN material and its built-in electric field. By adjusting the material composition and thickness of the intrinsic layer, as well as the thickness of the N-type GaN above it, the intensity and range of influence of the electric field can be flexibly controlled, thereby achieving effective control of photogenerated holes.

[0050] The beneficial effects of this invention are:

[0051] (1) The LED structure proposed in this invention grows an intrinsic layer and an N-type GaN layer above the P-type GaN capping layer of a conventional LED. By adjusting the thickness and composition of the intrinsic layer and the doping concentration of the N-type GaN layer, the internal electric field of the ultraviolet light absorbing material layer is precisely controlled. This effectively separates the electron-hole pairs generated after the material absorbs photons, allowing photogenerated carriers to be re-injected into the LED's multiple quantum wells under the influence of the electric field, and recombine with electrons in the quantum wells, thereby generating radiative emission. (See attached diagram) Figure 10 As shown, the hole concentration of the lower quantum well with the PIN structure of this patent in Example 3 is increased by nearly 200% compared with the conventional structure in Example 1.

[0052] (2) The LED structure of the present invention has extremely high flexibility. The thickness of the intrinsic layer, the material composition, and the doping concentration of the N-type GaN layer can be adjusted according to the absorption characteristics of the material and the emission spectrum of the quantum well. This flexible adjustment mechanism enables the LED structure of the present invention to adapt to the application requirements of ultraviolet LEDs of different wavelengths, especially in special fields such as ultraviolet light irradiation and disinfection.

[0053] (3) The preparation method proposed in this invention is simple and easy to implement, with convenient operation and strong repeatability, which can effectively reduce the instability in the production process. In addition, the preparation process of this invention has low cost, and the materials and processes used are relatively common and mature, thus having good prospects for industrial application. Attached Figure Description

[0054] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0055] Figure 1 This is a schematic diagram of the structure of a standard LED device in the prior art.

[0056] Figure 2 For standard LEDs, Figure 1 The diagram shows the structure of the product after steps are created by photolithography and dry etching, exposing the N-type electron injection layer.

[0057] Figure 3 For standard LEDs, Figure 2 The diagram shown is a schematic of the structure of a standard LED chip, which is obtained by photolithography and metal evaporation to fabricate N-type and P-type electrodes, namely Example 1.

[0058] Figure 4 This is a schematic diagram of the epitaxial structure of the first and second intrinsic layers, the intrinsic interlayer, and the top N contact layer grown on the surface of the top P contact layer of the standard LED epitaxial wafer in Example 2.

[0059] Figure 5 This is a schematic diagram of the structure of the product after steps are created by photolithography and dry etching in Example 2, exposing part of the N-type electron injection layer.

[0060] Figure 6 This is a schematic diagram of the structure of an LED chip of the present invention, obtained by photolithography and metal evaporation to fabricate an N-type electrode in Example 2.

[0061] Figure 7 This is a schematic diagram of the structure of the product after the first and second intrinsic layers, the intrinsic interlayer and the top N contact layer are patterned by photolithography and dry etching in Example 3, exposing part of the ohmic contact layer.

[0062] Figure 8 This is a schematic diagram of the structure of an LED chip of the present invention, obtained by photolithography and metal evaporation to fabricate N-type and P-type electrodes in Example 3.

[0063] Figure 9 The IV curves are for the standard LED device, namely Example 1 and Example 3 of the device structure of the present invention.

[0064] Figure 10 The lateral one-dimensional hole concentration distribution in the last quantum well of the standard LED device, namely Example 1 and Example 3 of the device structure of the present invention.

[0065] Among them, 101. Substrate, 102. Buffer layer, 103. N-type electron injection layer, 104. Multiple quantum well layer, 105. P-type electron blocking layer, 106. P-type semiconductor transport layer, 107. Top P contact layer, 108. N-type ohmic electrode, 109. P-type ohmic electrode, 110. First intrinsic layer, 111. Intrinsic interlayer, 112. Top N contact layer. Detailed Implementation

[0066] The present invention will be further described below with reference to embodiments and accompanying drawings, but this should not be construed as limiting the scope of protection of the claims of this application.

[0067] The preparation methods involved include photolithography, etching, and metal evaporation, all of which are common processes, and the raw materials involved can be obtained through general means.

[0068] Figure 1 The illustrated embodiment shows that the standard LED epitaxial wafer structure in the prior art includes: a substrate 101, a buffer layer 102, an N-type electron injection layer 103, a multiple quantum well layer 104, a P-type electron blocking layer 105, a P-type semiconductor transport layer 106, and a top P-contact layer 107.

[0069] Example 1 (Comparative Example)

[0070] The LED chip structure of this embodiment includes, from bottom to top, a substrate 101, a buffer layer 102, an N-type electron injection layer 103, an N-type ohmic electrode 108 formed on the N-type electron injection layer 103, a multiple quantum well layer 104, a P-type electron blocking layer 105, a P-type semiconductor transport layer 106, a top P-contact layer 107, and a P-type ohmic electrode 109 formed on the top P-contact layer 107.

[0071] In the above, the substrate 101 is sapphire; the buffer layer 102 is made of AlN with a thickness of 2μm; and the N-type electron injection layer 103 is made of Al. 0.82 Ga 0.18 N, with a thickness of 4 μm; the multi-quantum well layer 104 is made of Al. 0.6 Ga 0.4 N / Al 0.8 Ga 0.2 N, where the quantum barrier Al 0.8 Ga 0.2 The thickness of N is 9 nm, and the quantum well Al 0.6 Ga 0.4The thickness of N is 1 nm; the material of the P-type electron blocking layer 105 is Al. 0.82→0.67 Ga 0.18→0.33 N, with a thickness of 40nm, the P-type semiconductor transport layer 106 is made of Al. 0.67→0 Ga 0.33→0 The N-type ohmic electrode 108 is made of GaN with a thickness of 10 nm. The top P-type contact layer 107 is made of GaN with a thickness of 2 nm. The N-type ohmic electrode 108 is made of Ti / Al / Ti / Au with a thickness of 20 / 30 / 60 / 100 nm. The P-type ohmic electrode 109 is made of Ni / Au with a thickness of 10 / 10 nm.

[0072] The method for fabricating the above-mentioned LED chip structure includes the following steps:

[0073] The first step is to bake the sapphire substrate 101 at 1200°C in a reactor to remove foreign matter from the substrate surface.

[0074] The second step is to epitaxially grow a buffer layer 102 with a thickness of 2 μm made of AlN on the surface of the sapphire substrate 101 after the first step in the reactor.

[0075] In the third step, in the reactor, an N-type electron injection layer 103 with a thickness of 4 μm and a multi-quantum well layer 104 made of Al are epitaxially grown sequentially on the buffer layer obtained in the second step. 0.6 Ga 0.4 N / Al 0.8 Ga 0.2 N, where the quantum barrier Al 0.8 Ga 0.2 The thickness of N is 9 nm, and the quantum well Al 0.6 Ga 0.4 The thickness of N is 1 nm; the material of the P-type electron blocking layer 105 is Al. 0.82→0.67 Ga 0.18→ 0.33 N, with a thickness of 40nm, the P-type semiconductor transport layer 106 is made of Al. 0.67→0 Ga 0.33→0 The N layer has a thickness of 10nm. The top P-contact layer 107 is made of GaN and has a thickness of 2nm.

[0076] The fourth step involves creating steps using photolithography and dry etching processes to expose the aforementioned N-type electron injection layer 103 (see [link to process]). Figure 2 );

[0077] The fifth step involves vapor deposition and photolithography to fabricate an N-type ohmic electrode 108 made of Ti / Al / Ti / Au and a P-type ohmic electrode 109 made of Ni / Au (see [link to documentation] for this process). Figure 3 );

[0078] Thus, an LED chip structure of this embodiment is obtained.

[0079] In standard LED devices, a heavily doped GaN layer is typically used as the top layer to achieve good ohmic contact. However, the significant absorption of ultraviolet light by GaN materials and their electrodes leads to low light extraction efficiency. Therefore, solving the light absorption problem is a pressing challenge to improve the optoelectronic performance of the device.

[0080] Example 2

[0081] The first type of LED chip structure with dual-channel hole injection function includes, from bottom to top, a substrate 101, a buffer layer 102, and an N-type electron injection layer 103; wherein, the N-type electron injection layer 103 is divided into two parts, the upper part is exposed, the area of ​​the exposed part is 5% to 90% of the lower layer (30% in this embodiment), and the thickness is 10% to 80% of the entire N-type electron injection layer 103 (20% in this embodiment);

[0082] The upper layer of the N-type electron injection layer 103, from bottom to top, consists of a P-type electron blocking layer 105, a P-type semiconductor transport layer 106, and a top P-contact layer 107. The top P-contact layer 107 has a sandwich-like structure, consisting of two intrinsic layers 110 and an intrinsic interlayer 111 sandwiching between them. Above the interlayer structure is a top N-contact layer 112. An ohmic electrode 108 is covered in the middle of the top N-contact layer 112. An ohmic electrode 108 is also provided in the middle of the exposed portion of the lower layer of the N-type electron injection layer 103.

[0083] In the above description, the substrate 101 is sapphire, and the fabricated device is typically in the shape of a square, rectangle, or circle (specifically, a square in this embodiment), with a size of 350 × 350 μm. 2 The buffer layer 102 is made of AlN and has a thickness of 2μm; the N-type electron injection layer 103 is made of Al. 0.82 Ga 0.18 N, with a thickness of 4 μm; the multi-quantum well layer 104 is made of Al. 0.6 Ga 0.4 N / Al 0.8 Ga 0.2 N, where the quantum barrier Al 0.8 Ga 0.2 The thickness of N is 9 nm, and the quantum well Al 0.6 Ga 0.4 The thickness of N is 1 nm, and the number of quantum well pairs is 3; the material of the p-type electron blocking layer 105 is Al. 0.82→0.67 Ga 0.18→0.33 N, with a thickness of 40nm, the P-type semiconductor transport layer 106 is made of Al. 0.67→0 Ga0.33→0 The N layer has a thickness of 10 nm. The top P-contact layer 107 is made of GaN and has a thickness of 2 nm; the two intrinsic layers 110 are made of Al. 0.1 Ga 0.9 N, all with a thickness of 10 nm, the intrinsic interlayer 111 is made of GaN with a thickness of 30 nm, and the top N contact layer 112 is also made of GaN with a doping concentration of 1 × 10⁻⁶. 20 cm -3 The thickness is 100nm. The N-type ohmic electrode 108 is made of Ti / Al / Ti / Au material with a thickness of 20 / 30 / 60 / 100nm.

[0084] The method for fabricating the above-mentioned LED chip structure includes the following steps:

[0085] The first step is to bake the sapphire substrate 101 at 1200°C in a reactor to remove foreign matter from the substrate surface.

[0086] The second step is to epitaxially grow a buffer layer 102 with a thickness of 2 μm made of AlN on the surface of the sapphire substrate 101 after the first step in the reactor.

[0087] In the third step, an N-type electron injection layer 103 with a thickness of 4 μm is epitaxially grown on the buffer layer obtained in the second step in the reactor; the multi-quantum well layer 104 is made of Al. 0.6 Ga 0.4 N / Al 0.8 Ga 0.2 N, where the quantum barrier Al 0.8 Ga 0.2 The thickness of N is 9 nm, and the quantum well Al 0.6 Ga 0.4 The thickness of N is 1 nm, and the number of quantum well pairs is 3; the material of the p-type electron blocking layer 105 is Al. 0.82→0.67 Ga 0.18→0.33 N, with a thickness of 40nm; the P-type semiconductor transport layer 106 is made of Al. 0.67→0 Ga 0.33→0 The N layer is 10nm thick; the top P-contact layer 107 is made of GaN and has a thickness of 2nm; the first intrinsic layer 110 is made of Al. 0.1 Ga 0.9 The first intrinsic layer has a thickness of 10 nm; the second intrinsic layer 111 is made of GaN with a thickness of 30 nm; and the third intrinsic layer 110 is made of Al. 0.1 Ga 0.9 The material of N, which is 10 nm thick, and the top N-contact layer 112, is GaN with a doping concentration of 1 × 10⁻⁶. 20 cm -3 The thickness is 100nm.

[0088] The fourth step involves creating steps using photolithography and dry etching processes to expose the aforementioned N-type electron injection layer 103 (see [link to process]). Figure 5 );

[0089] The fifth step involves vapor deposition and photolithography to fabricate an N-type ohmic electrode 108 made of Ti / Al / Ti / Au (see [link to documentation] for this process). Figure 6 );

[0090] Thus, an LED chip structure of this embodiment is obtained.

[0091] Example 3

[0092] The structural parameters of the chip epitaxy in this example are the same as those in Example 2.

[0093] The second type of LED chip structure with dual-channel hole injection function includes, from bottom to top, a substrate 101, a buffer layer 102, and an N-type electron injection layer 103; wherein, the N-type electron injection layer 103 is divided into two parts, the upper part is exposed, the area of ​​the exposed part is 5% to 90% of the lower layer (30% in this embodiment), and the thickness is 10% to 80% of the entire N-type electron injection layer 103 (20% in this embodiment);

[0094] The upper layer of the N-type electron injection layer 103, from bottom to top, consists of a P-type electron blocking layer 105, a P-type semiconductor transport layer 106, and a top P-contact layer 107. The top P-contact layer 107 has an array-distributed "sandwich-like" sandwich structure, consisting of two intrinsic layers 110 and an intrinsic interlayer 111 sandwiching between them. The array-distributed sandwich structure occupies 10% to 90% of the surface area of ​​the top P-contact layer 107 (specifically 50% in this embodiment). Above the sandwich structure is the top N-contact layer 112, together forming an array-distributed protruding structure. A P-type ohmic electrode 109 covers the surface, sidewalls, and exposed top P-contact layer 107 of the protruding structure.

[0095] An ohmic electrode 108 is disposed in the middle of the exposed portion of the lower layer of the N-type electron injection layer 103;

[0096] The second method for fabricating an LED chip structure with dual-channel hole injection capability includes the following steps:

[0097] The first step is to bake the sapphire substrate 101 at 1200°C in a reactor to remove foreign matter from the substrate surface.

[0098] The second step is to epitaxially grow a buffer layer 102 with a thickness of 2 μm made of AlN on the surface of the sapphire substrate 101 after the first step in the reactor.

[0099] In the third step, an N-type electron injection layer 103 with a thickness of 4 μm is epitaxially grown on the buffer layer obtained in the second step in the reactor; the multi-quantum well layer 104 is made of Al. 0.6 Ga 0.4 N / Al 0.8 Ga 0.2 N, where the quantum barrier Al 0.8 Ga 0.2 The thickness of N is 9 nm, and the quantum well Al 0.6 Ga 0.4 The thickness of N is 1 nm; the material of the P-type electron blocking layer 105 is Al. 0.82→0.67 Ga 0.18→ 0.33 N, with a thickness of 40nm; the P-type semiconductor transport layer 106 is made of Al. 0.67→0 Ga 0.33→0 The N layer is 10nm thick; the top P-contact layer 107 is made of GaN and has a thickness of 2nm; the first and second intrinsic layers 110 are made of Al. 0.1 Ga 0.9 The N layer is 10 nm thick; the intrinsic interlayer 111 is made of GaN with a thickness of 30 nm and the top N contact layer 112 is made of GaN with a thickness of 100 nm.

[0100] The fourth step involves creating steps using photolithography and dry etching processes to expose the aforementioned N-type electron injection layer 103.

[0101] The fifth step involves patterning the first and second intrinsic layers 110, the intrinsic interlayer 111, and the top N-contact layer 112 using photolithography and dry etching processes, partially exposing the top P-contact layer 107 (see [link to process details]). Figure 7 );

[0102] Step 6: N-type ohmic electrode 108 made of Ti / Al / Ti / Au and P-type ohmic electrode 109 made of Ni / Au are fabricated by vapor deposition and photolithography (see [link to process]). Figure 8 );

[0103] In the above embodiments, the epitaxial growth process is performed using metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), or plasma-enhanced chemical vapor deposition (PECVD), all known in the art. The P-type ohmic electrode 108 and N-type ohmic electrode 109 are fabricated using electron beam deposition (E-beam) or magnetron sputtering methods, all known in the art; the photolithography, dry etching, and evaporation processes are also known in the art.

[0104] Figure 9The figures show the IV characteristic curves of the standard LED device (Example 1) and the device structures of Examples 2 and 3 of this invention, obtained through simulation calculations using Crosslight's APSYS software. As can be seen from the figures, Example 2 of this invention exhibits relatively poor IV performance due to the increased built-in electric field and depletion region width caused by the PIN structure. In contrast, Example 3 of this invention effectively improves the IV characteristics of the device through patterning of the intrinsic semiconductor layer and the N-type GaN layer.

[0105] Figure 10 The figure shows the lateral one-dimensional hole concentration distribution in the last quantum well of the standard LED device (i.e., Example 1) and the device structure of Example 3 of this invention. As can be seen from the figure, the hole concentration in the quantum well below the PIN structure is improved compared to the standard device. This further demonstrates that our proposed structure can effectively utilize photogenerated carriers, improve carrier injection, and thus enhance device performance.

[0106] Matters not covered in this invention are common knowledge.

Claims

1. A chip structure for an LED with dual-channel hole injection capability, characterized in that, The structure, from bottom to top, includes: The substrate consists of a buffer layer and an N-type electron injection layer. The N-type electron injection layer is divided into two parts: the upper part is exposed, and the area of ​​the exposed part is 5% to 90% of the area of ​​the lower part, while the thickness is 10% to 80% of the total thickness of the N-type electron injection layer. The upper layer of the N-type electron injection layer, from bottom to top, consists of a multi-quantum well layer, a P-type electron blocking layer, a hole transport layer, and a top P-contact layer. Above the top P-contact layer is a sandwich-like structure, consisting of two intrinsic layers and an intrinsic interlayer sandwiched between them. Above the interlayer structure is the top N-contact layer. An ohmic electrode is placed in the middle of the top N-contact layer. An ohmic electrode is also placed in the middle of the exposed portion of the lower layer of the N-type electron injection layer. The intrinsic layer material is Al. x6 In y6 Ga 1-x6-y6 N, where 0≤x6≤1, 0≤y6≤1, 0≤1-x6-y6, has a thickness of 1~100nm, and is not intentionally doped; The intrinsic interlayer material is Al. x7 In y7 Ga 1-x7-y7 N, where 0≤x7≤x6, y6≤y7≤1, 0≤1-x7-y7, and the thickness is 1~100nm, unintentionally doped; The top N-contact layer is made of Al. x8 In y8 Ga 1-x8-y8 N, where 0≤x8≤1, 0≤y8≤1, 0≤1-x8-y8, thickness is 10~1000nm, material is N-type heavily doped, and doping concentration is 10. 18 -10 21 cm -3 .

2. A chip structure for an LED with dual-channel hole injection capability, characterized in that: The structure, from bottom to top, includes: The substrate consists of a buffer layer and an N-type electron injection layer. The N-type electron injection layer is divided into two parts: the upper part is exposed, and the area of ​​the exposed part is 5% to 90% of the area of ​​the lower part, while the thickness is 10% to 80% of the total thickness of the N-type electron injection layer. The upper layer of the N-type electron injection layer, from bottom to top, consists of a multi-quantum well layer, a P-type electron blocking layer, a hole transport layer, and a top P-contact layer. Above the top P-contact layer is an array-distributed "sandwich-like" sandwich structure, consisting of two intrinsic layers and an intrinsic sandwich layer sandwiching between them. The array-distributed sandwich structure occupies 10% to 90% of the surface area of ​​the top P-contact layer, and the top N-contact layer is on top of the sandwich structure, together forming an array-distributed protruding structure. The P-type ohmic electrode covers the surface, sidewalls, and exposed top P-contact layer of the protruding structure. An ohmic electrode is provided in the middle of the exposed portion of the lower layer of the N-type electron injection layer; The intrinsic layer material is Al. x6 In y6 Ga 1-x6-y6 N, where 0≤x6≤1, 0≤y6≤1, 0≤1-x6-y6, has a thickness of 1~100nm, and is not intentionally doped; The intrinsic interlayer material is Al. x7 In y7 Ga 1-x7-y7 N, where 0≤x7≤x6, y6≤y7≤1, 0≤1-x7-y7, and the thickness is 1~100nm, unintentionally doped; The top N-contact layer is made of Al. x8 In y8 Ga 1-x8-y8 N, where 0≤x8≤1, 0≤y8≤1, 0≤1-x8-y8, thickness is 10~1000nm, material is N-type heavily doped, and doping concentration is 10. 18 -10 21 cm -3 .

3. The chip structure of an LED with dual-channel hole injection function as described in claim 1 or 2, characterized in that, The substrate is sapphire, Si, SiC, AlN, quartz glass, or GaN; The buffer layer is made of Al. x1 In y1 Ga 1-x1-y1 N, where 0≤x1≤1, 0≤y1≤1, 0≤1-x1-y1≤1, and the thickness is 10~2000nm; The N-type electron injection layer is made of Al. x1 In y1 Ga 1-x1-y1 N, where 0≤x1≤1, 0≤y1≤1, 0≤1-x1-y1≤1, and the thickness is 2~8μm; The material of the multi-quantum well layer is Al. x1 In y1 Ga 1-x1-y1 N / Al x2 In y2 Ga 1-x2-y2 N, where 0≤x1≤1, 0≤y1≤1, 0≤1-x1-y1≤1, 0≤x2≤1, 0≤y2≤1, 0≤1-x2-y2≤1; where, quantum barrier Al x2 In y2 Ga 1-x2-y2 The thickness of N is 5–50 nm, and the quantum well Al x1 In y1 Ga 1-x1-y1 The thickness of N is 1–10 nm; The material of the P-type electron blocking layer is Al. x3 In y3 Ga 1-x3-y3 N, where 0≤x3≤1, 0≤y3≤1, 0≤1-x3-y3, and the thickness is 10~500nm; The hole transport layer is made of Al. x4 In y4 Ga 1-x4-y4 N, where 0≤x4≤1, 0≤y4≤1, 0≤1-x4-y4, and the thickness is 10~500nm; The material of the top P contact layer is Al. x5 In y5 Ga 1-x5-y5 N, where 0≤x5≤1, 0≤y5≤1, 0≤1-x5-y5, has a thickness of 10~500nm, and the material is heavily doped with P-type doping.

4. The chip structure of an LED with dual-channel hole injection function as described in claim 1 or 2, characterized in that, The material of the P-type ohmic electrode is Ni / Au, Cr / Au, Pt / Au, or Ni / Al; The N-type ohmic electrode is made of N-type ohmic electrode material Al / Au, Cr / Au, or Ti / Al / Ti / Au.

5. The method for fabricating a chip structure of an LED with dual-channel hole injection function as described in claim 1, characterized in that, Includes the following steps: Method 1 includes the following steps: The first step is to bake the substrate at 950°C to 1400°C in an MOCVD (Metal-Organic Chemical Vapor Deposition) or MBE (Molecular Beam Epitaxy) reactor. The second step is to epitaxially grow a buffer layer with a thickness of 10 to 2000 nm on the surface of the substrate after the first step in a reactor. In the third step, in the reactor, an N-type electron injection layer with a thickness of 2–8 μm and a quantum barrier Al are epitaxially grown sequentially on the buffer layer obtained in the second step. x2 In y2 Ga 1-x2-y2 The thickness of N is 5–50 nm, and the quantum well Al x1 In y1 Ga 1-x1-y1 N consists of a multi-quantum well layer with a thickness of 1–10 nm and a P-type electron blocking layer, a P-type semiconductor transport layer, and a top P-contact layer with a thickness of 100–500 nm. In the fourth step, in the reactor, an intrinsic layer and an intrinsic interlayer with a thickness of 1 to 100 nm and a top N contact layer with a thickness of 10 to 1000 nm are epitaxially grown sequentially on the epitaxial layer obtained in the third step. The fifth step involves creating steps using photolithography and dry etching processes to expose the N-type electron injection layer. The sixth step is to vapor deposit and photolithography to fabricate the N-type ohmic electrode; Thus, a chip structure for an LED with dual-channel hole injection function was successfully fabricated.

6. The method for fabricating a chip structure of an LED with dual-channel hole injection function as described in claim 2, characterized in that, Includes the following steps: The first step is to bake the substrate at 950°C to 1400°C in an MOCVD (Metal-Organic Chemical Vapor Deposition) or MBE (Molecular Beam Epitaxy) reactor. The second step is to epitaxially grow a buffer layer with a thickness of 10 to 2000 nm on the surface of the substrate after the first step in a reactor. In the third step, in the reactor, an N-type electron injection layer with a thickness of 2–8 μm and a quantum barrier Al are epitaxially grown sequentially on the buffer layer obtained in the second step. x2 In y2 Ga 1-x2-y2 The thickness of N is 5–50 nm, and the quantum well Al x1 In y1 Ga 1-x1-y1 N consists of a multi-quantum well layer with a thickness of 1–10 nm and a P-type electron blocking layer, a P-type semiconductor transport layer, and a top P-contact layer with a thickness of 100–500 nm. In the fourth step, in the reactor, an intrinsic layer and an intrinsic interlayer with a thickness of 1 to 100 nm and a top N contact layer with a thickness of 10 to 1000 nm are epitaxially grown sequentially on the epitaxial layer obtained in the third step. The fourth step involves creating steps using photolithography and dry etching processes to expose the aforementioned N-type electron injection layer. The fifth step involves patterning the intrinsic layer, intrinsic interlayer, and top N contact layer using photolithography and dry etching processes, partially exposing the top P contact layer. The sixth step involves vapor deposition and photolithography to fabricate an N-type ohmic electrode made of Ti / Al / Ti / Au and a P-type ohmic electrode made of Ni / Au. Thus, a chip structure for an LED with dual-channel hole injection function was successfully fabricated.

Images