Tuning voltage tracker for receive / transmit phase locked loop (PLL) fast switching

Abstract

A method and apparatus for storing, for a phase-locked loop (PLL), a control voltage of the PLL when switching from a task mode to a standby mode, and restoring the control voltage of the PLL when switching back to the task mode. An example PLL circuit includes: a charge pump; a voltage controlled oscillator (VCO) having a control input coupled to an output of the charge pump via a node; and a tracking circuit coupled to the node. The tracking circuit is generally configured to: sample a voltage of the node during a task mode; saving a representation of the sampled voltage prior to entering a standby mode; and recovering the sampled voltage to the node using the saved representation of the sampled voltage to re-enter the task mode.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. patent application serial number 17 / 934,654, filed on September 23, 2022, which is hereby incorporated by reference into this application. Technical Field

[0003] Certain aspects of the present disclosure relate generally to electronic circuits, and more particularly to phase-locked loops (PLLs). Background Art

[0004] Wireless communication devices are widely deployed to provide various communication services, such as telephony, video, data, messaging, broadcast, etc. Such wireless communication devices may send and / or receive radio frequency (RF) signals via any of a variety of suitable radio access technologies (RATs), including but not limited to 5G New Radio (NR), Long Term Evolution (LTE), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Wideband CDMA (WCDMA), Global System for Mobile (GSM), Bluetooth, Bluetooth Low Energy (BLE), ZigBee, Wireless Local Area Network (WLAN) RATs (e.g., WiFi), etc.

[0005] A wireless communication network may include multiple base stations capable of supporting communications for multiple mobile stations. A mobile station (MS) may communicate with a base station (BS) via a downlink and an uplink. A downlink (or forward link) refers to a communication link from a base station to a mobile station, and an uplink (or reverse link) refers to a communication link from a mobile station to a base station. A base station may send data and control information to a mobile station on a downlink, and / or may receive data and control information from a mobile station on an uplink. A base station and / or a mobile station may include at least one phase-locked loop (PLL), which may be used, for example, in a frequency synthesizer to generate and control a local oscillator (LO) signal for mixing with a baseband signal (or radio frequency (RF) signal) so as to be up-converted (or down-converted) to an intermediate frequency (IF) signal or an RF signal (or an IF signal or a baseband signal) before transmission (after reception). Summary of the invention

[0006] The systems, methods, and devices of the present disclosure each have several aspects, no single aspect of which is solely responsible for its desirable characteristics. Without limiting the scope of the present disclosure as expressed by the claims that follow, some features will now be briefly discussed. After considering this discussion, and particularly after reading the section entitled "Detailed Description," it will be understood how the features of the present disclosure provide advantages, including reducing the initial frequency error of a phase-locked loop (PLL) when stopping and restarting the PLL, and locking the PLL faster over a temperature range.

[0007] Certain aspects of the present disclosure provide a PLL circuit. The PLL circuit includes: a charge pump; a voltage controlled oscillator (VCO) having a control input coupled to an output of the charge pump via a node; and a tracking circuit coupled to the node. The tracking circuit is generally configured to: sample a voltage of the node during a mission mode; save a representation of the sampled voltage before entering a standby mode; and restore the sampled voltage to the node using the saved representation of the sampled voltage to re-enter the mission mode.

[0008] Certain aspects of the present disclosure provide a radio frequency (RF) transceiver circuit. The RF transceiver circuit generally includes: a receive path; a receive phase-locked loop (RxPLL) coupled to the receive path; a transmit path; and a transmit phase-locked loop (TxPLL) coupled to the transmit path. At least one of the RxPLL or the TxPLL includes: a charge pump; a VCO having a control input coupled to an output of the charge pump via a node; and a tracking circuit coupled to the node. The tracking circuit is generally configured to: sample a voltage of the node during a mission mode; save a representation of the sampled voltage before entering a standby mode; and restore the sampled voltage to the node using the saved representation of the sampled voltage to re-enter the mission mode.

[0009] Certain aspects of the present disclosure provide a method of wireless communication. The method generally includes: for a first circuit path associated with a first PLL, operating the first PLL during a first mission mode; sampling a control voltage of the first PLL during the first mission mode; for the first circuit path, before entering a first standby mode, saving a representation of the sampled control voltage of the first PLL; stopping operation of at least a portion of the first PLL during the first standby mode; and restoring the sampled control voltage to the first PLL using the saved representation of the sampled control voltage of the first PLL to re-enter the first mission mode.

[0010] Certain aspects of the present disclosure provide an apparatus for wireless communication. The apparatus generally includes: a PLL configured to operate during a mission mode for a circuit path associated with the PLL; components for sampling a control voltage of the PLL during the mission mode; components for saving a representation of the sampled control voltage of the PLL for the circuit path before entering a standby mode, wherein the PLL is also configured to stop operating during the standby mode; and components for restoring the sampled control voltage to the PLL using the saved representation of the sampled control voltage to re-enter the mission mode.

[0011] To achieve the foregoing and related ends, one or more aspects include the features fully described below and particularly pointed out in the claims. The following description and the accompanying drawings set forth in detail some illustrative features of one or more aspects. However, these features are merely indicative of some of the various ways in which the principles of the various aspects may be employed, and this specification is intended to include all such aspects and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to be able to understand in detail the manner in which the above-mentioned features of the present disclosure are achieved, a more specific description briefly summarized above can be obtained by reference to various aspects, some of which are illustrated in the accompanying drawings. However, it should be noted that the accompanying drawings illustrate only certain typical aspects of the present disclosure and are therefore not to be considered as limiting the scope thereof, as the specification may admit to other equally effective aspects.

[0013] Figure 1 is an illustration of an example wireless communication network in which aspects of the present disclosure may be practiced.

[0014] Figure 2 is a block diagram conceptually illustrating designs of example base stations (BSs) and user equipment (UEs) in which aspects of the present disclosure may be practiced.

[0015] Figure 3 is a block diagram of an example radio frequency (RF) transceiver in which aspects of the present disclosure may be practiced.

[0016] Figure 4 is a block diagram of an example phase-locked loop (PLL) in which aspects of the present disclosure may be practiced.

[0017] Figure 5 Included are example receive and transmit timing diagrams, corresponding chip temperature versus time graphs, and corresponding example receive phase-locked loop (RxPLL) tuning voltage versus time graphs.

[0018] Fig. 6A An example portion of a PLL circuit with a tracking circuit in accordance with certain aspects of the present disclosure is illustrated.

[0019] Figure 6B Illustrate some aspects of the present disclosure for implementing Fig. 6A An example circuit of a PLL circuit.

[0020] Figure 7 is a flow diagram of example operations for wireless communications in accordance with certain aspects of the present disclosure.

[0021] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one aspect may be beneficially utilized on other aspects without specific recitation. DETAILED DESCRIPTION

[0022] Certain aspects of the present disclosure relate to techniques and apparatus for sampling and storing a control voltage (Vtune) of a phase-locked loop (PLL) when the PLL switches from a mission mode to a standby mode, and restoring the control voltage when the PLL switches from the standby mode back to the mission mode. In this way, when re-entering the mission mode, the initial frequency error of the PLL can be reduced, the PLL can stabilize faster, and the PLL can exhibit lower temperature drift.

[0023] The various aspects of the present disclosure are described more fully below with reference to the accompanying drawings. However, the present disclosure can be embodied in many different forms, and should not be interpreted as being limited to any specific structure or function presented throughout the present disclosure. Instead, these aspects are provided so that the present disclosure will be thorough and complete, and the scope of the present disclosure will be fully conveyed to those skilled in the art. Based on the teachings of this article, it should be understood by those skilled in the art that the scope of the present disclosure is intended to cover any aspect of the disclosure disclosed herein, whether it is implemented independently or in combination with any other aspect of the present disclosure. For example, any number of aspects set forth herein can be used to implement a device or practice method. In addition, the scope of the present disclosure is intended to cover such a device or method that is practiced using other structures, functionality, or structure and functionality in addition to or different from the various aspects of the disclosure set forth herein. It should be understood that any aspect of the disclosure disclosed herein can be embodied by one or more elements of the present invention.

[0024] The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

[0025] As used herein, the term "connected with" in various tenses of the verb "connect" may mean that element A is directly connected to element B or that other elements may be connected between element A and element B (i.e., element A is indirectly connected to element B). In the context of electronic components, the term "connected with" may also be used herein to mean that wires, traces, or other conductive materials are used to electrically connect element A and element B (and any components electrically connected therebetween).

[0026] Example Wireless System

[0027] Figure 1 An example wireless communication network 100 in which aspects of the present disclosure may be practiced is illustrated. For example, the wireless communication network 100 may be a New Radio (NR) system (e.g., a fifth generation (5G) NR network), an Evolved Universal Terrestrial Radio Access (E-UTRA) system (e.g., a fourth generation (4G) network), a Universal Mobile Telecommunications System (UMTS) (e.g., a second generation / third generation (2G / 3G) network), or a Code Division Multiple Access (CDMA) system (e.g., a 2G / 3G network), or may be configured for communication according to IEEE standards such as one or more of the 802.11 standards.

[0028] like Figure 1 As illustrated in FIG. 1 , the wireless communication network 100 may include several base stations (BSs) 110 a to 110 z (each also individually referred to herein as BS 110 or collectively referred to herein as BS 110) and other network entities. A BS may also be referred to as an access point (AP), an evolved Node B (eNodeB or eNB), a next generation Node B (gNodeB or gNB), or some other terminology.

[0029] BS 110 may provide communication coverage for a particular geographic area (sometimes referred to as a "cell"), which may be stationary or may move depending on the location of mobile BS 110. In some examples, BS 110 may be interconnected with each other and / or connected to one or more other BSs or network nodes (not shown) in wireless communication network 100 through various types of backhaul interfaces (e.g., direct physical connections, wireless connections, virtual networks, etc.) using any suitable transport network. Figure 1 In the example shown, BSs 110a, 110b, and 110c may be macro BSs for macro cells 102a, 102b, and 102c, respectively. BS 110x may be a pico BS for pico cell 102x. BSs 110y and 110z may be femto BSs for femto cells 102y and 102z, respectively. A BS may support one or more cells.

[0030] The BS 110 communicates with one or more user equipment (UE) 120a to 120y (each also individually or collectively referred to herein as UE 120) in the wireless communication network 100. A UE may be fixed or mobile, and may also be referred to as a user terminal (UT), a mobile station (MS), an access terminal, a station (STA), a client, a wireless device, a mobile device, or some other terminology. A user terminal may be a wireless device such as a cellular phone, a smart phone, a personal digital assistant (PDA), a handheld device, a wearable device, a wireless modem, a laptop computer, a tablet computer, a personal computer, etc.

[0031] BS 110 is considered a transmitting entity for downlink and a receiving entity for uplink. UE 120 is considered a transmitting entity for uplink and a receiving entity for downlink. As used herein, a "transmitting entity" is an independently operated device or equipment capable of transmitting data via a frequency channel, and a "receiving entity" is an independently operated device or equipment capable of receiving data via a frequency channel. In the following description, the subscript "dn" indicates a downlink, and the subscript "up" indicates an uplink. N may be selected. up UEs are used for simultaneous transmission on the uplink, N dn UEs are used for simultaneous transmission on the downlink. up May or may not be equal to N dn , and N up and N dn It may be a static value or may change for each scheduling interval.Beam steering or some other spatial processing technique may be used at the BS 110 and the UE 120.

[0032] UEs 120 (e.g., 120x, 120y, etc.) may be dispersed throughout the wireless communication network 100, and each UE 120 may be stationary or mobile. The wireless communication network 100 may also include a relay station (e.g., relay station 110r) (also referred to as a repeater, etc.) that receives transmissions of data and / or other information from an upstream station (e.g., BS 110a or UE 120r) and transmits transmissions of data and / or other information to a downstream station (e.g., UE 120 or BS 110), or relays transmissions between UEs 120 to facilitate communication between devices.

[0033] BS 110 may communicate on the downlink and uplink with one or more UEs 120 at any given moment. The downlink (i.e., forward link) is the communication link from BS 110 to UE 120, while the uplink (i.e., reverse link) is the communication link from UE 120 to BS 110. A UE 120 may also communicate peer-to-peer with another UE 120.

[0034] The wireless communication network 100 may use multiple transmit antennas and multiple receive antennas to transmit data on the downlink and uplink. The BS 110 may be equipped with several (N ap A group of (N) antennas can be used to implement transmit diversity for downlink transmission and / or receive diversity for uplink transmission. u Each UE 120 may receive downlink transmissions and send uplink transmissions. Each UE 120 may send user-specific data to and / or receive user-specific data from BS 110. Typically, each UE 120 may be equipped with one or more antennas. u The UEs 120 may have the same or different numbers of antennas.

[0035] The wireless communication network 100 may be a time division duplex (TDD) system or a frequency division duplex (FDD) system. For a TDD system, the downlink and uplink share the same frequency band. For an FDD system, the downlink and uplink use different frequency bands. The wireless communication network 100 may also utilize a single carrier or multiple carriers for transmission. Each UE 120 may be equipped with a single antenna (e.g., to reduce costs) or multiple antennas (e.g., where additional costs can be supported).

[0036] The network controller 130 (sometimes also referred to as a "system controller") can communicate with a set of BSs 110 and provide coordination and control for these BSs 110 (e.g., via backhaul). In some cases (e.g., in a 5G NR system), the network controller 130 may include a centralized unit (CU) and / or a distributed unit (DU). In some aspects, the network controller 130 may communicate with a core network 132 (e.g., a 5G core network (5GC)), which provides various network functions such as access and mobility management, session management, user plane functions, policy control functions, authentication server functions, unified data management, application functions, network open functions, network repository functions, network slice selection functions, etc.

[0037] In certain aspects of the present disclosure, BS 110 and / or UE 120 may include at least one phase-locked loop (PLL) circuit having a tuning voltage (Vtune) tracking circuit, as described in more detail herein.

[0038] Figure 2 1 and 120a (eg, from a BS 110a) in which various aspects of the present disclosure may be implemented. Figure 1 Example components of a wireless communication network 100).

[0039] On the downlink, at BS 110a, the transmit processor 220 may receive data from the data source 212, control information from the controller / processor 240, and / or possibly other data (e.g., from the scheduler 244). Various types of data may be transmitted on different transport channels. For example, control information may be designated for a physical broadcast channel (PBCH), a physical control format indicator channel (PCFICH), a physical hybrid automatic repeat request (HARQ) indicator channel (PHICH), a physical downlink control channel (PDCCH), a group common PDCCH (GC PDCCH), etc. Data may be designated for a physical downlink shared channel (PDSCH), etc. A medium access control (MAC)-control element (MAC-CE) is a MAC layer communication structure that may be used for the exchange of control commands between wireless nodes. The MAC-CE may be carried in a shared channel such as a PDSCH, a physical uplink shared channel (PUSCH), or a physical sidelink shared channel (PSSCH).

[0040] The processor 220 may process (e.g., encode and symbol map) data and control information to obtain data symbols and control symbols, respectively. The transmit processor 220 may also generate reference symbols such as for a primary synchronization signal (PSS), a secondary synchronization signal (SSS), a PBCH demodulation reference signal (DMRS), and a channel state information reference signal (CSI-RS).

[0041] The transmit (TX) multiple-input multiple-output (MIMO) processor 230 may perform spatial processing (e.g., pre-decoding) on ​​data symbols, control symbols, and / or reference symbols where applicable, and may provide an output symbol stream to a modulator (MOD) in a transceiver 232a-232t. Each modulator 232a-232t in the transceiver may process a respective output symbol stream (e.g., for orthogonal frequency division multiplexing (OFDM) or the like) to obtain an output sample stream. Each transceiver 232a-232t may further process (e.g., convert to analog, amplify, filter, and up-convert) the output sample stream to obtain a downlink signal. The downlink signals from the transceivers 232a-232t may be transmitted via antennas 234a-234t, respectively.

[0042] At UE 120a, antennas 252a-252r may receive downlink signals from BS 110a and may provide received signals to transceivers 254a-254r, respectively. Transceivers 254a-254r may condition (e.g., filter, amplify, downconvert, and digitize) the corresponding received signals to obtain input samples. Each demodulator (DEMOD) in transceivers 232a-232t may further process the input samples (e.g., for OFDM, etc.) to obtain received symbols. MIMO detector 256 may obtain received symbols from the demodulators in transceivers 254a to 254r, perform MIMO detection on the received symbols (where applicable), and provide detected symbols. Receive processor 258 may process (e.g., demodulate, deinterleave, and decode) the detected symbols, provide decoded data for UE 120a to data sink 260, and provide decoded control information to controller / processor 280.

[0043] On the uplink, at the UE 120a, a transmit processor 264 may receive and process data from a data source 262 (e.g., for a physical uplink shared channel (PUSCH)) and control information from a controller / processor 280 (e.g., for a physical uplink control channel (PUCCH)). The transmit processor 264 may also generate reference symbols for reference signals (e.g., for a sounding reference signal (SRS)). The symbols from the transmit processor 264 may be pre-decoded by a TX MIMO processor 266 (if applicable), further processed by a modulator (MOD) in the transceivers 254a to 254r (e.g., for single carrier frequency division multiplexing (SC-FDM), etc.), and transmitted to the BS 110a. At BS 110a, the uplink signal from UE 120a may be received by antenna 234, processed by demodulators in transceivers 232a-232t, detected by MIMO detector 236 (if applicable), and further processed by receive processor 238 to obtain decoded data and control information transmitted by UE 120a. Receive processor 238 may provide the decoded data to a data sink 239 and the decoded control information to controller / processor 240.

[0044] Memories 242 and 282 may store data and program codes for BS 110a and UE 120a, respectively. Memories 242 and 282 may also interface with controllers / processors 240 and 280, respectively. Scheduler 244 may schedule UEs for data transmission on the downlink and / or uplink.

[0045] The antennas 252, processors 258, 264, 266, and / or controller / processor 280 of the UE 120a and / or the antennas 234, processors 220, 230, 238, and / or controller / processor 240 of the BS 110a may be used to perform the various techniques and methods described herein.

[0046] In certain aspects of the present disclosure, transceiver 232 and / or transceiver 254 may include at least one phase-locked loop (PLL) circuit having a tuning voltage (Vtune) tracking circuit, as described in more detail herein.

[0047] Example RF Transceiver

[0048] Figure 3 is a block diagram of an example radio frequency (RF) transceiver circuit 300 in accordance with certain aspects of the present disclosure. The RF transceiver circuit 300 includes at least one transmit (TX) path 302 (also referred to as a “transmit chain”) for transmitting signals via one or more antennas 306 and at least one receive (RX) path 304 (also referred to as a “receive chain”) for receiving signals via antenna 306. When TX path 302 and RX path 304 share antenna 306, these paths can be connected to the antenna via interface 308, which can include any of a variety of suitable RF devices, such as switches, duplexers, diplexers, multiplexers, etc.

[0049] Receiving in-phase (I) and / or quadrature (Q) baseband analog signals from a digital-to-analog converter (DAC) 310, the TX path 302 may include a baseband filter (BBF) 312, a mixer 314, a driver amplifier (DA) 316, and a power amplifier (PA) 318. The BBF 312, the mixer 314, the DA 316, and the PA 318 may be included in a radio frequency integrated circuit (RFIC). For certain aspects, the PA 318 may be external to the RFIC.

[0050] The BBF 312 filters the baseband signal received from the DAC 310, and the mixer 314 mixes the filtered baseband signal with a transmit local oscillator (LO) signal to convert the baseband signal of interest to a different frequency (e.g., upconvert from baseband to radio frequency). This frequency conversion process produces sum and difference frequencies between the LO frequency and the frequency of the baseband signal of interest. The sum and difference frequencies are referred to as "beat frequencies." The beat frequencies are typically in the RF range, so that the signal output by the mixer 314 is typically an RF signal, which may be amplified by the DA 316 and / or by the PA 318 before being transmitted by the antenna 306. Although one mixer 314 is illustrated, several mixers may be used to upconvert the filtered baseband signal to one or more intermediate frequencies and thereafter upconvert the intermediate frequency (IF) signal to a frequency for transmission.

[0051] The RX path 304 may include a low noise amplifier (LNA) 324, a mixer 326, and a baseband filter (BBF) 328. The LNA 324, the mixer 326, and the BBF 328 may be included in one or more RFICs, which may be the same RFIC as the RFIC that includes the TX path components, or may be a different RFIC. The RF signal received via the antenna 306 may be amplified by the LNA 324, and the mixer 326 mixes the amplified RF signal with a receive local oscillator (LO) signal to convert the RF signal of interest to a different baseband frequency (e.g., down-convert). The baseband signal output by the mixer 326 may be filtered by the BBF 328 before being converted to a digital I and / or Q signal by an analog-to-digital converter (ADC) 330 for digital signal processing.

[0052] Some transceivers may employ a frequency synthesizer with a variable frequency oscillator (e.g., a voltage controlled oscillator (VCO) or a digitally controlled oscillator (DCO)) to generate a stable, tunable LO with a specific tuning range. Thus, the transmit LO may be generated by a TX frequency synthesizer 320 having a transmit phase-locked loop (TxPLL). The transmit LO may be buffered or amplified by an amplifier 322 before mixing with the baseband signal in the mixer 314. Similarly, the receive LO may be generated by an RX frequency synthesizer 332 having a receive phase-locked loop (RxPLL). The receive LO may be buffered or amplified by an amplifier 334 before mixing with the RF signal in the mixer 326. For certain aspects, a single frequency synthesizer may be used for both the TX path 302 and the RX path 304. In certain aspects, the TX frequency synthesizer 320 and / or the RX frequency synthesizer 332 may include a frequency multiplier (such as a doubler) driven by an oscillator (e.g., VCO) in the frequency synthesizer.

[0053] For certain aspects, the RxPLL and / or TxPLL may be coupled to a tuning voltage (Vtune) tracking circuit, as described herein. For example, the RxPLL may be coupled to a first Vtune tracking circuit, and the TxPLL may be coupled to a second Vtune tracking circuit.

[0054] Controller 336 (eg, Figure 2Controller / processor 280 in the RF transceiver circuit 300A may direct the operation of the RF transceiver circuit 300A, such as transmitting signals via TX path 302 and / or receiving signals via RX path 304. Controller 336 may be a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof. Memory 338 (e.g., Figure 2 Memory 282 in RF transceiver circuit 300 may store data and / or program code for operating RF transceiver circuit 300. Controller 336 and / or memory 338 may include control logic (eg, complementary metal oxide semiconductor (CMOS) logic).

[0055] Although Figures 1 to 3 Wireless communications are provided as an example application in which certain aspects of the present disclosure may be implemented to facilitate understanding, but certain aspects described herein may be used for PLLs in any of a variety of other suitable systems (e.g., video monitors, microprocessors, high-speed serializer / deserializer (SerDes) systems, or other electronic systems).

[0056] Example Phase-Locked Loop

[0057] Figure 4 4 is a block diagram of an example phase-locked loop (PLL) 400 in which aspects of the present disclosure may be practiced. PLL 400 may be used in a frequency synthesizer, such as Figure 3 The transmit phase-locked loop (TxPLL) in the TX frequency synthesizer 320 or the receive phase-locked loop (RxPLL) in the RX frequency synthesizer 332.

[0058] like Figure 4 , a charge pump 406 coupled to a low-pass loop filter 408 (also referred to as a "charge pump filter" or "PLL loop filter") can provide a control voltage (also referred to as a "tuning voltage" or "Vtune") to a voltage controlled oscillator (VCO) 402, wherein the control voltage is used to adjust the oscillation frequency of the VCO 402. The charge pump 406 and the VCO 402 can receive power via two power rails: a positive power rail and a negative power rail. Switches in the charge pump 406 can be controlled by up / down pulse signals 410, 412 (labeled "UP" and "DN"), and the loop filter 408 can suppress high-frequency transient signals from this switching activity. These up / down pulse signals 410, 412 can be generated by a phase frequency detector (PFD) 414, which can compare a feedback signal 416 (based on the output or processed output of the VCO 402 and labeled "DIV") with a reference frequency signal 418 (labeled "REF"). On the one hand, Figure 4 As illustrated in , feedback signal 416 may be generated by buffering the output of VCO 402 using VCO buffer 404, scaling the buffered signal in prescaler 422 to generate an output signal 424 of the PLL (labeled “PLLOUT”), and dividing the output of prescaler 422 in feedback divider 420.

[0059] In some aspects of the present disclosure, such as Figure 4 , the input control voltage for the VCO 402 may be provided by the charge pump 406 and the low pass loop filter 408 via the VCO control inputs 426, 428. The resonant tank circuit of the VCO 402 may generate a periodic signal having a particular frequency (e.g., determined by the voltage at the VCO control inputs 426, 428) at the differential VCO outputs 430, 432, which may be input to the VCO buffer 404. The VCO buffer 404 may be coupled to the differential VCO outputs 430, 432 in an attempt to isolate the VCO 402 from loads in the PLL 400 and other circuits that receive the output signal 424 of the PLL. The VCO buffer 404 may also be employed in an attempt to amplify the signal swing and correct any duty cycle distortion of the differential VCO outputs 430, 432.

[0060] Although PLL 400 Figure 4 embodied as a differential circuit, but it should be understood that the PLL may alternatively be implemented as a single-ended circuit.

[0061] Example Vtune Tracker

[0062] To save power, a phase-locked loop (PLL) (e.g., PLL 400) may switch between a mission mode, in which the PLL is in operation, and a standby mode, in which the PLL is inactive. For example, a receive phase-locked loop (RxPLL) may enter mission mode when a receive chain (e.g., RX path 304) is receiving or scheduled to receive a signal (e.g., on a downlink for a user equipment (UE) or on an uplink for a base station), and may otherwise enter standby mode. Conversely, a transmit phase-locked loop (TxPLL) may enter mission mode when a transmit chain (e.g., TX path 302) is transmitting or scheduled to transmit a signal (e.g., on an uplink for a UE or on a downlink for a base station), and may otherwise enter standby mode.

[0063] Figure 5 An example receive and transmit timing diagram 500 is included that illustrates switching the receive and transmit PLLs of a UE between mission mode and standby mode. Figure 5Also included is an example chip temperature versus time graph 520 and an example RxPLL tuning voltage (Vtune) versus time graph 540, both of which correspond to the timing diagram 500. The chip may be an integrated circuit (IC) having an RxPLL and a TxPLL. The chip temperature graph 520 depicts how the chip temperature changes with respect to time when the UE's PLL switches between task mode and standby mode, and the RxPLL Vtune graph 540 shows how the Vtune of the example RxPLL changes with respect to time.

[0064] With reference to timing diagram 500, when the UE switches between downlink (DL) reception and uplink (UL) transmission, each PLL may be switched to task mode or standby mode. In the task mode of each corresponding PLL, the PLL is operating, and in the standby mode of each corresponding PLL, the PLL 400 is not operating (e.g., power may be removed from certain PLL sub-blocks and / or the PLL may be operated in an extremely low power mode). For example, when the UE is in a DL time slot and is receiving (or scheduled to receive) a signal, the RxPLL is generally in task mode, and the TxPLL is generally in standby mode. On the other hand, when the UE is in a UL time slot and is sending (or scheduled to send) a signal, the RxPLL is generally in standby mode, and the TxPLL is generally in task mode. The opposite may apply to the PLL of the base station.

[0065] As illustrated in the timing diagram 500, as an example, in the first DL time slot 502a, at least most of the time, the RxPLL may be in the first receive task mode 506a, and the TxPLL may be in the first transmit standby mode 510a. In the first UL time slot 504a, most of the time, the RxPLL may be in the first receive standby mode 508a, and the TxPLL may be in the first transmit task mode 512a. In the second DL time slot 502b, at least most of the time, the RxPLL may be in the second receive task mode 506b, and the TxPLL may be in the second transmit standby mode 510b. In the second UL time slot 504b, the RxPLL may be in the second receive standby mode 508b, and the TxPLL may be in the second transmit task mode 512b. This may continue for each subsequent UL and DL time slot. As illustrated, there may be a gap 501 (eg, a 7 μs delay) between each pair of DL and UL timeslots, which may allow time to activate and deactivate each of the PLLs.

[0066] The corresponding chip temperature graph 520 illustrates how the temperature of the corresponding chip (labeled "chip temperature") changes with respect to time when the PLL switches between modes. The temperature of the chip may also change when the PLL operates and switches between transmission and reception. For example, transmission in a UL timeslot may cause a greater temperature increase than reception in a DL timeslot.

[0067] For example, in the first DL time slot 502a, when the RxPLL and the receive chain are operating, the temperature of the chip increases from a first temperature T0 (e.g., a starting temperature) to a second temperature T1 (e.g., when the chip is warming up). Next, when the UE is in the first UL time slot 504a and transmits a signal, the chip temperature may increase from the second temperature T1 to a third temperature T2. Since in this example, the transmit signal involves more energy than the receive signal, the temperature of the chip increases at a faster rate in the first UL time slot 504a than in the first DL time slot 502a. In other cases, the receive signal may involve more energy than the transmit signal.

[0068] Subsequently, in the second DL time slot 502b, the chip temperature may decrease from the third temperature T2 to the fourth temperature T3. Here, since receiving a signal involves less energy than transmitting, the chip temperature may decrease from the third temperature T2 to the fourth temperature T3, as shown in the graph 520. In other examples, the chip temperature may alternatively increase between temperatures T2 and T3 at a slower rate than the temperature change between temperatures T1 and T2.

[0069] Then, in the second UL time slot 504 b , since the energy during transmission is high, the chip temperature may increase from the fourth temperature T3 to the fifth temperature T4 .

[0070] When the PLL is in mission mode, as the chip temperature changes, the components of the PLL may change with temperature, and therefore, the PLL may change the tuning voltage (Vtune) to maintain frequency and phase lock of the oscillation signal output by the VCO (e.g., VCO 402). Therefore, Vtune drifts in proportion to the change in chip temperature. However, once the PLL switches to standby mode, Vtune is lost (e.g., not maintained in the feedback loop) when the PLL is not operating. Then, when the PLL re-enters mission mode, Vtune may be reset and start from the same initial starting point (e.g., 0V or half of the power rail voltage (e.g., Vdd of a charge pump, such as Figure 6B Referring back to the timing diagram 500, it may be desirable for Vtune to settle within a predefined time for the gap 501 between each of the DL and UL time slots so that the PLL has little or no frequency error at the beginning of the time slot.

[0071] Referring to the corresponding graph 540, when the RxPLL is in the first receiving task mode 506a, as the chip temperature changes from the first temperature T0 to the second temperature T1, Vtune changes from the initial voltage V0 to the voltage V1 to maintain the frequency of the oscillation signal from the VCO caused by the temperature change. In some cases, the initial voltage V0 may be a predefined starting voltage of the RxPLL, such as Vdd / 2.

[0072] When the RxPLL switches to the first receive standby mode 508a, Vtune is lost and may drop (e.g., to 0V, as illustrated in the graph 540). When the RxPLL is in the first receive standby mode 508a, the temperature of the chip changes from the second temperature T1 to the third temperature T2, and Vtune is not updated, thereby allowing a larger VCO frequency drift to occur with temperature. When the RxPLL switches to the second receive task mode 506b and reactivates, the RxPLL can be restored at a predefined starting voltage (e.g., 0V or Vdd / 2). Due to temperature changes during the first receive standby mode 508a where Vtune is not updated, there may be a considerable Vtune offset between the predefined starting voltage (e.g., voltage V0) and the final new Vtune to maintain locking at the new temperature (temperature T2). A high Vtune offset results in a larger initial PLL frequency error. Therefore, as Vtune rises from the predefined starting voltage to a new Vtune at a voltage V2 corresponding to the third temperature T2, Vtune may take longer to stabilize. In other words, a larger initial PLL frequency error causes the PLL and Vtune to stabilize slowly, as shown by waveform 542 in graph 540 .

[0073] Once Vtune stabilizes at voltage V2, Vtune is updated by the RxPLL during the second mission mode and reaches voltage V3 (when the temperature drops to temperature T3) before entering the second receive standby mode 508b, where Vtune is lost (and reset) again.

[0074] Certain aspects of the present disclosure provide a Vtune tracking circuit that saves Vtune from a PLL's mission mode before entering the PLL's standby mode and restores Vtune before re-entering the PLL's mission mode, thereby significantly reducing Vtune offsets, initial PLL frequency errors, and PLL / Vtune stabilization times upon re-entry, especially under temperature variations. In other words, when the PLL is reactivated, the Vtune tracking circuit helps the PLL lock quickly over a temperature range.

[0075] For example, in graph 540, such a Vtune tracking circuit may store a voltage V1 before the RxPLL enters the first receive standby mode 508a. When the RxPLL enters the second receive task mode 506b, the stored Vtune (voltage V1) is restored, and since the restored voltage V1 is closer to a new Vtune voltage (voltage V2) associated with temperature T2 than a predefined starting voltage (e.g., voltage V0), the Vtune stabilization time is reduced, as illustrated by waveform 544.

[0076] Fig. 6A A portion of an example PLL circuit 600 having a tracking circuit 602 in accordance with certain aspects of the present disclosure is illustrated. PLL circuit 600 may be similar to PLL 400, but with the addition of tracking circuit 602. For certain aspects, an RxPLL may have a tracking circuit coupled thereto, and a TxPLL may have another tracking circuit coupled thereto.

[0077] As shown, the tracking circuit 602 may be coupled to the output of the charge pump 406 at a node 698, but for other aspects, may alternatively be coupled to the output of the loop filter 408 at a node 699. The tracking circuit 602 may include a sample-and-hold circuit 604, an analog-to-digital converter (ADC) 606, a memory 608, and a digital-to-analog converter (DAC) 610. The sample-and-hold circuit 604 may have an input coupled to the output of the charge pump 406 and may have an output coupled to the input of the ADC 606. The output of the ADC 606 and the input of the DAC 610 may be coupled to the memory 608. The memory 608 may include, for example, a register or any other suitable storage component capable of storing a digital code representing Vtune at a desired resolution. The output of the DAC 610 may be coupled to the node 698 (or the node 699) via a buffer and / or other suitable components.

[0078] The sample and hold circuit 604 may be configured to sample and hold an analog voltage value of Vtune (e.g., unfiltered at the output of the charge pump 406) when the PLL circuit 600 is in mission mode or just before the PLL exits mission mode. The ADC 606 may be configured to convert the sampled and held analog value of Vtune into a digital representation of Vtune and write the representation into the memory 608. The memory 608 may be configured to store the digital representation of Vtune for subsequent recovery. Just before or when the PLL re-enters mission mode, the DAC 610 may be configured to read the stored digital representation of Vtune from the memory 608 and convert it into an analog version of the stored representation to be used as the starting value of Vtune when the PLL is reactivated. In other words, the DAC 610 (and other associated circuits) may be configured to restore the sample and hold value of Vtune once the PLL circuit 600 re-enters mission mode so as to stabilize the PLL faster than starting from a predefined starting voltage.

[0079] For some aspects, the tracking circuit may be powered off most of the time to save power. In this case, the tracking circuit may be powered on just before the PLL associated with it exits the mission mode and enters the standby mode to capture Vtune and store Vtune or a representation of Vtune (e.g., a digital code). For some aspects, the tracking circuit may remain on during the standby mode, while in other aspects, the tracking circuit may be powered off after storing (a representation of) Vtune. In the latter case, the tracking circuit may be powered on just before the PLL re-enters the mission mode and restores Vtune in the PLL or when the PLL re-enters the mission mode and restores Vtune in the PLL. For other aspects (e.g., without considering the power consumption of the tracking circuit), the tracking circuit may remain powered on most or all of the time.

[0080] Figure 6B Illustrate some aspects of the present disclosure for implementing Fig. 6A 4. Example circuits of various aspects of the PLL circuit 600 of FIG. 600. As described above, the PLL circuit 600 may include a charge pump (CP) 406, a tracking circuit 602, a loop filter 408, and a voltage controlled oscillator (VCO) 402.

[0081] As illustrated, loop filter 408 may be implemented as a fourth-order low-pass filter (LPF) having series resistor elements R1 and R2, shunt capacitor elements C1 and C2, shunt capacitor elements C3 and C4, and resistor element R3. However, it should be understood that loop filter 408 may be designed as any suitable filter and have any suitable number of poles and zeros. Charge pump 406 may include current sources I for charging and discharging, respectively. UPand current sink I DN For PLL circuit 600, shunt capacitor element C3 may be coupled between the output of charge pump 406 and a reference potential node (e.g., electrical ground). As illustrated and explained above, charge pump 406 generates a tuning voltage (Vtune). Vtune is low pass filtered by loop filter 408 to remove transients and other higher frequency components (e.g., from the switching action of charge pump 406), thereby generating a reference potential node (e.g., ground) at node 699.

[0082] A filtered tuning voltage (Vtune*) is generated at VCO 402. Vtune* may be more similar to a DC voltage. Vtune* may be used to adjust the frequency of the oscillating signal generated by VCO 402.

[0083] like Figure 6B As implemented in the example of , the sample-and-hold circuit 604 in the Vtune tracking circuit 602 may include a switch S1, which may be coupled between the resistor element R3 and the capacitor element C4. Therefore, the resistor element R3 and the capacitor element C4 may also be considered as part of the sample-and-hold circuit 604. When the switch S1 is closed during the mission mode, the resistor element R3 and the capacitor element C4 may operate in a manner similar to a low-pass filter and filter out transient and other high-frequency components of Vtune from the switching action of the charge pump during the mission mode. The sample-and-hold circuit 604 is configured to sample Vtune (e.g., when the PLL circuit 600 is in the mission mode or just before exiting the mission mode) and hold the sampled Vtune (e.g., for quantization and storage). Therefore, switch S1 may be opened during quantization of Vtune (referred to as "sampling mode", "quantization mode" or "conversion mode") so that capacitor element C4 may not discharge to Vtune or charge pump 406, and switch S1 may be closed during task mode and when PLL circuit 600 exits standby mode and restores Vtune (referred to as "recovery mode").

[0084] The sample-and-hold circuit 604 may also include a switch S2 coupled between a node 697 (between the switch S1 and the capacitive element C4) and an input of the ADC. The switch S2 may be closed during sampling of Vtune (while the switch S1 is open) and may be opened after the sampled Vtune is quantized (e.g., during standby mode, recovery mode, and mission mode).

[0085] As illustrated, the ADC 606 may be implemented by a successive approximation register (SAR) analog-to-digital converter (ADC) 611. The SAR ADC 611 may include a comparator 612, a SAR logic component 614, and a digital-to-analog converter (DAC) 616. The comparator 612 may have a first input (e.g., a positive input) coupled to a switch S2 and may have a second input (e.g., a negative input) coupled to an output of the DAC 616. The SAR logic component 614 may include a register, for example, may have an input coupled to the output of the comparator 612 and may have an output coupled to an input of the DAC 616. Through this loop, the SAR ADC 611 may perform a binary search for different quantization levels (e.g., different DAC steps) before converging to a final digital signal to be output from the SAR ADC.

[0086] More specifically, the comparator 612 may be configured to compare the held Vtune with the analog output voltage of the DAC 616 and output an indication of the comparison result. For example, the comparator 612 may be configured to output a logic "0" if the output voltage of the DAC 616 is greater than the held Vtune, and to output a logic "1" if the output voltage of the DAC 616 is less than the held Vtune. The SAR logic component 614 may be configured to continuously update, store, and output a digital voltage signal to the DAC 616 based on the output of the comparator 612. The DAC 616 may be configured to convert each continuous digital voltage signal into an analog voltage signal applied to a second input terminal of the comparator 612. After the SAR ADC 611 has quantized the held Vtune voltage, the switch S2 may be disconnected, and the SAR logic component 614 may store a digital codeword representing the sampled and held Vtune. Thus, Figure 6B The SAR logic unit 614 in the Fig. 6A ADC 606 and part of memory 608 in. In addition, Figure 6B The DAC 616 in the embodiment may be used as part of the ADC 606 and as Fig. 6A DAC 610 in.

[0087] like Figure 6BAs illustrated in the example implementation of , the tracking circuit 602 may also include a buffer 618, a switch S3, and a switch S4. In the feedback loop, the buffer may have a first input (e.g., a positive input) coupled to the output of the DAC 616 and a second input (e.g., a negative input) coupled to the output of the buffer 618. The switch S3 may be coupled between the node 698 and the output of the buffer 618. The switch S4 may be coupled between the node 697 and the output of the buffer 618. The buffer 618 and the switches S3 and S4 may be used to recover the stored Vtune, as described below.

[0088] In operation, each of these switches operates based on the operating mode of the PLL circuit 600. For example, when the PLL circuit 600 is in mission mode, switches S2, S3, and S4 are opened, and switch S1 is closed. When switch S1 is closed, Vtune is sampled by charging the capacitive element C4 when the PLL circuit 600 operates. Just before or at the moment when the PLL circuit 600 exits mission mode, in sampling mode, switch S1 may be opened, and switch S2 may be closed, while switches S3 and S4 remain open. Closing switch S2 couples Vtune to the SAR ADC 611 for quantization. Switches S1, S3, and S4 are opened, disconnecting the SAR ADC 611 from the output of the charge pump 406 and the buffer 618.

[0089] After switch S2 is closed, the held Vtune is quantized by the SAR ADC 611. At the end of the conversion, a digital representation of the held Vtune is stored by the SAR logic component 614. Depending on the resolution of the SAR ADC 611, the digital representation may be substantially equivalent to the held Vtune. Even though the capacitive element C4 may be discharging during the conversion, the SAR ADC 611 may operate fast enough to quantize the held Vtune before C4 discharges a significant amount.

[0090] Also after the transition, switch S2 may be opened to exit the sampling mode and enter the standby mode.When switches S1, S2, and S4 are open, capacitive element C4 may be slowly discharged via leakage during the standby mode.

[0091] Before the PLL circuit 600 re-enters the mission mode, the PLL circuit enters a recovery mode to restore the previous level of Vtune. In the recovery mode, switches S1, S3, and S4 are closed, and switch S2 may remain open. The stored Vtune representation is output by the SAR logic component 614, converted to an analog voltage by the DAC 616, buffered by the buffer 618, and output to nodes 697 and 698 to begin controlling the VCO 402. Advantageously, Vtune is restored to the previous level of Vtune at the end of the previous mission mode and is not reset to a predefined starting voltage (e.g., Vdd / 2). For certain aspects, after Vtune is restored, switches S3 and S4 are disconnected, and the SAR ADC 611 and buffer 618 may be turned off to save power. Then, the PLL circuit 600 may re-enter the mission mode (where switches S2, S3, and S4 are disconnected and switch S1 is closed).

[0092] The above process may be repeated as PLL circuit 600 switches between operating modes.

[0093] Example Operations for Wireless Communication

[0094] Figure 7 700 for wireless communications in accordance with certain aspects of the present disclosure. Operations 700 may be performed, for example, by a radio frequency (RF) transceiver (e.g., a receive phase-locked loop (RxPLL) (e.g., in RX frequency synthesizer 332) and / or a transmit phase-locked loop (TxPLL) (e.g., in TX frequency synthesizer 320). Figure 3 ), wherein at least one of the PLLs is coupled to a tuning voltage (Vtune) tracking circuit (e.g., Fig. 6A Operation 700 may be performed by a controller (e.g., Figure 3 Controller 336) is used to control.

[0095] Operations 700 may generally involve operating a first phase-locked loop (PLL) (e.g., an RxPLL or a TxPLL, such as PLL circuit 600) during a first mission mode (e.g., mission mode 506a or 512a) for a first circuit path (e.g., RX path 304 or TX path 302) associated with a first PLL at block 702. At block 704, a tracking circuit may sample a control voltage (e.g., Vtune) of the first PLL during the first mission mode, and at block 706, for the first circuit path, save a representation (e.g., a digital code) of the sampled control voltage of the first PLL before entering a first standby mode (e.g., standby mode 508a or 510b). At block 708, stopping operation of the first PLL (or at least a portion of the first PLL) for the first standby mode. At block 710, the tracking circuit may restore the sampled control voltage to the first PLL using the saved representation of the sampled control voltage of the first PLL to re-enter the first mission mode.

[0096] According to certain aspects, the first circuit path is a receive path (e.g., RX path 304). In this case, the first PLL may include a receive phase-locked loop (RxPLL), and the first mission mode may be used for reception of downlink (DL) signals. For other aspects, the first circuit path is a transmit path (e.g., TX path 302). In this case, the first PLL includes a transmit phase-locked loop (TxPLL), and the first mission mode may be used for transmission of uplink (UL) signals.

[0097] According to certain aspects, operation 700 also involves converting the sampled control voltage of the first PLL using a successive approximation register (SAR) analog-to-digital converter (ADC) (e.g., SAR ADC 611) to generate a representation of the sampled control voltage (e.g., before saving at block 706). The SAR ADC may include a SAR logic component (e.g., SAR logic component 614). For certain aspects, saving the representation at block 706 includes saving a digital representation of the sampled control voltage of the first PLL in the SAR logic component. The SAR ADC may also include a digital-to-analog converter (DAC) (e.g., DAC 616). For certain aspects, restoring the sampled control voltage to the first PLL at block 710 involves converting the digital representation of the sampled control voltage of the first PLL into an analog signal using the DAC. Restoring the sampled control voltage to the first PLL may also include buffering the analog signal (e.g., using buffer 618) and using the buffered analog signal as the control voltage for restarting the first PLL to re-enter the first mission mode.

[0098] According to certain aspects, operation 700 also involves, for a second circuit path (e.g., TX path 302 or RX path 304) associated with the second PLL, operating the second PLL (e.g., TxPLL or RxPLL, such as PLL circuit 600) during a second mission mode (e.g., mission mode 506b or 512b); sampling a control voltage (Vtune) of the second PLL during the second mission mode; for the second circuit path, saving a representation (e.g., a digital code) of the sampled control voltage of the second PLL to enter a second standby mode (e.g., standby mode 508b); for the second standby mode, stopping operation of the second PLL; and restoring the sampled control voltage to the second PLL using the saved representation of the sampled control voltage of the second PLL to re-enter the second mission mode. For certain aspects, the first circuit path is a receive path (e.g., RX path 304), the first PLL includes an RxPLL, and the first mission mode is for reception of DL signals. For certain aspects, the second circuit path is a transmit path (eg, TX path 302), the second PLL comprises a TxPLL, and the second duty mode is for transmission of UL signals.

[0099] For some aspects, the first task mode may overlap in time with the second standby mode.Alternatively or additionally, the second task mode may overlap in time with the first standby mode.

[0100] Example aspects

[0101] In addition to the above-mentioned aspects, specific combinations of the aspects are also within the scope of the present disclosure, and the details of some of the specific combinations are as follows:

[0102] Aspect 1: A phase-locked loop (PLL) circuit, comprising: a charge pump; a voltage-controlled oscillator (VCO), the voltage-controlled oscillator (VCO) having a control input terminal coupled to the output terminal of the charge pump via a node; and a tracking circuit, the tracking circuit being coupled to the node and configured to sample the voltage of the node during a task mode, save a representation of the sampled voltage before entering a standby mode, and restore the sampled voltage to the node using the saved representation of the sampled voltage to re-enter the task mode.

[0103] Aspect 2: The PLL circuit according to aspect 1, wherein the PLL circuit comprises a receive phase-locked loop (RxPLL), and wherein the mission mode is for reception of a downlink (DL) signal.

[0104] Aspect 3: The PLL circuit according to aspect 1, wherein the PLL circuit comprises a transmit phase-locked loop (TxPLL), and wherein the mission mode is used for transmission of an uplink (UL) signal.

[0105] Aspect 4: The PLL circuit according to any one of aspects 1 to 3, wherein the tracking circuit comprises a sample-and-hold circuit.

[0106] Aspect 5: The PLL circuit according to aspect 4, wherein the sample-and-hold circuit comprises a resistance element, a first switch, and a capacitance element coupled in series between the node and a reference potential node of the PLL circuit.

[0107] Aspect 6: The PLL circuit according to aspect 5, wherein the sample-and-hold circuit further comprises a second switch coupled to a node between the first switch and the capacitive element.

[0108] Aspect 7: A PLL circuit according to any one of Aspects 4 to 6, wherein the tracking circuit further includes a successive approximation register (SAR) analog-to-digital converter (ADC), the successive approximation register (SAR) analog-to-digital converter (ADC) having an input terminal coupled to the output terminal of the sample-and-hold circuit.

[0109] Aspect 8: A PLL circuit according to Aspect 7, wherein the SAR ADC comprises: a comparator having a first input terminal coupled to the output terminal of the sample-and-hold circuit; a SAR logic component having an input terminal coupled to the output terminal of the comparator; and a digital-to-analog converter (DAC) having an input terminal coupled to the output terminal of the SAR logic component and having an output terminal coupled to a second input terminal of the comparator.

[0110] Aspect 9: The PLL circuit according to Aspect 8, wherein the tracking circuit further comprises: a buffer having an input coupled to the output of the DAC; and a first switch coupled between the output of the buffer and the node.

[0111] Aspect 10: The PLL circuit according to Aspect 9, wherein the tracking circuit further comprises a second switch coupled between the output terminal of the buffer and the sample-and-hold circuit.

[0112] Aspect 11: According to any one of Aspects 1 to 10, the PLL circuit also includes a low-pass filter, which is coupled between the output terminal of the charge pump and the control input terminal of the VCO, wherein the node includes an input terminal of the low-pass filter.

[0113] Aspect 12: A radio frequency transceiver circuit, the radio frequency transceiver circuit comprising: a receive path; a receive phase-locked loop (RxPLL), the receive phase-locked loop (RxPLL) coupled to the receive path; a transmit path; and a transmit phase-locked loop (TxPLL), the transmit phase-locked loop (TxPLL) coupled to the transmit path, wherein at least one of the RxPLL or the TxPLL comprises: a charge pump; a voltage-controlled oscillator (VCO), the voltage-controlled oscillator (VCO) having a control input terminal coupled to the output terminal of the charge pump via a node; and a tracking circuit, the tracking circuit is coupled to the node and is configured to sample the voltage of the node during a task mode, save a representation of the sampled voltage before entering a standby mode, and restore the sampled voltage to the node using the saved representation of the sampled voltage to re-enter the task mode.

[0114] Aspect 13: A method of wireless communication, the method comprising: for a first circuit path associated with a first phase-locked loop (PLL), operating the first PLL during a first task mode; sampling a control voltage of the first PLL during the first task mode; for the first circuit path, saving a representation of the sampled control voltage of the first PLL before entering a first standby mode; stopping operation of at least a portion of the first PLL during the first standby mode; and restoring the sampled control voltage to the first PLL using the saved representation of the sampled control voltage of the first PLL to re-enter the first task mode.

[0115] Aspect 14: The method of aspect 13, wherein the first circuit path comprises a receive path, wherein the first PLL comprises a receive phase-locked loop (RxPLL), and wherein the first mission mode is for reception of a downlink (DL) signal.

[0116] Aspect 15: The method according to aspect 13, wherein the first circuit path includes a transmission path, wherein the first PLL includes a transmit phase-locked loop (TxPLL), and wherein the first mission mode is used for transmission of an uplink (UL) signal.

[0117] Aspect 16: According to the method of any one of Aspects 13 to 15, the method also includes converting the sampled control voltage of the first PLL using a successive approximation register (SAR) analog-to-digital converter (ADC) to generate the representation of the sampled control voltage.

[0118] Aspect 17: The method of aspect 16, wherein the SAR ADC comprises a SAR logic component, and wherein saving the representation comprises saving a digital representation of the sampled control voltage of the first PLL in the SAR logic component.

[0119] Aspect 18: A method according to aspect 17, wherein the SAR ADC further comprises a digital-to-analog converter (DAC), and wherein restoring the sampled control voltage to the first PLL comprises converting the digital representation of the sampled control voltage of the first PLL into an analog signal using the DAC.

[0120] Aspect 19: The method according to Aspect 18, wherein restoring the sampled control voltage to the first PLL further comprises: buffering the analog signal; and using the buffered analog signal as the control voltage for restarting the first PLL to re-enter the first task mode.

[0121] Aspect 20: According to the method described in any one of Aspects 13 to 19, the method further includes: for a second circuit path associated with a second PLL, operating the second PLL during a second task mode; sampling the control voltage of the second PLL during the second task mode; for the second circuit path, saving a representation of the sampled control voltage of the second PLL to enter a second standby mode; stopping the operation of the second PLL during the second standby mode; and restoring the sampled control voltage to the second PLL using the saved representation of the sampled control voltage of the second PLL to re-enter the second task mode.

[0122] Aspect 21: A method according to Aspect 20, wherein: the first circuit path includes a receiving path; the first PLL includes a receiving phase-locked loop (RxPLL); the first task mode is used for receiving a downlink (DL) signal; the second circuit path includes a transmitting path; the second PLL includes a transmitting phase-locked loop (TxPLL); and the second task mode is used for transmitting an uplink (UL) signal.

[0123] Aspect 22: The method according to aspect 20 or 21, wherein the first task mode overlaps with the second standby mode in time, and / or wherein the second task mode overlaps with the first standby mode in time.

[0124] Aspect 23: An apparatus for wireless communication, the apparatus comprising: a phase-locked loop (PLL) configured to operate during a mission mode for a circuit path associated with the PLL; a component for sampling a control voltage of the PLL during the mission mode; a component for saving a representation of the sampled control voltage of the PLL for the circuit path before entering a standby mode, wherein the PLL is also configured to stop operating during the standby mode; and a component for restoring the sampled control voltage to the PLL using the saved representation of the sampled control voltage to re-enter the mission mode.

[0125] Aspect 24: The apparatus of aspect 23, further comprising means for converting the sampled control voltage of the PLL to generate the representation of the sampled control voltage.

[0126] Additional considerations

[0127] Certain aspects of the present disclosure use a tuning voltage (Vtune) tracking circuit to assist a phase-locked loop (PLL) to lock quickly over a temperature range. The Vtune tracking circuit can measure and digitize Vtune and save the digital code before the PLL enters standby mode. When exiting standby mode, the Vtune tracking circuit restores the saved Vtune, and the PLL restarts from the restored Vtune in mission mode, which results in smaller initial PLL frequency error and faster PLL stabilization.

[0128] The above description provides examples, but does not limit the scope, applicability or examples set forth in the claims. Without departing from the scope of the present disclosure, the functions and arrangements of the elements discussed may be changed. Various procedures or components may be omitted, replaced or added to each example as appropriate. For example, the method described may be performed in a different order from that described, and various steps may be added, omitted or combined. In addition, the features described for some examples may be combined in some other examples. For example, any number of aspects set forth herein may be used to implement a device or practice method. In addition, the scope of the present disclosure is intended to cover such devices or methods practiced using other structures, functional functions or structures and functionality in addition to or different from the various aspects of the present disclosure given herein. It should be understood that any aspect of the disclosure disclosed herein may be embodied by one or more elements of the present invention. The word "exemplary" is used herein to mean "used as an example, instance, or illustration". Any aspect described as "exemplary" herein is not necessarily interpreted as being preferred or having advantages over other aspects.

[0129] The various operations of the above methods may be performed by any suitable means capable of performing the corresponding functions. The means may include various hardware and / or software components and / or modules, including but not limited to circuits, application specific integrated circuits (ASICs), or processors. In general, where there are operations illustrated in the figures, these operations may have corresponding corresponding means plus functional components. For example, a means for sampling may include a sample-and-hold circuit (e.g., Fig. 6A The component for converting may include an analog-to-digital converter (ADC) (e.g., Fig. 6A ADC 606 or Figure 6B SAR ADC 611). The means for storing may include a memory or a register, such as Fig. 6A Memory 608 or Figure 6B SAR logic component 614. The component for recovery may include a digital-to-analog converter (DAC) (e.g., Fig. 6A DAC 610 or Figure 6B DAC 616), buffer (e.g., Figure 6B buffer 618) and / or one or more switches (e.g., Figure 6B switches S3 and S4).

[0130] As used herein, a phrase referring to "at least one of" a list of items refers to any combination of those items (including single members). For example, "at least one of a, b, or c" is intended to cover: a, b, c, ab, ac, bc, and abc, as well as any combination with multiple of the same elements (e.g., aa, aaa, aab, aac, abb, acc, bb, bbb, bbc, cc, and ccc or any other ordering of a, b, and c).

[0131] The methods disclosed herein include one or more steps or actions for implementing the described methods. The steps and / or actions of the methods may be interchangeable with each other without departing from the scope of the claims. In other words, unless a specific order of steps or actions is specified, the order and / or use of specific steps and / or actions may be modified without departing from the scope of the claims.

[0132] It is to be understood that the claims are not limited to the precise configuration and components illustrated above. Various modifications, changes and variations may be made in the arrangement, operation and details of the methods and apparatus described above without departing from the scope of the claims.

Claims

1. A phase-locked loop (PLL) circuit, the phase-locked loop (PLL) circuit comprising: Charge pump; a voltage controlled oscillator (VCO) having a control input coupled to an output of the charge pump via a node; and A tracking circuit is coupled to the node and is configured to sample a voltage of the node during a mission mode, save a representation of the sampled voltage before entering a standby mode, and restore the sampled voltage to the node using the saved representation of the sampled voltage to re-enter the mission mode.

2. The PLL circuit of claim 1, wherein the PLL circuit comprises a receive phase-locked loop (RxPLL), and wherein the mission mode is for reception of a downlink (DL) signal.

3. The PLL circuit of claim 1, wherein the PLL circuit comprises a transmit phase locked loop (TxPLL), and wherein the mission mode is for transmission of an uplink (UL) signal.

4. The PLL circuit of claim 1, wherein the tracking circuit comprises a sample-and-hold circuit.

5. The PLL circuit according to claim 4, wherein the sample-and-hold circuit comprises a resistance element, a first switch, and a capacitance element coupled in series between the node and a reference potential node of the PLL circuit. 6 . The PLL circuit of claim 5 , wherein the sample-and-hold circuit further comprises a second switch coupled to a node between the first switch and the capacitive element.

7. The PLL circuit of claim 4, wherein the tracking circuit further comprises a successive approximation register (SAR) analog-to-digital converter (ADC) having an input coupled to the output of the sample-and-hold circuit.

8. The PLL circuit according to claim 7, wherein the SAR ADC comprises: a comparator having a first input coupled to the output of the sample and hold circuit; a SAR logic component having an input coupled to an output of the comparator; and A digital-to-analog converter (DAC) having an input coupled to the output of the SAR logic component and having an output coupled to the second input of the comparator.

9. The PLL circuit of claim 8, wherein the tracking circuit further comprises: a buffer having an input coupled to the output of the DAC; and A first switch is coupled between an output terminal of the buffer and the node.

10. The PLL circuit of claim 9, wherein the tracking circuit further comprises a second switch coupled between the output terminal of the buffer and the sample-and-hold circuit.

11. The PLL circuit of claim 1 , further comprising a low pass filter coupled between the output of the charge pump and the control input of the VCO, wherein the node comprises an input of the low pass filter.

12. A radio frequency transceiver circuit, the radio frequency transceiver circuit comprising: receiving path; a receive phase-locked loop (RxPLL) coupled to the receive path; Send path; and a transmit phase locked loop (TxPLL) coupled to the transmit path, wherein at least one of the RxPLL or the TxPLL comprises: Charge pump; a voltage controlled oscillator (VCO) having a control input coupled to an output of the charge pump via a node; and A tracking circuit is coupled to the node and is configured to sample a voltage of the node during a mission mode, save a representation of the sampled voltage before entering a standby mode, and restore the sampled voltage to the node using the saved representation of the sampled voltage to re-enter the mission mode.

13. A method of wireless communication, the method comprising: For a first circuit path associated with a first phase locked loop (PLL), operating the first PLL during a first mission mode; sampling a control voltage of the first PLL during the first mission mode; for the first circuit path, prior to entering a first standby mode, saving a representation of the sampled control voltage of the first PLL; stopping operation of at least a portion of the first PLL during the first standby mode; as well as The sampled control voltage is restored to the first PLL using the saved representation of the sampled control voltage of the first PLL to re-enter the first mission mode.

14. The method of claim 13, wherein the first circuit path comprises a receive path, wherein the first PLL comprises a receive phase locked loop (RxPLL), and wherein the first mission mode is for reception of a downlink (DL) signal.

15. The method of claim 13, wherein the first circuit path comprises a transmit path, wherein the first PLL comprises a transmit phase locked loop (TxPLL), and wherein the first duty mode is for transmission of an uplink (UL) signal.

16. The method of claim 13, further comprising converting the sampled control voltage of the first PLL using a successive approximation register (SAR) analog-to-digital converter (ADC) to generate the representation of the sampled control voltage.

17. The method of claim 16, wherein the SAR ADC comprises a SAR logic component, and wherein saving the representation comprises saving a digital representation of the sampled control voltage of the first PLL in the SAR logic component.

18. The method of claim 17, wherein the SAR ADC further comprises a digital-to-analog converter (DAC), and wherein restoring the sampled control voltage to the first PLL comprises converting the digital representation of the sampled control voltage of the first PLL into an analog signal using the DAC.

19. The method of claim 18, wherein restoring the sampled control voltage to the first PLL further comprises: buffering the analog signal; as well as The buffered analog signal is used as the control voltage for restarting the first PLL to re-enter the first mission mode.

20. The method according to claim 13, further comprising: for a second circuit path associated with a second PLL, operating the second PLL during a second mission mode; sampling a control voltage of the second PLL during the second mission mode; for the second circuit path, saving a representation of the sampled control voltage of the second PLL to enter a second standby mode; stopping operation of the second PLL during the second standby mode; as well as The sampled control voltage is restored to the second PLL using the saved representation of the sampled control voltage of the second PLL to re-enter the second mission mode.

21. The method of claim 20, wherein: The first circuit path includes a receive path; The first PLL comprises a receive phase-locked loop (RxPLL); The first task mode is used for receiving downlink (DL) signals; The second circuit path includes a transmit path; The second PLL comprises a transmit phase locked loop (TxPLL); and The second task mode is used for sending an uplink (UL) signal.

22. The method of claim 20, wherein the first task mode overlaps in time with the second standby mode, and wherein the second task mode overlaps in time with the first standby mode.

23. An apparatus for wireless communication, the apparatus comprising: a phase locked loop (PLL) configured to operate during a mission mode for a circuit path associated with the PLL; means for sampling a control voltage of the PLL during the mission mode; means for saving, for the circuit path, a representation of the sampled control voltage of the PLL prior to entering a standby mode, wherein the PLL is further configured to cease operation during the standby mode; and Means for restoring the sampled control voltage to the PLL using the saved representation of the sampled control voltage to re-enter the mission mode.

24. The apparatus of claim 23, further comprising means for converting the sampled control voltage of the PLL to generate the representation of the sampled control voltage.

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