Vertical channel field effect transistor (VCFET) with reduced contact resistance and / or parasitic capacitance and related fabrication methods

Abstract

Vertical channel field effect transistors (VCFETs) with reduced contact resistance and / or parasitic capacitance and related methods of manufacture. In an exemplary aspect, to reduce contact resistance of the VCFET, an end of the vertical channel has a semiconductor structure having an extended width in a horizontal direction parallel to the substrate surface. This provides a larger area for source / drain formation contacts, thereby reducing the contact resistance of the VCFET. To reduce parasitic capacitance between the gate and the contact of the VCFET, the spacer region includes one or more air gaps, and an air spacer region is formed between the gate and the contact to reduce the overall average dielectric constant of the spacer region. In one example, the air spacer region of the VCFET is elongated in a horizontal direction parallel to the substrate surface (and perpendicular to a vertical direction of the vertical channel) to further reduce parasitic capacitance.

Description

[0001] Priority application

[0002] This application claims priority to U.S. patent application serial number 17 / 933,568, filed on September 20, 2022, entitled “VERTICAL CHANNEL FIELDEFFECT TRANSISTOR (VCFET) WITH REDUCED CONTACT RESISTANCE AND / OR PARASITIC CAPACITANCE, AND RELATED FABRICATION METHODS,” and the entire contents of the above-mentioned U.S. patent application are incorporated herein by reference. Technical Field

[0003] The field of the present disclosure relates to semiconductor devices forming integrated circuits (ICs), and more particularly, to gate-around transistors (eg, fin field effect transistors (FETs) (FinFETs) and gate-around-all-around (GAA) transistors). Background Art

[0004] Transistors are fundamental elements of modern electronic devices. They are used in large numbers in integrated circuits (ICs) found in many modern electronic devices. For example, components such as central processing units (CPUs), graphics processing units (GPUs), and memory systems all use large numbers of transistors for both logic circuits and memory devices.

[0005] As the functionality of electronic devices becomes more complex, it is necessary to include more transistors in such devices. However, as electronic devices are required to be provided in smaller and smaller packages, such as in mobile devices, it is necessary to provide a larger number of transistors in smaller IC chips. This increase in the number of transistors is achieved in part by the continuous efforts to miniaturize transistors in ICs (i.e., placing more and more transistors in the same amount of space). In particular, the node size in ICs is constantly shrinking by reducing the minimum metal line width in ICs (e.g., 65 nanometers (nm), 45nm, 28nm, 20nm, etc.). Therefore, the gate length of planar transistors can also be reduced proportionally, thereby reducing the channel length of transistors and interconnect devices. Reducing the channel length in planar transistors can have the benefit of increasing drive strength (i.e., increasing drain current) with less parasitic capacitance, thereby causing reduced circuit delay. However, when the channel length in a planar transistor is reduced so that the channel length is on the same order of magnitude as the depletion layer width, a short channel effect (SCE) that reduces performance will occur. More specifically, SCE in a planar transistor may result in increased leakage current, reduced threshold voltage, and / or threshold voltage roll-off (ie, reduced threshold voltage for shorter gate lengths). Summary of the invention

[0006] Various aspects disclosed herein include a vertical channel (VC) field effect transistor (FET) (VCFET) with reduced contact resistance and / or parasitic capacitance. Related manufacturing methods are also disclosed. In an exemplary aspect, a VCFET is a FET including a semiconductor channel ("channel") having a height extending along a longitudinal axis in a first horizontal direction orthogonal to a substrate surface of a substrate. The VCFET is disposed on or adjacent to the substrate. The VCFET also includes a source and a drain (e.g., an epitaxial source layer and an epitaxial drain layer), each of which is disposed as a corresponding end surface contact with the vertical channel. The vertical channel of the VCFET is configured to transmit charge in a vertical direction orthogonal to the substrate along the height of the vertical channel between the source and the drain in response to an electric field generated by energy applied to a gate (e.g., a fin field effect transistor (FET) (FinFET) gate, a fully surrounding gate) disposed adjacent to the vertical channel. The VCFET supports the ability to provide a longer channel length in the vertical direction to save the area of ​​the VCFET in the horizontal direction on the substrate. The vertical channel of the VCFET also supports the ability to place more gate material near and / or around the vertical channel to support better electrostatic control and higher current. However, the vertical channel is elongated in the vertical direction, which also reduces the area where source / drain contacts can be formed (e.g., by epitaxial growth), thereby increasing the parasitic contact resistance of the VCFET. In addition, in an exemplary aspect, in order to reduce the contact resistance of the VCFET, the end of the vertical channel has a semiconductor structure that has an extended width in a horizontal direction parallel to the substrate surface. This provides a larger area for the source / drain to form contacts, thereby reducing the contact resistance of the vertical VCFET.

[0007] In addition, in other exemplary aspects, the VCFET further includes a spacer region, which includes a dielectric material for isolating the second drain / source contact from the gate. When energy is applied to the gate of the VCFET to generate an electric field in the vertical channel, a parasitic capacitance exists between the gate and the contact. In one example, the increase in the end of the vertical channel reduces the dielectric material of the spacer region, thereby contributing to a higher parasitic capacitance between the gate and the contact. Therefore, in other exemplary aspects, in order to reduce the parasitic capacitance of the VCFET, the spacer region includes one or more air gaps, which form an air spacer region between the gate and the contact to reduce the overall average dielectric constant of the spacer region. The dielectric constant of air is less than the dielectric constant of the dielectric material of the spacer region. Reducing the dielectric constant of the spacer region between the gate and the contact can reduce the parasitic capacitance of the VCFET. In one example, the air spacer region of the VCFET is elongated in a horizontal direction parallel to the substrate surface (and perpendicular to the vertical direction of the vertical channel) to further reduce the parasitic capacitance. This is because the horizontal air gap has the effect of contributing series capacitance to the parasitic capacitance between the gate and the contact due to the orientation of the air gap relative to the electric field generated between the gate and the contact. The series capacitance added to the parasitic capacitance between the gate and the contact reduces the parasitic capacitance between the gate and the contact and thereby reduces the overall parasitic capacitance of the VCFET.

[0008] In this regard, in an exemplary aspect, a VCFET is provided. The VCFET includes a substrate including a substrate surface. The VCFET also includes a channel. The channel includes a first channel portion, the first channel portion including a first end surface and a second end surface opposite to the first end surface. The second end surface has a first width in a first direction parallel to the substrate surface. The channel also includes a second channel portion, the second channel portion including a third end surface coupled to the second end surface and a fourth end surface opposite to the third end surface. The fourth end surface has a second width greater than the first width in the first direction. The VCFET also includes a gate adjacent to the first channel portion. The VCFET also includes a source / drain coupled to the first end surface of the first channel portion. The VCFET also includes a drain / source coupled to the fourth end surface of the second channel portion.

[0009] In another example aspect, a method for manufacturing a VCFET is provided. The method includes providing a substrate including a substrate surface. The method also includes forming a channel, the forming the channel including forming a first channel portion, the first channel portion including a first end surface and a second end surface opposite to the first end surface, wherein the second end surface has a first width in a first direction parallel to the substrate surface. Forming the channel also includes forming a second channel portion, the second channel portion including a third end surface coupled to the second end surface and a fourth end surface opposite to the third end surface, wherein the fourth end surface has a second width greater than the first width in the first direction. The method also includes forming a gate adjacent to the first channel portion. The method also includes forming a source / drain coupled to the first end surface of the first channel portion. The method also includes forming a drain / source coupled to the fourth end surface of the second channel portion.

[0010] In another exemplary aspect, an integrated circuit (IC) is provided. The IC includes a substrate, the substrate including a substrate surface. The IC also includes a plurality of field effect transistors (FETs) on the substrate surface. The plurality of FETs include a P-type semiconductor (P-type) FET, the P-type FET including a P-type channel, the P-type channel including a first P-type channel portion and a second P-type channel portion, the first P-type channel portion including a first end surface and a second end surface opposite to the first end surface, wherein the second end surface has a first width in a first direction parallel to the substrate surface; the second P-type channel portion includes a third end surface coupled to the second end surface and a fourth end surface opposite to the third end surface, wherein the fourth end surface has a second width greater than the first width in the first direction. The P-type FET also includes a first gate adjacent to the first P-type channel portion. The P-type FET also includes a P-type source / drain coupled to the first end surface of the first P-type channel portion. The P-type FET also includes a P-type drain / source coupled to the fourth end surface of the second P-type channel portion. The plurality of FETs also include an N-type semiconductor (N-type) FET, the N-type FET including an N-type channel, the N-type channel including a first N-type channel portion and a second N-type channel portion, the first N-type channel portion including a fifth end surface and a sixth end surface opposite to the fifth end surface, wherein the sixth end surface has a third width in a first direction parallel to the substrate surface; the second N-type channel portion includes a seventh end surface coupled to the sixth end surface and an eighth end surface opposite to the seventh end surface, wherein the eighth end surface has a fourth width greater than the third width in the first direction. The N-type FET also includes a second gate adjacent to the first N-type channel portion. The N-type FET also includes an N-type source / drain coupled to the fifth end surface of the first N-type channel portion. The N-type FET also includes an N-type drain / source coupled to the eighth end surface of the second N-type channel portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1is a top perspective view of an exemplary vertical channel field effect transistor (VCFET);

[0012] Figure 2A-2D is a side view of an exemplary VCFET including a vertical channel and / or a spacer between a gate and a contact, the vertical channel having an end portion that is expanded in width in a horizontal direction perpendicular to a height of the vertical channel to reduce contact resistance, the spacer including one or more horizontal air gaps that are elongated in a horizontal direction to reduce an overall average dielectric constant of the spacer and thereby reduce parasitic capacitance of the VCFET;

[0013] Figure 3 is a side view of an exemplary integrated circuit (IC) that includes an N-type semiconductor (N-type) VCFET and a P-type semiconductor (P-type) VCFET disposed on a substrate and that can be used in a complementary metal oxide semiconductor (CMOS) circuit;

[0014] Figure 4 is a side view of another exemplary IC, the IC including Figure 2A and Figure 2B The VCFET shown is in the form of an N-type VCFET and a P-type VCFET disposed on a substrate, and can be used in a complementary metal oxide semiconductor (CMOS) circuit, wherein the N-type and P-type VCFETs include a vertical channel and / or a spacer region, the vertical channel having an end portion that is extended in width in a horizontal direction perpendicular to the height of the vertical channel to reduce contact resistance, and the spacer region includes one or more horizontal air gaps that are elongated in the horizontal direction to reduce parasitic capacitance between the gate and the contact;

[0015] Figure 5 is a flow chart of an exemplary manufacturing process for manufacturing a VCFET including a vertical channel and / or a spacer region between a gate and a contact, the vertical channel having an end portion that is extended in width in a horizontal direction perpendicular to the height of the vertical channel to reduce contact resistance, the spacer region including one or more horizontal air gaps that are elongated in the horizontal direction to reduce the overall average dielectric constant of the spacer region and thereby reduce the parasitic capacitance of the VCFET, the VCFET including but not limited to Figure 2A-Figure 3 VCFET in;

[0016] Figure 6A-6G is a flow chart showing another exemplary manufacturing process for manufacturing an IC including a VCFET, the VCFET including a vertical channel having an end portion that is extended in width in a horizontal direction perpendicular to the height of the vertical channel to reduce contact resistance, a spacer region including one or more horizontal air gaps that are elongated in the horizontal direction to reduce the overall average dielectric constant of the spacer region and thereby reduce the parasitic capacitance of the VCFET, the VCFET including but not limited to Figure 3 The vertical VCFET in

[0017] Figure 7A-7M yes Figure 6A-6G Exemplary manufacturing stages in the manufacture of an IC;

[0018] Figure 8 is a block diagram of an exemplary wireless communication device including electrical components, the electrical components may include an IC, the IC including a VCFET, the VCFET including a vertical channel and / or a spacer between a gate and a contact and manufactured according to a manufacturing process, the vertical channel having an end portion that is extended in width in a horizontal direction perpendicular to the height of the vertical channel to reduce contact resistance, the spacer including one or more horizontal air gaps that are elongated in the horizontal direction to reduce the overall average dielectric constant of the spacer and thereby reduce the parasitic capacitance of the VCFET, the VCFET including but not limited to Figure 2A-Figure 3 The VCFET in the present invention includes but is not limited to the manufacturing process Figure 5-6G An exemplary manufacturing process in; and

[0019] Fig. 9 is a block diagram of an exemplary electronic device in the form of a processor-based system, the electronic device may include an IC, the IC including a VCFET, the VCFET including a vertical channel, the vertical channel having an end extending in width in a horizontal direction perpendicular to the height of the vertical channel to reduce contact resistance, a spacer region including one or more horizontal air gaps elongated in the horizontal direction to reduce the overall average dielectric constant of the spacer region and thereby reduce the parasitic capacitance of the VCFET, the VCFET including but not limited to Figure 2A-Figure 3 The VCFET in the present invention includes but is not limited to the manufacturing process Figure 5-6G An exemplary manufacturing process in.

[0020] Specific implementation method

[0021] Referring now to the accompanying drawings, several exemplary aspects of the present disclosure are described. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or superior to other aspects.

[0022] Various aspects disclosed herein include a vertical channel (VC) field effect transistor (FET) (VCFET) with reduced contact resistance and / or parasitic capacitance. Related manufacturing methods are also disclosed. In an exemplary aspect, a VCFET is a FET including a semiconductor channel ("channel") having a height extending along a longitudinal axis in a first horizontal direction orthogonal to a substrate surface of a substrate. The VCFET is disposed on or adjacent to the substrate. The VCFET also includes a source and a drain (e.g., an epitaxial source layer and an epitaxial drain layer), each of which is disposed as a corresponding end surface contact with the vertical channel. The vertical channel of the VCFET is configured to transmit charge in a vertical direction orthogonal to the substrate along the height of the vertical channel between the source and the drain in response to an electric field generated by energy applied to a gate (e.g., a fin field effect transistor (FET) (FinFET) gate, a fully surrounding gate) disposed adjacent to the vertical channel. The VCFET supports the ability to provide a longer channel length in the vertical direction to save the area of ​​the VCFET in the horizontal direction on the substrate. The vertical channel of the VCFET also supports the ability to place more gate material near and / or around the vertical channel to support better electrostatic control and higher current. However, the vertical channel is elongated in the vertical direction, which also reduces the area where source / drain contacts can be formed (e.g., by epitaxial growth), thereby increasing the parasitic contact resistance of the VCFET. In addition, in an exemplary aspect, in order to reduce the contact resistance of the VCFET, the end of the vertical channel has a semiconductor structure having an extended width in a horizontal direction parallel to the substrate surface. This provides a larger area for the source / drain to form contacts, thereby reducing the contact resistance of the vertical VCFET.

[0023] In addition, in other exemplary aspects, the VCFET further includes a spacer region, which includes a dielectric material for isolating the second drain / source contact from the gate. When energy is applied to the gate of the VCFET to generate an electric field in the vertical channel, a parasitic capacitance exists between the gate and the contact. In one example, the increase in the end of the vertical channel reduces the dielectric material of the spacer region, thereby contributing to a higher parasitic capacitance between the gate and the contact. Therefore, in other exemplary aspects, in order to reduce the parasitic capacitance of the VCFET, the spacer region includes one or more air gaps, which form an air spacer region between the gate and the contact to reduce the overall average dielectric constant of the spacer region. The dielectric constant of air is less than the dielectric constant of the dielectric material of the spacer region. Reducing the dielectric constant of the spacer region between the gate and the contact can reduce the parasitic capacitance of the VCFET. In one example, the air spacer region of the VCFET is elongated in a horizontal direction parallel to the substrate surface (and perpendicular to the vertical direction of the vertical channel) to further reduce the parasitic capacitance. This is because the horizontal air gap has the effect of contributing series capacitance to the parasitic capacitance between the gate and the contact due to the orientation of the air gap relative to the electric field generated between the gate and the contact. The series capacitance added to the parasitic capacitance between the gate and the contact reduces the parasitic capacitance between the gate and the contact and thereby reduces the overall parasitic capacitance of the VCFET.

[0024] Examples of VCFETs including extended vertical channels and / or spacer regions for reducing contact resistance are discussed below. Figure 2A Starting from the spacer region, the spacer region includes one or more horizontal air gaps to reduce parasitic capacitance. Figure 1 An exemplary VCFET 100 is described.

[0025] in this regard, Figure 1 is a top perspective view of an exemplary VCFET 100. Figure 1As shown, the VCFET 100 includes a vertical channel 102 that is elongated and has a height H1 in a vertical direction (Z-axis direction). The height H1 is in a vertical direction (Z-axis direction) orthogonal to a substrate surface 104 of a substrate 106 in which the VCFET 100 is formed. The vertical channel also has a channel width W1 in a horizontal direction (X-axis direction) parallel to the substrate surface 104 of the substrate 106. A source structure (“source”) S and a drain structure (“drain”) D are disposed at opposite ends of the vertical channel 102. The vertical channel 102 is a semiconductor material that is configured to transmit current in response to an electric field formed in the vertical channel 102. In this example, the source S is disposed on a first bottom end 108 of the vertical channel 102 in the vertical direction (Z-axis direction). The drain D is disposed on a second top end 110 of the vertical channel 102 in the vertical direction (Z-axis direction) opposite to the first bottom end 108. The source S and the drain D are made of semiconductor materials and can be formed as epitaxial layers on the respective first 108 and second ends 110 of the vertical channel 102. For example, the source S and the drain D can be epitaxial layers made of N-type semiconductor for N-type (N) metal oxide semiconductor (MOS) (NMOS) devices and P-type semiconductor materials for P-type (P) PMOS devices. The source S is disposed in a well 112, which is a P-well for NMOS devices and an N-well for PMOS devices.

[0026] Continue to refer Figure 1 , a gate structure (“gate”) G is disposed around a vertical channel 102 between the drain D and the source S of the VCFET 100. In this manner, the voltage potential between the gate G and the source S generates an electric field in the vertical channel 102, which causes the vertical channel 102 to conduct a current I in the vertical channel 102 between the source S and the drain D. A The channel height H1 of the vertical channel 102 defines the effective gate length L of the gate G. eff The structure of the VCFET 100 including the vertical channel 102 elongated in the vertical direction (Z-axis direction) so that the effective channel length extends in the vertical direction (Z-axis direction) has the following advantages: saving area in the horizontal direction (X-axis and Y-axis directions) on the substrate 106. In a conventional planar FET design, the channel would extend in the horizontal direction parallel to the substrate surface 104 of the substrate 106, thereby consuming additional area in the substrate 106 in the horizontal direction (X-axis and Y-axis directions). The channel height H1 and L effAn epitaxial process can be used to define layer by layer. For example, this is more accurate than the photolithography process used to define the same distance in the FinFET structure. The source S and drain D formed by the epitaxial layer can also provide stress and strain to the vertical channel 102 to increase the current mobility in the vertical channel 102. In NMOS devices, tensile stress can be introduced into the vertical channel 102 to increase current mobility, and for PMOS devices, compressive stress can be introduced into the vertical channel 102 to increase current mobility.

[0027] Continue to refer Figure 1 , a source contact 114 and a drain contact 116 made of a metal material (e.g., copper) are coupled to the corresponding source S and drain D to provide metal contacts for providing conductive contacts to the source S and drain D of the VCFET 100. Since the vertical channel 102 blocks direct access to the source at the first bottom end 108 of the vertical channel 102, in this example, the source contact 114 is also elongated in the vertical direction (Z-axis direction) and is shifted a distance from the vertical channel 102 in the horizontal direction (Y-axis direction). The drain contact 116 is disposed above the drain D on the top surface 118 of the drain D in the vertical direction (Z-axis direction) because the vertical channel 102 does not block access to the drain D. Since the drain D is formed on the second top end 110 of the vertical channel 102 in the vertical direction (Z-axis direction), the surface area defined in part by the channel width W1 of the second top end 110 of the vertical channel 102 will control the available surface where the drain D can be disposed or formed. Therefore, the size of the drain D is limited by the channel width W1 of the vertical channel 102 in the VCFET 100. And further, the size of the drain contact 116 is limited by the size of the drain D. Therefore, the limited channel width W1 of the vertical channel 102 can cause the contact resistance between the drain contact 116 and the drain D to be greater than desired, thereby resulting in a larger contact resistance in the VCFET 100.

[0028] In an example, to meet the desire to provide a VCFET with reduced contact resistance, Figure 2A-2DA side view of an exemplary VCFET 200 is shown, which includes a vertical channel 202 having a second channel portion 204(2) extending in width in a horizontal direction (X-axis and / or Y-axis direction). The second channel portion 204(2) is a semiconductor structure that is a portion of the entire vertical channel 202. The second channel portion 204(2) extends in width W2 in a horizontal direction (X-axis direction) perpendicular to a height H2 of the vertical channel 202 in the vertical direction (Z-axis direction) to reduce the contact resistance of the VCFET 200. The height H2 of the vertical channel 202 is in a vertical direction (Z-axis direction) orthogonal to a substrate surface 205 of a substrate 206 in which the VCFET 200 is formed. For example, the substrate surface 205 can be a semiconductor material such as silicon. In this example, the vertical channel 202 is composed of a first channel portion 204(1) and a second channel portion 204(2). The first channel portion 204(1) is a semiconductor structure that is a portion of the entire vertical channel 202. Both the first channel portion 204(1) and the second channel portion 204(2) are made of a semiconductor material that is configured to allow current to flow therethrough when subjected to an electric field. The first channel portion 204(1) has a first end surface 208(1) and a second end surface 208(2) opposite to the first end surface 208(1) in the vertical direction (Z-axis direction). The first channel portion 204(1) has a height H3 in the vertical direction (Z-axis direction), and the height H3 is in a direction orthogonal to the substrate surface 205 of the substrate 206. The first channel portion 204(1) is elongated in the vertical direction (Z-axis direction) so that its width W3 in the horizontal direction (X-axis direction) (and parallel to the substrate surface 205) is smaller than its height H3 in the vertical direction (Z-axis direction). Therefore, the first channel portion 204 ( 1 ) of the vertical channel 202 is configured to transmit current in the vertical direction (Z-axis direction).

[0029] Continue to refer Figure 2A , the vertical channel 202 also has a second channel portion 204(2), and the second channel portion 204(2) has a third end surface 208(3) and a fourth end surface 208(4) opposite to the third end surface 208(3) in the vertical direction (Z-axis direction). In this example, the third end surface 208(3) of the second channel portion 204(2) is coupled to the second end surface 208(2) of the first channel portion 204(1), so that the first channel portion 204(1) and the second channel portion 204(2) form a continuous channel structure for the vertical channel 202. The second channel portion 204(2) has a height H in the vertical direction (Z-axis direction). 4，The height H4 is orthogonal to the direction of the substrate surface 205 of the substrate 206. Therefore, the height H3 of the first channel portion 204(1) and the height H4 of the second channel portion 204(2) of the vertical channel 202 contribute to the overall height H2 of the vertical channel 202 and therefore the effective channel length. As discussed above, at least a portion of the second channel portion 204(2) has a width in the horizontal direction (X-axis direction) that is greater than the width W3 of the first channel portion 204(1). In this example, the fourth end surface 208(4) of the second channel portion 204(2) has a width W2 that is greater than the width W3 of the first channel portion 204(1). Since the drain 210 is formed in the vertical direction (Z-axis direction) on the fourth end surface 208(4) of the second channel portion 204(2) of the vertical channel 202, the surface area defined in part by the channel width W2 of the fourth end surface 204(4) of the second channel portion 204(2) controls the available surface in which the drain 210 can be disposed or formed. In this way, the fourth end surface 208(4) of the second channel portion 204(2) can have a larger surface area than the second end surface 208(2) of the first channel portion 204(1), so that in this example, a larger size of the drain 210 in contact with the vertical channel 202 can be formed. This has the effect of reducing the contact resistance between the drain contact 212 coupled to the drain 210 and the drain 210, which effectively reduces the contact resistance of the VCFET 200 relative to a design in which the drain 210 would be formed in contact with the second end surface 208(2) of the first channel portion 204(1) of the vertical channel 202. This is similar to, for example, Figure 3 The VCFET 300 in FIG. Figure 3 In the VCFET 300 in FIG. 1 , the source 314 is disposed on the first end surface 308(1) of the vertical channel 302, and the drain 310 is disposed on the second end surface 308(2) of the vertical channel 302. The drain contact 312 is in contact with the drain 310. The vertical channel 302 has only one channel portion having a constant width W4, so that the vertical channel 302 does not have a channel portion having an extended width for forming the drain 310. Therefore, based on the constant width W4 of the vertical channel 302, the drain 310 formed in contact with the vertical channel 302 may be limited in size.

[0030] Reference back Figure 2AIn the VCFET 200 of FIG. 200 , as an example, the width W2 of the second channel portion 204(2) of the vertical channel 202 can be between one (1) nanometer (nm) and twenty (20) nm. As an example, the width W3 of the first channel portion 204(1) of the vertical channel 202 can be between one (1) nm and 10 nm. The ratio of the width W2 of the second channel portion 204(2) of the vertical channel 202 to the width W3 of the first channel portion 204(1) of the vertical channel 202 can be at least 1.1, as an example. The width difference between the width W2 of the second channel portion 204(2) and the width W3 of the first channel portion 204(1) can be selected based on the desired performance criteria of the VCFET 200. For example, if lower contact resistance is desired, the width W2 of the second channel portion 204(2) can be increased to increase the surface area of ​​the fourth end surface 208(4) and the volume of the second channel portion 204(2). Since the third end surface 208(3) of the second channel portion 204(2) is coupled to the second end surface 208(2) of the first channel portion 204(1) to form the vertical channel 202, increasing the width W2 of the second channel portion 204(2) may require increasing the width W3 of the first channel portion 204(1) based on the manufacturing method used.

[0031] Continue to refer Figure 2A , the VCFET 200 includes a source structure ("source") 214 and a drain 210 disposed at opposite ends of the vertical channel 202, which are adjacent to or in contact with the first end surface 208(1) and the fourth end surface 208(4) of the corresponding first channel portion 204(1) and the second channel portion 204(2). In this example, the source 214 is disposed adjacent to the first end surface 208(1) of the first channel portion 204(1) of the vertical channel 202 in the vertical direction (Z-axis direction). The drain D is adjacent to the fourth end surface 208(4) of the second channel portion 204(2) of the vertical channel 202 in the vertical direction (Z-axis direction), and the fourth end surface 208(4) is opposite to the first end surface 208(1). The source S and the drain D are made of semiconductor material and can be formed as epitaxial layers on the respective first end surface 208(1) and fourth end surface 208(2) of the vertical channel 202. For example, the source S and the drain can be epitaxial layers made of N-type semiconductor for N-type (N) metal oxide semiconductor (MOS) (NMOS) devices and P-type semiconductor material for P-type (P) PMOS devices. The source 214 is disposed in a well 216, which is a P-well for NMOS devices and an N-well for PMOS devices. As non-limiting examples, the source 214 and the drain 210 can be silicon (Si) or silicon germanium (SiGe).

[0032] As an example, the substrate 206 of the VCFET 200 may be <100> If VCFET 200 is provided as a PMOS device / transistor, the vertical channel 202 of VCFET 200 may be at a position 206 of the substrate surface 205. <011> If VCFET 200 is provided as an NMOS device / transistor, the vertical channel 202 of VCFET 200 may be oriented in the plane relative to substrate surface 205. <001> This orientation configuration between substrate 206 and VCFET 200 can provide optimized charge mobility in vertical channel 202. When used in this context, <100> is an indication of the crystal planes of the silicon substrate surface 205 using the Miller indices. These indices are used to indicate the orientation of atoms in the silicon crystal structure. The orientation is caused by the growth direction of the silicon ingot from which the silicon slices are cut. Thus, in the example provided, the silicon has been manufactured to present <100> Oriented surface, additional structure can be fabricated on it <100> The N-type VCFET 200 can be oriented perpendicular to the <100> The P-type VCFET 200 can be fabricated on the <-001> plane of the silicon substrate surface 205, and can be fabricated on the <-001> plane of the silicon substrate surface 205. <100> The surface of the silicon substrate 205 <011> Made at 45 degrees on a flat surface.

[0033] Continue to refer Figure 2A , a gate structure ("gate") 218 ​​is disposed in a vertical direction (Z-axis direction) to surround the vertical channel 202 of the VCFET 200 between the drain D and the source S. For example, the gate 218 can completely surround the vertical channel 202 in the X-axis and Y-axis directions, making the VCFET 200 a full gate-around (GAA) device. For example, the vertical channel 200 has a width of one (1) to ten (10) nm in the X-axis direction and a depth of ten (10) to fifty (50) nm in the Y-axis direction. The gate 218 is a metal layer or structure that can conduct current. In this way, the voltage potential between the gate 218 and the source 214 generates an electric field in the vertical channel 202, which causes the vertical channel 202 to conduct a current I in the vertical channel 202 between the source 214 and the drain 210. B The channel height H2 of the vertical channel 202 defines the effective gate length L of the gate 218 eff The structure of the VCFET 200 having the vertical channel 202 elongated in the vertical direction (Z-axis direction) so that the effective channel length extends in the vertical direction (Z-axis direction) has the following advantages: saving the area in the horizontal direction (X-axis and Y-axis directions) on the substrate 206. The channel height H1 and the effective length L of the gate 218 are effThe distance may be determined layer by layer using an epitaxial process. For example, this may be more accurate than the photolithography process used to determine the same distance in a FinFET structure. The source 214 and drain 210 formed by the epitaxial layer may also provide stress and strain to the vertical channel 202 to increase the current mobility in the vertical channel 202. In an NMOS device, tensile stress may be introduced to the vertical channel 202 to increase current mobility, while for a PMOS device, compressive stress may be introduced to the vertical channel 202 to increase current mobility.

[0034] Continue to refer Figure 2A , a source contact 220 and a drain contact 212 made of a metal material such as copper are coupled to the respective source 214 and drain 210 of the VCFET 200. The source contact 220 and the drain contact 212 provide metal contacts for providing conductive contacts to the respective source 214 and drain 210. Since the vertical channel 202 blocks direct access to the source 214, in this example, the source contact 220 is also elongated in the vertical direction (Z-axis direction) along the first longitudinal axis A1 and is offset from the vertical channel 202 in the horizontal direction (Y-axis direction) by a certain distance. Since the second channel portion 204(2) of the vertical channel 202 does not block access to the drain 210, the drain contact 212 is disposed above the drain D on the top surface 222 of the drain 210. The drain contact 212 is elongated in the vertical direction (Z-axis direction) along a second longitudinal axis A2 parallel to the first longitudinal axis A1. The gate 218 is disposed adjacent to the first channel portion 204(1) of the vertical channel 202. In this example, the gate 218 is a "all around" structure that is disposed completely around the entire sidewall 224 of the first channel portion 204(1). The crystal structure of the channel sidewalls of the vertical channel 202 for the N-type VCFET 200 may be at a position 224-300 degrees relative to the substrate surface 205. <001> The crystal structure of the channel sidewall of the vertical channel 202 of the P-type VCFET 200 may be oriented in a plane relative to the substrate surface 205. <011> Oriented on a plane.

[0035] Figure 2A VCFET 200 in this example also includes a first bottom spacer 226(1) and a second top spacer 226(2) between gate 218 and source contact 220. The first bottom spacer 226(1) and the second top spacer 226(2) are designed to reduce the parasitic capacitance of VCFET 200. It may be desirable to reduce not only the contact resistance of VCFET 200 but also its parasitic capacitance so that VCFET 200 has better resistance and capacitance (RC) performance characteristics. In this regard, Figure 2B yes Figure 2AFIG. 2 is another side view of VCFET 200 to show exemplary details of first bottom spacer 226 ( 1 ) and second top spacer 226 ( 2 ). Figure 2C and Figure 2D Too Figure 2B FIG. 2 is a partial side view of VCFET 200 in FIG. 2 to illustrate exemplary details of second top spacer 226(2) and first bottom spacer 226(1), respectively. Figure 2B-Figure 2D Discussion The first bottom spacer region 226(1) and the second top spacer region 226(2) of the VCFET 200 are designed to reduce the parasitic capacitance thereof.

[0036] In this regard, Figure 2B As shown, in this example, a first bottom spacer 226(1) and a second top spacer 226(2) are disposed between the gate 218 and the source contact 220 to isolate the gate 218 from the source contact 220 and the drain contact 212. The first spacer 226(1) and the second spacer 226(2) may be dielectric structures made of a dielectric material (e.g., an oxide layer or silicon nitride (SiN) as an example). The dielectric constant of the dielectric material making the first spacer 226(1) and the second spacer 226(2) affects the capacitance formed between the source contact 220 and the drain contact 212 and the gate 218. Therefore, it is desirable to provide the first spacer 226(1) and the second spacer 226(2) with a lower dielectric constant. In this example, in order to further reduce the dielectric constant of the first spacer 226(1) and the second spacer 226(2), air gaps 228(1), 228(2) are formed in the respective dielectric structures of the first spacer 226(1) and the second spacer 226(2) to reduce the overall average dielectric constant of the first spacer 226(1) and the second spacer 226(2). This has the effect of reducing the parasitic capacitance of the VCFET 200.

[0037] Figure 2C A side view of the second top spacer 226(2) of the VCFET 200 is shown. As shown, the second spacer 226(2) is disposed adjacent to the second end surface 208(2) of the first channel portion 204(1), which end surface is also adjacent to the third end surface 208(3) of the second channel portion 204(2). The second spacer 226(2) surrounds the second channel portion 204(2) of the vertical channel 202. The second spacer 226(2) includes a plurality of air gaps 228(1), 228(2) disposed between adjacent dielectric layers 230. Since the dielectric constant of air is 1.0 and the dielectric constant of the dielectric layer 230 is greater than 1.0, the introduction of the air gaps 228(1), 228(2) in the second spacer 226(2) reduces the overall dielectric constant of the second spacer 226(2). As shown in FIG. Figure 2CAs shown, the second spacer 226(2) further includes a spacer sidewall 232, which is adjacent to the substrate surface 205( Figure 2B ) and extends along the longitudinal axis A3 in a vertical direction (Z-axis direction) orthogonal to the gate electrode 218. The spacer sidewall 232 is disposed between the gate electrode 218 and the source contact 220. Figure 2D As shown, the spacer sidewall 232 also extends downwardly adjacent to the first bottom spacer 226(1).

[0038] Continue to refer Figure 2C In this example of VCFET 200, second spacer region 226(2) further includes air gaps 228(1), 228(2) that are elongated and parallel to substrate surface 205( Figure 2B ). The air gaps 228(1), 228(2) also each have a height H5 in the vertical direction (Z-axis direction), such that the height H5 is smaller than the length L1 of the air gaps 228(1), 228(2). By making the air gaps 228(1), 228(2) in the second spacer 226(2) horizontally elongated by having their height H5 smaller than their length L1, the air gaps 228(1), 228(2) have the effect of contributing series capacitance to the parasitic capacitance between the gate 218 and the drain contact 212 and / or the source contact 220 because of the orientation of the air gaps 228(1), 228(2) relative to the electric field generated in the vertical channel 202 when a voltage difference is applied between the gate 218 and the source 214. The series capacitance added to the parasitic capacitance between the gate 218 and the drain contact 212 and / or the source contact 220 reduces the parasitic capacitance between the gate 218 and the drain contact 212 and / or the source contact 220 , and thus reduces the overall parasitic capacitance of the VCFET 200 .

[0039] and Figure 2C Similar to the second top spacer region 226(2) in the VCFET 200 shown, the VCFET 200 also includes Figure 2D A first bottom spacer 226(1) is shown. Figure 2DA side view of a first bottom spacer 226(1) of the VCFET 200 is shown. As shown in the figure, the first spacer 226(1) is disposed adjacent to the second end surface 208(2) of the first channel portion 204(1), which is also adjacent to the first end surface 208(1) of the first channel portion 204(1) of the vertical channel 202. The first spacer 226(1) surrounds a portion of the first channel portion 204(1) of the vertical channel 202. Similar to the second top spacer 226(2), the first bottom spacer 226(1) also includes a plurality of air gaps 234(1), 234(2) disposed between adjacent dielectric layers 236. Since the dielectric constant of air is 1.0 and the dielectric constant of the dielectric layer 236 is greater than 1.0, the introduction of the air gaps 234(1), 234(2) in the first spacer 226(1) reduces the overall dielectric constant of the first spacer 226(1). In this example of VCFET 200, first spacer region 226(1) further includes air gaps 234(1), 234(2) that are elongated and extend over a first length L1 in a horizontal direction (X-axis direction) parallel to substrate surface 205 ( Figure 2B ). The length L1 of the air gaps 228(1), 228(2) in the second spacer 226(2) and the air gaps 234(1), 234(2) in the first spacer 226(1) are the same in this example, but are not necessarily the same. The air gaps 234(1), 234(2) also each have a height H5 in the vertical direction (Z-axis direction), so that the height H5 is smaller than the length L1 of the air gaps 228(1), 228(2). The height H5 of the air gaps 228(1), 228(2) in the second spacer 226(2) and the air gaps 234(1), 234(2) in the first spacer 226(1) are the same in this example, but are not necessarily the same.

[0040] By making the air gaps 234(1), 234(2) in the first spacer region 226(1) horizontally elongated by having their height H5 less than their length L1, the air gaps 234(1), 234(2) have the effect of contributing series capacitance to the parasitic capacitance between the gate 218 and the source contact 220 due to the orientation of the air gaps 234(1), 234(2) relative to the electric field generated in the vertical channel 202 when a voltage difference is applied between the gate 218 and the source 214. The series capacitance added to the parasitic capacitance between the gate 218 and the source contact 220 can reduce the parasitic capacitance between the gate 218 and the source contact 220 and, therefore, reduce the overall parasitic capacitance of the VCFET 200.

[0041] Notice, Figure 2A-2DThe source 214 and drain 210 in the VCFET 200 in FIG. 2 may be reversed in an alternative arrangement. In this alternative arrangement, the drain 210 may be disposed in the well 216 and the source 214 may be disposed adjacent to the fourth end surface 208(4) of the second channel portion 204(2) of the vertical channel 202.

[0042] VCFET (such as Figure 2A-2D VCFET 200) can be provided in the form of NMOS and PMOS devices / transistors in an integrated circuit (IC) to form a CMOS circuit. In this regard, Figure 4 4 is a side view of an exemplary IC 400 including an N-type VCFET 402N as an NMOS device / transistor and a P-type VCFET 402P as a PMOS device / transistor. Figure 2A-2D The common elements between the VCFETs 200 in FIG. 1 are shown using common element numbers. Figure 4 As shown, the N-type VCFET 402N and the P-type VCFET 402P are formed on a common substrate 206. The N-type VCFET 402N and the P-type VCFET 402P may be similar to Figure 2A-2D 200 in the VCFET 202N. For the N-type VCFET 402N, its source 214N and drain 210N are N-type sources and drains. The source 214N is formed in the P-type well 216P. For the P-type VCFET 402P, its source 214P and drain 210P are P-type sources and drains. The source 214P is formed in the N-type well 216N.

[0043] VCFET (including but not limited to Figure 2A-2D and Figure 4 The VCFET 200, 402N, 402P) in the embodiment includes a vertical channel and / or a spacer between a gate and a contact, the vertical channel having an end portion that is expanded in width in a horizontal direction perpendicular to the height of the vertical channel to reduce the contact resistance, the spacer including one or more horizontal air gaps that are elongated in the horizontal direction to reduce the overall average dielectric constant of the spacer, and thus reduce the parasitic capacitance of the VCFET, which can be manufactured according to various processes. For example, Figure 5 is a flow chart illustrating an exemplary fabrication process 500 for fabricating a VCFET including a vertical channel having a tip to reduce contact resistance and / or a spacer between a gate and a contact to reduce the overall average dielectric constant of the spacer and, therefore, reduce parasitic capacitance of the VCFET. Figure 5 The manufacturing process 500 is referenced Figure 2A-2D However, it is noted that the manufacturing process 500 is not limited to manufacturing Figure 2A-2D VCFET200, and can also be used to make Figure 4 VCFET 402N, 402P or other VCFETs in.

[0044] In this regard, Figure 5 As shown, the steps of the manufacturing process 500 may be: providing a substrate 206 ( Figure 5 The next step of the manufacturing process 500 may be to form the vertical channel 202 ( Figure 5 Forming the vertical channel 202 may include forming a first channel portion 204(1) including a first end surface 208(1) and a second end surface 208(2) opposite the first end surface 208(1) ( Figure 5 The first channel portion 204(1) may have a first height H3 in a first direction (Z-axis direction) orthogonal to the substrate surface 205. The second end surface 208(2) may have a first width W3 less than the first height H4 in a second direction (X-axis direction) parallel to the substrate surface 205. Forming the vertical channel 202 may also include forming the second channel portion 204(2), the second channel portion 204(2) including a third end surface 208(3) coupled to the second end surface 208(2) and a fourth end surface 208(4) opposite to the third end surface 208(3) ( Figure 5 The second channel portion 204(2) may have a second height H4 in the first direction (Z-axis direction). The fourth end surface 208(4) may have a second width W2 in the second direction (X-axis direction) that is greater than the first width W3. Another step in the manufacturing process 500 may include forming a gate 218( Figure 5 5. Another step in the manufacturing process 500 may include forming a source / drain 214 / 210 ( 214 / 210 ) coupled to the first end surface 208(1) of the first channel portion 204(1). Figure 5 Another step in the manufacturing process 500 may include forming a drain / source 210 / 214 ( coupled to a fourth end surface of the second channel portion 204(2) ) Figure 5 514 in FIG.

[0045] VCFET ICs including vertical channels and / or spacers between gates and contacts may be manufactured according to various processes and may be manufactured according to other manufacturing processes (including but not limited to Figure 2A-2D and Figure 4VCFET 200, 402N, 402P), the vertical channel has an end portion that is expanded in width in a horizontal direction perpendicular to the height of the vertical channel to reduce contact resistance, and the spacer includes one or more horizontal air gaps that are elongated in the horizontal direction to reduce the overall average dielectric constant of the spacer, and thus reduce the parasitic capacitance of the VCFET. For example, Figure 6A-6G is a flow chart showing another exemplary manufacturing process 600 for manufacturing an IC including a VCFET including a vertical channel and / or a spacer between a gate and a contact, the vertical channel having ends extending in width in a horizontal direction perpendicular to the height of the vertical channel, the spacer including one or more horizontal air gaps elongated in the horizontal direction to reduce an overall average dielectric constant of the spacer. Figure 7A-7M is based on Figure 6A-6G 1 and 2. Exemplary manufacturing stages 700A-700M during the manufacturing of an IC and its VCFETs in the manufacturing process 600 of FIG. Figure 6A-6G The manufacturing process 600 is referenced Figure 7A-7M The manufacturing stages 700A-700M in are discussed below, wherein the manufacturing stages 700A-700M are referred to VCFET 200, but are not limited thereto.

[0046] like Fig. 7A As shown in the exemplary manufacturing stage 700A in FIG. 6 , the first step of the manufacturing process 600 is to pattern the fins to serve as the first channel portion 204 (1) of the vertical channel 202 for the plurality of VCFETs ( Fig. 6A 602 in FIG. Fig. 7A As shown, a substrate 206 is provided. A well layer 705 is formed on a substrate surface 205 of the substrate 206, in which a well 216 is formed. Figure 2D As shown, in order to prepare the first bottom spacer region 226 (1) which will become the VCFET and to form the air gaps 234 (1), 234 (2) therein, the first dielectric layer 702 and the second dielectric layer 704 are disposed on the well layer 705 in an alternating manner, as shown in FIG. Fig. 7A700A in the manufacturing process. If the VCFET to be formed is an NMOS device, the well layer 705 will be implanted with a P-type material to form a P-type well. If the VCFET to be formed is a PMOS device, the well layer 705 will be implanted with an N-type material to form an N-type well. The first dielectric layer 702 is a layer that will be retained as part of the first bottom spacer 226 (1). For example, the first dielectric layer 702 can be a layer made of SiN. The second dielectric layer 704 is a layer that acts as a sacrificial layer and will eventually be removed in a later processing step to leave a gap that will form the air gap 234 (1), 234 (2) for the first bottom spacer 226 (1). The first dielectric layer 702 and the second dielectric layer 704 are then patterned and dry etched to form an opening 706 with a width W3 to define the final sidewall 708 of the first channel portion 204 (1). The first channel portion 204(1) is formed in the opening 706, for example, by growing a silicon material in the opening 706. A hard mask 710 made of a material that is not easily etched (e.g., SiN) is deposited on the second end surface 208(2) of the first channel portion 204(1) to protect the first channel portion 204(1) in subsequent processing steps.

[0047] Then, if Figure 7B As shown in the exemplary manufacturing stage 700B in FIG. 7 , the well layer 705 is patterned to form individual wells 216 ( Fig. 6A As part of patterning the well 216, the first bottom spacer 226(1) is also patterned so that portions of the first dielectric layer 702 and the second dielectric layer 7704 that are outside the well 216 in the vertical direction (Z-axis direction) are also removed. For example, the well 216 may be patterned using an etching process. The hard mask 710 formed on the second end surface 208(2) of the first channel portion 204(1) protects the first channel portion 204(1) during the patterning of the well 216 and the first spacer 226(1).

[0048] Then, if Figure 7C As shown in the exemplary manufacturing stage 700C in FIG. 1 , in order to form the air gaps 234 ( 1 ), 234 ( 2 ) in the first spacer region 226 ( 1 ), the second dielectric layer 704 is removed ( Figure 6B 6). For example, the second dielectric layer 704 may be removed by a wet etching process (e.g., using dilute hydrofluoric acid (DHF)). Then, as shown in FIG. Fig.7D As shown in the exemplary manufacturing stage 700D in FIG. 1 , in order to prepare the top second spacer 226 ( 2 ) to be formed adjacent to the second end surface 208 ( 2 ) of the first channel portion 204 ( 1 ), Figure 2C), an oxide layer 712 is deposited on the substrate surface 205 outside the well 216 and on the first spacer 226 (1) and around the first channel portion 204 (1) ( Figure 6B 6. The oxide layer 712 is then processed (eg, by a chemical mechanical polishing (CMP) process) to form an oxide layer surface 714 that is coplanar with the second end surface 208(2) of the first channel portion 204(1).

[0049] Then, if Fig. 7E As shown in the exemplary manufacturing stage 700E in FIG. 1 , in order to prepare the second top spacer region 226 ( 2 ) which will become the VCFET, and to form air gaps 228 ( 1 ), 228 ( 2 ) therein, as shown in FIG. Figure 2C As shown, the third dielectric layer 716 and the fourth dielectric layer 718 are disposed on the oxide layer surface 714 and the second end surface 208 (2) of the first channel portion 204 (1) in an alternating manner ( Figure 6C 610 in FIG. 610 ). The third dielectric layer 716 is a layer that will be retained as part of the second top spacer 226 ( 2 ). For example, the third dielectric layer 716 may be a layer made of SiN. The fourth dielectric layer 718 is a layer that serves as a sacrificial layer and will eventually be removed in a later processing step to leave a void that will form the air gap 228 ( 1 ), 228 ( 2 ) for the second top spacer 226 ( 2 ). Then, as shown in FIG. Figure 7F As shown in exemplary manufacturing stage 700F in FIG. 1 , in preparation for the second channel portion 204(2) to be formed into contact with the second end surface 208(2) of the first channel portion 204(1), the third dielectric layer 716 and the fourth dielectric layer 718 are patterned to form openings 720(a) above and below the second end surface 208(2) of the first channel portion 204(1). Figure 6C The opening 720 is formed so that the fourth end surface 208(4) of the second channel portion 204(2) to be formed in the opening 720 will have a width of W2, such as Figure 2A shown.

[0050] Then, if Figure 7G As shown in the exemplary manufacturing stage 700G in FIG. 1 , a second channel portion 204 ( 2 ) is formed in the opening 720 patterned in the third dielectric layer 716 and the fourth dielectric layer 718 ( Fig.6D614 in the block). For example, the second channel portion 204(2) can be formed by growing a silicon material in the opening 720. The second channel portion 204(2) is formed so that its bottom third end surface 208(3) is formed on the second end surface 208(2) of the first channel portion 204(1). The fourth end surface 208(4) is formed on the top of the second channel portion 204(2) and can be processed (e.g., by a CMP process) so that the fourth end surface 208(4) is coplanar with the outer surface 724 of the topmost third dielectric layer 716. Then, as Figure 7H As shown in the exemplary manufacturing stage 700H, Figure 7G The third dielectric layer 716 and the fourth dielectric layer 718 in the present example are then patterned and dry etched to form the second top spacer 226 (2) ( Fig.6D 616 in FIG.

[0051] Then, if Fig.7I As shown in the exemplary manufacturing stage 700I in FIG. 1 , in order to form the air gaps 228 ( 1 ), 228 ( 2 ) in the second top spacer region 226 ( 2 ), the fourth dielectric layer 718 is removed ( Fig. 6E 618 in FIG. 5 ). For example, the fourth dielectric layer 718 may be removed by a wet etching process (eg, using dilute hydrofluoric acid (DHF)). Then, as shown in FIG. Figure 7J As shown in the exemplary manufacturing stage 700J in FIG. 1 , a sidewall 711 is formed adjacent to the air gaps 228(1), 228(2) and the third dielectric layer 716 of the second spacer 226(2) to seal the air gaps 228(1), 228(2) ( Fig. 6E Then, as in block 620. Figure 7K As shown in the exemplary manufacturing stage 700K in FIG. 1 , the oxide layer 712 is recessed adjacent to the first channel portion 204 ( 1 ) to form a shallow trench ( Fig. 6F A gate oxide 726 is then deposited as an insulator in the recess adjacent to the first channel portion 204 ( 1 ), and a metal gate material 728 is then deposited on the gate oxide 726 to form the gate 218 ( Fig. 6F Then, as in block 622 of FIG. Figure 7L As shown in the exemplary manufacturing stage 700L in FIG. 1 , a spacer sidewall 232 ( Fig. 6F The well 216 is also patterned and recessed so that the source electrode 214 ( 1 ) in contact with the first end surface 208 ( 1 ) of the first channel portion 204 ( 1 ) is epitaxially deposited in the well 216 . Fig. 6FThe drain 210 is also epitaxially grown on the fourth end surface 208(4) of the second channel portion 204(2), and has an expanded surface area ( Fig. 6F At this point, three (3) VCFETs 200(1)-200(3) are formed.

[0052] Then, if Figure 7M As shown in the exemplary manufacturing stage 700M in FIG. 7 , to finally complete the manufacture of IC 730, another oxide layer 732 is deposited as an interlayer dielectric (ILD) ( Figure 6G The source contact 220 and the drain contact 2212 are patterned and formed in the oxide layer 732 and contact the corresponding source 214 and drain 210 to form connections with the corresponding source 214 and drain 210 of the VCFETs 200(1)-200(3) ( Figure 6G 626 in FIG.

[0053] It should be understood that the term source / drain can mean source or drain. The term drain / source can mean drain or source. When discussing source / drain and drain / source with respect to the VCFET example, if the first element is referred to as source / drain and the second element is referred to as drain / source, if the first element is the source, the second element is the drain, and vice versa-if the first element is the drain, the second element is the source. It should also be understood that the terms "first", "second", "third", "fourth", etc. used in this article are relative terms and are not meant to limit or imply order or other orientation. It should also be understood that the terms "top", "above", "bottom", "below", etc. used in this article are relative terms and are not meant to limit or imply strict orientation. The element cited by "top" does not necessarily need to be above the element cited by "bottom" relative to the ground, and vice versa. The element cited as "top" or "bottom" may only be located at the top or bottom relative to the example and the specific example shown. An element referenced as "above" or "below" another element is not necessarily relative to the ground, and vice versa. An element referenced as "above" or "below" may be above or below such other referenced element, relative only to this example and the particular illustrated example. The term "adjacent" between elements does not necessarily require that the elements be physically connected or directly adjacent to each other without the presence of intervening elements.

[0054] A VCFET may be provided in a processor-based device or may be integrated into any processor-based device, the VCFET comprising a vertical channel and / or a spacer region between a gate and a contact, the vertical channel having ends extending in width in a horizontal direction perpendicular to the height of the vertical channel to reduce contact resistance, the spacer region comprising one or more horizontal air gaps elongated in a horizontal direction to reduce an overall average dielectric constant of the spacer and thereby reduce parasitic capacitance of the VCFET, the VCFET including but not limited to FIG. 2A to FIG. 2D , Figure 4 and FIG. 7A to FIG. 7M VCFETs 200, 402N, 402P, 200(1)-200(3) in the embodiment of the present invention, and according to Figures 5 to 6G Examples include, but are not limited to, set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, global positioning system (GPS) devices, mobile phones, cellular phones, smart phones, session initiation protocol (SIP) phones, tablet computers, tablet phones, servers, computers, portable computers, mobile computing devices, wearable computing devices (e.g., smart watches, health or fitness trackers, glasses, etc.), desktop computers, personal digital assistants (PDAs), displays, computer displays, televisions, tuners, radio units, satellite radio units, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, drones, and multirotors.

[0055] in this regard, Figure 8 An example of a processor-based system 800 is shown, which system may include one or more VCFETs 802, 802(1)-802(7), wherein the VCFET may be provided in a processor-based device or may be integrated into any processor-based device, the VCFET including a vertical channel and / or a spacer region between a gate and a contact, the vertical channel having ends extending in width in a horizontal direction perpendicular to a height of the vertical channel to reduce contact resistance, the spacer region including one or more horizontal air gaps elongated in a horizontal direction to reduce an overall average dielectric constant of the spacer and thereby reduce parasitic capacitance of the VCFET, the VCFET including but not limited to FIG. 2A to FIG. 2D , Figure 4 and FIG. 7A to FIG. 7M VCFETs 200, 402N, 402P, 200(1)-200(3) in the embodiment of the present invention, and according to Figures 5 to 6Gand manufactured according to any aspect disclosed herein. In this example, the processor-based system 800 can be formed as an IC 804 and as part of an IC package (e.g., a system on chip (SoC) 806). The processor-based system 800 includes a central processing unit (CPU) 808, which includes one or more processors 810, which can also be referred to as a CPU core or processor core. The CPU 808 can have a cache memory 812 coupled to the CPU 808 for quick access to temporarily stored data. The CPU 808 is coupled to a system bus 814 and can be mutually coupled with master devices and slave devices included in the processor-based system 800. As is well known, the CPU 808 communicates with these other devices by exchanging address, control, and data information via the system bus 814. For example, the CPU 808 can transmit a bus transaction request to a memory controller 816 (as an example of a slave device). Although Figure 8 Although not shown, multiple system buses 814 may be provided, wherein each system bus 814 constitutes a different structure.

[0056] Other master devices and slave devices may be connected to the system bus 814. Figure 8 As shown, these devices may include a memory system 820 (which includes a memory controller 816 and a memory array 818), one or more input devices 822, one or more output devices 824, one or more network interface devices 826, and one or more display controllers 828, as examples. The input device 822 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. The output device 824 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. The network interface device 826 may be any device configured to allow data to be exchanged with the network 830. The network 830 may be any type of network, including but not limited to a wired or wireless network, a dedicated or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a Bluetooth network, and the Internet. The network interface device 826 may be configured to support any type of communication protocol expected.

[0057] The CPU 808 may also be configured to access a display controller 828 via the system bus 814 to control information sent to one or more displays 832. The display controller 828 sends information to be displayed to the display 832 via one or more video processors 834, which processes the information to be displayed into a format suitable for the display 832. The display 832 may include any type of display, including but not limited to a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, a light emitting diode (LED) display, etc.

[0058] Fig. 9 An exemplary wireless communication device 900 is shown, the device including an electrical assembly formed of one or more ICs 902, wherein any of the ICs 902 may include one or more VCFETs 903, the VCFETs may be provided in a processor-based device or may be integrated into any processor-based device, the VCFETs including a vertical channel and / or a spacer between a gate and a contact, the vertical channel having ends extending in width in a horizontal direction perpendicular to the height of the vertical channel to reduce contact resistance, the spacer including one or more horizontal air gaps elongated in a horizontal direction to reduce an overall average dielectric constant of the spacer and thereby reduce parasitic capacitance of the VCFETs, the VCFETs including but not limited to FIG. 2A to FIG. 2D , Figure 4 and FIG. 7A to FIG. 7M VCFETs 200, 402N, 402P, 200(1)-200(3) in the embodiment of the present invention, and according to Figures 5 to 6G The wireless communication device 900 may be manufactured by any of the manufacturing processes 500 and 600 in the present invention and according to any aspect disclosed herein. As an example, the wireless communication device 900 may include any of the above-mentioned devices or be provided in any of the above-mentioned devices. Fig. 9 As shown, the wireless communication device 900 includes a transceiver 904 and a data processor 906. The data processor 906 may include a memory for storing data and program codes. The transceiver 904 includes a transmitter 908 and a receiver 910 that support two-way communication. Generally, the wireless communication device 900 may include any number of transmitters 908 and / or receivers 910 for any number of communication systems and frequency bands. All or part of the transceiver 904 may be implemented on one or more analog ICs, RF ICs (RFICs), mixed signal ICs, etc.

[0059] The transmitter 908 or the receiver 910 may be implemented using a super heterodyne architecture or a direct conversion architecture. In a super heterodyne architecture, the signal is frequency converted in multiple stages between RF and baseband, for example, from RF to an intermediate frequency (IF) in one stage, and then from IF to baseband in another stage of the receiver 910. In a direct conversion architecture, the signal is frequency converted in one stage between RF and baseband. Super heterodyne architectures and direct conversion architectures may use different circuit blocks and / or have different requirements. Fig. 9 In the wireless communication device 900, the transmitter 908 and the receiver 910 are implemented using a direct conversion architecture.

[0060] In the transmit path, the data processor 906 processes data to be transmitted and provides I and Q analog output signals to a transmitter 908. In the exemplary wireless communication device 900, the data processor 906 includes digital-to-analog converters (DACs) 912(1), 912(2) for converting digital signals generated by the data processor 906 into I and Q analog output signals (e.g., I and Q output currents) for further processing.

[0061] In the transmitter 908, low pass filters 914(1), 914(2) filter the I and Q analog output signals, respectively, to remove unwanted signals resulting from the previous digital-to-analog conversion. Amplifiers (AMPs) 916(1), 916(2) amplify the signals from the low pass filters 914(1), 914(2), respectively, and provide I and Q baseband signals. An up-converter 918 up-converts the I and Q baseband signals with I and Q (TX) LO signals from a transmit (TX) local oscillator (LO) signal generator 922 through mixers 920(1), 920(2) to provide an up-converted signal 924. A filter 926 filters the up-converted signal 924 to remove unwanted signals resulting from the frequency up-conversion and noise in the receive frequency band. A power amplifier (PA) 928 amplifies the up-converted signal 924 from the filter 926 to obtain a desired output power level and provides a transmit RF signal. The transmit RF signal passes through a duplexer or switch 930 and is transmitted via an antenna 932 .

[0062] In the receive path, antenna 932 receives the signal transmitted by the base station and provides a received RF signal, which is routed through a duplexer or switch 930 and provided to a low noise amplifier (LNA) 934. The duplexer or switch 930 is designed to operate with a specific receive (RX)-to-TX duplexer frequency spacing so that the RX signal is isolated from the TX signal. The received RF signal is amplified by LNA 934 and filtered by filter 936 to obtain the desired RF input signal. Down-conversion mixers 938 (1), 938 (2) mix the output of filter 936 with the I and Q RXLO signals (i.e., LO_I and LO_Q) from RX LO signal generator 940 to generate I and Q baseband signals. The I and Q baseband signals are amplified by AMPs 942(1), 942(2) and further filtered by low pass filters 944(1), 944(2) to obtain I and Q analog input signals, which are provided to the data processor 906. In this example, the data processor 906 includes analog-to-digital converters (ADCs) 946(1), 946(2) for converting the analog input signals into digital signals for further processing by the data processor 906.

[0063] exist Fig. 9 In the wireless communication device 900 of FIG. 1 , the TX LO signal generator 922 generates I and Q TX LO signals for frequency up-conversion, and the RX LO signal generator 940 generates I and Q RX LO signals for frequency down-conversion. Each LO signal is a periodic signal with a specific base frequency. The TX phase-locked loop (PLL) circuit 948 receives timing information from the data processor 906 and generates a control signal for adjusting the frequency and / or phase of the TX LO signal from the TX LO signal generator 922. Similarly, the RX PLL circuit 950 receives timing information from the data processor 906 and generates a control signal for adjusting the frequency and / or phase of the RX LO signal from the RX LO signal generator 940.

[0064] Those skilled in the art will further appreciate that the various illustrative logic blocks, modules, circuits and algorithms described in conjunction with the various aspects disclosed herein can be implemented as electronic hardware, stored in a memory or other computer-readable medium and executed by a processor or other processing device, or a combination of the two. As an example, the master device described herein and the slave device can be used in any circuit, hardware component, IC or IC chip. The memory disclosed herein can be a memory of any type and size, and can be configured to store any desired type of information. In order to clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits and steps have been generally described above from a functional perspective. How to implement these functions depends on specific applications, design choices and / or design restrictions imposed on the entire system. The technician can implement the functions in different ways for each specific application, but this implementation decision should not be interpreted as departing from the scope of the present disclosure.

[0065] The various illustrative logical blocks, modules, and circuits described in conjunction with the various aspects disclosed herein may be implemented using a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The processor may be a microprocessor, but in an alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, a combination of one or more microprocessors and a DSP core, or any other such configuration).

[0066] The various aspects disclosed herein may be embodied in hardware and instructions, which are stored in hardware and, for example, may be located in a random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to a processor so that the processor can read information from the storage medium and write information to the storage medium. Alternatively, the storage medium may be part of the processor. The processor and storage medium may be located in an ASIC. The ASIC may be located in a remote station. Alternatively, the processor and storage medium may be located in a remote station, a base station, or a server as discrete components.

[0067] It should also be noted that the operation steps described in any exemplary aspect herein are described to provide examples and discussions. In addition to the illustrated order, the described operations can also be performed in a variety of different orders. In addition, the operations described in a single operation step can actually be performed in a plurality of different steps. Additionally, one or more operation steps discussed in the exemplary aspects can be merged. It is to be understood that the operation steps shown in the flow chart can be modified in many different ways, which will be apparent to those skilled in the art. Those skilled in the art will also understand that information and signals can be represented using a variety of different techniques and methods. For example, the data, instructions, commands, information, signals, bits, symbols, and chips mentioned throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof.

[0068] The previous description of the disclosure is provided to enable those skilled in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to those skilled in the art, and the general principles defined herein may also be applied to other variations. Therefore, the disclosure is not limited to the examples and designs described herein, but is to be given the widest scope consistent with the principles and novel features disclosed herein.

[0069] Examples of implementations are also described in the following numbered clauses:

[0070] 1. A vertical channel field effect transistor (VCFET), the VCFET comprising:

[0071] a substrate including a substrate surface;

[0072] A channel, the channel comprising:

[0073] a first channel portion including a first end surface and a second end surface opposite to the first end surface,

[0074] The second end surface has a first width in a first direction parallel to the substrate surface; and

[0075] a second channel portion including a third end surface coupled to the second end surface and a fourth end surface opposite to the third end surface,

[0076] The fourth end surface has a second width in the first direction that is greater than the first width;

[0077] a gate adjacent to the first channel portion;

[0078] a source / drain coupled to the first end surface of the first channel portion; and

[0079] A drain / source is coupled to the fourth end surface of the second channel portion.

[0080] 2. The VCFET of clause 1, wherein the channel is configured to transport charge in a second direction orthogonal to the substrate surface.

[0081] 3. A VCFET according to clause 1 or 2, wherein a ratio of the second width to the first width is at least 1.1.

[0082] 4. A VCFET according to any one of clauses 1 to 3, wherein:

[0083] The first width is between one (1) nanometer (nm) and ten (10) nm; and

[0084] The second width is between one (1) nm and twenty (20) nm.

[0085] 5. A VCFET according to any one of clauses 1 to 4, wherein:

[0086] The first channel portion has a first height in a second direction orthogonal to the substrate surface;

[0087] The first width is smaller than the first height; and

[0088] The second channel portion has a second height in the second direction.

[0089] 6. A VCFET according to any one of clauses 1 to 5, further comprising:

[0090] a first spacer region adjacent to the first end surface of the first channel portion and the gate; and

[0091] a second spacer region adjacent to the second end surface of the first channel portion and the gate;

[0092] The first spacing region includes at least one first air gap; and

[0093] The second spacing region includes at least one second air gap.

[0094] 7. The VCFET of clause 6, further comprising:

[0095] spacer sidewalls extending in a second direction normal to the substrate surface and along a first longitudinal axis normal to the substrate surface; and

[0096] The spacer sidewalls are adjacent to the first spacer, the second spacer, and the gate.

[0097] 8. A VCFET according to clause 6 or 7, wherein:

[0098] Each of the at least one first air gap has a first length extending in the first direction parallel to the substrate surface and a first height extending in a second direction orthogonal to the substrate surface; and

[0099] The first length is greater than the first height; and

[0100] Each of the at least one second air gap has a second length extending in the first direction and a second height extending in the second direction; and

[0101] The second length is greater than the second height.

[0102] 9. A VCFET according to any one of clauses 6 to 8, wherein:

[0103] The at least one first air gap comprises a plurality of first air gaps; and

[0104] The at least one second air gap includes a plurality of second air gaps.

[0105] 10. A VCFET according to any one of clauses 6 to 9, wherein:

[0106] The first spacer region includes a first dielectric structure and the at least one first air gap disposed within the first dielectric structure; and

[0107] The second spacer region includes a second dielectric structure and the at least one second air gap disposed within the second dielectric structure.

[0108] 11. A VCFET according to clause 10, wherein:

[0109] The first dielectric structure includes silicon nitride (SiN); and

[0110] The second dielectric structure includes SiN.

[0111] 12. A VCFET according to any one of clauses 1 to 11, further comprising:

[0112] a first contact coupled to the source / drain coupling and extending in a second direction orthogonal to the substrate surface and along a first longitudinal axis; and

[0113] A second contact is coupled to the drain / source coupling and extends in the second direction along a second longitudinal axis parallel to the first longitudinal axis.

[0114] 13. A VCFET according to any one of clauses 1 to 12, wherein the first channel portion comprises a first sidewall; and

[0115] The gate surrounds the first sidewall of the first channel portion.

[0116] 14. A VCFET according to any one of clauses 1 to 13, wherein the effective length L of the gate eff The gate is defined by a first height of the gate in a second direction perpendicular to the surface of the substrate.

[0117] 15. A VCFET according to any one of clauses 1 to 14, further comprising a P-type semiconductor (P-type) well adjacent to the substrate;

[0118] in:

[0119] The source / drain comprises an N-type source / drain;

[0120] The drain / source comprises an N-type drain / source; and

[0121] The N-type source / drain is disposed in a P-type well.

[0122] 16. A VCFET according to clause 15, wherein the crystal structure of the channel sidewalls of the channel is <001> Oriented in plane.

[0123] 17. A VCFET according to any one of clauses 1 to 14, further comprising an N-type semiconductor (N-type) well adjacent to the substrate;

[0124] in:

[0125] The source / drain comprises a P-type source / drain;

[0126] The drain / source comprises a P-type drain / source; and

[0127] The P-type source / drain is disposed in the N-type well.

[0128] 18. A VCFET according to clause 17, wherein the crystal structure of the channel sidewalls of the channel is <011> Oriented in plane.

[0129] 19. A VCFET according to any one of clauses 1 to 18, wherein:

[0130] The source / drain is composed of a first material, the first material is composed of a group consisting of silicon and silicon germanium; and the source / drain is composed of a second material, the second material is composed of a group consisting of silicon and silicon germanium.

[0131] 20. A VCFET according to any one of clauses 1 to 19, wherein:

[0132] The source / drain is adjacent to the first end surface of the first channel portion adjacent to the substrate surface; and

[0133] The drain / source is adjacent to the fourth end surface of the second channel portion.

[0134] 21. A VCFET according to any one of clauses 1 to 20, wherein the VCFET is integrated in a device selected from the group consisting of: a set-top box; an entertainment unit; a navigation device; a communication device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a Session Initiation Protocol (SIP) phone; a tablet computer; a tablet phone; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a display; a computer display; a television; a tuner; a radio unit; a satellite radio unit; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; an avionics system; an unmanned aerial vehicle; and a multirotor aircraft.

[0135] 22. A method of manufacturing a vertical channel field effect transistor (VCFET), comprising:

[0136] providing a substrate including a substrate surface;

[0137] Forming a channel, comprising:

[0138] forming a first channel portion, the first channel portion including a first end surface and a second end surface opposite to the first end surface, the second end surface having a first width in a first direction parallel to the substrate surface;

[0139] as well as

[0140] forming a second channel portion, the second channel portion including a third end surface coupled to the second end surface and a fourth end surface opposite to the third end surface, the fourth end surface having a second width greater than the first width in the first direction;

[0141] forming a gate adjacent to the first channel portion;

[0142] forming a source / drain coupled to the first end surface of the first channel portion; and

[0143] A drain / source coupled to the fourth end surface of the second channel portion is formed.

[0144] 23. The method according to clause 22, further comprising:

[0145] forming a first spacer region including at least one first air gap adjacent to the first end surface of the first channel portion and the gate; and

[0146] A second spacer region including at least one second air gap is formed, the at least one second air gap being adjacent to the second end surface of the first channel portion and the gate.

[0147] 24. A method according to clause 23, wherein:

[0148] Forming the first spacer region includes: forming each of the at least one first air gap, each of the first air gaps having a first length extending in the first direction parallel to the substrate surface and a first height extending in a second direction orthogonal to the substrate surface, the first length being greater than the first height; and

[0149] Forming the second spacer includes forming each of the at least one second air gap, each second air gap having a second length extending in the first direction and a second height extending in the second direction, the second length being greater than the second height.

[0150] 25. A method according to any one of clauses 22 to 24, further comprising:

[0151] coupling a first contact to the source / drain, the first contact extending in a second direction normal to the substrate surface and along a first longitudinal axis; and

[0152] A second contact is coupled to the drain / source, the second contact extending in the second direction along a second longitudinal axis parallel to the first longitudinal axis.

[0153] 26. The method of clause 23 or 24, wherein forming the first spacer comprises:

[0154] forming a plurality of first dielectric layers;

[0155] forming a plurality of second dielectric layers, each of the plurality of second dielectric layers being disposed between two adjacent first dielectric layers of the plurality of first dielectric layers; and

[0156] The plurality of second dielectric layers are removed to form the at least one first air gap, each of the first air gaps being disposed between two adjacent first dielectric layers of the plurality of first dielectric layers.

[0157] 27. The method of clause 26, further comprising forming a hard mask on the second end surface of the first channel portion before removing the plurality of second dielectric layers.

[0158] 28. A method according to clause 26 or 27, further comprising:

[0159] forming a dielectric layer on the first spacer; and

[0160] Wherein, forming the second spacer region comprises:

[0161] forming a plurality of third dielectric layers; and

[0162] A plurality of fourth dielectric layers are formed, each of the plurality of fourth dielectric layers being disposed between two adjacent third dielectric layers of the plurality of third dielectric layers.

[0163] 29. The method according to clause 28, further comprising:

[0164] forming openings in the plurality of third dielectric layers and the plurality of fourth dielectric layers adjacent to the second end surface of the first channel portion;

[0165] forming the second channel portion coupled to the second end surface of the first channel portion in the opening; and

[0166] The plurality of fourth dielectric layers are removed to form the at least one second air gap, each of the second air gaps being disposed between two adjacent third dielectric layers among the plurality of third dielectric layers.

[0167] 30. The method according to clause 29, further comprising:

[0168] recessing the dielectric layer adjacent to the first channel portion; and

[0169] A metal gate is deposited adjacent to the first channel portion to form the gate.

[0170] 31. A method according to any one of clauses 22 to 30, wherein:

[0171] Forming the source / drain includes: epitaxially growing the source / drain in contact with the first end surface of the first channel portion; and

[0172] Forming the drain / source includes epitaxially growing the drain / source on the fourth end surface of the second channel portion.

[0173] 32. An integrated circuit (IC), comprising:

[0174] a substrate including a substrate surface;

[0175] a plurality of field effect transistors (FETs) on a surface of the substrate, the plurality of FETs comprising:

[0176] P-type semiconductor (P-type) FET, including:

[0177] P-channel, including:

[0178] a first P-type channel portion, the first P-type channel portion including a first end surface and a second end surface opposite to the first end surface,

[0179] The second end surface has a first width in a first direction parallel to the substrate surface; and a second P-type channel portion, the second P-type channel portion including a third end surface coupled to the second end surface and a fourth end surface opposite to the third end surface,

[0180] The fourth end surface has a second width in the first direction that is greater than the first width;

[0181] a first gate adjacent to the first P-type channel portion;

[0182] a P-type source / drain coupled to the first end surface of the first P-type channel portion; and

[0183] a P-type drain / source coupled to the fourth end surface of the second P-type channel portion; and

[0184] N-type semiconductor (N-type) FET, including:

[0185] N-type channel, including:

[0186] a first N-type channel portion, the first N-type channel portion including a fifth end surface and a sixth end surface opposite to the fifth end surface,

[0187] The sixth end surface has a third width in the first direction parallel to the substrate surface; and

[0188] a second N-type channel portion including a seventh end surface coupled to the sixth end surface and an eighth end surface opposite to the seventh end surface,

[0189] The eighth end surface has a fourth width in the first direction that is greater than the third width;

[0190] a second gate adjacent to the first N-type channel portion;

[0191] an N-type source / drain coupled to the fifth end surface of the first N-type channel portion; and

[0192] An N-type drain / source coupled to the eighth end surface of the second N-type channel portion.

[0193] 33. An IC according to clause 32, wherein:

[0194] The P-type channel is configured to transport charge in a second direction orthogonal to the substrate surface; and

[0195] The N-type channel is configured to transfer charges in the second direction orthogonal to the substrate surface.

Claims

1. A vertical channel field effect transistor (VCFET), the VCFET comprising: a substrate including a substrate surface; A channel, the channel comprising: a first channel portion including a first end surface and a second end surface opposite to the first end surface, The second end surface has a first width in a first direction parallel to the substrate surface; and a second channel portion including a third end surface coupled to the second end surface and a fourth end surface opposite to the third end surface, The fourth end surface has a second width in the first direction that is greater than the first width; a gate adjacent to the first channel portion; a source / drain coupled to the first end surface of the first channel portion; and A drain / source is coupled to the fourth end surface of the second channel portion.

2. The VCFET according to claim 1, wherein: The channel is configured to transport charge in a second direction orthogonal to the substrate surface.

3. The VCFET according to claim 1, wherein: A ratio of the second width to the first width is at least 1.

1.

4. The VCFET of claim 1 , wherein: The first width is between one (1) nanometer (nm) and ten (10) nm; and The second width is between one (1) nm and twenty (20) nm.

5. The VCFET of claim 1 , wherein: The first channel portion has a first height in a second direction orthogonal to the substrate surface; The first width is smaller than the first height; and The second channel portion has a second height in the second direction.

6. The VCFET of claim 1 , further comprising: a first spacer region adjacent to the first end surface of the first channel portion and the gate; as well as a second spacer region adjacent to the second end surface of the first channel portion and the gate; The first spacing region includes at least one first air gap; and The second spacing region includes at least one second air gap.

7. The VCFET of claim 6, further comprising: a spacer sidewall extending in a second direction normal to the substrate surface and along a first longitudinal axis normal to the substrate surface; as well as The spacer sidewalls are adjacent to the first spacer, the second spacer, and the gate.

8. The VCFET of claim 6, wherein: Each of the at least one first air gap has a first length extending in the first direction parallel to the substrate surface and a first height extending in a second direction orthogonal to the substrate surface; as well as The first length is greater than the first height; as well as Each of the at least one second air gap has a second length extending in the first direction and a second height extending in the second direction; as well as The second length is greater than the second height.

9. The VCFET of claim 6, wherein: The at least one first air gap comprises a plurality of first air gaps; and The at least one second air gap includes a plurality of second air gaps.

10. The VCFET of claim 6, wherein: The first spacer region includes a first dielectric structure and the at least one first air gap disposed within the first dielectric structure; as well as The second spacer region includes a second dielectric structure and the at least one second air gap disposed within the second dielectric structure.

11. The VCFET of claim 10, wherein: The first dielectric structure includes silicon nitride (SiN); and The second dielectric structure includes SiN.

12. The VCFET of claim 1 , further comprising: a first contact coupled to the source / drain coupling and extending in a second direction orthogonal to the substrate surface and along a first longitudinal axis; as well as A second contact is coupled to the drain / source coupling and extends in the second direction along a second longitudinal axis parallel to the first longitudinal axis.

13. The VCFET of claim 1, wherein: The first channel portion includes a first sidewall; and The gate surrounds the first sidewall of the first channel portion.

14. The VCFET of claim 1, wherein: The effective length L of the gate eff The gate is defined by a first height of the gate in a second direction perpendicular to the surface of the substrate.

15. The VCFET of claim 1, further comprising a P-type semiconductor (P-type) well adjacent to the substrate; in: The source / drain comprises an N-type source / drain; The drain / source comprises an N-type drain / source; as well as The N-type source / drain is disposed in a P-type well.

16. The VCFET of claim 15, wherein: The crystal structure of the channel sidewalls of the channel relative to the substrate surface is <001> Oriented in plane.

17. The VCFET of claim 1, further comprising an N-type semiconductor (N-type) well adjacent to the substrate; in: The source / drain comprises a P-type source / drain; The drain / source comprises a P-type drain / source; as well as The P-type source / drain is disposed in the N-type well.

18. The VCFET of claim 17, wherein: The crystal structure of the channel sidewalls of the channel relative to the substrate surface is <011> Oriented in plane.

19. The VCFET of claim 1 , wherein: The source / drain is composed of a first material, and the first material is composed of a group consisting of silicon and silicon germanium; as well as The drain / source is composed of a second material consisting of a group consisting of silicon and silicon germanium.

20. The VCFET of claim 1, wherein: The source / drain is adjacent to the first end surface of the first channel portion adjacent to the substrate surface; and The drain / source is adjacent to the fourth end surface of the second channel portion.

21. The VCFET of claim 1 , wherein the VCFET is integrated in a device selected from the group consisting of: a set-top box; an entertainment unit; a navigation device; a communication device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet computer; a tablet phone; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a display; a computer display; a television; a tuner; a radio unit; a satellite radio unit; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; an avionics system; an unmanned aerial vehicle; and a multirotor aircraft.

22. A method of manufacturing a vertical channel field effect transistor (VCFET), comprising: providing a substrate including a substrate surface; Forming a channel, comprising: forming a first channel portion including a first end surface and a second end surface opposite to the first end surface, the second end surface having a first width in a first direction parallel to the substrate surface; and forming a second channel portion, the second channel portion including a third end surface coupled to the second end surface and a fourth end surface opposite to the third end surface, the fourth end surface having a second width greater than the first width in the first direction; forming a gate adjacent to the first channel portion; forming a source / drain coupled to the first end surface of the first channel portion; and A drain / source coupled to the fourth end surface of the second channel portion is formed.

23. The method according to claim 22, further comprising: forming a first spacer region including at least one first air gap, the at least one first air gap being adjacent to the first end surface of the first channel portion and the gate; as well as A second spacer region including at least one second air gap is formed, the at least one second air gap being adjacent to the second end surface of the first channel portion and the gate.

24. The method of claim 23, wherein: Forming the first spacer region includes: forming each of the at least one first air gap, each of the first air gaps having a first length extending in the first direction parallel to the substrate surface and a first height extending in a second direction orthogonal to the substrate surface, the first length being greater than the first height; and Forming the second spacer includes forming each of the at least one second air gap, each second air gap having a second length extending in the first direction and a second height extending in the second direction, the second length being greater than the second height.

25. The method of claim 22, further comprising: coupling a first contact to the source / drain, the first contact extending in a second direction normal to the substrate surface and along a first longitudinal axis; as well as A second contact is coupled to the drain / source, the second contact extending in the second direction along a second longitudinal axis parallel to the first longitudinal axis.

26. The method of claim 23, wherein: Forming the first spacer region includes: forming a plurality of first dielectric layers; forming a plurality of second dielectric layers, each of the plurality of second dielectric layers being disposed between two adjacent first dielectric layers of the plurality of first dielectric layers; and The plurality of second dielectric layers are removed to form the at least one first air gap, each of the first air gaps being disposed between two adjacent first dielectric layers of the plurality of first dielectric layers.

27. The method according to claim 26, further comprising: Before removing the plurality of second dielectric layers, a hard mask is formed on the second end surface of the first channel portion.

28. The method of claim 26, further comprising: forming a dielectric layer on the first spacer; as well as Wherein, forming the second spacer region comprises: forming a plurality of third dielectric layers; and A plurality of fourth dielectric layers are formed, each of the plurality of fourth dielectric layers being disposed between two adjacent third dielectric layers of the plurality of third dielectric layers.

29. The method according to claim 28, further comprising: forming openings in the plurality of third dielectric layers and the plurality of fourth dielectric layers adjacent to the second end surface of the first channel portion; forming the second channel portion in the opening coupled to the second end surface of the first channel portion; as well as The plurality of fourth dielectric layers are removed to form the at least one second air gap, each of the second air gaps being disposed between two adjacent third dielectric layers among the plurality of third dielectric layers.

30. The method of claim 29, further comprising: recessing the dielectric layer adjacent to the first channel portion; as well as A metal gate is deposited adjacent to the first channel portion to form the gate.

31. The method of claim 22, wherein: Forming the source / drain includes: epitaxially growing the source / drain in contact with the first end surface of the first channel portion; and Forming the drain / source includes epitaxially growing the drain / source on the fourth end surface of the second channel portion.

32. An integrated circuit (IC), comprising: a substrate including a substrate surface; a plurality of field effect transistors (FETs) on a surface of the substrate, the plurality of FETs comprising: P-type semiconductor (P-type) FET, including: P-channel, including: a first P-type channel portion including a first end surface and a second end surface opposite to the first end surface, the second end surface having a first width in a first direction parallel to the substrate surface; and a second P-type channel portion including a third end surface coupled to the second end surface and a fourth end surface opposite to the third end surface, The fourth end surface has a second width in the first direction that is greater than the first width; a first gate adjacent to the first P-type channel portion; a P-type source / drain coupled to the first end surface of the first P-type channel portion; and a P-type drain / source coupled to the fourth end surface of the second P-type channel portion; and N-type semiconductor (N-type) FET, including: N-type channel, including: a first N-type channel portion, the first N-type channel portion including a fifth end surface and a sixth end surface opposite to the fifth end surface, The sixth end surface has a third width in the first direction parallel to the substrate surface; and a second N-type channel portion including a seventh end surface coupled to the sixth end surface and an eighth end surface opposite to the seventh end surface, The eighth end surface has a fourth width in the first direction that is greater than the third width; a second gate adjacent to the first N-type channel portion; an N-type source / drain coupled to the fifth end surface of the first N-type channel portion; and An N-type drain / source coupled to the eighth end surface of the second N-type channel portion.

33. The IC of claim 32, wherein: The P-type channel is configured to transport charge in a second direction orthogonal to the substrate surface; and The N-type channel is configured to transfer charges in the second direction orthogonal to the substrate surface.

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