Selective tungsten contact plugs over gate and source / drain contacts

Abstract

In one aspect, a transistor includes a gate structure having a metal gate, a dielectric layer at least partially surrounding the metal gate, a metal cap over a portion of the metal gate not surrounded by the dielectric layer, and a gate contact including tungsten in direct contact with the metal cap. In another aspect, a transistor includes a source, a drain, and a channel region, a gate structure including a metal gate between gate spacers over the channel region, and a source or drain (S / D) contact structure. An S / D contact structure including an S / D barrier layer over at least a portion of the source or drain region and in direct contact with the gate spacer, and an S / D contact including a first portion over the S / D barrier layer; and a second portion including tungsten over the first portion.

Description

Technical Field

[0001] Generally speaking, aspects of the present disclosure relate to wafer fabrication methods, and more particularly, but not exclusively, aspects of the present disclosure relate to selective tungsten contact plugs over gate and source / drain contacts and fabrication techniques thereof. Background Art

[0002] Wafer fabrication techniques involve stacking different materials on top of a substrate material to create transistors, resistors, capacitors, and more complex structures (referred to herein as "devices") and the electrical interconnections between them. Devices and interconnects are formed using a variety of wafer process techniques, including diffusing or embedding ions into a neutral substrate, depositing one material on top of another using chemical vapor deposition (CVD), depositing metals using sputtering techniques, growing oxides in a furnace in the presence of oxygen, and selectively growing one material from a seed layer of the same or similar material, to name a few.

[0003] A typical wafer cross section shows a substrate, transistors and other devices built in or on the substrate, and metal interconnect layers above the transistors and other devices, with insulating layers between devices, between devices and interconnect layers, and between interconnect layers. Electrical connections from one conductive layer to another conductive layer are made using vertical connections called vias through an insulating layer separating two conductive layers. For example, a transistor includes a source and a drain separated by a gate, which controls the flow of carriers between the source and the drain. Electrical connections to the source, drain, and gate typically involve vias from the source, drain, or gate to the metal interconnect layers above. The electrical connection to the source or drain region is generally referred to as a source / drain (S / D) contact, and the electrical connection to the gate is generally referred to as a gate contact. In order to make a via through the insulating layer, a hole needs to be etched through the insulating layer and then filled with metal. The metal filling the hole can be called a plug.

[0004] Figure 1 A cross-sectional view of an example 100 of a conventional contact plug structure over a gate and source / drain contacts is shown. Figure 1 As shown, the wafer substrate 102 includes an epitaxial structure 104 connected to a source or drain region 106, which may be referred to herein as a "source / drain region" or "S / D region". The S / D region 106 may be a source region or a drain region, and the contact structure thereon may be a source contact or a drain contact, which may be referred to herein as a "source / drain contact" or "S / D contact".

[0005] Between the paired S / D regions 106 is a channel region 108. Figure 1In the example shown, the S / D contact structure includes an S / D contact barrier layer 110, such as titanium nitride (TiN), which buffers the S / D contact 112 from the surrounding passivation material 114 (e.g., silicon dioxide (SiO2)). The S / D contact 112 is typically tungsten (W) or cobalt (Co), and the S / D contact barrier layer 110 prevents the contact metal from diffusing into the passivation material 114.

[0006] Figure 1 Also shown are cross sections of two transistors, each transistor including a pair of gate spacers 116 between which is a gate structure including a metal gate 118, which is at least partially surrounded by a high-k material 120, such as hafnium oxide (HfO2). An interface layer 122 separates the high-k material 120 from the wafer substrate 102. A dielectric etch stop layer 124, such as silicon oxycarbide (SiOC), separates the passivation material 114 from an upper passivation layer 126, which may be SiO2.

[0007] like Figure 1 As shown, the tungsten contact plug 128 is directly connected to the S / D contact 112 through the hole in the etch stop layer 124. Figure 1 As shown, the gate contact 130 is not directly connected to the metal gate 118, but is separated from the metal gate 118 by a gate contact barrier layer 132 (e.g., titanium (Ti) or TiN). The gate contact barrier layer 132 can increase the resistance of the gate contact 130, which may limit device performance. Selective tungsten cannot be grown directly on the metal gate surface (e.g., TiN or TiAlC), which means that the tungsten gate contact cannot be a selective tungsten structure, but must be created using chemical vapor deposition (CVD) and etching. Moreover, due to the relatively small size of the metal gate 118 (e.g., less than 10 nanometers (nm) in width), the gate contact barrier layer 132 has a relatively small contact area with the metal gate 118, which further increases the resistance.

[0008] Therefore, there is a need for a contact plug and a method of manufacturing the same that overcomes the drawbacks of conventional contact plugs. Summary of the invention

[0009] The following presents a simplified summary of the invention related to one or more aspects disclosed herein. Therefore, the following summary of the invention should not be regarded as a broad overview related to all expected aspects, nor should it be considered that the following summary of the invention identifies key or important elements related to all expected aspects or delimits the scope associated with any particular aspect. Therefore, the sole purpose of the following summary of the invention is to present certain concepts related to one or more aspects related to the mechanisms disclosed herein in a simplified form, prior to the specific embodiments presented below.

[0010] In one aspect, a transistor includes: a gate structure, including: a metal gate; a dielectric layer, which at least partially surrounds the metal gate; a metal cap, which is disposed over a portion of the metal gate not surrounded by the dielectric layer; and a gate contact, which includes tungsten, disposed over the metal cap and in direct contact with the metal cap.

[0011] In one aspect, a semiconductor structure includes a transistor, the transistor including: a source region; a drain region; a channel region, the channel region being disposed between the source region and the drain region; a gate structure, which is disposed above the channel region and includes a metal gate disposed between gate spacers; and a source or drain (S / D) contact structure, the S / D contact structure including: an S / D barrier layer, which is disposed above at least a portion of the source region or the drain region, wherein at least a portion of the S / D barrier layer is in direct contact with one of the gate spacers; and an S / D contact, which includes a first portion disposed above the S / D barrier layer; and a second portion including tungsten, which is disposed above the first portion.

[0012] In one aspect, a method of manufacturing a gate contact structure for a transistor includes: etching a top portion of the metal gate to create a first recess having a first depth within the gate spacer; depositing a metal cap to substantially fill the first recess within the gate spacer; and forming selective tungsten over and in direct contact with the metal cap.

[0013] On the one hand, a method of manufacturing a source or drain (S / D) contact structure for a transistor including a source region includes: depositing an S / D barrier layer over at least a portion of the source region or the drain region, wherein at least a portion of the S / D barrier layer is in direct contact with one of the gate spacers; and depositing an S / D contact over the S / D barrier layer, wherein at least a portion of the S / D contact includes selective tungsten.

[0014] Other objects and advantages associated with the aspects disclosed herein will be apparent to those skilled in the art based on the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] A more complete appreciation of the various aspects of the disclosure and its many attendant advantages will be readily obtained as the disclosure will be better understood by reference to the following detailed description when considered in conjunction with the accompanying drawings, which are presented for purposes of illustration only and not limitation of the disclosure.

[0016] Figure 1 A cross-sectional view of an example of a conventional contact plug structure over a gate and source / drain contacts is shown.

[0017] Figure 2A and Figure 2B A cross-sectional view of an example of a selective tungsten contact plug structure over gate and source / drain contacts according to aspects of the present disclosure is shown.

[0018] FIG. 3A to FIG. 3H is a cross-sectional view illustrating a manufacturing technique according to one or more aspects of the present disclosure.

[0019] Figure 4A and Figure 4B is a flow chart illustrating portions of an example process 400 associated with selective tungsten contact plugs over gate contacts in accordance with aspects of the present disclosure.

[0020] Figure 5 is a flow chart illustrating an example process 400 associated with selective tungsten contact plugs over source / drain contacts in accordance with aspects of the present disclosure.

[0021] Figure 6 An exemplary mobile device according to some examples of the present disclosure is shown.

[0022] As per common practice, features depicted in the drawings may not be drawn to scale. Accordingly, the dimensions of the depicted features may be arbitrarily enlarged or reduced for clarity. As per common practice, some drawings have been simplified for clarity. Thus, the drawings may not show all components of a particular device or method. In addition, throughout the specification and drawings, the same reference numerals refer to the same features. DETAILED DESCRIPTION

[0023] Disclosed herein are semiconductor dies having selective tungsten contact plugs over gate and source / drain contacts (S / D) and methods for manufacturing the same. In one aspect, a transistor includes a gate structure having a metal gate, a dielectric layer at least partially surrounding the metal gate, a metal cap over a portion of the metal gate not surrounded by the dielectric layer, and a gate contact including selective tungsten in direct contact with the metal cap. In another aspect, a transistor includes a source, a drain, and a channel region, a gate structure including a metal gate between gate spacers over the channel region, and a source or drain (S / D) contact structure. The S / D contact structure includes an S / D barrier layer over at least a portion of the source or drain region and in direct contact with the gate spacer, and an S / D contact including a first portion located over the S / D barrier layer; and a second portion including tungsten located over the first portion.

[0024] Aspects of the present disclosure are described in the following description and related drawings relating to specific embodiments. Alternative aspects or embodiments may be designed without departing from the scope of the teachings herein. In addition, well-known elements of exemplary embodiments herein may not be described in detail or may be omitted to avoid obscuring the relevant details of the teachings in the present disclosure.

[0025] In some of the described exemplary embodiments, examples are identified where various component structures and operating parts can be taken from known conventional techniques and then arranged according to one or more exemplary embodiments. In such cases, internal details of known conventional component structures and / or operating parts may be omitted to help avoid potential confusion of the concepts described in the illustrative embodiments disclosed herein.

[0026] The terms used herein are for the purpose of describing specific embodiments only and are not intended to be limiting. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that when used herein, the terms "comprises", "comprising", "includes", and / or "including" specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0027] Figure 2A and Figure 2B Two different cross-sectional views of an example 200 of a selective tungsten contact plug structure over a gate and source / drain contact according to aspects of the present disclosure are shown. As described below, Figure 2A and Figure 2B Shown with Figure 1 However, the epitaxial structure 104, S / D regions 106, channel region 108, passivation material 114, gate spacer 116, metal gate 118, high-k material 120, interface layer 122, dielectric etch stop layer 124, and upper passivation layer 126 are substantially similar in structure to Figure 1 and thus will not be described again here, except in Figure 2A and Figure 2B In the embodiment, the metal gate 118 may include titanium nitride (TiN) or titanium aluminum carbon (TiAlC).

[0028] For the sake of clarity, Figure 2A A cross-sectional view of a portion of a circuit having only S / D contacts but no gate contact is shown. Figure 2AAs shown, the gate structure includes an additional metal cap 202 with a dielectric layer 204 on top. In some aspects, the metal cap 202 is deposited using a CVD process. In some aspects, the metal cap 202 can be tungsten or cobalt. In some aspects, the dielectric layer 204 can be silicon nitride (SiN).

[0029] Once the self-aligned gate structure is fabricated, the structure allows for subsequent fabrication of a large self-aligned S / D contact including an S / D contact barrier layer 206 and a tungsten or cobalt contact 208 to achieve minimal S / D contact resistance. The self-aligned process allows the S / D contact structure to fill the space between the gate spacers 116. In some aspects, the S / D contact barrier layer 206 is in physical contact with the gate spacers 116. Figure 2A As shown, the S / D contacts may include a selective barrier-less tungsten plug 210 for electrically connecting to a metal interconnect layer above the upper passivation layer 126. In some aspects, the selective barrier-less tungsten plug 210 is formed on a metal surface by selective CVD.

[0030] For the sake of clarity, Figure 2B A cross-sectional view of a portion of a circuit is shown with only a gate contact but no S / D contacts. Figure 2B The gate contact is shown in more detail. The gate contact includes a contact plug 212 that includes selective barrier-free tungsten grown on top of the metal cap 202 after removing the dielectric layer 204. In some aspects, the selective barrier-free tungsten plug 212 is formed on the metal surface by selective CVD. Because the gate contact barrier layer 132 is not required, Figure 2B The gate contact structure shown (ie, contact plug 212 and metal cap 202) has a larger Figure 1 The gate contact structure shown in the example 200 has a lower resistance. Because the self-aligned S / D contact structure can fill the space between the gate spacers 116, the S / D contact resistance can be minimized. Therefore, due to the reduced S / D contact resistance and the reduced gate contact resistance, the circuit in the example 200 will have better performance than the circuit shown in the example 100. It should be understood that although the S / D contact is only Figure 2A shown in Figure 1 and the gate contact is only Figure 2B , but both can coexist in the same device.

[0031] In order to fully illustrate various aspects of the design of the present disclosure, a manufacturing method is proposed. Other manufacturing methods are also possible, and the manufacturing method discussed is only presented to help understand the concepts disclosed herein.

[0032] FIG. 3A to FIG. 3H1 is a cross-sectional view illustrating a manufacturing technique according to one or more aspects of the present disclosure. The passivation material 114, gate spacer 116, metal gate 118, high-k material 120, interface layer 122, dielectric etch stop layer 124, and upper passivation layer 126 are substantially similar to Figure 1 2 , and the metal cap 202, the dielectric layer 204, and the contact plug 212 are substantially similar to the same numbered elements in FIG. 2 , and thus their descriptions are not repeated here.

[0033] Figure 3A A cross-sectional view of a transistor is shown having a gate spacer 116 surrounding a gate structure including a metal gate 118, a high-k material 120, and an interface layer 122, which may be created using conventional wafer processing, such as by depositing the high-k material 120 and the metal gate 118, and planarizing using, for example, a chemical / mechanical planarization (CMP) process.

[0034] Figure 3B A cross-sectional view of the transistor is shown after an etching process to create metal recesses within the gate spacers 116 , for example by etching away the metal gate 118 and the high-k material 120 to a desired depth.

[0035] Figure 3C A cross-sectional view of the transistor is shown after a metal cap 202 is deposited and then planarized, for example using a CMP process. In some aspects, the metal cap 202 can be tungsten or cobalt.

[0036] Figure 3D A cross-sectional view of the transistor is shown after an etching process to create metal recesses within the gate spacers 116 , for example by etching away the metal cap 202 to a desired depth.

[0037] Figure 3E 2 shows a cross-sectional view of a transistor after a dielectric layer 204 is deposited and then planarized using a CMP process. In some aspects, the dielectric layer 204 can include SiN. In some aspects, the dielectric layer 204 can be deposited using a CVD process. The SiN dielectric layer 204 enables self-aligned contacts to be formed on the source and drain epitaxial layers, such as Figure 2A shown.

[0038] Figure 3F A cross-sectional view of the transistor is shown after deposition of a dielectric etch stop layer 124 and an upper passivation layer 126. In some aspects, the dielectric etch stop layer 124 can include silicon oxycarbide (SiOC). In some aspects, the upper passivation layer 126 can include SiO2.

[0039] Figure 3GA cross-sectional view of the transistor is shown after an etching process for creating contact holes through the upper passivation layer 126 , the dielectric etch stop layer 124 , and the dielectric layer 204 until the metal cap 202 is exposed.

[0040] Figure 3H A cross-sectional view of the transistor is shown after selective tungsten growth to create a contact plug 212 over the metal cap 202, followed by planarization, for example using a CMP process. The resulting gate contact structure includes the metal gate 118, the metal cap 202, and the contact plug 212, but does not include the gate contact barrier layer 132. Figure 1 The use of selective tungsten for the contact plug 212 and the absence of a barrier layer both result in lower gate contact resistance compared to the conventional gate contact structure shown.

[0041] Figure 4A and Figure 4B 4 is a flow chart illustrating a portion of an example process 400 associated with a selective tungsten contact plug over a gate contact according to various aspects of the present disclosure. It will be appreciated from the foregoing disclosure that additional processes for manufacturing various aspects disclosed herein will be apparent to those skilled in the art, and a literal reproduction of the processes discussed above will not be provided or shown in the included figures. It should be appreciated that the order of the manufacturing processes is not necessarily in any order, and that later processes may be discussed earlier to provide an example of the breadth of the various aspects disclosed.

[0042] like Figure 4A As shown, process 400 may include: at block 402 , manufacturing a transistor, the transistor including a metal gate, a dielectric layer at least partially surrounding the gate, and a gate spacer, wherein the metal gate and the dielectric layer are disposed between the gate spacers.

[0043] like Figure 4A As further shown, process 400 may include, at block 404 , etching a top portion of the metal gate to create a first recess having a first depth within the gate spacer.

[0044] like Figure 4A As further shown, process 400 may include, at block 406, depositing a metal cap to substantially fill the first recess within the gate spacer. In some aspects, depositing the metal cap includes depositing tungsten or cobalt.

[0045] like Figure 4A As further shown, process 400 may include forming selective tungsten over the first portion of the metal cap at block 408. The selective tungsten may be deposited directly over the metal cap, ie, without requiring a barrier layer between the selective tungsten and the metal cap.

[0046] Figure 4BAn example implementation of block 408 is shown in more detail. Figure 4B As shown, block 408 may include, at block 410 , etching a top portion of the metal cap to create a second recess within the gate spacer having a second depth less than the first depth.

[0047] like Figure 4B As further shown, block 408 may include depositing a second dielectric layer to substantially fill the second recess within the gate spacer at block 412. In some aspects, depositing the second dielectric layer includes depositing silicon nitride (SiN).

[0048] like Figure 4B As further shown, block 408 may include, at block 414 , depositing at least one passivation layer over the second dielectric layer, etching the at least one passivation layer to expose a first portion of the second dielectric layer, and etching the first portion of the second dielectric layer to expose a first portion of the metal cap.

[0049] like Figure 4B As further shown, block 408 may include, at block 416 , forming selective tungsten over and in direct contact with the first portion of the metal cap.

[0050] In some aspects, process 400 includes depositing a source / drain (S / D) barrier layer over at least a portion of a source region or a drain region, and depositing an S / D contact over the S / D barrier layer, at least a portion of which includes selective tungsten. In some aspects, depositing the S / D barrier layer includes depositing titanium (Ti) or titanium nitride (TiN). In some aspects, depositing the S / D contact includes depositing a first portion of the S / D contact using a CVD process, and depositing a second portion of the S / D contact over the first portion of the S / D contact, the second portion of the S / D contact including selective tungsten.

[0051] Process 400 may include additional implementations, such as any single implementation or any combination of implementations described below and / or in conjunction with one or more other processes described elsewhere herein. Figure 4A and Figure 4B An example block diagram of process 400 is shown, but in some implementations, process 400 may include Figure 4A and Figure 4B Additional blocks, fewer blocks, different blocks, or blocks arranged in a different manner than those depicted. Additionally or alternatively, two or more of the blocks of process 400 may be performed in parallel.

[0052] Figure 5 is a flow chart illustrating an example process 500 associated with selective tungsten contact plugs over source / drain contacts in accordance with aspects of the present disclosure. Figure 5As shown, process 500 may include: at box 502, manufacturing a transistor, the transistor including a source region, a drain region, a channel region disposed between the source region and the drain region, and a gate structure disposed above the channel region and located between gate spacers, wherein the gate structure includes a metal gate and a dielectric layer at least partially surrounding the metal gate.

[0053] like Figure 5 As further shown, process 500 may include, at block 504 , depositing an S / D barrier layer over at least a portion of the source region or the drain region, wherein at least a portion of the S / D barrier layer is in direct contact with one of the gate spacers.

[0054] like Figure 5 As further shown, process 500 may include, at block 506 , depositing an S / D contact over the S / D barrier layer, wherein at least a portion of the S / D contact includes selective tungsten.

[0055] In some aspects, the gate structure is manufactured before the S / D barrier layer is deposited. For example, after the gate structure is manufactured, they can be covered with a second dielectric layer, which can then be etched to expose the source region and drain region outside the gate spacer and the outer wall of each gate spacer (the inner wall of each gate spacer is in contact with the first dielectric layer that partially surrounds the metal gate). Since the source region and the drain region are exposed, but the gate structure is not exposed, the S / D barrier layer and the S / D contact material can be deposited in a self-aligned manner. Therefore, the S / D contact structure proposed in this article can be referred to as a self-aligned S / D contact. The self-aligned property allows the S / D contact to fill all available space from the contact point on the source or drain region to the outer wall of the gate spacer (or to the outer wall of a gate spacer if the S / D contact is not between two transistors).

[0056] In some aspects, depositing the S / D barrier layer includes depositing titanium (Ti) or titanium nitride (TiN).

[0057] In some aspects, depositing the S / D contact includes depositing a first portion of the S / D contact using a chemical vapor deposition (CVD) process, and depositing a second portion of the S / D contact over the first portion of the S / D contact, the second portion of the S / D contact including selective tungsten.

[0058] In some aspects, process 500 may also include: before depositing the S / D barrier layer: etching a top portion of the metal gate to create a first groove having a first depth within the gate spacer; depositing a metal cap to substantially fill the first groove within the gate spacer; etching a top portion of the metal cap to create a second groove having a second depth less than the first depth within the gate spacer; and depositing a second dielectric layer to substantially fill the second groove within the gate spacer.

[0059] In some aspects, process 500 may further include, after depositing the S / D contacts: etching the second dielectric layer to expose a second recess within the gate spacer, the second recess having a second depth less than the first depth; and forming selective tungsten at least within the second recess and in direct contact with the metal cap.

[0060] Process 500 may include additional implementations, such as any single implementation or any combination of implementations described below and / or in conjunction with one or more other processes described elsewhere herein. Figure 5 An example block diagram of process 500 is shown, but in some implementations, process 500 may include Figure 5 Additional blocks, fewer blocks, different blocks, or blocks arranged in a different manner than those shown. Additionally or alternatively, two or more of the blocks of process 500 may be performed in parallel.

[0061] In some aspects, process 400 and process 500 can include at least one chemical / mechanical planarization (CMP) step.

[0062] The gate and S / D contacts disclosed herein provide various technical advantages. These technical advantages include, but are not limited to, the following: reduced gate resistance, at least in part due to the barrier-free structure disclosed herein and the use of selective tungsten instead of CVD tungsten for the gate contact plug through the passivation layer, and reduced resistance of the self-aligned S / D contacts, at least in part due to the self-aligned process, which allows the creation of larger S / D contacts (e.g., filling the space between the gate spacer of one transistor and the gate spacer of another transistor). Other technical advantages will be recognized from the various aspects disclosed herein, and these technical advantages are provided only as examples and should not be construed as limiting any of the various aspects disclosed herein.

[0063] The aforementioned disclosed devices and functions may be designed and stored in computer files (e.g., register transfer level (RTL), geometry data flow (GDS) Gerber, etc.) stored on a computer readable medium. Some or all of such files may be provided to a manufacturing processor that manufactures devices based on such files. The resulting products may include various components, including semiconductor wafers, which are then cut into semiconductor dies and packaged into semiconductor packages, integrated devices, package-on-package devices, system-on-chip devices, etc., which may then be used in various devices described herein.

[0064] It should be understood that the foregoing manufacturing process is provided only as a general illustration of some aspects of the present disclosure and is not intended to limit the present disclosure or the appended claims. In addition, many details of the manufacturing process known to those skilled in the art may have been omitted or combined in the abstract process section to facilitate understanding of the various aspects disclosed without having to reproduce every detail and / or all possible process variations in detail.

[0065] It will be understood that the various aspects disclosed herein may be described as functional equivalents to structures, materials, and / or devices described and / or recognized by those skilled in the art. For example, in one aspect, an apparatus may include units for performing the various functions discussed above. It will be understood that the foregoing aspects are provided only as examples, and the various aspects claimed are not limited to the specific references and / or illustrations cited as examples.

[0066] The transistors and semiconductor structures described herein can be incorporated into a variety of devices. For example, the transistor can be part of a device such as a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, an Internet of Things (IoT) device, a laptop computer, a server, an access point, a base station, and a device in a motor vehicle. In some aspects, the transistor or semiconductor structure can be part of a mobile device.

[0067] Figure 6 An exemplary mobile device according to some examples of the present disclosure is shown. Figure 6 , which depicts a block diagram of a mobile device configured according to exemplary aspects, and generally represented by a mobile device 600. In some aspects, the mobile device 600 can be configured as a wireless communication device. As shown, the mobile device 600 includes a processor 602. The processor 602 can be communicatively coupled to a memory 604 via a link, which can be a die-to-die or chip-to-chip link. The mobile device 600 also includes a display 606 and a display controller 608, wherein the display controller 608 is coupled to the processor 602 and the display 606.

[0068] In some respects, Figure 6 Can include a coder / decoder (codec) 610 (e.g., an audio and / or voice codec) coupled to the processor 602; a speaker 612 and a microphone 614 coupled to the codec 610; and a wireless circuit 616 coupled to a wireless antenna 618 and the processor 602.

[0069] In certain aspects, where one or more of the above blocks are present, the processor 602, display controller 608, memory 604, codec 610, and wireless circuitry 616 may be included in a system-in-package or system-on-chip (SoC) device 620. An input device 622 (e.g., a physical or virtual keyboard), display 606, speaker 612, microphone 614, wireless antenna 618, and power source 624 (e.g., a battery) may be external to the SoC device 620 and may be coupled to a component of the SoC device 620, such as an interface or controller. For example, selective tungsten contact plugs over gate and S / D contacts may be present in the processor 602, memory 604, or any other component within the SoC device 620.

[0070] It should be noted that although Figure 6 Mobile device 600 is depicted, but processor 602 and memory 604 may also be integrated into a set-top box, music player, video player, entertainment unit, navigation device, personal digital assistant (PDA), fixed location data unit, computer, laptop, tablet computer, communication device, mobile phone, or other similar device.

[0071] Other electronic devices may also have a processor 602 and a memory 604, including but not limited to a group of devices (e.g., electronic devices) including handheld personal communication system (PCS) units, portable data units, global positioning system (GPS) enabled devices, wearable devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous vehicles), Internet of Things (IoT) devices, or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0072] As used herein, the word "exemplary" means "serving as an example, instance, or illustration." Any detail described herein as "exemplary" should not be construed as being advantageous over other examples. Likewise, the term "example" does not mean that all examples include the discussed feature, advantage, or mode of operation. Furthermore, particular features and / or structures may be combined with one or more other features and / or structures.

[0073] It should be noted that the terms "connected", "coupled" or any variations thereof refer to any connection or coupling between elements, whether direct or indirect, and may include the presence of intermediate elements between elements via which the two elements are "connected" or "coupled" together, unless the connection is explicitly disclosed as a direct connection.

[0074] Any reference to elements in this document using designations such as "first," "second," etc. does not limit the number and / or order of those elements. Rather, these designations are used as a convenient method of distinguishing between two or more elements and / or instances of elements. Furthermore, unless explicitly stated, a set of elements may include one or more elements.

[0075] Nothing described or illustrated in this application is intended to provide the public with any component, act, feature, benefit, advantage, or equivalent, regardless of whether the component, act, feature, benefit, advantage, or equivalent is recited in the claims.

[0076] In addition, it will be understood by those skilled in the art that each illustrative logic box, module, circuit and algorithm action described in conjunction with each example disclosed herein can be implemented as electronic hardware, computer software or a combination thereof. In order to clearly represent the interchangeability between hardware and software, each illustrative component, box, module, circuit and action are generally described above around their functions. Whether such function is implemented as hardware or software depends on the specific application and the design constraints imposed on the entire system. Those skilled in the art can implement the described functions in an alternative manner for each specific application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

[0077] Although some aspects have been described in conjunction with devices, it is self-evident that these aspects also constitute a description of the corresponding method, and therefore, the blocks or components of the device should also be understood as corresponding method actions or features of method actions. Similarly, the various aspects described in conjunction with method actions or as method actions also constitute a description of corresponding blocks or details or features of the corresponding device. Some or all of the method actions can be performed by hardware devices (or using hardware devices), for example, microprocessors, programmable computers, or electronic circuits. In some examples, such devices can perform some or more of the most important method actions.

[0078] In the above specific embodiments, it can be seen that in the examples, different features are grouped together. This disclosure should not be understood as the following intention: the example clause has more features than the features explicitly mentioned in each clause. Instead, various aspects of the present disclosure may include fewer features than all the features of the disclosed individual example clauses. Therefore, the following clause requirements should be considered to be combined in the specification, wherein each clause itself can be used as a separate example. Although each dependent clause can be cited in a clause with a specific combination of one of the other clauses, the aspects of the dependent clause are not limited to the specific combination. It will be understood that other example clauses may also include a combination of the subject matter of the dependent clause aspect with any other dependent clause or independent clause, or any feature with other dependent clauses and independent clauses. Unless it is clearly expressed or can be easily inferred that a specific combination is not intended (for example, conflicting aspects, such as defining an element as both an insulator and a conductor), the various aspects disclosed herein include these combinations exactly. In addition, it is also intended that the aspects of the clause can be included in any other independent clause, even if the clause is not directly dependent on the independent clause.

[0079] Implementation examples are described in the following numbered clauses:

[0080] Item 1. A transistor comprising: a gate structure comprising: a metal gate; a dielectric layer at least partially surrounding the metal gate; a metal cap disposed over a portion of the metal gate not surrounded by the dielectric layer; and a gate contact comprising tungsten disposed over and in direct contact with the metal cap.

[0081] Item 2. The transistor of Item 1, wherein the dielectric layer comprises a material having a dielectric constant greater than 3.9.

[0082] Item 3. The transistor of Item 2, wherein the dielectric layer comprises hafnium oxide (HfO2).

[0083] Clause 4. A transistor as described in any one of clauses 1 to 3, wherein the metal gate comprises titanium nitride (TiN) or titanium aluminum carbon (TiAlC).

[0084] Clause 5. A transistor as described in any one of clauses 1 to 4, wherein the metal cap comprises tungsten or cobalt.

[0085] Item 6. A transistor according to any one of Items 1 to 5, wherein the metal gate and the dielectric layer are disposed between gate spacers, and wherein the transistor further comprises: a source region; a drain region; and an S / D contact structure, wherein the S / D contact structure comprises: an S / D barrier layer disposed on at least a portion of the source region or the drain region, wherein at least a portion of the S / D barrier layer is in direct contact with one of the gate spacers; and an S / D contact comprising a first portion disposed on the S / D barrier layer; and a second portion comprising tungsten, which is disposed on the first portion and in direct contact with the first portion.

[0086] Item 7. The transistor of Item 6, wherein the S / D barrier layer comprises titanium (Ti) or titanium nitride (TiN).

[0087] Clause 8. The transistor of any one of clauses 6 to 7, wherein the first portion of the S / D contact comprises tungsten or cobalt.

[0088] Clause 9. A transistor according to any one of clauses 1 to 8, wherein the transistor is part of a device selected from the group consisting of: a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, an Internet of Things (IoT) device, a laptop computer, a server, an access point, a base station, and a device in a motor vehicle.

[0089] Item 10. A semiconductor structure comprising a transistor, the transistor comprising: a source region; a drain region; a channel region, the channel region being disposed between the source region and the drain region; a gate structure disposed above the channel region, comprising a metal gate disposed between gate spacers; and an S / D contact structure, the S / D contact structure comprising: an S / D barrier layer disposed above at least a portion of the source region or the drain region, wherein at least a portion of the S / D barrier layer is in direct contact with one of the gate spacers; and an S / D contact comprising a first portion disposed above the S / D barrier layer; and a second portion comprising tungsten disposed above the first portion.

[0090] Item 11. The semiconductor structure of Item 10, wherein the S / D barrier layer comprises titanium (Ti) or titanium nitride (TiN).

[0091] Clause 12. The semiconductor structure of any one of clauses 10 to 11, wherein the first portion of the S / D contact comprises tungsten or cobalt.

[0092] Item 13. A method for manufacturing a gate contact structure for a transistor, the transistor comprising: a metal gate, a dielectric layer at least partially surrounding the metal gate, and a gate spacer, wherein the metal gate and the dielectric layer are disposed between the gate spacer, the method comprising: etching a top portion of the metal gate to create a first groove having a first depth within the gate spacer; depositing a metal cap to substantially fill the first groove within the gate spacer; and forming selective tungsten above and in direct contact with the metal cap.

[0093] Clause 14. The method of Clause 13, wherein depositing the metal cap comprises depositing tungsten or cobalt.

[0094] Item 15. A method according to any one of items 13 to 14, wherein the selective tungsten formed above the metal cap and in direct contact with the metal cap includes: etching the top portion of the metal cap to create a second groove having a second depth less than the first depth within the gate spacer; and forming selective tungsten at least within the second groove and in direct contact with the metal cap.

[0095] Item 16. A method for manufacturing an S / D contact structure of a transistor, the transistor comprising a source region, a drain region, a channel region disposed between the source region and the drain region, and a gate structure disposed above the channel region and located between gate spacers, wherein the gate structure comprises a metal gate and a dielectric layer at least partially surrounding the metal gate, the method comprising: depositing an S / D barrier layer over at least a portion of the source region or the drain region, wherein at least a portion of the S / D barrier layer is in direct contact with one of the gate spacers; and depositing an S / D contact over the S / D barrier layer, wherein at least a portion of the S / D contact comprises selective tungsten.

[0096] Item 17. The method of Item 16, wherein depositing the S / D barrier layer comprises depositing titanium (Ti) or titanium nitride (TiN).

[0097] Item 18. A method according to any one of items 16 to 17, wherein depositing the S / D contact includes: depositing a first portion of the S / D contact using a chemical vapor deposition (CVD) process, and depositing a second portion of the S / D contact over the first portion of the S / D contact, the second portion of the S / D contact comprising selective tungsten.

[0098] Item 19. The method according to any one of items 16 to 18 further includes: before depositing the S / D barrier layer: etching a top portion of the metal gate to create a first groove having a first depth in the gate spacer; depositing a metal cap to substantially fill the first groove in the gate spacer; etching a top portion of the metal cap to create a second groove having a second depth less than the first depth in the gate spacer; and depositing a second dielectric layer to substantially fill the second groove in the gate spacer.

[0099] Item 20. The method of Item 19, further comprising: after depositing the S / D contacts: etching the second dielectric layer to expose the second recess within the gate spacer; and forming selective tungsten at least within the second recess and in direct contact with the metal cap.

[0100] It should also be pointed out that the methods, systems, and apparatuses disclosed in the specification or claims can be implemented by devices including units for executing corresponding actions and / or functions of the disclosed methods.

[0101] In addition, in some examples, a single action can be subdivided into multiple sub-actions or include multiple sub-actions. Such sub-actions can be included in the disclosure of a single action and can be used as part of the disclosure of a single action.

[0102] Although the foregoing disclosure shows illustrative examples of the present disclosure, it should be noted that various changes and modifications may be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions and / or actions of the method claims according to the examples of the disclosure described herein do not need to be performed in any particular order. In addition, well-known elements will not be described in detail or may be omitted so as not to obscure the relevant details of the aspects and examples disclosed herein. In addition, although the elements of the present disclosure may be described or claimed in the singular, unless it is explicitly stated to be limited to the singular, the plural number is also intended.

Claims

1. A transistor, comprising: A gate structure comprising: Metal gate; a dielectric layer at least partially surrounding the metal gate; a metal cap disposed over a portion of the metal gate that is not surrounded by the dielectric layer; and A gate contact, comprising tungsten, is disposed above and in direct contact with the metal cap.

2. The transistor according to claim 1, wherein The dielectric layer includes a material with a dielectric constant greater than 3.

9.

3. The transistor according to claim 2, wherein: The dielectric layer includes hafnium oxide (HfO 2 ).

4. The transistor according to claim 1, wherein The metal gate includes titanium nitride (TiN) or titanium aluminum carbon (TiAlC).

5. The transistor according to claim 1, wherein The metal cap includes tungsten or cobalt.

6. The transistor according to claim 1, wherein The metal gate and the dielectric layer are disposed between gate spacers, and wherein the transistor further comprises: source region; a drain region; and A source or drain (S / D) contact structure, the S / D contact structure comprising: An S / D barrier layer is disposed on at least a portion of the source region or the drain region, wherein at least a portion of the S / D barrier layer is in direct contact with one of the gate spacers; and an S / D contact including a first portion disposed on the S / D barrier layer; and A second portion including tungsten is disposed over and in direct contact with the first portion.

7. The transistor according to claim 6, wherein: The S / D barrier layer includes titanium (Ti) or titanium nitride (TiN).

8. The transistor according to claim 6, wherein The first portion of the S / D contact includes tungsten or cobalt.

9. The transistor according to claim 1, wherein: The transistor is part of a device selected from the group consisting of: a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, an Internet of Things (IoT) device, a laptop computer, a server, an access point, a base station, and a device in a motor vehicle.

10. A semiconductor structure comprising: A transistor comprising: source region; drain region; a channel region, the channel region being disposed between the source region and the drain region; a gate structure disposed above the channel region, comprising a metal gate disposed between gate spacers; and A source or drain (S / D) contact structure, the S / D contact structure comprising: an S / D barrier layer disposed over at least a portion of the source region or the drain region, wherein at least a portion of the S / D barrier layer is in direct contact with one of the gate spacers; and an S / D contact including a first portion disposed above the S / D barrier layer; and a second portion including tungsten disposed on the first portion.

11. The semiconductor structure according to claim 10, wherein: The S / D barrier layer includes titanium (Ti) or titanium nitride (TiN).

12. The semiconductor structure according to claim 10, wherein: The first portion of the S / D contact includes tungsten or cobalt.

13. A method for manufacturing a gate contact structure of a transistor, the transistor comprising: A metal gate, a dielectric layer at least partially surrounding the metal gate, and a gate spacer, wherein the metal gate and the dielectric layer are disposed between the gate spacer, the method comprising: etching a top portion of the metal gate to create a first recess having a first depth within the gate spacer; depositing a metal cap to substantially fill the first recess within the gate spacer; and Selective tungsten is formed over and in direct contact with the metal cap.

14. The method according to claim 13, wherein: Depositing the metal cap includes depositing tungsten or cobalt.

15. The method according to claim 13, wherein: The selective tungsten formed on and in direct contact with the metal cap includes: etching a top portion of the metal cap to create a second recess in the gate spacer having a second depth less than the first depth; and Selective tungsten is formed at least within the second recess and in direct contact with the metal cap.

16. A method for manufacturing a source or drain (S / D) contact structure of a transistor, the transistor comprising a source region, a drain region, a channel region disposed between the source region and the drain region, and a gate structure disposed above the channel region and between gate spacers, wherein: The gate structure includes a metal gate and a dielectric layer at least partially surrounding the metal gate, and the method includes: depositing an S / D barrier layer over at least a portion of the source region or the drain region, wherein at least a portion of the S / D barrier layer is in direct contact with one of the gate spacers; and An S / D contact is deposited over the S / D barrier layer, wherein at least a portion of the S / D contact comprises selective tungsten.

17. The method according to claim 16, wherein: Depositing the S / D barrier layer includes depositing titanium (Ti) or titanium nitride (TiN).

18. The method according to claim 16, wherein: Depositing the S / D contact includes depositing a first portion of the S / D contact using a chemical vapor deposition (CVD) process, and depositing a second portion of the S / D contact over the first portion of the S / D contact, the second portion of the S / D contact including selective tungsten.

19. The method according to claim 16, further comprising: Before depositing the S / D barrier layer: etching a top portion of the metal gate to create a first recess having a first depth within the gate spacer; depositing a metal cap to substantially fill the first recess within the gate spacer; etching a top portion of the metal cap to create a second recess in the gate spacer having a second depth less than the first depth; as well as A second dielectric layer is deposited to substantially fill the second recess within the gate spacer.

20. The method according to claim 19, further comprising: After depositing the S / D contacts: etching the second dielectric layer to expose the second recess within the gate spacer; as well as Selective tungsten is formed at least within the second recess and in direct contact with the metal cap.

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